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Array molded, cost effective, space saving package solution Available
Top Searches for this datasheetFine Pitch Ball Grid Array Array molded, cost effective, space saving package solution Available 1.40mm (LFBGA), 1.20mm (TFBGA), 1.00mm (VFBGA), 0.80mm (WFBGA) 0.55mm (UFBGA) maximum thickness Laminate substrate based package which enables layers routing flexibility Thin, lightweight, space saving package Flexible body sizes range from 23mm 23mm 0.50, 0.65, 0.75, 0.80, 1.00mm ball pitch Eutectic free solder balls Green package available Multiple routing layers dedicated ground/power planes available improved electrical performance laminate materials metal layers) JEDEC standard compliant DESCRIPTION STATS ChipPAC's Fine Pitch Ball Grid Array (FBGA) laminate substrate based chip scale package with plastic overmolded encapsulation array fine pitch solder ball terminals. FBGA package's reduced outline thickness higher density options make ideal advanced technology packaging solution high performance and/or portable applications. latest materials advanced assembly infrastructure produce reliable cost effective package. Lead free halogen free compatible material sets available. STATS ChipPAC's FBGA available broad range JEDEC standard body sizes with LFBGA (<1.70mm [typically <1.40mm]), TFBGA (<1.20mm), VFBGA (<1.00mm), WFBGA (<0.80mm) UFBGA (0.55mm max.) thickness. LFBGA-H (with attached heatsink) qualified small body sizes. APPLICATIONS Microprocessors/Controllers Wireless Analog ASIC Memory Simple PLDs Others www.statschippac.com Fine Pitch Ball Grid Array SPECIFICATIONS Thickness Mold Thickness Marking Packing Options 75-300µm (3-12 mils) 0.25-0.90mm Laser Tape reel/JEDEC tray RELIABILITY Moisture Sensitivity Level Temperature Cycling High Temp Storage Pressure Cooker Test Temperature/Humidity Test Unbiased HAST JEDEC Level 260°C Reflow Condition (-65°C 150°C), 1000 cycles 150°C, 1000 121°C/100% RH/2atm, 85°C/85% 1000 130°C/85% RH/2 atm, THERMAL PERFORMANCE, (°C/W) Package LFBGA Body Size (mm) (2L) (4L) Count Thermal performance highly dependent package size, size, substrate layers thickness, solder ball configuration. Simulation specific applications should performed obtain maximum accuracy. Size (mm) 10.2 10.2 Thermal Performance 34.1 19.4 Note: Simulation data package mounted layer (per JEDEC JESD51-9) under natural convection defined JESD51-2. ELECTRICAL PERFORMANCE Electrical parasitic data highly dependent package layout. electrical simulation used specific package design provide best prediction electrical behavior. First order approximations calculated using parasitics unit length constituents signal path. Data below frequency 100MHz assumes gold bonding wire. Conductor Component Wire (2L) Total (2L) Wire (4L) Total (4L) Length (mm) Resistance (mOhms) -119 Inductance (nH) 1.65 1.30 4.55 2.95 6.20 1.65 0.90 3.15 2.55 4.80 Inductance Mutual (nH) 0.45 0.85 0.26 2.28 0.71 3.13 0.45 0.85 0.18 1.58 0.63 2.43 Capacitance (pF) 0.10 0.25 0.95 0.35 1.05 0.10 0.35 1.10 0.45 1.20 Capacitance Mutual (pF) 0.01 0.02 0.06 0.42 0.07 0.44 0.01 0.02 0.06 0.42 0.07 0.44 Note: Total Trace Length Solder Ball. CROSS-SECTION PACKAGE CONFIGURATIONS 23x23; Common body sizes: 5x10, 7x9, 8x10, 8x11, 8x12, 8x14, 10x12, 10x14, 13x13, 15x15, 16x16, 17x17 Ball Count Ball Pitch (mm) 0.50 0.80 Typ. Pkg. Thickness LFBGA: 1.70mm (1.40mm max. typical) TFBGA: 1.20mm max. VFBGA: 1.00mm max. WFBGA: 0.80mm max. UFBGA: 0.55mm max. Body Sizes (mm) LFBGA-H Corporate Office Global Offices #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823 510-979-8000 JAPAN 81-3-5789-5850 KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 CHINA 86-21-5976-5858 44-1483-413-700 MALAYSIA 603-4257-6222 NETHERLANDS 31-38-333-2023 STATS ChipPAC logo registered trademark STATS ChipPAC Ltd. other product names other company names herein identification purposes only trademarks registered trademarks their respective owners. STATS ChipPAC disclaims rights those marks. STATS ChipPAC makes guarantee warranty accuracy information given, that such information will infringe intellectual rights third parties. Under circumstances shall STATS ChipPAC liable damages whatsoever arising inability materials this document. STATS ChipPAC reserves right change information time without notice. ©Copyright 2006. STATS ChipPAC Ltd. rights reserved. 2006 Other recent searchesPM25RL1C120 - PM25RL1C120 PM25RL1C120 Datasheet MC100ES6220 - MC100ES6220 MC100ES6220 Datasheet HFAN-09 - HFAN-09 HFAN-09 Datasheet CS5157 - CS5157 CS5157 Datasheet C3200 - C3200 C3200 Datasheet 2200 - 2200 2200 Datasheet 2SD882 - 2SD882 2SD882 Datasheet 1721728 - 1721728 1721728 Datasheet
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