EM6812 Ultra Power 8-bit FLASH Microcontroller EM6812 designed ba
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EM6812 Ultra Power 8-bit FLASH Microcontroller
EM6812 designed battery operated extended lifetime applications. Brownout powercheck functions ensure reliable operation near undervoltage conditions, offering greater reliability complex operation modes. Each I/Os freely programmable microcontroller dual quartz trimmable oscillator 10MHz. 8-bit RISC architecture specially designed very power consumption. With clocks instruction, EM6812 executes MIPS 5MHz achieves astonishing 2200 MIPS/Watt.
Block Diagram
Power Supply Voltage Regulator Supply Voltage Level Detector 8-level
Power Reset
Brownout
SECURITY
FLASH
22.5 kByte 11.2 kByte kByte
CoolRISC 8-bit
CR816L registers Hardware multiplier
512x8
Power
12x8
CORE MEMORY
Dual Port
1-10MHz Crystal 32kHz
Prescaler Prescaler
Watchdog
bit) Timer
CLOCK TIMING
Features
Green mold leadfree package True current: active mode 1MHz standby mode, standby mode, 0.16 sleep mode MIPS 5MHz On-chip brownout detection Powercheck functions start-up 8-level Supply Voltage Level Detection (SVLD) Fast wake-up from standby mode fully configurable I/Os Input Output Pull-up, Pull-down CMOS, N-channel open drain high currents outputs, Wide supply voltage range Flash read monitor (allows save instruction execution lowest voltages) Dual mode quartz oscillators: 32768 crystal external clock source 8-bit CoolRISC architecture registers clock instruction 8x8bit hardware multiplier Power-On-Reset watchdog Various Flash memory size: (5.6k Byte) (11.2k Byte) (22.5k Byte) Fully static 512B 256B RAM, power RAM, Dual port Internal external interrupts Frequency generator functions 8/16-bit timers Prescaler: 10-bit divider 15-bit crystal divider interface, UART programmable software Small 24-pin TSSOP packages (leadfree)
PORT
Pull-up/-down, Edge, Debounce
PORT
SPI, soft UART, PWM, Frequency generator
I/Os
Tools Services
Easy emulator with full debug functions, full peripheral integration, C-compiler Windows-based software programs Programmer from different vendors Dedicated team engineers outstanding support
Pinout Configuration
VREG
EM6812
TSSOP-24 SO-24 Package
(top view)
N.C. TEST RESET
Typical Applications
Metering Heat Cost Allocation Smoke detector Security Body care Sports Computer peripherals, Bluetooth chipset
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EM6812
EM6812 glance
Prescaler's
Prescaler Xtal Oscillators input clock software selectable interval IRQ's (RTC others) clock source other peripherals Divider capture, MSB's power architecture Voltage regulator internal logic supply External regulator capacitor
Power supply
CoolRisc 816L Core internal registers hardware subroutine stacks hardware multiplier refer also CR816L reference manual
Parallel In/Output Port
wide direct input read functions bit-wise configurable Input output debouncer pos. neg. edge Pull-up, pull-down pull selectable Freq. Input timer Input combination reset CMOS NCH. Open Drain outputs
Flash
4096 Instructions 11.26 Kbytes Flash 8192 Instructions 22.5 Kbytes
static SRAM (for Instructions) static SRAM (for Instructions) voltage data retention
Parallel In/Output Port
multipurpose I/O's wide direct input read functions bit-wise configurable high current outputs Input output Pull-up, pull-down pull selectable CMOS NCH. Open Drain outputs special function: Serial Interface I/O's,
power RAM, Byte
lowest power calculations
Dual Port RAM, Byte
Data port Control port
Serial Interface Operating modes
Active mode: peripherals running Standby mode: halted, peripherals Sleep mode: clocks, reset state Wake from port inputs wire serial Interface, Sclk, Din, Dout
Timer bit, bit)
(16) wide, Zero-Stop Auto-Reload mode External signal pulse width measurement generation Event Counter requests
Resets
Power Reset Reset from watchdog timer External Reset Input Brown Reset with Port reset combination Reset Flags identify reset source
Watchdog timer
generation watchdog reset after time
Interrupt
external IRQ's from Port Comparator internal IRQ's from Timer, Prescaler
Oscillator XTAL 32kHZ
Oscillation clock pre-divider sec) External clock frequency input
SVLD
levels supply voltage level check
Oscillator
internal oscillator External clock high frequency input Freq. Trimming register 1MHz 10MHz Clocks stable over temperature voltage
Brown
On-chip Brown-Out detection, reset state Power check Startup
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EM6812
Table contents EM6812 glance Circuit Connectivity
Terminal usage Programming connections Active mode Standby Mode Sleep Mode System registers Memory miss
Operating modes
10.3.2 Input splitting 10.3.3 Actions 10.3.4 Condition match 10.3.5 Don't care bits 10.3.6 Debouncer 10.4 Oscillation Loop 10.4.1 Inverter function 10.5 Dual Port interface
Port
11.1 Basic features 11.1.1 Special function priority handling 11.1.2 Overview 11.2 Register map, functions 11.3 Normal operation 11.4 Special operation 11.4.1 Frequency Output 11.4.2 outputs 11.4.3 inputs 11.4.4 Dual Port terminals
Program Memory
Data Memory
SRAM General Purpose Registers, Bytes Dual Port 5.3.1 access 5.3.2 External Write Access 5.3.3 Read Access from 5.3.4 Conflict handling 5.3.5 Register overview
Serial Port Interface
12.1 Basic features: 12.1.1 Overview: 12.1.2 terminal configuration 12.2 Functionality 12.2.1 Master Slave modes 12.2.2 data stream Output (Auto-Start) 12.2.3 Interruptions 12.2.4 edge synchronization selection 12.2.5 start-up 12.2.6 first selection 12.3 Registers overview:
Reset Controller
Basic features 7.1.1 Reset functions registers PowerCheck Reset PortA Input Reset BrownOut reset 7.5.1 Timings Watchdog 7.6.1 Watchdog counter 7.6.2 Lock/Unlock
Timers
13.1 Basic features: 13.2 Functionality 13.2.1 Auto-Reload mode 13.2.2 Zero-Stop mode 13.2.3 Start control system 13.2.4 Stopping timer 13.2.5 Clock selection 13.2.6 Frequency generation 13.2.7 16-bits configuration 13.2.8 Interrupts 13.3 Recommended programming order 13.4 Registers overview: 13.4.1 General configuration registers 13.4.2 Timer1 configuration 13.4.3 Timer2 configuration 13.4.4 Timer3 configuration 13.4.5 Timer4 configuration
Clock management
Basic features 8.1.1 Overview High frequency clock source 8.2.1 oscillator 8.2.2 High frequency external clock frequency clock source: 8.3.1 Crystal oscillator 8.3.2 frequency external clock 8.3.3 Data input OscOut Clock synchronization clock selection Peripheral clocks generation 8.6.1 Prescaler2 stages) 8.6.2 Prescaler1 stages) clock trimming with Xtal oscillator Registers overview
Interruptions
14.1 Basic features 14.2 Interrupt acquisition 14.2.1 Interrupt acquisition masking. 14.2.2 Interrupt acquisition Clearing 14.2.3 Register map, Interrupt acquisition 14.3 Interrupt Event handling 14.3.1 Interrupt priority 14.3.2 Status register 14.3.3 Status register pipeline exception 14.3.4 Processor vector table 14.3.5 Context Saving
Supply Voltage Level Detector (SVLD) Port
10.1 Basic features 10.1.1 Overview 10.1.2 Register map, functions 10.1.3 Operation 10.2 Port Interrupt requests 10.2.1 Debouncer 10.3 Reset Wake-up 10.3.1 Register Copyright 2005, Microelectronic-Marin
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EM6812
Memory mapping Typical dependencies
16.1 16.2 16.3 16.4 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 IVDD Currents SVLD, Detection levels drives Pullup Pulldown
Electrical Specification
Absolute Maximum Ratings Handling Procedures Standard Operating Conditions Typical Crystal specification Characteristics Power Supply Currents Characteristics Voltage detection levels78 Characteristics Oscillators Characteristics Pins Package drawings
Ordering information Flash device
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EM6812
Circuit Connectivity
EM6812 same pin-out both SO24 TSSOP24 package. Minimum connectivity includes power supply VDD, capacitor Vreg, de-coupling capacitance VDD. Circuit reference terminal (substrate) VSS. 32kHz Crystal only needed systems requiring frequency Crystal operation. integrated supply voltage regulator filters supply noise allows lowest power peripheral operations. proper operation, capacitor (470nF minimum) must connected regulator's VREG terminal. This terminal must used other outside connection. Figure Sample minimum connectivity
EM6812
Vreg
i.c.
Test
470nF
OscOut 32khz
OscIn Shield with
Reset Reset Button
Note: circuit IO's (except OscIn) level. OscIn terminal only used conjunction with quartz Crystal. terminal input voltages must never exceed Vreg voltage. quartz crystal should shielded with keep noise away. When using Crystal oscillator PA[7] PA[6] should preferably used static inputs only avoid noise coupling OscIn OscOut high impedance inputs.
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EM6812
Terminal usage
Table Circuit terminals Name Vreg OscOut Description Standard Standard Standard Standard Connect 470nF Main power supply Crystal, External Clock input, Data input OscIn Reset Test Crystal only connection Standard IRQ, timer start clock, Standard IRQ, timer start clock Standard IRQ, timer start clock Standard IRQ, timer start clock Standard IRQ, timer start clock Standard IRQ, timer start clock Standard IRQ, timer start clock Standard IRQ, timer start clock Reset input, active high with internal pull-down resistor test Program high Voltage note. i.c. Reference terminal ExtAdr[1] ExtAdr[0] ExtWEn ExtCen SCLK SOUT Dual Port Programming connections
DPRData[4] DPRData[5] DPRData[6] DPRData[7] SDIO SCLK
Used test purposes, internally connected. Must connected externally Standard drive Standard drive Standard drive Standard drive DPRData[0] DPRData[1] DPRData[2] DPRData[3]
Notes: Connection Test pin: Flash device, either connect 10kOhm resistor close possible pad) foresee jumper programming (VSS connection) Connection i.c. (i.c stands internally connected). This used test modes. external connection must made this pin.
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EM6812
Programming connections
EM6812 embedded Flash program memory programmed using standard microcontroller programmers available from parties. Programmers which currently support EM6812: ELNEC (SmartProg LabProg JetProg) updated list please consult: www.elnec.com
Erase/Write:The programmer allows erase/write whole program memory once (bulk erase). Typical erase time 20ms whole Flash memory. Erase immediately followed write (writing intruction after other). Typical write time 60µs/word. Code protection: program memory content read back, instead checksum (CRC) generated compared with programmer's value. Last Address read: very last address program memory read back. (code identification) Connection into connector goes TSSOP pin1 adapter needed TSSOP packages. On-board programming possible connecting programming terminals directly onto PCB. This done with connecting cable (not furnished) using on-board programming connector, which present some programmers. Figure On-board programming with DIL-adapter cable
Reset Test
programming interface terminals automatically configured input mode soon Test terminal goes high. This allows programmer download programming setup into circuit. soon valid programming mode recognized circuit will enter special state allow only Flash programming check done. During programming PortA configured output driving level, PB[4:0] input state, output.
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EM6812
SCLK
SDIO
Vreg
OscOut
OscIn
EM6812
Footprint Programmer
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EM6812
Operating modes
Figure Operating modes transition
Reset Reset Reset Reset Sleep Sleep
EM6812 main operation modes. Active Mode running, Instruction executing, Periphery clocked. Standby Mode stopped, Instruction execution, Periphery clocked. Sleep Mode reset, Instruction execution, Periphery stopped.
Wake-Up
Start-up
Within these operating modes different submodes exist with different clock selections allow lowest power consumption given cases. Please refer clockmanaging unit specific peripherals clock selections possibilities. When activated embedded peripherals clocked therefore unnecessary power consumption.
Reset IRQ, Event Standby Active HALT Instruction IRQ, Event Instruction execution
Table Mode dependent peripheral status Peripheral block Active mode Running defined frequency Clock source Running defined frequency SVLD Software selectable BrownOut Software selectable Prescalers Interrupts/ Events Possible Watchdog timer Software selectable Timer Software selectable Ports Software selectable Software selectable
Clock Clock
Standby mode Stopped Running defined frequency Software selectable Software selectable Possible Software selectable Software selectable Software selectable Software selectable Clock
Sleep mode Reset internal clock sources Disabled Disabled clock, retain value Wake-up only clock, retain value clock, retain value Retain state, input debouncers by-passed. Retains value
Active mode
active mode default mode after power-up. executes instructions after other. peripheral settings performed this mode before eventualy switching power modes. interrupt arriving will immediately next instruction branch into interrupt vector.
Standby Mode
standby mode commonly used power dissipation mode. During standby instruction execution halted peripheral circuitry still clocked. interrupt event will bring circuit back into active mode next active clock edge. Standby mode entered with HALT instruction.
Sleep Mode
This lowest power possible mode. Circuit operation stopped clock anymore) most peripheries retain their value. Exceptions are: debouncer circuits by-passed allow reaset wake-up. SVLD Brownout function disabled have minimum power dissipation. reset state. into sleep mode needs first SleepEn `1', then Sleep `1'. While SleepEn ='0' write Sleep bit. Resume from sleep mode either wake-up pre-specified port combination (refer 7.4) reset. Inspection reset status register allows determining restart origin.
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EM6812
System registers
Register name RegResStat RegSys1 RegSys2 Basic function Reset Flags identify reset source Sleep main oscillator settings, reset configuration High frequency clock selections, Xtal enable
Functions SleepEn Reset status Sleep mode external Resets selections Xtal clock selections
Table System registers
RegResStat
Name ResetPadFlag ResetWDFlag ResInpPAFlag ResBwnOutFlag SleepEn EnDebResPad CkDebResPad DatOscOut
0x12
0x10 Reset RegSysSlp ResSys Description Flag Reset terminal, clear write'0' Flag watchdog reset, clear write'0' Flag PortA input reset ,clear write'0' Flag also BrownOut case DisResInp='1' Flag BrownOut reset, clear write'0' Enables write Sleep Debounced reset input Direct reset input high speed clock (Pr1Ck[13], 8kHz) speed clock (Pr1Ck[8], 256Hz) Read data Oscout terminal XTAL
RegSys1 Name Sleep DisResetPad DisResInp FlagXtal OPTCldStart[1] OPTCldStart[0] FreqRange EnRC
Reset ResSys ResMain ResSys ResSys
Description circuit sleep mode Disable input reset Disable port reset input Xtal cold start flag, Xtal ready Xtal cold start duration: `00' `10' 3/4s, `01'=1/2s, `11'=1/4s. osc. frequency range selection: `1'=10MHz `0'=1MHz Enable oscillator
RegSys2 Name EnXtal SelExtHFck SelHFckSource SelExtLFck Sel32k RCDiv[1] RCDiv[0]
0x11
Reset ResMain ResMain ResMain ResMain -ResMain ResMain ResMain
Description Enable Xtal oscillator Enable external clock instead Select external clock '0', Enable external clock instead Xtal used, read always clock `1'=low freq (F1) `0'=high freq (F2) domain division factor `00'=1, `01'=2 `10'=4, `11'=8
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EM6812
Program Memory
instructions executed stored Program Memory, general-purpose data well peripheral registers values stored separate data memory (see chapter This special Harvard-RISC like architecture gives core ability read operands data memory simultaniously with instruction fetch. Maximum program memory size EM6812 22.5 kBytes. Each Instruction bits wide, which gives total 8192 Instruction words. Program Memory implemented Flash memory (EM6812-Fx). I.e. EM6812-F2 which contains instruction words. device delivered with different program memory sizes from 8192 down 2048 instruction words. Please refer ordering information section different memory types sizes.
Memory miss
unique Memory Miss feature CoolRISC products allows operating with high-speed peripheral clocks even voltage power supplys Memory Read Monitor memory miss) important feature ensuring correct program execution while allowing graceful performance reduction voltage conditions. access times memory cells dependent mainly supply voltage temperature. Figure showing general Figure Read Monitor funtion case were wait states automatically added depending actual power supply voltage. monitoring each program memory access assured that memory accesses good. necessary, wait- states will added. supply voltage reaches interrupt (PM_Miss_skip) generated signal that Memory Read Monitor will soon start adding wait states ensure accurate Full speed operation program execution. sure always running error free standard processor would have stop activity this point. Nearing critical timing Using this warning processor can, example, turn absolutely required functions reduce power supply load. Automatically adding processor starts automatically adding wait states wait states assure necessary ensure proper operation. processor will then error free functionality continue operate flawlessly power supply voltage level continues descend down Brownout voltage, this Brownout reset diagram. voltage falls number wait states will increase necessary assure that memory read correctly each Wait states access. Memory Read Monitor hardware function that uses actual memory cell standard takes into account factors that influence real memory read time memory array. works accurately combinations voltage, frequency temperature. This guarantees stable processor operation graceful performance reduction. addition Memory Read Monitor allows extending working range application from down without compromising operating security way. Figure Wait insertion versous Power supply voltage)
PM_Miss; Wait cycles insertion
MIPS
10MHz RCDiv=2
Wait Cycle insertion
Wait Cycle insertion
10MHz RCDiv=4 1MHz RCDiv=1
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Power Supply
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EM6812
program memory miss interrupt asserted long condition true. Above `Figure Wait insertion versous Power supply voltage) shows actual values memory miss interrupt generation. Typically Miss generated running system frequencies 2.5Mhz 10MHz RC_div=4) below Flash based circuits. While running RC=10MHz RCDiv=1 (5Mips) PM_Miss_skip interrupt triggered every Flash access. high frequency 5MHz clock needed peripheral blocks, user should mask PM_Miss_skip IRQ.
Table Memory miss interrupt generation Interrupt source Priority PM_Miss_skip
IntCtrl connection Int0[0]
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EM6812
Data Memory
data memory connected CoolRisc core 8-bit wide bi-directional data bus. contains: 512Bytes fully static Dedicated peripheral data registers timers ports, etc. Bytes general purpose registers. Bytes RAM, Bytes DPR) Table Data memory mapping Data Memory Address ranges 0x0257 Instr) 0x0157 Instr) SRAM Byte Instructions) Byte Instructions) 0x0060 Peripherals (Timers Ports, Configurations, Interfaces, etc) 0x0010 Dual Port 0x0000 Power Page (direct indexed addressing) Page Indexed addressing Description Data memory page
peripherals part SRAM accessible with addressing modes CoolRisc instruction set. portion SRAM, which Page addressed with indexed addressing modes.
SRAM
SRAM size adapted program memory size. Byte SRAM: Versions with Instruction Memory Byte SRAM: Versions with Instruction Memory. SRAM reset functions, therefore should initialized before storing variables. Table SRAM mapping Instructions Program Memory Version) Name Reset Bytes 0x015F 0x0100 0x00FF 0x0060 Indexed addressing
Bytes
Direct addressing
Table SRAM mapping Instructions Program Memory Version) Name Reset 0x025F Bytes 0x0100 0x00FF Bytes 0x0060
Indexed addressing
Direct addressing
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EM6812
General Purpose Registers, Bytes
total general purpose 8-bit registers available. these registers realized power store recall frequently accessed variables with minimum power whereas power saving realized minimizing parasitic capacitance which inherent large memories. other bytes shared with Dual Port function. These registers reset `00' only. Table General purpose register mapping Name Register Name LPRam0 Power (General purpose registers) LPRAM11 DPRam0 shared with Dual Port DPRam3
0000 0011 0012 0015
0x0000 0x000B 0x000C 0x000F
Direct indexed addressing
Dual Port (DPR)
memory block, which allows data, read write, accesses from either core external processor total asynchronous way. Dual Port external data mapped Port control signals Port occurrence possible access conflicts flagged with Interrupts. Priority given external access. Table Port mapping external connection ExtDat[7:0] ExtAddr[1:0] ExtWen ExtCen
Port mapping PB[7:0] PA[3:2] PA[1] PA[0]
Function External bi-directional data External address External write read access selector External chip enable, validates access
Setting EnDualRam register RegCfgPB enables function. still possible Port standard port even function enabled. Only while input ExtWen ExtCen high port forced output. other cases port configuration given defined port configuration registers. Please refer also port description. terminal configuration control inputs port totally free. Note: port terminals must left floating while EnDualRam='1'. integrated pull resistors drive conditions sure.
5.3.1
access
Read Write access performed same other general-purpose registers. special precautions need done long EnDualRam set. When EnDualRam set, conflicts with external access occur. Such conflicts flagged with interrupts CPU. Refer 5.3.4 Conflict handling. Table memory address mapping ExtAddr[1:0] Register Bit_Names port DPRam0 DPR0[7:0] DPRam1 DPRam2 DPRam3 DPR1[7:0] DPR2[7:0] DPR3[7:0]
Reset
Adr(Dec)
Adr(Hex) 0x0C 0x0D 0x0E 0x0F
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EM6812
5.3.2 External Write Access write access from external uses control signals ExtWen, ExtCen address signals ExtAddr[1:0] from port write value given port into location inside EM6812. Setting EnDualRam='1' RegCfgPB then configure port port allow external circuitry drive necessary control data lines operation. Figure DPR, Write into EM6812
ExtData[7:0] ExtAddr[1:0] ExtWen ExtCen cell @h000D
Data written into rising edge ExtCen. While ExtWen high selected address location write protected against writes.
5.3.3
Read Access from
Read access from external uses control signals ExtWen, ExtCen address signals ExtAddr[1:0] from port output addressed value port First necessary port configuration allow external circuitry drive input port. soon ExtCen becomes high (and ExtWen low) port will become output drive currently selected data value. Figure DPR, Read from EM6812
ExtData[7:0] ExtAddr[1:0] ExtWen ExtCen cell @h000D
While ExtCen high selected memory location write protected guarantee value read external device.
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EM6812
5.3.4 Conflict handling
external device always priority against read write operations. interrupts used flag occurrence possible conflicts. Conflicts only occur simultaneous access same memory location external device CPU. Table interrupt flags conflict handling operation Read Write Write External operation Write Read Write Conflict description, External write during read. External read during write Concurrent writes Interrupt signification data read corrupted write operation have failed write have failed. IrqDR[1] IrqDR[0]
Table interrupt mapping Interrupt source IrqDR[1:0]
Priority
Interrupt controller connection Int2[7:6]
5.3.5
Register overview
0x32 -0x0C 0x0D 0x0E 0x0F
Table registers RegCfgPB Name EnDualRAM EnSPI EnSig1 EnSig2 EnSig3 EnSig4 RegDPRAM0 Name DPR0[7:0] RegDPRAM1 Name DPR1[7:0] RegDPRAM2 Name DPR2[7:0] RegDPRAM3 Name DPR3[7:0]
Reset ResSys ResSys ResSys ResSys ResSys ResSys
Description Enable Dual Port Enable Serial Interface function Connecting internal Signal1 PB[0] Connecting internal Signal2 PB[1] Connecting internal Signal3 PB[2] Connecting internal Signal4 PB[3] Reads Reads
Reset
Description Dual port location
Reset
Description Dual port location
Reset
Description Dual port location
Reset
Description Dual port location
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EM6812
Core, CR816L
µProcessor Core CR816L true power RISC Core including `one instruction cycle' hardware multiplier. main features described below. bits RISC register-memory processor based Harvard architecture internal registers (Accu, general purpose, Index, offset, status) internal hardware multiplier stage pipeline architecture delay slots branch delays) Kbytes Program Memory size Kinstruction, wide) EM6812 uses Instruction Kbytes Data Memory size (organized kBytes pages) EM6812 uses Byte hardware subroutines unlimited software subroutines EM6812 uses subroutines different addressing modes direct addressing indexed addressing with immediate offset indexed addressing with register offset indexed addressing with post-incrementation offset indexed addressing with pre-decrementaion offset Table CR816L Instruction Mnemonic Instruction Addition. ADDC Addition with carry. Logical AND. CALL Jump subroutine. CALLS Jump subroutine, using return address. Unsigned compare. CMPA Signed compare. CMVD Conditional move, carry clear. CMVS Conditional move, carry set. CPL1 One's complementation. CPL2 Two's complementation. CPL2C Two's complementation with carry. Decrementation. DECC Decrementation with carry. HALT Halt mode selection Increment. INCC Increment with carry. Conditional jump. MOVE Data move. Unsigned multiplication. MULA Signed multiplication. operation. Logical index from hardware stack. PUSH Push index onto hardware stack. Return from subroutine. RETI Return from interrupt. SFLAG Save flags. Logical shift left. SHLC Logical shift left with carry. Logical shift right. SHRA Arithmetic shift right. SHRC Logical shift right with carry. SUBD Subtraction (op1 op2). SUBDC Subtraction with carry (op1 op2). SUBS Subtraction (op2 op1). SUBSC Subtraction with carry (op2 op1). TSTB Test bit. Logical exclusive Please refer CoolRISC 816L Microprocessor Core Hardware Software Manual Version dated 2002
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EM6812
Reset Controller
Basic features
Internal external reset sources handled within RESET controller. these reset used device defined state power-up, user request system exceptions. reset sources flagged, inspected after reset event allow detection reset source. Reset will keep reset state approx. 300µs once reset condition released. Internal sources Power Reset with powercheck start-up BrownOut detection voltage supervisory function Watchdog reset with protected disable External sources Reset (User reset) Input reset combination PortA these sources initialize re-initialize either whole part circuit. These sources are: Table Reset sources Function Signal Activated reset signals POR, ResMain, ResSys, ResSysSleep, ResCPU Reset DebResetPad ResMain, ResSys, ResSysSleep, ResCPU PowerCheck PwrCheck ResCPU Port Input Reset DebResInpPA ResSys, ResSysSleep, ResCPU Watchdog Reset ResetWD ResSys, ResSysSleep, ResCPU Brownout Reset BrownOut ResSys, ResSysSleep, ResCPU Sleep Sleep ResSysSleep, ResCPU After every reset circuit restart with clock 1MHz only clock selection. periphery released from reset after clocks (Reset synchronizer) clocks later (CPU Reset Delay). Figure Reset controller architecture
DebResetPad DisResetPad ResetWD BrownOut DebResInpPA DisResInp
ResSys ResCPU
ResMain Reset Synchronizer Flag Reset Source Reset Delay PwrCheck Sleep ResSysSlp ResCPU
ResSys
POR: initializes whole circuit; ResMain: initializes whole circuit except ResetPad configuration ResSys: initializes internal registers, does reset terminal configuration settings (I.e. pull resistors) ResSysSleep: Enables path able come sleep. ResCPU: Initializes Signals POR, ResMain, ResSys, ResSysSleep, ResCPU actual reset signals which initialize different latches registers. Please refer different register tables know reset source each register bit. Note: BrownOut reset will BrownOut flag also ResInpPA flag DisResInp set. power faster than BrownOut Filter (~10ms) Reset Flag will set. (allowing identification) case slow power both BrownOut ResPAInp flag will show. SleepEn (reset only) used distinguish between slow power `normal BrownOut condition.
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EM6812
7.1.1 Reset functions registers
Basic function Reset Flags identify reset source Direct debounced input debouncer clock selection Disable reset input Enabling Brownout function (default: Reset wake-Up system configuration, Combination mask selection Reset wake-up Watchdog setup keylock Table Reset register overview Functions Register name Reset status RegResStat RegResStat Reset configuration RegSys1 BrownOut RegAnaCfg RegCfgPA Reset input configuration RegMskRstWkUp Refer PortA description RegCmbKey RegWDkey Watchdog reset RegWDSys
Table Reset registers detail RegResStat 0x12 Name ResetPadFlag ResetWDFlag ResInpPAFlag ResBwnOutFlag SleepEn EnDebResPad CkDebResPad DatOscOut 0x10 0x3B
Reset ResSysSlp ResSys
Reset Flags determine reset source Description Flag Reset terminal, clear write'0' Flag watchdog reset, clear write'0' Flag PortA input reset ,clear write'0' Flag also BrownOut case DisResInp='1' Flag BrownOut reset, clear write'0' Enables write Sleep `1': Debounced reset input `0': Direct reset input `1': high speed clock (Pr1Ck[13], 8kHz) `0': speed clock (Pr1Ck[8], 256Hz) Read data Oscout terminal XTAL
RegSys1 Name Sleep DisResetPad DisResInp FlagXtal OPTCldStart[1] OPTCldStart[0] FreqRange EnRC
Reset ResSys ResMain ResSys ResSys
User reset handling Description circuit sleep mode Disable Input reset Disable port reset input Xtal cold start flag, XTal ready Xtal cold start duration: `00' `10' 3/4s, `01'=1/2s, `11'=1/4s. osc. frequency range selection: `1'=10MHz 0=1MHz Enable oscillator Watchdog setup register including lock Description Clear counterby writing =Reset; `0'=no action. Read always Enable watchdog `1'. word must loaded prior force EnWD='0' counter status, MSB-bit counter status LSB-bit Clock selection. Pr1Ck[0] (typ 1Hz) Pr1Ck[7] (typ 128Hz) Unlock work `111'
RegWDSys Name WDClear EnWD WDVal[1] WDVal[0] WDClkSel WDKeyLock[2] WDKeyLock[1] WDKeyLock[0]
Reset -ResSys ResSys ResSys ResSys ResSys ResSys ResSys
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EM6812
RegWDKey Name WDKey Watchdog register Description word allow software disabling watchdog `10010110' WDkey bits always read '00' valid WDKey WDKeyLock locked Reset ResSys R*/W 0x3C
RegAnaCfg Name EnSvld EnBrownOut SvldLevel1 SvldLevel2 SvldLevel3 SVLDStatus
0x20
Reset ResSys ResSys ResSys ResSys
BrownOut SVLD handling Description Enable SVLD function Enable Brownout function SVLD level selection levels)
Svld result SVLD Level SVLD Level
PowerCheck
power-up initializes whole circuit enables power check function. signal remains active keeps until supply voltage above VPOR (~1.5V). held reset state until power supply reaches power check level voltage VPWC (~2.05V) minimum arround 10ms after releasing. Power Check eliminating grey zone between VPOR VDDmin (2.0V) releasing system operation before minimal specified supply voltage reached. cell supervises regulated voltage observable VREG terminal. Vreg also supply voltage whole peripheral logic including core. Voltage regulator output impedance together with external capacitor VREG terminal form pass filter which protect core logic cell from noisy power supplies. Pulling VREG below VPOR voltage will also trigger event putting circuit reset state. Figure Power Check behavior
VPWC VDDmin
2.05 2.0V VREG 1.5V
time Check minimum around 10ms
Power phase, power reset Power check switched Noise filtered Vreg Large long drop VDD, Vreg terminal falls below VPOR voltage. power check initiated. Large short drop voltage. Vreg filter prevents initiate POR.
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EM6812
Reset
high level RESET terminal will trigger system reset. registers except ones connected will initialized with reset input. pull-down resistor connected this terminal. input debounced with either high frequency clock. This reset terminal disabled desired with DisResInp located RegSys1. default configuration reset input directly routed reset controller. Reset occurance flagged with ResetPadFlag register RegResStat. Write clear. Figure Reset terminal architecture
EnDebResPad
Reset
8kHz 256Hz
DebResetPad
Debouncer
ResSys
CkDebResPad
With debouncer, EnDebResPad `1', reset input signal must remain high during full debouncer clock cycle pass eventually create ResetPad signal. high frequency debouncing clocks issued from Prescaler1 (Pr1Ck[13], Pr1Ck[8]). selection performed with CkDebResPad register register RegResStat
PortA Input Reset
Single port input states port combinations defined trigger system reset. This function inhibited with DisResInp register RegSys1. Please refer chapter PortA input reset combination set-up. Reset occurance flagged with ResInpPAFlag register RegResStat. Write clear. ResInpPAFlag will also show case BrownOut reset when DisResInp `1'. Figure PortA input reset
EnDebResInp
PortA logic
ResInpPA
8kHz 256Hz
DebResInpPA
Debouncer
ResSys
CkDebResInp
ResInpPA signal, which output combination matrix, used debounced straight system reset. High debouncing clock frequencies selectable, both issued from Prescaler1 (Pr1Ck[13], Pr1Ck[8]). Debouncer clock selections performed with EnDebResInp CkDebResInp register RegCfgPA.
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EM6812
BrownOut reset
Figure BrownOut PowerCheck architecture
Vbat
BrownOut voltage supervisory function. monitors main power supply puts circuit reset state when supply drops below predefined value voltage (~2.05V). BrownOut enabled power EnBrownOut='1' automatically. Afterwards user switch brown function with EnBrownOut='0' register RegAnaCfg. During Sleep mode function temporarily disabled (most analog cells switched during sleep). After sleep mode brownout function which selected before sleep will reactivated. brown reset occurrence flagged with ResBwnOutFlag register RegResStat. Write clear this flag. BrownOut reset will also ResInpPAFlag when DisResInp `1'. brown voltage reached faster than Brown start-up delay time constant, then reset condition will flag. case lower speed start both ResBwnOutFlag ResInpPAFlag will show. user distinguish between initial `slow' power-up `normal' brown using SleepEN. This reset only. this case after re-start SleepEn ResBwnOutFlag set, then circuit coming from brown condition. SleepEn reset circuit comes from power-up condition. While Brownout function enabled circuit will draw additional ~6µA IVDD current (for Bandgap Comparator) modes except sleep mode.
PwrCheck
BROWN
Filter 30µs
Enable
BrownOut Start-Up delay 10ms
Sleep EnBrownOut
Figure SVLD consumption
[µA]
SVLD consumption adder IVDD=f(Temp) SVLD consumption adder IVDD=f(VDD)
[°C]
[µA]
7.5.1 7.5.1.1
Timings BrownOut Startup delay ~10ms
start-up delay allows integrated Bandgap reference Comparator stabilize after switching function. start-up delay switched after power-up (voltage rises above VPOR), setting EnBrownOut='1' resuming from Sleep mode. start-up delay independent current voltage. During whole start-up delay phase BrownOut reset will generated.
7.5.1.2
BrownOut Filter (~30µs)
BrownOut condition needs least approx. 30µs present initiate system reset. case VBAT undervoltage reaching VPOR, then starts operate approx. 330µs after voltage again above Re-start after BrownOut). undervoltage reaches switches function 1.5V), then BrownOut start-up delay described 7.5.1.1 applies addition meet powercheck voltage VPWC before able operate again.
7.5.1.3
Re-start after BrownOut (~330µs)
rising again above voltage will allow restart operation. However this restart delayed approx. 330µs (cold start delay, reset synchronization BrownOut Filter) Refer also Figure BrownOut PowerCheck architecture Note: Time constants based Prescaler2 clock output that closest to32kHz. takes into account prescaler clock selection, Oscillator frequency range divider settings. running external clock input time constants change accordingly input frequency clock management set-ups.
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EM6812
Watchdog
digital watchdog part integrated safety functions. main task supervise good firmware execution flow. such prevent being stuck unwanted endless loop allow system recovery other cases. implementation realised with speed counter, which asserts reset signal overrun. Watchdog reset flagged with ResetWDFlag register RegResStat. used localize reset source. Write clear. firmware must regularly clear watchdog otherwise watchdog reset will occur timer overrun, this watchdog reset will itself trigger system reset forces circuit restart. watchdog function always enabled after start-up after reset. watchdog configurable 128Hz clock sources (timeouts ~30ms) Secure watchdog disabling (locking) with special watchdog Reading watchdog counter value
7.6.1
Watchdog counter
clear watchdog counter firmware must write WDClear register RegWDSys. this bits counter reset watchdog restart from WDClear always read writing effect. recommended clear counter frequently I.e. every while working with counter clock source. Figure Watchdog timing diagram
WDClk0 WDVal[1:0] WDReset ResSys cold start System cold start
watchdog counter status accessible reading WDVal[1:0] RegWDSys. These bits accessible write mode. counter value disabled. With WDClkSel possible select from prescaler1 clock sources; Pr1Ck[0] (typ.1Hz) Pr1ck[7] (typ.128Hz), meaning that watchdog time respectively ~30ms. Changing prescaler1 input clock selection might also change watchdog counter frequency.
7.6.2
Lock/Unlock
possible disable watchdog save prevent that system malfunction itself inhibit Disabling needs follow strict protocol using lock bits which need confirmed with writing EnWD `0'. lock system WDKeyLock[2:0] RegWDSys allows software writing word WDKey register RegWDKey. possible write EnWD only when watchdog word been loaded. When watchdog disable, WDKey WDKeyLock must change; them modified EnWD written watchdog directly enabled. Note: EnWD written long valid lock number valid word set. When WDKeyLock valid number, WDKey reset changed.
Write valid lock number hex47 RegWDSys Write valid word hex96 register RegWDKey Disable writing register RegWDSys
Unlock (Disable watchdog)
Lock (Enable watchdog)
Locking clearing WDKeyLock. This action will automatically also clear WDKey EnWD bits.
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EM6812
Clock management
Basic features
EM6812 core peripherals several clock sources that involved same time. There main clock domains both them split sub-sources: High frequency clock sources oscillator 1MHz 10MHz base frequency External clock input from PA[4] PA[5] frequency clock source 32kHz Crystal oscillator (typical watch crystal) External clock input terminal CLKOUT instead crystal main features clock management system are: high frequency domain Fully internal oscillator. external component needed. Trimmable, continuous based frequencies from typically 75kHz 14MHz. Pre-Division factors Peripheral clocks available. Accurate frequency generation software using trim known timing. Automatic clock selection ~32kHz Prescaler1 Xtal available. Power saving switch case Oscillator used (i.e. Halt). frequency domain Lowest power watch type Crystal oscillator 32kHz. signal generation, division Prescaler1. interval interrupts CPU. both frequency domains High frequency clock domains fully synchronized working together. read registers thanks synchronization between both frequency domains. Completely free clock glitches, even when switching clocks while running. Fully synchronous core operations. clock prescalers (dividers) peripheral clock generation Independent clock selection both prescalers (high frequency domain).
8.1.1
Overview
Figure Clock management block diagram
SelExtHFck
PA[4] PA[5]
ExtHFck HFck
Pre-Divider
Peripheral clock selection
CkCPU Halt
CoolRISC
EnRc
EnXtal
8*F1
LFck
CkPeri_High_Freq
Prescaler1 Prescaler2
Pr1Ck[15:0]
Xtal OSCOUT
ExtLFck
SelExtLFck
Clock synchronization
CkPeri_Low_Freq
Pr2Ck[9:0]
Int0[3:1] (128Hz, 32Hz, 1Hz)
Note: When both frequency domains used, minimum frequency after pre-division (F2) should least times higher than maximum frequency (F1) allow proper system synchronization.
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EM6812
8.2.1 High frequency clock source oscillator
oscillator main clock generator high frequency domain. function based internal elements only. 8-bit trim register provided allow precise frequency adjustment based known timing functions (software Frequency Locked Loop FLL). switched default system startup after reset base frequency 1MHz. Pre-Divider which results peripheral clock frequency 125KHz (typ). Frequency range: 1MHz 10MHz. Selectable with FreqRange register RegSys1. Frequency division Selectable with bits RCDiv[1:0] register RegSys2. trimming: Range ~40%. Coded bits Trim[7:0] register RegTrimRC.
Figure Overlapping Oscillator trimming regions (75kHz 14MHz)
1MHz 10MHz
Pre-Divider
-40%
+40%
Pre-Divider
-40%
+40%
500kHz
5MHz
1MHz
250kHz
10MHz
2.5MHz
125kHz
Min. 75kHz(RC=1MHz) Max. 1.4MHz(RC=1Mhz)
1.25MHz
750kHz(RC=10MHz)
Max. 14MHz(RC=10Mhz)
Frequency after Pre-Division
Frequency after Pre-Division
user generate almost frequency from typ. ~75kHz ~14MHz continuously with combinations mentioned above. clock mainly depends selected frequency range, divider setting trimm value. Table Clock selection after Pre-Division (signal Figure oscillator FreqRange RegSys1 Divide RCDiv[1:0] 75kHz 175kHz Divide RCDiv[1:0] 150kHz 250kHz 350kHz Divide RCDiv[1:0] Divide RCDiv[1:0] Divide RCDiv[1:0]
oscillator FreqRange RegSys1 Divide RCDiv[1:0] Divide RCDiv[1:0] 3MHz 5MHz 7MHz Divide RCDiv[1:0] 6MHz 10MHz 14MHz
trimming: minimum frequency Trim[7:0] 300kHz 0.6MHz 0.75MHz 1.5MHz trimming: nominal frequency Trim[7:0] (default) 500kHz 1MHz 1.25MHz 2.5MHz trimming: maximum frequency Trim[7:0] 700kHz 1.4MHz 1.75MHz 3.5MHz
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EM6812
8.2.1.1 switch
oscillator switched save power consumption setting EnRC '0'. this state system clock must come from either frequency clock domain external high-speed clock input. While sufficient switch Oscillator setting EnRC '1', sufficient clear this switching oscillator will only stop peripheral circuitry (prescaler CPU) clock input selection. special case occurs during Halt mode. this state, will switched automatically until returns from Halt, either Reset. This automatic switch will take place prescalers have based clock active input clock. switch procedure (running XTAL): Enable Crystal oscillator, enabled, writing EnXtal register RegSys2. 2nd: Switch prescalers 32kHz Clock; Pr1CkSel[2:0]='000', AutoSel='1', Pr2CkSel='0' register RegPrCkSel Switch 32kHz operation; Sel32k ='1' register RegSys2 Once Crystal ready, Flag FlagXtal='1', disable oscillator with EnRC='0' register RegSys1
oscillator also switched when running high speed external clock (SelExtHFck='1' ENRC='0'). 8.2.2 High frequency external clock
possible external clock instead oscillator. There pads from Port which usable input clock. External clock selection performed with SelExtHFck clock source chosen with SelHFckSource, both register RegSys2. PA[4] SelHFckSource RegSys2 PA[5] SelHFckSource RegSys2 using these pads clock source, must configured input. Pull resistor selection remains available. Using loop function, external oscillator build using PA[4] clock clock switching based scheme shown Figure Synchronous Clock switching input.
8.2.2.1
Switching from external clock
glitch free clock-switching scheme implemented. Switch over procedure: 1st: writes clock selection change SelExtHFck 2nd: next falling edge current clock clock signal forced '0'. newly selected input will become clock source following falling edge. Figure Synchronous Clock switching
clock SelExtClk1 Clock
RC_osc Force clock
clock selection output will switchover clock next falling clock edge when initial selected clock been disabled. After switchover external clock, oscillator stopped save current consumption.
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EM6812
frequency clock source
Before switching frequency clock source, make sure that pre-devised high frequency clock least times higher than expected frequency clock. Once frequency clock running high frequency clock source stopped needed anymore. clock switching based scheme shown Figure Synchronous Clock switching. There several conditions which activate possible frequency clock sources, Crystal oscillator external clock. Crystal oscillator: EnXTAL Forces XTAL (must never XTAL present) Sel32k frequency clock source (F1) Pr1CkSel[2:0] `000' Prescaler running frequency clock source (F1) Pr2CkSel Prescaler running frequency clock source (F1) external clock: EnXtal SelExtLFCk `1': able external frequency clock, above condition must true before crystal oscillator selection conditions true. select frequency clock source this source present does vehicule clock.
8.3.1
Crystal oscillator
Xtal oscillator main clock generator frequency domain. default. Writing EnXtal register RegSys2 enables Xtal oscillator. Xtal management system waits defined number oscillation periods before allows using this source clock. This phase called Xtal cold-start. possible this wait time using OPTCldStart[1:0] RegSys1 between typically second. peripheral Crystal derived clocks blocked during cold-start (Prescaler inputs). This cold start time also active after every crystal oscillator re-start. Whenever peripheral block frequency clock selection external frequency clock (SelExtLFCk= `0') then crystal oscillator gets switched also even EnXtal `0'. Again every start-up crystal oscillator followed with cold-start period. avoid frequent cold start delays, permanantly switch Xtal with EnXtal='1'. Table Table Xtal cold-start duration selection. Number cold-start pulses Typical wait time 32768 24576 3/4s 16384 1/2s 8192 1/4s
OPTCldStart[1]
OPTCldStart[0]
During startup phase, check Xtal cold start done reading FlagXtal RegSys1. Xtal available clock source while FlagXtal `0'. After cold-start time, this flag becomes thus allows switchover. Note: Avoid high frequency operation fast transitions while 32kHz Crystal Oscillator running. induced crosstalk OscOut terminal (PCB, Package) influence good Crystal operation.
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EM6812
8.3.2 frequency external clock
frequency external clock coming from OscOut terminal used replace Xtal oscillator. SelExtLFck RegSys2 controls selection between Xtal external clock. same glitch-free clock switching scheme shown Figure Synchronous Clock switching implemented. While running external frequency clock, cold start delay does apply FlagXtal forced `1'. Also OscOut input must always driven. frequency external clock selection: SelExtLFck EnXtal '1'. SelExtLFck EnXtal '0'. SelExtLFck EnXtal '0'. Xtal oscillator selected. external clock selected. active frequency clock input (default state startup)
possible have Xtal frequency clock active same time since both share same circuit terminal OscOut. crystal oscillator must disabled EnXtal='0' allow external frequency clock input. With EnXtal='1' external clock input blocked. frequency external clock OscOut terminal only selected crystal oscillator active. Therfore EnXtal must `0', Sel32k `0', Pr1CkSel[2:0] equal `000' Pr2CkSel='1' prior setting SelExtLFCk `1'.
8.3.3
Data input OscOut
OscOut terminal status read when Crystal Oscillator used (EnXtal='0'). reading performed with read access DatOscOut register RegResStat. OscOut input internal pull resistor. left floating while used.
Clock synchronization
Besides already described clock synchronization schemes between internal external clocks their respective frequency domain, EM6812 re-synchronizes internally asynchronous clocks (see `Figure Clock management block diagram') periphery always stable clock edge conditions. implementation done synchronization frequency clock (F1) with higher speed clock (F2). proper operation rule applies. active peripheral clock edge issued from will never occur during read write cycle thus allows manage peripherals while they quiet state. Note that this does apply peripherals, which asynchronous clock that been re-synchronized (i.e. undebounced timer clock sources). Maximum peripheral clock selection half high frequency pre-divided clock.
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EM6812
clock selection
high frequency frequency clock domain. clock selection peripheral clock selection independent. Xtal cold-start finished external clock selected, cannot switch clock domain, continuous clock domain until cold-start time. Sel32k RegSys2 controls clock selection: Sel32k `0'. runs clock domain. Sel32k `1'. runs clock domain. this case prescalers must also with clock (either Pr1CkSel='000' Pr2CkSel='0') Internal external clock sources chosen within both high frequency clock domains. clock switching based scheme shown Figure Synchronous Clock switching.
Peripheral clocks generation
There prescalers dedicated peripheral clocks input clock either issued from high frequency domain. Their default setup Prescaler2: 10-stages clock division; pre-division results 62.5kHz prescaler input clock. Prescaler1: 15-stage divider, `auto selected' close 32kHz input clock coming from prescaler2. Each prescalers most significant read reset.
Figure Prescaler clock selection architecture
FreqRange RcDiv[2:0] AutoSel Pr1CkSel[2:0]
Clock Selector
Int0[3:1] (128Hz, 32Hz, 1Hz)
Pr1CkSource
Prescaler stage divider)
Pr1Ck[15:0]
PrCk2[9:3]
DataBus
Pr2Ck[9:0]
CkPeri_Low_Freq CkPeri_High_Freq Pr2CkSource
Prescaler stage divider)
Pr2CkSel
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EM6812
8.6.1 Prescaler2 stages)
prescaler selectable clock sources possible. default running oscillator. Pr2CkSel `0': clock domain (F1: Xtal oscillator external clock). Pr2CkSel `1': clock domain after pre-division (F2) divided oscillator external clock) F2/2. Pr2CkSource clock source prescaler2. different clocks from prescaler2; Pr2Ck[9:0]. shaded values selected prescaler1 clock input case autoselect active frequency. clock duty cyles expecpt Pr2CkSource which high issued from high frequency input clock. Table Prescaler2 output frequencies when running clock domain (CkPeri_High_Freq) Prescaler2 output Oscillator Pre-Division Pr2CkSource (Duty: high) Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource 1024 10MHz F2/2 5MHz 2.5MHz 1.25MHz 625kHz 313kHz 156kHz 78kHz 39kHz 20kHz 10kHz 5kHz 10MHz F2/2 2.5MHz 1.25MHz 625kHz 313kHz 156kHz 78kHz 39kHz 20kHz 10kHz 5kHz 2.4kHz 10MHz F2/2 1.25MHz 625kHz 313kHz 156kHz 78kHz 39kHz 20kHz 10kHz 5kHz 2.4kHz 1.2kHz 10MHz F2/2 625kHz 313kHz 156kHz 78kHz 39kHz 20kHz 10kHz 5kHz 2.4kHz 1.2kHz 610Hz 1MHz F2/2 500kHz 250kHz 125kHz 62.5kHz 31.3kHz 15.6kHz 7.8kHz 3.9kHz 2.0kHz 1.0kHz 500Hz 1MHz F2/2 250kHz 125kHz 62.5kHz 31.3kHz 15.6kHz 7.8kHz 3.9kHz 2.0kHz 1.0kHz 500Hz 250Hz 1MHz F2/2 125kHz 62.5kHz 31.3kHz 15.6kHz 7.8kHz 3.9kHz 2.0kHz 1.0kHz 500Hz 250Hz 125Hz 1MHz F2/2 62.5kHz 31.3kHz 15.6kHz 7.8kHz 3.9kHz 2.0kHz 1.0kHz 500Hz 250Hz 125Hz 62Hz
Pr2Ck[9] Pr2Ck[8] Pr2Ck[7] Pr2Ck[6] Pr2Ck[5] Pr2Ck[4] Pr2Ck[3] Pr2Ck[2] Pr2Ck[1] Pr2Ck[0]
prescaler2 clock values, MSB's, Pr2CkStatus[7:0] read register RegPr2Status. These most significative bits cleared simple write operation value RegPr2Status register. Pr2Ck sources used input clock sources several other peripheries (SPI, Timers, Prescaler1, etc). Clearing MSB's therefore influence proper operation these peripheries. Table Prescaler2 output frequencies when running clock domain (CkPeri_Low_Freq) Signal name Division Presacler output frequency case XTAL 32kHz active frequency clock Pr2CkSource Pr2Ck[9] Pr2Ck[8] Pr2Ck[7] Pr2Ck[6] Pr2Ck[5] Pr2Ck[4] Pr2Ck[3] Pr2Ck[2] Pr2Ck[1] Pr2Ck[0] Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource Pr2CkSource 1024 32768Hz 16384Hz 8192Hz 4096Hz 2048Hz 1024Hz 512Hz 256Hz 128Hz 64Hz 32Hz
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8.6.2
Prescaler1 stages)
clock input selections from Xtal Prescaler2 clocks. real time clock function case 32kHz Xtal input. `Autoselect' close 32kHz input clock selection from prescaler2 case Xtal. autoselection based oscillator settings (FreqRange RCDiv) switched with AutoSel register RegPrCkSel. case active frequency clock selection (Xtal external frequency enabled) autoselect will select frequency input prescaler clock source. clock switching based scheme shown Figure Synchronous Clock switching.
Table Table Prescaler1 automatic clock selection from prescaler2. (AutoSel `1', Pr2CkSel ='1') FreqRange RCDiv Pr2CkSource Pr2Ck[9:0] selected Pr1CkSource, AutoSel 5MHz 39.1kHz 2.5MHz 39.1kHz 1.25MHz 39.1kHz 625kHz 39.1kHz 500kHz 31.3kHz 1MHz 250kHz 31.3kHz 125kHz 31.3kHz 62.5kHz 31.3
frequency clock gets automatic selected Pr2CkSource case Autosel Pr2CkSel `0'. prescaler1 clock values, MSB's, Pr1CkStatus[7:0] read register RegPr1Status. These most significative bits cleared simple write operation value RegPr1Status register. Pr1Ck sources used input clock sources several other peripheries (SPI, Timer, etc). Clearing MSB's therefore influence proper operation these peripheries. also possible select specific prescaler1 input clock source setting AutoSel=`0'. selection done with bits Pr1CkSel[2:0] register RegPrescCkSel. Table Prescaler1 clock selection, non-automatic mode. (AutoSel `0') Pr1CkSel[2:0] Clock selected case Pr2CkSel='1' (high freq.) Oscillator (default) frequency clock domain (Xtal ExtLFck) Prc2Ck[3], refer Table Prc2Ck[4], refer Table Prc2Ck[5], refer Table Prc2Ck[6], refer Table Prc2Ck[7], refer Table Prc2Ck[8], refer Table Prc2Ck[9], refer Table Clock selected case Pr2CkSel='0' (low freq.) with 32kHz Crystal frequency clock domain (Xtal ExtLFck) Prc2Ck[3] 16384Hz Prc2Ck[4] 8192Hz Prc2Ck[5] 4096Hz Prc2Ck[6] 2048Hz Prc2Ck[7] 1024Hz Prc2Ck[8] 512Hz Prc2Ck[9] 256Hz
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EM6812
Table Prescaler1 output clock frequencies based selected input clock source. XTAL Prescaler1 output Pr2Source AutoSelect based 10MHz Pre-Div. (10MHz) Highest value Pr1CkSource frequency Pr1Ck[14] Pr1Ck[13] Pr1Ck[12] Pr1Ck[11] Pr1Ck[10] Pr1Ck[9] Pr1Ck[8] Pr1Ck[7] Pr1Ck[6] Pr1Ck[5] Pr1Ck[4] Pr1Ck[3] Pr1Ck[2] Pr1Ck[1] Pr1Ck[0] 1024 2048 4096 8192 16384 32768 32kHz 16kHz 8kHz 4kHz 2kHz 1kHz 512Hz 256Hz 128Hz 64Hz 32Hz 16Hz Pr2cK auto ~32kHz ~16kHz ~8kHz ~4kHz ~2kHz ~1kHz ~512Hz ~256Hz ~128Hz ~64Hz ~32Hz ~16Hz ~8Hz ~4Hz ~2Hz ~1Hz Pr2ck[9] 2.5MHz 1.25MHz 625kHz 313kHz 156kHz 78kHz 39kHz 20kHz 10kHz 5kHz 2.4kHz 1.2kHz 600Hz 300Hz 150Hz 75Hz Pr2ck[9:3] 1.25Mhz 500Hz 625KHz 500Hz 313kHz 250Hz 156kHz 125Hz 78kHz 62Hz 39kHz 31Hz 20kHz 16Hz 10kHz 5kHz 2.4kHz 1.2kHz 600Hz 0.5Hz 300Hz 0.25Hz 150Hz 0.125Hz 75Hz 0.062Hz 38Hz 0.031Hz Clock Pre-Division F2:12 intermediate values from Pre-Div. Xtal 32kHz
Pr1CkSource origin
Xtal
(125kHz) Xtal from Lowest value Pr2Ck[3] 500Hz 250Hz 125Hz 62Hz 31Hz 16Hz 0.5Hz (2s) 0.25Hz (4s) 0.125Hz (8s) 0.062Hz (16s) 0.031Hz (32s) 0.016Hz (64s) Pr2Ck[3] 256Hz 128Hz 64Hz 32Hz 16Hz 0.5Hz (2s) 0.25Hz (4s) 0.125Hz (8s) 0.062Hz (16s) 0.031Hz (32s) 0.016Hz (64s) 0.008Hz (128s)
clock trimming with Xtal oscillator
oscillator trimmed precise frequency using either internal 32kHz Xtal based frequencies other known timing reference. base frequencies oscillator trimmable 40%, combining trimming frequency divider gives total overlapping frequency regions with each possible frequencies. also Figure frequency precision within 75kHz 10MHz range better than 0.5%. Repeating frequency adjustment regularly allows compensating slow voltage temperature changes. trim value obtained successive approximation using timer count clock during given timing period (i.e. prescaler interrupts), then change trim value based timer result until result within desired precision window. also Application note trimming.
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EM6812
Registers overview
Table Clock management registers RegSys1 0x10 Name Sleep DisResetPad DisResInp FlagXtal OPTCldStart[1] OPTCldStart[0] FreqRange EnRC 0x11 0x15
Reset ResSys ResMain ResSys ResSys
Description circuit sleep mode Disable input reset Disable port reset input Xtal cold start flag, Xtal ready Xtal cold start duration: `00' `10' 3/4s, `01'=1/2s, `11'=1/4s. osc. frequency range selection: `1'=10MHz `0'=1MHz Enable oscillator
RegSys2 Name EnXtal SelExtHFck SelHFckSource SelExtLFck Sel32k RCDiv[1] RCDiv[0] RegPr1Status Name Pr1CkStatus[7:0]
Reset ResMain ResMain ResMain ResMain -ResMain ResMain ResMain
Description Enable Xtal oscillator Enable external clock instead Select external clock '0', Enable external clock instead Xtal used, read always clock `1'=low freq (F1) `0'=high freq (F2) domain division factor `00'=1, `01'=2 `10'=4, `11'=8
Reset ResSys
R/C*
Description Prescaler1 Clock status
RegPr2Status 0x16 Name Reset Pr2CkStatus[7:0] ResSys R/C* Write access resets register value counter values) RegTrimRC Name Trim[7:0] RegPrCkSel Name Pr1CkSel[2] Pr1CkSel[1] Pr1CkSel[0] AutoSel Pr2CkSel -0x13 0x14
Description Prescaler2 Clock status
Reset ResMain
Description oscillator trimming byte
Reset ResSys ResSys ResSys ResSys ResSys
Description Refer Table Prescaler1 clock selection, non-automatic mode Auto prescaler1 clock selection ~32kHz Prescaler2 clock selection `0'=low freq (F1), 1=high freq Read always Read always Read always
Table Clock interrupts mapping Interrupt source Pr1Ck[0] (1Hz Xtal) Pr1Ck[5] (32Hz Xtal Pr1Ck[7] (128Hz Xtal)
Priority
IntCtrl connection Int0[1] Int0[2] Int0[3]
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EM6812
Supply Voltage Level Detector (SVLD)
EM6812 built level supply voltage detector that compares supply voltage against predefined voltage level. inspect result comparison, reads supply voltage higher than compare level lower. lowest compare level equivalent brown detection level. Obviously this level only measured brown function switched off. Also SVLD function temporarily disabled during Sleep mode. internal bandgap reference shared between SVLD BrownOut function. active, will consume extra ~6µA during whole measuring time Figure SVLD architecture
SVLDLevel selector
Level8 Level7 Level6 Level5 Level4 Level3 Level2 Level1
SVLDResult
Timings: Internal voltage reference settling time: (From either EnSVLD='1' EnBrownOut='1'). Must respected when voltage reference gets switched Comparator settling time: 10µs (From EnSVLD='1' readout) Must respected every measure before reading result.
Vref 1.2V EnSVLD EnBrownOut
Table Analogue configurations register RegAnaCfg 0x20 Name Reset EnSVLD ResSys EnBrownOut SVLDLevel1 SVLDLevel2 SVLDLevel3 SVLDStatus ResSys ResSys ResSys
Table SVLD selection table SVLDLevel3 SVLDLevel2
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EnSVLD
BrownOut EnBrownOut
Analogue configurations Description Enable SVLD function Enable Brownout function SVLD level selection levels)
SVLD result SVLD Level SVLD Level
SVLDLevel1
Typical Detection Level
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EM6812
Port
10.1 Basic features
port 8-bit general-purpose input/output port. read input state modes. selections concerning port bit-wise executable: Bit-wise executable PA[0] PA[7]: Input Output selection CMOS Open Drain Outputs Interrupt with rising falling edge selection, direct debounced. Pull resistor selection. Pull-up Pull-down. When both selected, pull-up priority. Special features Input reset wakeup capabilities input pattern single External system clock input PA[4] PA[5] Oscillation Loop PA[6] PA[4] Timer clock start stop inputs. Dual Port Control signals PA[0] PA[3]
Table Port External Connectivity Port input connectivity output
Enable with bits MskIRQPA[7:0]
Enable with SelExtClk1
Enable with RCLoop
Always active
Enable with EnDualRAM
Enable with corresponding Timer configuration bits
input
External Interrupt IRQPA[7]
External system clock
Oscillati Loop
Dual Port
Timer1
Timer2
Timer3
Timer4
Output drive Drive
PA[7]
Start[7]
Start[7]
Start[7]
Start[7] Clk[1]
PA[6]
IRQPA[6]
RCOut
Start[6]
Start[6]
Start[6] Clk[1]
Start[6]
Drive
PA[5]
IRQPA[5]
ExtClk1
Start[5]
Start[5] Clk[1]
Start[5]
Start[5]
Drive
PA[4] PA[3] PA[2] PA[1] PA[0]
IRQPA[4] IRQPA[3] IRQPA[2] IRQPA[1] IRQPA[0]
ExtClk1
RCIn ExtAdr[1] ExtAdr[0] ExtWEn ExtCEn
Start[4] Clk[1] Start[3] Start[2] Start[1] Clk[0]
Start[4]
Start[4]
Start[4]
Drive Drive Drive Drive Drive
Start[3] Start[2] Clk[0] Start[1]
Start[3] Clk[0] Start[2] Start[1]
Clk[0] Start[3] Start[2] Start[1]
These input connections remain active also corresponding terminal configured output.
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10.1.1 Overview
Figure Port pull selection
RegInPA RegOpenDrainPA RegIOSelPA RegOutPA
[7:0]
PAIn
PAIn input Vbat 100k RegPullUpPA interrupts reset wake-up timer clock, start-stop external clock Dual Port control RegPullDownPA Oscillation Loop
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10.1.2 Register map, functions
Table Port Registers overview Functions Register name RegInPA Base RegOutPA RegIOSelPA RegPullUpPA Pull resistor RegPullDownPA open drain RegOpenDrainPA RegIntEdgPA related RegEnDebPA Reset Wake-up Reset Wake-up Table Port Registers RegInPA Name PAIn[7:0] RegCfgPA RegMskRstWkUp RegCmbKey Basic function Direct read input terminal state Data output register Direction selection Pull-up resistor selection Pull-down resistor selection Enable n-channel open drain output Interrupt edge selection Debouncer selection interrupt signal Reset wake system configuration, Oscillation Loop selection Combination mask selection Reset wake-up
0x21
Reset
Input register Description Direct read input terminal state `0'=read low, `1'= read high Output data Description Data output register `0'= output low, `1'=output high Direction setting Description Direction selection; `1'=Output, `0'=Input Pull-up selection Description Pull-up resistor selection `0'=no pull-up, `1'=pull-up enabled Pull-down selection Description Pull-down resistor selection `0'=no pull-down, `1'=pull-down enabled pullup) N-channel Open drain selection Description N-channel open drain selection output) `0'=CMOS mode, `1'= open drain enabled
RegOutPA Name OutPA[7:0]
0x22
Reset ResSys
RegIOSelPA Name IOSelPA[7:0]
0x24
Reset ResSys
RegPullUpPA Name PullUpPA[7:0]
0x2A
Reset ResMain
RegPullDownPA Name PullDownPA[7:0]
0x2B
Reset ResMain
RegOpenDrainPA Name OpenDrainPA[7:0]
0x29
Reset ResMain
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10.1.3 Operation
Port input terminal status always read directly. registers influencing modes bit-wise selectable. integrated switchable pull resistors selectable output drive mode allow maximum different terminal modes. Refer Table Port mode details. default state after power terminals input mode with pull-down resistor. Table Port modes OpenDrainPA[i]
PullDownPA[i]
Modes
PA[i] terminal
PullUpPA[i]
IOSelPA[i]*
Notes
OutPA[i]
Input mode Input mode with pull-up Input mode with pull-down Output mode, CMOS high drive Output mode, CMOS drive Output mode, open drain, high-Z Output mode, open drain with pull-up Output mode, open drain drive
High-Z Weak Weak High-Z Weak
Needs external drive (PA[i] must never floating) Pull-up priority over pull-down Default state after Power-up Pull resistors disabled Pull resistors disabled Pull-down disabled Needs external drive (PA[i] must never floating) Pull-up active Pull-up disabled
Note: Every port input always needs least driver. floating input generate hazards induce cross current input amplifier. Note: Avoid high frequency operation fast transitions while 32kHz Crystal Oscillator running. induced crosstalk OscOut terminal (PCB, Package) influence good Crystal operation.
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10.2 Port Interrupt requests
Each port input interrupt request source active rising falling edge corresponding individual IntEdgPA setting. interrupt source debounced direct, bit-wise selection with EnDebPA. Figure Schematic view Debouncer Edge selection
PAIn
Debouncer function
IRQPA[i]
CkDebPA
ResSys EnDebPA[i] IntEdgPA[i]
Table Port Registers Debouncer Interrupts RegIntEdgPA 0x27 Name Reset IntEdgPA[7:0] ResMain
Debouncer edge selection Description interrupt edge selection; 0=falling, 1=rising Debouncer selection Description interrupt debouncer selection 0=direct, 1=debounced Pr1Ck[8] (256Hz).
RegEnDebPA Name EnDebPA[7:0]
0x28
Reset ResSysSlp
Table Port Interrupt mapping Interrupt source IRQPA[7:0]
Priority
IntCtrl connection Int1[7:0]
10.2.1 Debouncer
debouncer selected corresponding input signal must remain stable during full debouncer clock cycle pass eventually create interrupt request. recommended debouncer functionality port interrupt inputs. debouncer frequency CkDebPA coming from prescaler1, Pr1Ck[8] (256Hz). Minimum input pulse length pass debouncer: Pulse length smaller debouncer clock period Pulse length in-between debouncer clock periods Pulse length grater than debouncer clock periods:
Pulse does pass (filtered out) Pulse pass Pulse always passes
Note: debouncer output reset with signal ResSys. second debouncer clock edge after reset generated. interrupt mask overcome this. Note: Changing RegIntEdgPA result transition interpreted valid IRQ. Avoid masking while changing edge selection.
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10.3 Reset Wake-up
Port input comparison register detect incoming reset and/or wakeup condition. compare match with defined pattern, selected functionality will activated. When working inputs, only reset wake-up function active. With input split time's 4-pin input, reset wake-up functions used simultaneously. this case, upper bits attached reset lower wake-up. `don't care' condition allows masking specific inputs their state taken into account. reset wake-up signal individually debounced. input reset function disabled with DisResInp register RegSys1 (Reset section). Table Port Reset wake-up selection
Wk_nRes SplitCmb
Description PAIn[7:4] used reset function. PAIn[3:0] used wake function. PAIn[7:0] used reset function. (default) PAIn[7:0] used wake-up function.
Figure Reset Wake-up diagram
Excl_nComb MskRstWkUp PAIn CmbKey MskRstWkUp(0) MskRstWkUp(1) MskRstWkUp(2) MskRstWkUp(3) match
EnDebResInp
ResInpPA
MskRstWkUp(0) PAIn(0) CmbKey(0) MskRstWkUp(1) PAIn(1) CmbKey(1) MskRstWkUp(2) PAIn(2) CmbKey(2) MskRstWkUp(3) PAIn(3) CmbKey(3) MskRstWkUp(4) PAIn(4) CmbKey(4) MskRstWkUp(5) PAIn(5) CmbKey(5) MskRstWkUp(6) PAIn(6) CmbKey(6) MskRstWkUp(7) PAIn(7) CmbKey(7) Excl_nComb SplitCmb Wk_nRes
Comp mask Comp mask Comp mask Comp mask Comp mask Comp mask Comp mask Comp mask
DebResInpPA
match(0)
MskRstWkUp(4) MskRstWkUp(5) MskRstWkUp(6) MskRstWkUp(7) SplitCmb
8kHz 256Hz
Debouncer
match(1)
CkDebResInp
ResSys
match(2)
match(3)
match(4)
match(5)
EnDebWk
WakeUp
DebWakeUp
match(6)
8kHz 256Hz
Debouncer
match(7)
CkDebWk
ResSys
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10.3.1 Register
Table Port Reset wake-up registers RegCfgPA 0x23 Name Reset Excl_nComb ResMain Wk_nRes SplitCmb EnDebResInp CkDebResInp EnDebWk CkDebWk RCLoop ResMain ResMain ResSysSlp ResMain ResSysSlp ResMain ResSys Configuration settings reset wake-up system. Description Mode selection reset wake-up system `0'=Input combination, `1'=Individual action Selects either reset wake-up function `0'=Reset, `1'=Wake-up (has action SplitCmb=0) PA[7:4] Reset combination PA[3:0] Wake-up combination `0'=full port `1'=port split, Enable reset debouncer function `0'=No debouncer, `1'= debouncer enabled Select reset debouncer clock `0'=Pr1Ck[8] (256Hz); `1'=Pr1Ck[13] (8kHz) Enable wake-up debouncer function `0'=No debouncer, `1'= debouncer enabled Select wake-up debouncer clock `0'=Pr1Ck[8] (256Hz); `1'=Pr1Ck[13] (8kHz) Enable Loop PA[6], PA[4] `0'=RC Loop disabled, `1'= Loop enabled Input mask reset wake-up selection Description Input selection reset wake-up system 1=input selected, care Reset Wake-up definition Description Reset wake-up 0=match 1=match
RegMskRstWkUp Name MskRstWkUp[7:0]
0x26
Reset ResMain
RegCmbKey Name CmbKey[7:0]
0x25
Reset ResMain
10.3.2 Input splitting
Both reset wake-up functions activated port split parts. PA[7:4] gets reset function PA[3:0] wake-up. With SplitCmb='0' split port only function defined Wk_nRes active.
10.3.3 Actions
Resetting microcontroller condition match. Wake-up signal microcontroller condition match. Reset will trigger system reset (ResSys) Wake-up will resume from unclocked power modes. main actions are: Halt mode: Sending Event (resumes from HALT mode back active mode). Refer Interrupt section. Wake-up will activate signal DebWakeUP give CPUEvent0. Sleep mode: Cancel Sleep mode (resets Sleep bit, restarts from
10.3.4 Condition match
match condition obtained either selected bits match (AND-function Combination trigger) least selected bits match input status (OR-function Exclusive trigger). Combination (AND-Type): input, bit, need fully match corresponding combination pattern, except `don't care' bits trigger reset and/or wake-up. Exclusive (OR-Type): least combination matching selected input status will trigger reset and/or wakeup inhibited `don't care' condition.
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10.3.5 Don't care bits
don't care function provided that input status only taken into account corresponding mask selection set. Special: relevant bits function `don't care', then this function inhibited.
10.3.6 Debouncer
Reset Wake-Up signal have debouncer selection with either fast speed clock. debouncer selected, corresponding input signal must remain stable during full debouncer clock period pass. sleep mode clock) debouncer automatically by-passed. debouncer clock coming from prescaler1, either Pr1ck[8] (256Hz) Pr1ck[13] (8kHz) selected with CkDebWk wake-up CkDebRes reset function. Note: avoid detection spikes input mask changes strongly encouraged always selecting debouncer functionality.
10.4 Oscillation Loop
terminals PA[6] (RCOut) PA[4] (RCIn) simple oscillation system made using external components (i.e. oscillator with resistor from, PA[6] PA[4] capacitor from PA[4] VSS). Oscillation loop configured with RCLoop RegCfgPA. With RCLoop inverted PA[4] input value output PA[6]. input schmitt-trigger levels give oscillation signal PA[4]. correct operation PA[6] needs configured output PA[4] input. Refer Table Port mode. Figure Port oscillation loop
PAIOSel[6] RCLoop OutPA[6]
PA[4], PA[6] Signal flow
Rext Input high threshold
PAIn[4] Cext
Input threshold
internal
external
10.4.1 Inverter function
oscillation loop also used signal inverter. signal connected PA[4] will feed inverted PA[6] RCLoop set.
10.5 Dual Port interface
control signals addresses embedded dual port mapped port Refer Table Port External Connectivity. involved port terminals must input mode. Pull selection will active specified Table Port mode. Please refer chapter Dual Port full description.
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Port
11.1 Basic features
port 8-bit general-purpose input/output port. read input state modes. selections concerning port bit-wise executable PB[0] PB[7]. These are: Input Output selection CMOS Open Drain Outputs Pull resistor selection. Pull-up Pull-down. When both selected, pull-up priority. Special features serial port interface Frequency outputs Timer Frequency generation Divided Crystal oscillator frequencies Dual Port data Table Port External Connectivity
Port output connectivity
Direction selection normal function depending OutEn bits output settings with corresponding EnSig[n] direction settings with EnSPI terminals
Signal1 selection PB[3:0] with EnSig
output with EnDualRAM
Sig1Sel[1:0] selects special output source PB[0]
ExtWEn
Sig2Sel[1:0] selects special output source PB[1] Sig3Sel[1:0] selects special output source PB[2] Sig4Sel[1:0] selects special output source PB[3]
ExtCEn
PortB PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0]
Normal Output PBOut[7] PBOut[6] PBOut[5] PBOut[4] PBOut[3] PBOut[2] PBOut[1] PBOut[0]
Serial Interface
Freq Output
Dual Port DPData[7]
output
SigXSel[1,0] `00'
SigXSel[1,0] `01'
SigXSel[1,0] `10'
SigXSel[1,0] `11'
Output drive Drive Drive
input
SOUT
output
SCLK
DPData[6]
output
DPData[5]
output
Drive Drive
input/o utput
Signal4 Signal3 Signal2 Signal1
DPData[4]
output
DPData[3]
output
PWM4 PWM3 PWM2 PWM1
PWM3 PWM4 PWM1 PWM2
Pr1Ck[11] Pr2CkSource Pr1Ck[11] Pr2CkSource
Pr1Ck[0] Pr1CkSource Pr1Ck[0] Pr1CkSource
Drive Drive Drive Drive
DPData[2]
output
DPData[1]
output
DPData[0]
output
11.1.1 Special function priority handling
Highest priority Dual Port function which takes full control output when externally accessed read mode (EnDualRAM='1', ExtCEn='1', ExtWEn='0'). Second priority Serial interface settings Frequency outputs. serial interface selection with EnSPI automatically configures SIN, SOUT SCLK terminals. same priority level also Frequency outputs. soon EnSig bits written corresponding terminal becomes output. Last priority normal mode data output with PBOut[n] direction with IOSelPB[n].
Please note that SPI, Frequency selection selections change normal port output data direction setting, force their requirement while used. Refer chapter 11.4 Special operation. Copyright 2005, Microelectronic-Marin
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11.1.2 Overview
Figure Port pull selection normal mode
RegInPB RegOpenDrainPB RegIOSelPB RegOutPB
[7:0]
Vbat 100k
PBIn
PBIn input Dual Port input Serial Interface inputs
RegPullUpPB
RegPullDownPB
RegCfgPB RegIntSel
Configuration registers Port special functions, (may change output data direction selection)
during port read pulse mode while ExtCen=`1' mode (Inp 7,6,5) Signal selected (Inp 3:0) other cases (normal mode, read)
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11.2 Register map, functions
Table Port registers overview Functions Register name RegInPB Base RegOutPB RegIOSelPB RegPullUpPB Pull resistor RegPullDownPB open drain RegOpenDrainPB Dual Port selection Freq. output selection RegCfgPB Serial Interface selection Signal selection RegSigSel
Basic function Direct read input terminal state Data output register Direction selection Pull-up resistor selection Pull-down resistor selection Enable n-channel open drain output Configures corresponding bits accordingly mode selection. also 11.1.1 Special function priority handling Selection internal signal port
Table Port registers RegInPB Name PBIn[7:0]
0x30
Reset
Input register Description Direct read input terminal state `0'=read low, `1'= read high Output data Description Data output register `0'= output low, `1'=output high Direction register Description Direction selection; `1'=Output, `0'=Input Pull-up selection Description Pull-up resistor selection `0'=no pull-up, `1'=pull-up enabled Pull-down selection Description Pull-down resistor selection `0'=no pull-down, `1'=pull-down enabled pullup) N-channel Open drain selection Description N-channel open drain selection output) `0'=CMOS mode, `1'= open drain enabled Port configuration settings, DPR, SPI, Signals Description Enable Dual Port Enable Serial Interface function Connecting internal Signal1 PB[0] Connecting internal Signal2 PB[1] Connecting internal Signal3 PB[2] Connecting internal Signal4 PB[3] Reads Reads
RegOutPB Name OutPB[7:0]
0x31
Reset ResSys
RegIOSelPB Name IOSelPB[7:0]
0x34
Reset ResSys
RegPullUpPB Name PullUpPB[7:0]
0x36
Reset ResMain
RegPullDownPB Name PullDownPB[7:0]
0x37
Reset ResMain
RegOpenDrainPB Name OpenDrainPB[7:0]
0x35
Reset ResMain
RegCfgPB Name EnDualRAM EnSPI EnSig1 EnSig2 EnSig3 EnSig4
0x32
Reset ResSys ResSys ResSys ResSys ResSys ResSys
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RegSigSel Name Sig1Sel[1:0] Sig2Sel[1:0] Sig3Sel[1:0] Sig4Sel[1:0] 0x33 Reset ResSys ResSys ResSys ResSys Description Select internal Signal1 output PB[0] Select internal Signal2 output PB[1] Select internal Signal3 output PB[2] Select internal Signal4 output PB[3]
Internal signal selection frequency output port when corresponding signal enable set. SigXSel[1:0]='00' Sig4Sel[1:0] Sig3Sel[1:0] Sig2Sel[1:0] Sig1Sel[1:0] PWM4 PWM3 PWM2 PWM1 SigXSel[1:0]='01' PWM3 PWM4 PWM1 PWM2 SigXSel[1:0]='10' Pr1Ck[11] Pr2CkSource Pr1Ck[11] Pr2CkSource SigXSel[1:0]='11' Pr1Ck[0] Pr1CkSource Pr1Ck[0] Pr1CkSource Description Output PB[3] Output PB[2] Output PB[1] Output PB[0]
11.3 Normal operation
Port input terminal status always read directly. registers influencing modes bit-wise selectable. integrated, switchable pull resistors selectable output drive mode allow maximum different terminal modes. Refer Table Port mode details. Default state after power terminals input mode with pull-down resistor. Table Port settings normal mode OpenDrainPB[i] PullDownPB[i] Normal mode selection Frequency selection Dual Port output mode Input mode Input mode with pull-up Input mode with pull-down Output mode, CMOS high drive Output mode, CMOS drive Output mode, open drain, high-Z Output mode, open drain with pull-up Output mode, open drain drive PB[i] terminal
PullUpPB[i]
IOSelPB[i]
OutPB[i]
Notes
High-Z Weak Weak High-Z Weak
Port left floating Pull-up priority Default state after Power-up Pull resistors disabled Pull resistors disabled Pull-down disabled Port left floating Pull-up active Pull-up disabled
11.4 Special operation 11.4.1 Frequency Output
Signal1 Signal4, Prescaler frequencies Table Port settings Frequency mode OpenDrainPB[i] PB[i] terminal Frequency output terminals Pr1ck[n] Pr1CkSource, Pr2CkSource Output mode, CMOS high drive Output mode, open drain Output mode, open drain, Pull-up PullDownPB[i]
PullUpPB[i]
IOSelPB[i]
OutPB[i]
Notes
Signal High-Z Weak
Selected signal output Selected signal output, needs external pull-up Signal output, pull-up intern
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11.4.2 outputs
SPI: SOUT, SCLK master mode) Table Port settings outputs OpenDrainPB[i] PullDownPB[i] PB[i] terminal
PullUpPB[i]
IOSelPB[i]
OutPB[i]
output terminals SOUT SCLK master mode
Notes
Output mode, CMOS high drive Output mode, open drain Output mode, open drain, Pull-up
SOUT SCLK High-Z Weak
outputs outputs, needs external pull-up outputs, pull-up intern
11.4.3 inputs
SPI: SIN, SCLK slave mode) Table Port settings inputs. OpenDrainPB[i] PullDownPB[i] PB[i] terminal
PullUpPB[i]
IOSelPB[i]*
OutPB[i]
input terminals SCLK slave mode
Notes
SCLK, input SCLK, input with pull-up SCLK, input with pull-down
High-Z Weak Weak
pull, Terminals must driven externally Pull-up priority Default state after Power-up
11.4.4 Dual Port terminals
Dual Port output (while EnDualRAM='1', ExtCEn='1', ExtWrEn='0') Table Port settings outputs OpenDrainPB[i] PullDownPB[i] PB[i] terminal
PullUpPB[i]
IOSelPB[i]*
Output mode, CMOS high drive Output mode, open drain Output mode, open drain, Pull-up
OutPB[i]
Dual Port data output DPData[7:0]
Notes
DPData High-Z Weak
outputs outputs, needs external pull-up outputs, pull-up intern
other Dual Port cases (not during read access), port terminals configured based normal mode settings. only difference that port inputs must left floating.
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Serial Port Interface
12.1 Basic features:
3-wire serial interface, inputs outputs mapped port following manner: SIN: Serial Input Data PB[7] SOUT: Serial Output Data PB[6] SCLK: Serial Clock PB[5] Master Slave byte-wise serial communication. Master mode: internal clock sources (prescaler frequencies from selected timer1 periods) external clock input PA[5]. Slave Mode External clock source from port PB[5] Transmission order, first selection. active edge serial interface selectable (positive negative edge) Data output synchronization with opposite shift clock. Auto-Start mode; which allows have data stream output (UART support) maskable interruptions generated. Beginning transmission transmission.
12.1.1 Overview:
Figure architecture
RegSPILoad[7:0]
Load register
MSBnLSB Synchro
PB[7]:SIN Start PosnNegShft
PB[6]:SOUT
Shift Register State Count
Shift_Clk
IrqSPI[1:0] RegSPI[7:0]
Master clock1 Master clock2 Master clock3 Master clock4 Master clock5 Master clock6 Master clock7 EnSPI MS[2:0]
PB[5]:SCLK
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12.1.2 terminal configuration
When enabled EnSPI='1', pads used port transmission automatically input output mode according configuration SPI. pull resistors well possible open-drain selections depend port settings terminal direction. Table Terminal configurations Pads pins Direction PB[7] Input PB[6] PB[5] SOUT SCLK Output Output master mode. Input slave mode
Pull-down Selectable selectable Selectable slave mode
Pull-up Selectable Selectable opendrain mode Selectable slave open-drain master mode
Open-drain n.a. Selectable Selectable master mode
12.2 Functionality 12.2.1 Master Slave modes
slave mode SCLK given externally input PB[5]. master mode, SCLK generated output PB[5]. Master/Slave selection well active clock selection Master mode done with bits MS[2:0] RegSPICfg. Maximum Clock frequency master mode internal high-speed clock 5MHz case 10MHz). Different prescaler based clock frequencies timer1 frequencies available input clock. MS[2:0] MS[2:0] MS[2:0] MS[2:0] MS[2:0] MS[2:0] MS[2:0] MS[2:0] Slave mode. SCLK PB[5] Master mode, SCLK PWM1 Master mode, SCLK PA[5] Master mode, SCLK Prc2CkSource Master mode, SCLK Pr2Ck[9] Master mode, SCLK Pr2Ck[8] Master mode, SCLK Pr1CkSource Master mode, SCLK Pr1Clk[14] (internal signal coming timer1) (PA[5] input terminal) (clock source prescaler2) (Output clock from prescaler2 bit[9]) (Output clock from prescaler2 bit[8]) (clock source prescaler1) (Output clock from prescaler1 bit[14])
master mode, SCLK generated from beginning until transmission. necessary enable disable each burst. After each transmission, Start automatically reset after clocks, except cases where Load value rewritten during data transfer (AutoStart, data stream output).
12.2.2 data stream Output (Auto-Start)
transmission will immediately follow current transmission writes RegSPILoad while Start `1'. Load_nShift flag indicating that actually loading value from RegSPILoad (Load_nShift `1') transmission progress (Load_nShift `0'). RegSPILoad value must loaded while LoadnShift (during shift operation). re-load after transmission, Start reads '0', will trigger transmission. IrqSPI[1] used determine reload time. Note: Auto-Start mode, should slower then especially when access RegSPIDat transmission.
12.2.3 Interruptions
There interrupts generated SPI: IrqSPI[1]: Generated beginning transmission first active edge SCLK. used Auto-Start mode force write next value transmit RegSPILoad. IrqSPI[0]: Generated transmission last active edge SCLK. Both interruptions maskable with RegMsk20[5:4]. They priority RegInt20[5:4].
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12.2.4 edge synchronization selection
Depending protocol, shift data's falling rising edge SCLK with PosnNegShft register RegSPICfg. possible resynchronize SOUT opposite edge shift clock with Synchro register RegSPICfg: Figure Edge synchronization selection
SCLK SOUT RegSPILoad RegSPIDat IrqSPI[0] IrqSPI[1] Load_nShift
SCLK SOUT RegSPILoad RegSPIDat IrqSPI[0] IrqSPI[1] Load_nShift
PosnNegShft Synchro
SCLK SOUT RegSPILoad RegSPIDat IrqSPI[0] IrqSPI[1] Load_nShift
PosnNegShft Synchro
SCLK SOUT RegSPILoad RegSPIDat IrqSPI[0] IrqSPI[1] Load_nShift
PosnNegShft Synchro
PosnNegShft Synchro
12.2.5 start-up
enabled EnSPI RegCfgPB. Before enabling configuration must set. Configuration means, clock selection, edge selection synchronization SOUT selection. this parameter change while EnSPI `1', transmitted data guaranteed. last operation Start launch transmission. Configuration settings Clock, Edge, synch MSB/LSB selection 2nd: Enabling SPI: EnSPI RegCfgPB Write load data RegSPILoad Start transmission with Start RegSPICfg When transmission finished, RegSPIDat contains received value coming through SIN. Note: This register accessible read mode only. possible read time data guaranteed during transmission slave mode final value while Load_nShift `0'. value guaranteed when Load_nShift `1'. possible interrupt IrqSPI[0] start read this register. Start used determine shift operation ongoing finished. Master mode Start flag synchronized with next inversed active clock edge after writing start bit. (The user writes start reads start flag). slave mode start flag becomes active immediately after writing start bit. After full byte transfer Start also start flag reset. This used determine transfer software polling.
12.2.6 first selection
default, MSBnLSB `0', first transmission (receive send) LSB. first selected writing MSBnLSB='1'. selection must performed setup, before loading reading transmission value.
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12.3 Registers overview:
Table registers RegSPICfg Name Start PosnNegShft MSBnLSB Synchro Load_nShift RegSPIDat Name SPIDat[7:0] RegSPILoad Name SPILoad[7:0] RegCfgPB Name EnDualRAM EnSPI EnSig1 EnSig2 EnSig3 EnSig4 -0x38 0x39 0x3A 0x32 -SPI configuration Description Start transmission Selects master slave mode. Used select clock master mode well. Select active edge shift register Select first. first. SOUT synchronized opposite edge Flag indicating load transmit mode. Clock source External clock from SCLK PB[5] PWM1 from timer1 timer12 External clock from PA[5] input Pr2CkSource Pr2Ck[9] Pr2Ck[8] Pr1CkSource Pr1Ck[14] data register Description Shift register status load register Description Buffer used load data send through SOUT Port configuration Description Enable Dual port Enable serial port interface Enable internal signal driving PB[0] Enable internal signal driving PB[1] Enable internal signal driving PB[2] Enable internal signal driving PB[3] Read always Read always
Reset ResSysSlp ResSys ResSys ResSys ResSys ResSys ResSys -MS0
Mode Slave Master Master Master Master Master Master Master
Reset ResSys
Reset ResSys
Reset ResSys ResSys ResSys ResSys ResSys ResSys
Table interrupt mapping Interrupt source IrqSPI[1:0]
Priority
IntCtrl connection Int2[5:4]
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Timers
13.1 Basic features:
EM6812 contains identical, individual configurable 8-bit timers. They used standalone chained together 16-bit timers. Possible configurations 8-bit: Timer1, Timer2, Timer3, Timer4 8-bit, 16-bit Timer1, Timer2, Timer34 Timer12, Timer3, Timer4 16-bit Timer12, Timer34 Each timer work with input signals from port (clock start, stop, input capture), output frequency signals port generating interrupt signals `zero' 'compare' match conditions. Each timer configuration bits setup registers. Input clock source (external inputs prescaler clock frequencies), select Start condition (software write external condition); select Auto-Reload Zero-Stop mode. Pulse Width Modulation (PWM) Frequency generation. Interrupts source (compare zero). Timer value read fly. When chained together 16bit Timer34, Timer4 will take over full configuration Timer3. Same thing applies Timer12. basic timer function counting from start value down then interrupt generated timer stops. With autorelod set, timer reloads start value after reaching zero runs endless loop until stopped. every zero detect interrupt signal generated. With set, pulse width modulated signal output directly inverted port Pulse width period depend timer compare timer load value. Either compare condition zero condition create interrupt. Frequency generation done mode selecting desired signal period (load value) putting compare value half period. Figure Timer architecture
Data
Timer compare value
Enable Enable
IRQ_Comp
Ext._start CPU_Start
Comparator
Freq generation
Start/stop IRQ_Zero
Timer
int._clk
8/16 timer status Timer configuration
Auto Reload Clock source Start source generation Interrupt source
Ext._clk
Timer load value
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EM6812
13.2 Functionality 13.2.1 Auto-Reload mode
"Auto-Reload" mode means that after having down-counted from start value RegTimXLoad zero, timer restart down-counting automatically from start value. start value changes during down counting, timer waits until loop before loading start value. Auto-Reload mode, RegTimersCfg must set. period Auto-Reload mode equal RegTimXLoad value. Startup synchronization based first negative edge selected clock source after start condition fulfilled. After startup phase, RegTimXLoad value transferred into timer down counting starts next active clock edge. After every zero detection timer value loaded again, RegTimXLoad altered, value will loaded. timer stops first active clock edge following removed start condition. Also, when cleared during down counting, timer will stop when reaching zero Zero-Stop mode). every zero crossing interrupt IRQTimX will generated. Figure Timing diagram Auto-Reload mode (SWStart)
writes Stop
writes Start SWStart Internal(Start) synchronized Timer Start Internal(Stop) ClkIn
TimXLoad
IrqTimer
AutoReload
AutoReload
Load Stop=0
generation
generation
Start=0 Stop=1
Count down
Count down
Count down
Stopping timer during down-count Will freeze timer current value (positive timer input clock synchronization) Restart stopped timer during down-count synchronized based negative edge selected timer input clock source. such acts like initial timer start will start loading TimXLoad value start down-count. Special cases apply timer stopped short periods below timer-input clocks. such cases count value enlarged unit (stop seen, restart just afterwards) TimXLoad take place (stop seen) proper restart, internal, synchronized Start signal must least full clock period. Note: Above mentioned timer restart delay times drastically reduced when after going into stop condition timer frequency temporarily highest available frequency (i.e. setting Pr2CkSource, NOP, going back original clock).
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Gated clock
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Gated clock
EM6812
13.2.2 Zero-Stop mode
"Zero-Stop" mode, timer stops counting after reaching zero. generates interrupt IRQTimX resets Start bit. Startup synchronization based first negative edge selected clock source after start condition fulfilled. After startup phase, RegTimXLoad value transferred into timer down counting starts next active clock edge. Counting based positive edge selected timer input clock source. Figure Timing diagram Zero-Stop mode (SWStart)
write SwStart reset Stop
Re-Start (earliest possible)
SwStart
Internal(Start) synchronized Timer Start Internal(Stop) ClkIn Internal(ClkTim) TimXLoad TimXStatus IrqTimerX
Load Stop=0
generation
Count down
Restart stopped timer after detect synchronized based negative edge selected timer input clock source. timer stop condition must valid full timer clock periods before being able restart. This means that timer restarted clock period after SWStartX automatically cleared clock timer clock cycles after interrupt detect. respecting this restart delay prevent timer reload, value will remain will generated independent fact that start condition true. Stopping timer during down-count Will freeze timer current value (positive timer input clock synchronization) Restart stopped timer during down-count synchronized based negative edge selected timer input clock source. such acts like initial timer start will start loading TimXLoad value start down-count. Special cases apply timer stopped short periods below timer-input clocks. such cases count value enlarged unit (stop seen, restart just afterwards) TimXLoad take place (stop seen) proper restart, internal, synchronized Start signal must least full clock period. Note: Above mentioned timer restart delay times drastically reduced when after going into stop condition timer frequency temporarily highest available frequency (i.e. setting Pr2CkSource, NOP, going back original clock).
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Load Stop=0
Start synchro
Gated clock
EM6812
13.2.3 Start control system
There principal ways start counter: Internal start: Software writing SWStart bit. External signals port input: State condition: External start input state (down-counting while condition true) Pulse condition: External start input pulse, stop next pulse. selection start source corresponding port input done register RegTimXCfg bits StartXSel[2:0]. controlled software Start State Pulse Start condition case external start defined registers RegTimersStart. SwStartX bits used busy flags case software start. timer started port input conditions, SwStartX bits will remain `0', busy information derived from reading timers status value detecting start stop conditions. Each timer different start sources. Software start selected default, activated writing SWStartX register RegTimersStart. selection other start sources done with StartXSel[2:0] RegTimXCfg. Table Start selection StartXSel[2:0] Timer1 Selection with Start1Sel[2:0] Soft start SwStart1 Ext. start Ext. start Ext. start Ext. start Ext. start Ext. start Ext. start Timer2 Selection with Start2Sel[2:0] Software with SwStart2 Ext. start Ext. start Ext. start Ext. start Ext. start Ext. start Ext. start Timer3 Selection Start3Sel[2:0] Software SwStart3 Ext. start Ext. start Ext. start Ext. start Ext. start Ext. start Ext. start with with Timer4 Selection Start4Sel[2:0] Software SwStart4 Ext. start Ext. start Ext. start Ext. start Ext. start Ext. start Ext. start with with
Start selection must changed while timer running.
13.2.3.1 Software Start Condition
Software start, writes start condition SWStartX='1'. software start gets synchronized next falling edge selected counter clock. positive edge synchronization signal then enables counter function. counter stopped either writing SWStartX='0' Zero-Stop mode when counter value reaches Please refer Figure Timing diagram Auto-Reload mode (SWStart) Figure Timing diagram Zero-Stop mode (SWStart) more details
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EM6812
13.2.3.2 External Signal State Condition
Counter active long specified input reads `1'. Zero-Stop mode will stop soon counter reaches external state condition first synchronized with negative edge counter clock. positive edge this synchronized signal will enable timer start. basic restart conditions described 13.2.1 13.2.2 apply. Figure External start: State condition, Auto-Reload mode.
Ext. Start (State) Internal(Start) synchronized Timer Start ClkIn TimXLoad TimXStatus
Figure External start: State condition, Zero-Stop mode.
Ext. Start (State) Internal(Start) synchronized Timer Start ClkIn TimXLoad TimXStatus
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EM6812
13.2.3.3 External Signal Pulse Condition
Counter function gets activated first positive edge selected input signal, following positive edge will stop counter. Zero-Stop mode will stop soon counter reaches internal Pulse Start recognition signal first synchronized with negative edge counter clock. positive edge this synchronized signal will enable timer start. basic restart conditions described 13.2.1and 13.2.2 apply. pulse start recognition signal first positive edge external start condition reset either following positive edge input will also reset when counter value reaches Figure External start: Pulse condition, Auto-reload mode.
Ext. Start (Pulse) Pulse Start recognition Internal(Start) synchronized Timer Start ClkIn TimXLoad TimXStatus
Figure External start: Pulse condition, Zero-Stop mode.
Ext. Start (Pulse) Pulse Start recognition Internal(Start) synchronized Timer Start ClkIn TimXLoad TimXStatus
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EM6812
13.2.4 Stopping timer
timer stops always next clock following valid stop condition. These are: Reaching Zero-Stop mode. software start control SWStart cleared. external start control, input state selected input value becomes external start control, input pulse, timer stops pulse. Refer also previous timing diagrams hints restart.
13.2.5 Clock selection
There different clock sources each timer. Some them come from external sources. others from prescaler1 prescaler2. selection done with ClkXSel[2:0] RegTimXCfg. Table Input clock selection Timer1 ClkXSel[2:0] Selection with value Clk1Sel[2:0] Pr2CkSource Pr2Ck[8] Pr2Ck[6] Pr1CkSource Pr1Ck[13] Pr1Ck[11]
Timer2 Selection with Clk2Sel[2:0] Pr2CkSource Pr1CkSource Pr1Ck[14] Pr1Ck[12] Pr1Ck[10] Pr1Ck[8]
Timer3 Selection Clk3Sel[2:0] Pr2CkSource Pr2Ck[8] Pr2Ck[4] Pr1CkSource Pr1Ck[13] Pr1Ck[9]
with
Timer4 Selection with Clk4Sel[2:0] Pr2ClkSource Pr1ClkSource Pr1Ck[13] Pr1Ck[11] Pr1Ck[9] Pr1Ck[7]
Clock selection should only changed while timer stopped avoid timer clock glitches, which influence actual counter value.
13.2.6 Frequency generation
With pulse width modulation function, possible generate signals defined frequency duty cycle. These signals output port frequencies PWM. function based comparison actual timer value compare value. when timer starts counting until reaches comparison value, then PWM='1' until loop when timer reaches value figure below more details. function enabled with EnPWMX RegTimXCfg. This enables comparator also routes signal port Compare match interrupt generated mode. TimEqX allows select between timer compare match timer zero detect (default value). Also refer chapter 13.2.8 Interrupts. Figure Frequency generation Auto-Reload mode.
SwStartX ClkIn TimXLoad TimXComp TimXStatus PWMX Comparison Count down
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Comparison
Start synchro
Count down
EM6812
Zero-Stop mode becomes stops after zero detection. below. Figure Frequency generations Zero-Stop mode.
SwStartX ClkIn TimXLoad TimXComp TimXStatus PWMX Comparison count down Zero detected, PWM=0 Stop
Load PWM=0
Start synchro
13.2.6.1 Frequency Duty cycle Calculation
FPWM FClkTim (TimXLoad TimXComp TimXLoad
Count down
DutyCyle
13.2.6.2 Frequency generation
Frequency generation extension function. only difference that Frequency generation duty cycle signal period both change. period adjustment made with autoreload load value. Whenever load value changed, will applied next following loop after zero crossing.
13.2.7 16-bits configuration
Timer1 timer2 form together 16-bit timer12. timer3 timer4 which form timer34. this configuration, timer1 timer3) becomes master configuration start source, clock source, mode, Auto-Reload ZeroStop mode selection. comes from timer1 timer3 from timer2 timer4. functionality remains identical standalone 8-bit timers load, compare status values split registers: RegTimXStatus, RegTimXLoad RegTimXComp. merge timer1 timer2 EnTim12 RegTimersCfg must `1'. merge timer3 timer4 EnTim34 RegTimersCfg must `1'. With timers merged specific selection bits timer2 have function anymore interrupt source from slave timers will inactive.
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EM6812
13.2.8 Interrupts
Each timer selectable interrupt sources: IrqTimer1 (zero detect compare match) IrqTimer2 (zero detect compare match) IrqTimer3 (zero detect compare match) IrqTimer4 (zero detect compare match) Table Timer interrupts selection EnPWMX TimEqX
Interrupt timer `Zero detect' timer generated timer `Zero detect' timer `Compare match'
these interrupt priority level mapped register RegInt20[3:0]. source individually selectable each interrupt masked register RegMsk20[3:0]. TimEq selection only valid when corresponding EnPWMX set. mode interruption generated when timer reaches value when reaches comparison value with TimEqX RegTimXCfg. needing both interrupts, user change source after each event. Another solution consists routing from port output onto port input configure this input input (slave timer interrupt). configured 16-bit timer, only master timer will generate interrupts. Figure Interrupts generation mode.
SwStart ClkIn TimXLoad TimXComp TimXStatus TimEq IrqTim
after Comparison
Table Timer interrupts mapping Interrupt source IrqTimer1 IrqTimer2 IrqTimer3 IrqTimer4
Priority
IntCtrl connection Int2[0] Int2[1] Int2[2] Int2[3]
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after Comparison
after zero detect
EM6812
13.3 Recommended programming order
2nd: 4th:
Select general timer configuration RegTimersCfg. Select specific timer configuration RegTimXCfg. Write necessary load compare values RegTimXLoad, RegTimXComp. Start timer (software start) enable start condition case external start, RegTimerStart.
Note: change configuration while running. Clock glitches occur influence result.
13.4
Registers overview:
13.4.1 General configuration registers
Table General Timer configuration RegTimersCfg 0x4E Name EnTim12 EnTim34
Reset ResSys ResSys ResSys ResSys ResSys ResSys
Description Timer1 timer2 merge 16bits timer Timer3 timer4 merge 16bits timer timer1 Auto-Reload mode timer2 Auto-Reload mode timer3 Auto-Reload mode timer4 Auto-Reload mode
RegTimersStart Name SWStart1 Tim1Pulse SWStart2 Tim2Pulse SWStart3 Tim3Pulse SWStart4 Tim4Pulse
0x4F
Reset ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
Description Timer1 software start-bit Timer1 start state `0', pulse `1') Timer2 software start-bit Timer2 start state `0', pulse `1') Timer3 software start-bit Timer3 start state `0', pulse `1') Timer4 software start-bit Timer4 start state `0', pulse `1')
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EM6812
13.4.2 Timer1 configuration
Table Timer1 configuration RegTim1Cfg 0x50 Name EnPWM1 Tim1Eq Start1Sel[2] Start1Sel[1] Start1Sel[0] Clk1Sel[2] Clk1Sel[1] Clk1Sel[0] Start1Sel[2:0]
Reset ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
Description Enable timer1 IrqTimer1 comparison mode Start source selection timer1 Clock source selection timer1
Start source Software start with SWStart1
External start
External start External start External start External start External start External start
Clk1Sel[2:0]
Clock input Pr2CkSource Pr2Ck[8] Pr2Ck[6] Pr1CkSource Pr1Ck[13] Pr1Ck[11]
RegTim1Status Name Tim1Status RegTim1Load Name Tim1Load RegTim1Comp Name Tim1Comp
0x51 0x52
Reset ResSys
Description Timer1 status
0x53
Reset ResSys
Description Start value timer1
Reset ResSys
Description Comparison value timer1 mode
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EM6812
13.4.3 Timer2 configuration
Table Timer2 configuration RegTim2Cfg 0x54 Name EnPWM2 Tim2Eq Start2Sel[2] Start2Sel[1] Start2Sel[0] Clk2Sel[2] Clk2Sel[1] Clk2Sel[0] Start2Sel[2:0] RegTim2Status Name Tim2Status RegTim2Load Name Tim2Load RegTim2Comp Name Tim2Comp
Reset ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
Description Enable timer2 IrqTimer2 comparison mode Start source selection timer2 Clock source selection timer2
Start source Software start with SWStart2 External start External start External start External start External start External start External start 0x55 0x56 0x57
Clk2Sel[2:0]
Clock input Pr
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