Manual AN-RQC-REP013V20 ©1985, ©1993, Electronics (Europe) G
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Quality Reliability
Manual
AN-RQC-REP013V20
©1985, ©1993, Electronics (Europe) GmbH
QUALITY RELIABILITY
Table Contents Preface 1.2.1 1.2.2 1.3.1 1.3.2 1.4.1 1.4.2 1.4.3 1.4.4 2.2.1 2.2.2 2.2.3 2.2.4 2.3.1 2.3.2 2.3.3 2.3.4 2.5.1 2.5.2 2.5.3 Fundamentals Quality Reliability Circuits Definitions Quality Reliability Mathematical Models Terms Quality Terms Reliability Failure Models Circuits Models Reliability Testing Failure Mechanisms Semiconductor Devices Application Impacts Circuits Reliability Latch-up Humidity Resistance Devices Plastic Packages Mechanical Stress Effects
Failure Rate Prediction Methods Implementation Quality Reliability Organizational Structures Design-in Quality Reliability Design Methods Design Review Testing VLSI Devices Confirmation Quality Products Quality Assurance during Production Process Quality Control Control Changes Human Factors Distributing Products
Reliability Assurance Examples Product Improvements Application OrientedQuality Grades General Design Precautions_ Improvements
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3.2.1 3.2.2 3.3.1 3.3.2 3.4.1 3.4.2
Customer Support Qualification Certification Application Support Common Support Application Hints Failure Analysis Handling Defects Failure Analysis Methods Reliability Forecast Data Product Reliability Prediction Methods
Appendix
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PREFACE Thank your interest semiconductor devices. aware development semiconductor industry been tremendous within past decades. Today, semiconductor devices used types machines systems. Microelectronics become leading most innovative technology all. Especially, VLSI devices have been increasingly demanded "systems silicon", which only includes hardware software electronic systems well. Accordingly, expectations regarding quality reliability semiconductor devices customers ever increasing. semiconductor industry been required demonstrate dramatic qualitative evolution. response expectations, made making constant efforts maintain improve quality products services, constantly. past, semiconductor devices have developed rate faster than that electronic systems. Certain applications became possible technologies implementations. which some call "decade system silicon", even more cooperation exchange information necessary realization truly satisfactory results. Fundamental precautions must taken when using semiconductor devices assure reliability devices right from planning stage product. This document will give summary philosophy activities related field quality reliability assurance. hope this document will help you. further product related features, please refer data sheets data books, also.
1993 Electronics (Europe) GmbH
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QUALITY RELIABILITY
FUNDAMENTALS QUALITY RELIABILITY CIRCUITS
DEFINITIONS QUALITY RELIABILITY
Quality image quality changed over years. Today said that quality capability satisfying requirements users.1) Since establishment 1899, biggest task company satisfy customers offering "Better Products Better Service". parallel, been using expression "Quality Reliability" long time since then, which indicates intention stress reliability well original quality. Nowadays, this expression coincides with world-wide understanding 8402. goal true quality means satisfy customers through offering right products services. fulfill market requirements, practices following: Develop appropriate time device that satisfies diverse needs customers Build product quality reliability which customers require expect Provide right amount products right time customers, continiously
global commitment customers, endeavors satisfy general requirements produce products with good balance quality, cost delivery-in-time. However, will make efforts offer customers devices that meet their expectations. Quality Assurance order realize high level quality, employees NEC, from planning development products after-sales service activities, conscious marketoriented attitude carrying activities stressing following points: Interpret customer needs correctly respond them appropriately. Establish required quality reliability product whole process (planning, development, production inspection). Respond customer complaints immediately.
There international standards that describes todays quality assurance requirements, called 9000 series. These standards define wide variety requirements regarding quality assurance quality control activities different business operations. 9000 being widely employed starting common rule industries. Companies around world investigating conform establish these standards practical mannor. Based history, mentioned above, same intention like 9000 standardizing internal specifications long time ago. Now, facilities checked independent auditors concerning conformance 9000 certified approvals have been achieved expected soon, respectively
Note 8402 defines quality "All features characteristics capability product service satisfy requirements users (easiness use, safety, availability, reliability, sturdiness, economy environmental safety) whether given explicitly implicitly."
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Quality Assurance System promoting quality assurance semiconductor devices overall activity that considered within each task stages products life related services. Therefore includes steps like market research, planning, development, design, production, inspection, distribution, customer services. Starting with market research planning, most important fundamental steps quality device later determined. Whether definition product good will determine whether final product will satisfy requirements expectations.
Customer Sales Circuit Technology Production Technology Reliability Quality Control Control Production Inspection
Market Research
Technical Research
Planning
Market Needs
Product Planning
Product Development Committee
System Design Process Design Circuit Design Package Design Layout Design
Development Design
Design Review
Trial Production
Evaluation Product Sales Committee
Distribution Samples Acknowledgement customer) Sales Planning Technology Standards Control Standards Production Planning Parts Inspection
Mass Production
Order
Production
Acquisition Utilization Information Quality Shipping Feedback Warehouse Control
Product Inspection
Customers (Market)
Usage Reception Complaints
Investigation, Analysis Execution Countermeasures
Investigation Report
Report Customer
Fig. Structure Quality Assurance System
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Development, design, production inspection processes which intended quality actually built into product. comprises central part quality assurance activity. During this phase realization product, elementary tasks covered, such Development high technology ahead competition Reliability design design review Evaluation reliability Control purchased parts materials Control environment facility Screening product inspections.
order provide customers good products schedule meet other requirements, supports customers during after distribution parts, too. Regardless, concerning preservations made assure high quality level during storage products, order help customers devices correctly efficiently, giving service users. These activities line with intention that quality measured expectations. conducting quality assurance within activities each business unit. This comprises total system, global Reliability Quality Control Division takes command this activity control promote applies reliability quality control each division head office, each production section, each factory, which treated separate production company. Reliability According Japanese standard 8115, which defines "Reliability Terminologies", reliability defined ability item fulfill given function under given condition given period. keep more simple VLSI products, that certain product fulfill application requirements defined period without failures. However, even when simplify expression, seems quite difficult measure indispensable rules, because conditions requirements each application quite different. Practically, certain standards guide lines necessary, measure degree reliability make results comparable.2 degree reliability abstract, reliability physics standardized test methods practical tools. addition, certain nomenclature defined identify subjects like: What object? What required function? What failure? What period lifetime? What (environmental) condition?
Note
8115 defines degree reliability probability that system, product, part fulfill given function given period time under given condition without failure.
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MATHEMATICAL MODELS
While words quality reliability quite abstract first meaning, necessary define certain mathematical rules. Otherwise comparison becoming difficult. will find certain national well international standards these rules.
1.2.1 TERMS QUALITY Incoming Inspection purchasing distribution process characterized certain checking procedures incoming goods. product liability concerned, customer basically requested follow this actual laws. Only both business partners agree special contract, like ship-to-stock agreement, purchaser free test material. Depending risk taken well complexity testing product itself, grade testing will specified. reason that field complex circuits complete testing products costly time consuming, sampling tests popular. Sampling Tests Sampling tests based experience, that forecast result with certain probability. example, throwing coin forecast that both sides will fall equal proceed long enough. Stopping early will reduce level confidence. Mathematically describe process sampling Poisson distribution which represents probability that certain feature included observed volume. practice, operating characteristic, which graphical description Poisson distribution, will choosen decide. Depending number failures found sample size forecast will made whole lot. Several standards like MIL-STD based this theory define parameters acceptance rejection incoming goods. Acceptable Quality Level (AQL) Based upon statistical rules mentioned above, defines sample size which necessary identify that number failures below defined percentage. assumption that result will target probability. Example: size 10000 pcs., AQL0.65% table (MIL 150) defines sample size n=125. number failures must less equal c=2.
From practical point view, idea behind such kind testing reduce costs. other hand, extremely values useful, because reduce either confidence level increase sample size drastically rules probability.
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Defects-per-Million; dpm, Because nowadays high quality levels stable state-of-the-art semiconductor manufacturing processes, characterization values useful. Trying implement zero defects high volume production, sampling methods only second choice verify quality lot. Design-in quality, checking each step during whole process, statistical process control, constant improvements biggest influence. Since 100% inspection finished goods performed either supplier both parties, definition defects-per-millions more suitable commonly used measure. Ship-to-Stock Having well established production process high quality level product, statistical rules will more less limit values measured. Additionally, likes cover risk possible fail, which might covered reason. Also, each additional handling products, including testing device, bears risk damage fail. Following such thinking, procedure called "ship-to-stock" becoming more more popular. Driven requirement reduce cost ownership, customers like avoid incoming inspection without getting less data about quality supplied goods. Therefore, ship-to-stock basically means that supplier documenting tests results, able solve problems shortest possible time frame. Instead doing 100% incoming inspection test, customer will sampling tests tests only case trouble. Based close cooperation between customer supplier, supplier doing quality reliability tests submits test results continuously.
1.2.2 TERMS RELIABILITY Probability Survival; R(t) probability that device system survives without failure until time expressed like
R(t)
where
c(t)
c(t): total number samples number failures time
reliability t=0, number failed samples increases with time, also realiability decreases zero. Complementary, probability failure F(t) increases with time both expressions equal one. Therefore, possible measure reliability observing either samples that fail failed samples also.
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F(t)
Probability function defect
R(t)
(Time)
Fig. 1-2: Plot relation probability failure F(t) probability survival R(t)
Failure Density Function; f(t) identify whether device fails within certain time interval following equation more practical:
f(t)
where
dF(t) dR(t)
f(t): failure density function dF(t) change probability failure time dR(t) change probability survival time
equation describes probability getting failure within certain time interval with limits t+dt. Failure Rate Function; correlate probability failure with units that still remain intact, following equation will defined
f(t) f(t) F(t) R(t)
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Cumulated Hazard Function; H(t) Accumulating failure rate time intervall between zero leads following expression
H(t)
Assuming that failure rate constant (random failures), reliability exponential distribution. equation reduced H(t)
Bath-tub Curve
Failure rate
Initial failure period
Random failure period
Wear-out failure period Time
Fig. 1-3: Failure rate curve (Bathtub curve)
failure rate graphically expressed like shown Fig. 1-3. Because shape, called bathtub curve. curve devided into three phases: Initial failure period (Infant mortality) Random failure period (Product usage) Wear-out failure period.
Failures initial failure period will normally caused faults production process. failure rate this period product life cycle decreases with time. When failure rate settles stable value, product usage phase will start, typically. After certain time failure rate will increase, carried wear-out failure modes.
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general, "flat" phase lifetime semiconductor devices relatively long compared lifetime whole system using them. Several steps design stage product have verify target level concerning device reliability. Therefore, devices which fail during infant mortality period main interest. These characterized latent failure modes screened burn-in other methods during production process. establish high reliability level right from beginning, four points must kept: Build reliability into devices design stage Confirm reliability qualification tests Establish high quality level production process Remove latent failures screening
Probability Distributions Failure rates recorded within limited observation intervals. Therefore, mathematical models based probability rules. order describe certain behaviour distribution functions used model. Each distribution function characterizes certain physical behaviour. Below most popular functions mentioned. Normal Distribution normal distribution (Gauszian distribution) most widely used distribution quality control. characterized bell shaped curve which symmetric around average value such that 68.3 total events covered period 95.45 total events covered period 99.73 total events covered period
Failure density
time
Fig. 1-4: Gauszian Distribution Curve
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Mathematically, express failure density f(t), failure rate (t), probability survival R(t) like this:
f(t)
R(t) f(t)
where
average value dispersion
Logarithmic Normal Distribution logarithmic normal distribution will used failure rate follows normal distribution constant over time. shape this function unsymmetrical around peak value, smaller values approaches normal distribution This formula will used descibe failure rate wear-out failures, like electromigration effects.
Failure density
time
Fig. 1-5: Log. normal distribution
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Exponential Distribution failure rate constant with respect time matches random failure period, probability density function f(t) reliability R(t) expressed following equations:
f(t)
contrast normal distribution which events concentrated period around average this distribution like smooth mountain trail from infinity. time which also called Mean-time-to-failure (MTTF), probability survival will 36.8%. practise, exponential distribution describes random failures. equivalent Weibull distribution with form parameter m=1, which will described later.
Fig. 1-6: Exponential Distribution
Weibull Distribution Historically, this distribution used first Weibull express distribution tension strength steel. choosing proper values form parameter failure distributions over life cycle matched distribution. Therefore this most widely used model analysis reliability industry.
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f(t)
where
form parameter
shape distribution function determined form parameter describes following situations: m=1: failure rate constant. represents accidential failure. m>1: failure rate increases with time. This represents wear-out failure.The shape failure density function will close logarithmic normal distribution (m=2) normal distribution(m=4). m<1: failure rate decreases with time. This represents infant mortality. discussion presumes that failure occur every moment. Actually, there period which failure observed. such cases, necessary modify above mentioned equation introducing time period which called no-failure period.
m(t-)
(t-)
f(t)
Failure density
time
Fig. 1-7: Graphs Weibull distribution
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FAILURE MODELS CIRCUITS
1.3.1 Models Reliability Testing Beside fact that product must satisfy requirements initial stage usage, also should perform defined functions through periods usage witout failure. confirm that product fulfilling targets concerning reliability design stage, accelerating tests applied representative samples. purpose simulate amount stress which representative whole life cycle from finished device until application. Typically, different kinds tests used checking reliability semiconductor devices, which will described below. Environmental Tests environmental tests apply stress condition certain limit which device will normally pass without deterioration. semiconductor devices, mechanical thermal environmental tests executed. Mechanical stress applied simulate conditions devices undergo during transportation, mounting, usage. Thermal stress applied check powerless conditions during mounting process final application. Endurance Tests endurance test conditions simulate stress which deteriorates parameters product during product's life cycle. Basically stress leads total fail product. semiconductor devices have long lifetime general, difficult confirm endurance under specific conditions. this reason, defined stress higher than specified conditions will applied. deterioration device's parameters accelerated, making possible analyze data estimate lifetime within reasonable time. Therefore, these tests also called accelerated life tests.
Failure mode
lifetime
Failure mode
Stress
Fig. 1-8: Influence lifetime different failure modes
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practice, failure mode assumed endurance life test failure mode real different. lifetime estimated from failure mode under stresses becomes L0'. failure modes actual mainly happen failure mode which represents smaller acceleration coefficient. calculated lifetime will wrong, same factor used calculation. Therefore, endurance tests must cover wide range influences, like temperature electrical effects, right prognosis. Acceleration temperature stress
(S1)
(S2)
(S3)
Failure rate
time
Fig. 1-9: Weibull distribution failure rate different temperatures
From data obtained endurance tests three different temperatures grade acceleration calculated. Using Weibull distribution certain test conditions, will chart like shown figure shown above. plotting data lifetime corrosponding diagram lifetime versus temperature, real lifetime corresponding actual temperature extrapolated.
Inclination (Ea)
lifetime
1/T1 1/T2 1/T3 1/T0 Temperature
Fig. 1-10: Plot activation energy (Arrhenius plot)
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Acceleration electrical stress influence electrical stress lifetime semiconductor devices mainly covered effects: effects that generate further thermal stress transportation material
electric resistance circuit temperature rises with power consumption.This expressed formula:
where Junction temperature Ambient temperature Temperature rise self heating
lifetime also determined movement material. Migration effects induced current flow, applied voltage generates movement ions. considerations made electrical stress summarized with following formula:
where Lifetime Electrical stress Constant
Calculating lifetime three standards minimum stress Weibull distribution plotting data corresponding diagram lifetime versus stress, actual stress estimated like figure below.
Lifetime
(stress)
Fig. 1-11: Influence electrical stress
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1.3.2 Failure Mechanisms Semiconductor Devices Complexity semiconductor devices growing four times about three years. While package size becomes smaller functionality well relative chip size increases, problems reliability come devices become more more important product within system, requirement high reliability getting stronger every day. Along with development semiconductors, failure modes have changed their importance. parallel, each failure mechanism been studied carefully measures have been taken keep mass-production assure high level product reliability. this section, some important failure modes their mechanisms will discussed, countermeasures described. Failures Junction Characteristics Many semiconductor devices utilize forward reverse characteristics pnjunction. main failure modes related junction characteristics soft breakdowns diodes, increased leakage junction, degredation amplification bipolar transistors. Soft Breakdown Soft breakdown characteristics defined leakage current which starts flow reverse direction when voltage lower than regular breakdown voltage reason this phenomenon partial breakdown junction junction leakage. failure will caused spots impurities like metals, dislocations across junction, partial destruction junction. case, leak path formed leakage current, which larger than normal reverse saturation current, will flow.
Reverse layer SiO2
Channel leakage Depletion layer Hard breakdown Soft breakdown Reverse bias voltage
Fig. 1-12: Electrical characteristics reverse pn-junction (A), pn-junction surface
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Fig. 1-12 shows example misalignment inversion layer. Normally, junction surface protected oxide film (SiO2) other material. polluted ions natrium potassium, transferable ions introduced into oxide film. inversion layer formed surface layer, thus causing channel leakage under reverse bias. Lifetime Carriers bipolar transistors, lifetime minority carriers affects electrical characteristics. Especially, impurities like metals (gold, platinum, iron, etc.) introduced into semiconductor crystal, some high energy particles (elctron rays, X-rays, neutrons) applied, capturing level will change lifetime carriers decreases. This results increasing leakage current, lowering current amplification well increasing saturation voltage. Additional dislocation that cuts across junction makes impossible control collector current base current.
Dislocation
Crystal defect
Fig. 1-13: Defective operation bipolar transistor dislocation
example where small leakage current affects VLSI device characteristics strongly, poor refreshing DRAM. DRAM, electric charge accumulated capacitor, recharged regularly keep data. there some defects crystal, charge capacitor lost quickly leakage current caused carriers. becomes impossible store data. fact that integration DRAM becomes more intense, area used capacitor memory cell getting smaller too. Therefore necessary keep misalignment relatively small reduce leakage current. Failures defects Insulation Layer reliability semiconductor strongly influenced insulation layer. Defects insulation layer will cause failure modes like deterioration breakdown voltage gate oxide threshold voltage drift transistor. Failures insulation layer related either initial imperfection quality layer itself. While imperfection comes initial stage test, poor quality might visible after some time interval, randomly. Therefore, this effect also called Time Dependent Dielectric Breakdown (TDDB).
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Frequency (relative value)
eCathode
Anode Insulation voltage [MV/cm]
Fig. 1-14: Distribution breakdown voltage oxide layer (A), deteoration model thin oxide
Fig. 1-14 shows histogram breakdown voltage thin oxide layer relatively high quality material. values around 10MV/cm represent insulation voltage uniform oxide. Opposite that, values around 0MV/cm stand uneven oxide made under unclean conditions. instance, there oxygen precipitation crystal, oxide film imperfect exhibits locally breakdown voltage. breakdown oxide layer explained following model. high electric field applied oxide layer, tunnel current (Fowler-Nordheim current) will flow. Through tunnel effect, electrons injected into oxide film from cathode. Accelerated electric field, (hot) electrons collide with crystal lattice produce electrons holes. holes mostly gather around cathode form space charge, which increases positive feedback, eventually leads breakdown insulation. Time Dependent Dielectric Breakdown; TDDB Because oxide thickness becomes thinner smaller design rules, strength electric field within oxide layer becomes larger. Therefore, voltage applied continiously oxide, TDDB occurs with lapse time. known that TDDB depends strength electric field temperature. However, mechanism this effect still unknown subject future research. Today, precaution, care being taken produce flawless oxide conduct proper burn-in operation, screen defective products that come accidentally.
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150°C 85°C 25°C
Cumulative percentage failed
MV/cm Time (Hours)
MV/cm
Cumulative percentage failed
MV/cm
MV/cm
Time (Hours)
Fig. 1-15: TDDB characteristics
Carrier Effects When high energy electrons injected into gate oxide MOSFET structure, surface charge boundary area silicon oxide film generated, which will influence transistor characteristics This phenomenon called carrier effect. With higher integration LSI, size MOSFET scaled down, whereas supply voltage been kept constant. Along with this trend, carrier effects became more important, carriers generated increase electrical field. mechanisms will explained.
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Carrier Generation n-Channel MOSFET electrons, moving from source drain, will obtain enough energy from horizontal electrical field overcome Si-SiO2 interface before reaching drain, they will injected into oxide. This effect called channel carrier. similar manor, electrons cause ionization collision avalanche multiplication generate electron-hole pairs, strong electric field exists near drain. such case, some electron positive hole pairs, which hot, injected into gate oxide. This effect called drain avalanche carrier.
Gate Source
Drain
Gate Source ISUB
Drain
Depletion layer type substrate well VSUB
Depletion layer VSUB
type substrate well
Fig. 1-16: Channel carrier effect (A), Avalanche carrier effect
carrier generation depends voltage applied MOSFET. Electrons holes injected into gate oxide generate interface states Si-SiO2 interface trap levels oxide layer. result, change threshold voltage current characteristics MOSFET occurs. sign change depends character carriers: electron, hole, both. Under equivalent voltage conditions, change characteristics expressed roughly following equation:
Where Change MOSFET characteristics Constants determined structure MOSFET stress bias conditions Stress time
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Threshhold voltage shift [mV]
(Drain avalanche carrier)
(Channel carrier)
Period stress applied [sec]
Fig. 1-17: Threshhold voltage shift channel MOSFET
Generally, voltage applied MOSFET operating conditions varies between ground level power supply voltage. Therefore, electrons well holes will generated both, because variation voltage, change characteristics will less than constant voltage applied. Furthermore, change depends duration active condition cycle time. Higher drain voltages, usually supply voltage level, lower operating temperatures will improve characteristics change carrier effects. prevent changes carrier effects from design point view, lightly doped diffusion region (called LDD) formed reduce internal electrical field. Additionally, circuit which controls operation voltage applied MOSFET implemented circuit design stage. Electromigration VLSI devices become more highly integrated related processes even finer, current density metal line increases. Metal atoms electrons tend collide. resulting mass motion momentum direction electrons cause metal line break, short circuits hillocks whiskers. This phenomenon called electromigration. Metal lines used semiconductor devices produced sputtering insulation layers. Therefore, metal line polycrystalline structure. Activated metal atoms move along grain boundary where dislocation dislocated diffusion occurs easily. number output paths larger than number inputs, void generated. Opposite that, number outputs smaller, hillock will result. width metal line smaller than diameter crystal, grain boundary crosses line like bamboo. Such case makes diffusion impossible takes longer until line breaks.(please refer also Fig. 1-19)
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Fig. 1-18: Example broken metal line Electromigration
Grain boundary
Fig. 1-19: Movement metal atoms grain boundary structures grain boundaries metal lines
mean time failure (MTTF) electromigration given Black's empirical formula: MTTF
where A,n: Constant Current density Activation energy constant Temperature
[eV] (8.6159 10-5 [eV/K]
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value approximately depending current density. activation energy, value about 0.7eV. Fig. 1-20 shows some example MTTF metal line with regard current density temperature.
A/cm
A/cm2
MTTF [hours]
Width wire [µm]
Temperature [°C]
Fig. 1-20: MTTF Dependence: width metal line (A), temperature
prevent defects electromigration several measures possible. First all, will large grain size reduce boundary area. adding copper titanium metal line, void space grain boundaries will reduced. smoothing base metal line improving step coverage steps, non-uniform current flow will avoided. Changing structure form cover layer well increasing strength, avoids growth hillocks; mainly making cover film stick well metal line. Stress Migration Stress migration failure created extremely thin metal lines used LSI. metal line subjected tension stress difference thermal expansion coefficients metal insulation layer cover film. relaxation process thermal stress creates void. Generally, there failure modes. mode called high temperature short period mode, which void generated during thermal treatment production process when metal line made. wedge shaped void appears cooling process after certain period high temperature treatment. avoid problems this phenomenon, thermal process settled lower temperatures cooling phase will kept short. This suppresses thermal diffusion metal atoms. Applying small compression stress tension stress materials structures metal line, insulation layer cover film will also reduce effect. Additionally design stage, form wiring used, which shape produces little stress concentration.
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other, so-called temperature long period mode, occurs while storing device about 200°C applying aging tests. wedge shape appears breakage appears along bamboo type grain boundary form slit. This type failure generally explained creep model, such that metal under tension stress shows plastic strain after some time.
Fig. 1-21: Example slit breakage temperature long period mode
Fig. 1-22: Temperature dependence creep velocity
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shown Fig. 1.22, creep velocity expressed product stress term diffusion term. According Arrhenius model, understood that high temperatures diffusion speed void also high. temperatures diffusion low. Hence, adding both terms, creep velocity peak value. mechanisms both modes completely clear yet. Various research activities, covering stress analysis, observation void generation growth process, under execution today create precise model. Life under stress migration depends mainly width thickness metal line bamboo structure tends break slit form opposite electromigration effect. Therefore obstacle when designing small structured VLSI's. addition countermeasures described high temperature mode above, elements like copper added reduce diffusion grain boundary. Also conductive layers with high melting points inserted redundancy (multilayer structure).
MTTF (hours)
Width wire [µm]
Fig. 1-23: Dependence MTTF wire width
Soft Errors Semiconductor memories bear types failure modes, typically. type irreversable one, so-called hard error. This mode equivalent other semiconductor devices. other type, so-called soft error, causes functional fail recovers later. cause such failures might influence electrical noise alpha particles. While soft errors caused electrical noise power supply lines influenced countermeasures system design stage, alpha particles cannot eliminated. alpha particles emitted from radioactive substances (uranium, thorium) contained materials small quantities.
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Alpha particle
Depletion layer
type substrate
Fig. 1-24: Generation carrier alpha particles penetrating p-type substrate
alpha particle, time irradiation, generates electron hole pairs while losing energy colliding with other atoms. alpha particle radiated from uranium thorium energy between produces about electron-holepairs. electrons gather around node, while holes collected p-type substrate, because electric field depletion layer. These elctrons holes change electric potential each node. case memories, since very small signal used memory cell, sense amplifier, line, such change lead mis-operation circuit. soft error caused penetration alpha particle memory cell called "cell mode". Causing soft error sense amplifier line called "bit line mode". According failure mechanism, information inverted line mode. cell mode, cell data will switched from high low. failure rate versus time different both modes. While failure rate cell mode constant, increases line mode when cycle time (refresh period) becomes faster.
Soft error rate
Cycle time [µsec]
Power source voltage
Fig. 1-25: Soft error rate DRAM versus cycle time (A), versus supply voltage
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example, fig. 1-26 shows results accelerated test check NEC's DRAM. seen that main failures line mode. This example shows also that soft error rate decreased internal signal voltage made larger. Reducing density impurities used material packaging wiring down soft error rate. past, most semiconductor manufacturers have already lowered densities below detectable levels, that further drastic improvement made. Decreasing influence soft errors alpha particles, sufficient capacity memory cell must designed. spite smaller areas available with higher integration, improvement thin film capacitor layers well introduction trench type stacked memory cell structures could retain required amount capacity. Another precaution that design should make difficult generate electron-hole pairs. drastic decrease cell area contributed this effect. area diffusion layer diminshes, quantity gathered electron hole pairs effecting electric potential diminishes, too.
Cell capacitance Cell area
Cell capacitance (fF)
Order integration
Fig. 1-26: Transition cell area cell capacitance
future, explained above, soft error rate expected same order like today. However, lower supply voltages, necessary assure reliability submicron devices, will necessary improve production process design more complex memory cell structures.
Cell area (µm2)
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APPLICATION IMPACTS CIRCUITS RELIABILITY
1.4.1 General gate oxide thickness integrated circuits getting thinner along with smaller design rules, gate oxide breakdown getting lower, too. Generally, electrical field V/cm will cause breakdown gate oxide. case very thin oxide layer used gate oxide, even will cause damage. proper work environment important keep possible electrical discharges low. Generally speaking, lower relative humidity, higher electrostatic voltage will relative humidity will best prevent electrostatic problems. Nevertheless, person handling semiconductors well equipment will charged certain levels. tables mentioned below will give some idea about existing static charge work benches. Table 1-1: Examples Electrostatic Charge Work Environment (from DOD-HDBK 263)
Electrostatic Voltage Relative Humidity 35,000 12,000 6,000 7,000 20,000 18,000 Relative Humidity 1,500 1,200 1,500
Cause Walking carpet Walking vinyl floor Person bench Vinyl cover work manuals Polyethylene picked from bench Chair using polyurethane foam
Table 1-2: Examples Electrostatic Charge Human Body
Work Environment Walking vinyl tile floor Person bench Sitting chair with antistatic measures Touching grounded tester station Lifting vinyl from shelf Putting vinyl shelf Working bonding station wrist strap Working bonding station wrist strap Electrostatic Voltage Ordinary Shoes Conductive Shoes Remarks 1,300 23°C, 40%rh
25°C, 52%rh
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Failure Models Test Methods discharge electrostatic energy, characteristics semiconductor device degraded. leakage current might increase, breakdown voltage might lower, current amplification might show variations, short circuits opens, respectively, might result. causes these degradations commonly four models: Human body model; electrostatic charge stored human body discharged upon contact with device damages discharge current limited serial resistance body. Machine model; Metal machines discharge damage device. discharge resistance very low.The electrostatic capacity relatively high against human body. Charged device model; device package lead frame charged, instance, friction. discharge will take place through terminal leads device damage Electric field induced model When structure exposed strong electric field, dielectric breakdown oxide film occurs.
failure models electrostatic discharge represented standard test methods. Fig. 1-27 Table give overview commonly used test methods human body model machine model. Fig. 1-28 describes different methods charged device model.
Sample
Fig. 1-27: Equivalent circuit test method
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Table 1-3: Test Method Standards
Standard Conditions Capacitance Resistor 100pF 1.5K Voltage applied application
(CO)
2000V 2000V 2000V
times
MIL-STD 883B, Method 3015.1 DOD-STD 1686 BS9400 MIL-M-38510/55C EIAJ IC-121-1981
100pF
1.5K
times
100pF 100pF 100pF 200pF 100pF 200pF
1.5K 1.5K
5000V 500V 1000V 500V Individually Individually specified times Once times
Sample
Sample
Voltage providing electrode
Arbitrary discharge impedance
Arbitrary discharge impedance
Fig. 1-28: Charged device model test method: Package charge method (A), Device charge method
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Examples Defects effect caused electrostatic discharge junction breakdown. This thermal breakdown happens flow excessive charge reverse bias direction pn-junction. This tends occur shortest part charge flow path bent junction part. leakage current increased breakdown voltage degraded, difficult identify damaged area.
Fig. 1-29 Example junction breakdown
electrode breakdown similar thermal breakdown like above. most cases, resistor layer breaks down. metal electrode burn down, too.
Fig. 1-30: Example resistor layer breakdown
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Another defect oxide breakdown. Thin silicon oxide films used gate dielectric. dielectric breakdown voltage such films range 10MV/cm. gate oxide thickness example, dielectric breakdown occurs about 30V. actual product, protective circuits resistors diodes prevent destruction degradation input pins. However, since device capable cause dielectric breakdown structure, great care must applied during handling.
Fig. 1-31: Example oxide film breakdown
Countermeasure Against Static Electricity Basically, every production step should checked against potential generating electrical charge well quick discharge. Once being encountered should eliminated immediately. prevent devices from destruction caused electrostatic discharge, following points important: charge package with static electricity. place charged parts near device. Avoid electric discharge.
Table next page shows examples antistatic measures prevent trouble course processing.
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Table 1-4: Examples Anti-static Measures
Item Device Handling Anti-static Measures Persons touch semiconductor circuits and/or assembled should have body grounding body grounding difficult provide, conductive mat, conductive shoes, anti-static working wears. Remove synthetic fiber blankets plastic foot stands from work area.
NOTE: body grounding done, necessary provide resistance about between body ground safety protection.
Storage
storage foamed polystyrene. Provide static electricity shielding means metal mesh bucket like. Provide grounding machines used. acrylic resin measuring parts. parts device with tool. Provide grounding possible. Keep belt conveyer contact with conductive material. anti-static spray. Wipe with duster. conductive belt. conductive mats. Install humidifier. careful when turning on/off main switch.
Equipment
Tools
Belt Conveyer
Others
Suitable Environment environment which static electricity less than 100V suitable handling semiconductor devices. such environment, nothing should left that might cause higher charge. Insulators, especially chemical textiles plastics, which charge easily, should kept away from work bench. handling, conductive equipment materials should used. devices must stored transported anti-static container. Also after assembly PCB's, parts should stored transported conductive bags, boxes, racks. Open connectors boards should left open. short-circuit aluminum foil attached connector recommended.
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Printed board Aluminum foil (short-circuit connector cover entire part)
Conductive
Short-circuit board
Separator board
Conductive plastic container (for transportation)
Conductive rack (for during work)
Fig. 1-32: Protecting PCB's from static electricity
machines, tools, work benches must securely grounded. Placing conductive (less than 1011 work bench well floor grounding each effective. When atmophere general, humidifier should applied.
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Conductive Wrist strap Conductive floor Humidifier Work suit with anti-static measure Conductive shoes
Fig. 1-33: Anti-static electricity measures during work
Additionally, operator should ground body using wrist ring. should wear antistatic gloves avoid touching device with bare hands. resistance shoes should range 100K 100M. Even when testing after board assembly these precautions should implemented. While grounding human body effective measure, dangerous there chance that operator gets touch with electric power. grounding must protect operator well handled material. Therefore, resistance must placed between body ground, which should range
Wrist ring
Grounding wire: threaded copper wire, vinyl covered, about meter
250K resistance built
Alligator clip
Fig. 1-34: Grounding human body
soldering iron will used during operation, should voltage type (12V 24V) with grounded tip. device should used little short possible avoid damages.
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Fig. 1-35: Grounding soldering iron
1.4.2 LATCH-UP Model Latch-up Generation Today, CMOS technology commonly used integrated circuits. traditional CMOS technology involves existence complementary structures, PNPN structures (commonly called thyristor, SCR, Shockley diode) also automatically implemented design. These structures latch positive feedback between coupled transistors produces regenerative switching. feedback caused power source variation surge from attached circuit. Fig. 1-36 outlines most important parasitic elements p-well process equivalent circuit. this equivalent circuit, transistors form thyristor structure. I/Oterminal biased positive surge pulse transistor turns current will flow through resistor cause voltage drop base will biased will also turn This lowers potential base Tr3, thus will switch also. whole circuit reached stable state large current will flow transistors Tr3. Thisphenomenon called latch-up.
VOUT
N-type substrate
VOUT
P-well
Fig. 1-36: CMOS structure equivalent circuit latch-up
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same like above, negative pulse trigger circuit transistor Tr4. Again positive feedback will generated. Although this phenomenon described pwell structure, also valid other CMOS processes. practise, sudden high current followed burned-out power supply lines open- /short-circuits commonly exhibits such problems. prevent latch circuit design several measures taken. avoid voltage variation, substrate well tied power supply. epitaxial substrate used down impurities and, therefore, improve parasitic resistance. Additionally, thick oxide between main functions circuitry will help. Elements like guard rings channel stoppers will create defined leakage carriers without latching. Evaluating Latch-up resistance, Test methods evaluate latch-up strength device current will forced until will trigger parasitic structure.
Monitor latch occurrence Input output Latch occurs
Latch trigger current
Fig. 1-37: Method measuring latch-up breakdown current flow
1.4.3 HUMIDITY RESISTANCE DEVICES PLASTIC PACKAGES Influence Moisture Plastic Molded Devices Currently, resin type used encapsulation widely used kinds semiconductors. Even strong improvements have been made resin, that such devices compete with ceramic packaged ones certain applications, humidity will still influence behaviour plastic molded devices, today. Depending application, humidity might deteriorate parameters.
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There mainly routes, where water might penetrate into device. along boundary between resin lead. mechanical stress adherence between lead material resin sufficient. Another permeation resin itself, fact, that today's state-of-the-art resin contain several chemical components.
Penetrate resin Chip Penetrate along boundary Lead wire Resin
Fig. 1-38: Path water into plastic molded device
Corrosion Effects main failure mode caused humidity corrosion aluminum used wiring. Corrosion electrochemical reaction which accelerated applied voltage. Also polarity bias applied will influence reaction since different ions attracted electric field. Chloride Sodium ions, implanted impurities base materials, known ions that will cause corrosion aluminum. Following reactions take place:
Anode side: ClAl Cl4- Cl4- (OH)3
Cathode side: 2H2O 4eAl (OH)2 Al3+ 6H2O (OH)Al (OH)3 (OH)3
Examples aluminum corrosion shown Fig. 1-39. Both show corrosion near bonding pad. They typical case when water penetrating from outside.
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Fig. 1-39: examples corrosion Aluminum
Passivation Improvement protect aluminum wiring chip passivation chip's surface. past, usage single layer quite common semiconductor industry. Even this passivation process proved highly reliable, started several years adopt more reliable one. double layer passivation introduced, using traditional first layer silicon nitride introduction this structure brought tremendous improvement concerning humidity resistance devices. Test elements have shown improvement least three times versus one. Popcorn Effects During more than decade, requirements market have forced trend smaller packages economic mounting technologies. result development surface mountable devices which small thin, mainly using resin encapsulation. mounting technologies hughe environmental stress will applied these devices. This will cause following special failure modes: Deformation packages Deterioration moisture resistance characteristics Cracked bonding wires
these defects mainly based effect which will explained now, commonly call "popcorn effect". Today's commonly used epoxy type mold resin used plastic packages absorbs moisture normal storage conditions. thermal stress applied such package, temperature rises quickly moisture evaporates. parallel also expands, resulting internal mechanical stress. Further, difference thermal expansion coefficient between resin metal (island leads) will stress, too. this way, swelling package surface and, later, cracking package will observed. Also bonding wires will broken. Even this process will lead visible destruction, device will degraded least with regard moisture resistance.
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Fig. 1-40: Cross-section package crack
Moisture absorption through Plastic bulk Interface between plastic metal
(II)
Soldering Thermal shock Package temperature
(III)
Moisture vaporisation causes pressure Plastic strength down Thermal expansion mismatch
(IV)
Interface generation Increase partial internal stress Different expansion interfaces
Package crack generation Internal stress relaxation Crack mode rate:
Fig. 1-41: Mechanism package crack generation
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avoid failures like these precautions must taken during storage mounting process. storage process must keep least critical devices condition. this purpose, introduced system where devices packed special, sealed plastic bags. This packing called "Dry-pack". device will stored these bags until their final usage dry-air condition. parallel with appropriate packing storage procedure, mounting process, especially soldering process, must classified. Each process basically different stress applied device. take approach from practical point-of-view, established ranking system which specifies recommended soldering conditions each SMD. major soldering processes covered. further details please refer document "Surface Mount Technology Report", available from sales office. Evaluation Methods Moisture Resistance order evaluate moisture resistance plastic encapsulated devices, various test methods used. uses various combinations these methods determine moisture resistance devices. Table 1-5: High Humidity Test Methods
Test Method High Temperature/ High Humidity Storage
Symbol Test Condition Ta=85°C, RH=85% Bias
Merit Very similar actual worstcase storage environment Very similar actual worstcase behaviour application conditions
Demerit long evaluation testing time
High Temperature/ HHBT High Humidity Operating
Ta=85°C, RH=85%, With Bias
long evaluation testing time
Pressure Cooker
Ta=125°C, RH=100% Detects fluctuations Bias process lots shorttesting term. Very easy carry out. Ta=130°C, RH=85%, With Bias
severe simulate actual storage conditions
Unsatured Pressure Cooker
HAST
Very similar actual worst- Limited equipment case situation relation capacity application short time testing
Since many years, most common tests evaluate moisture resistance HHBT.As condition this kind testing similar conditions real usage, consequently failure modes almost same. weakest points whole chip area detected, because contaminations, holes passivation, cracks, well poor coverage found corrosion defects. Although tests able cover good range practical applications, disadvantage long test time (1000 10000 hours) sufficient results.
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reduce test time required, introduced, this applies more strict condition. However, moisture forcibly penetrates into resin will often cause corrosion only bonding area. this sense, failure mode different real usage. same mannor like PCT, HAST (Highly Accelerated Stress Test) developed. Even more difficult execute, allows detect weakest points device within hours. moisture forced into device, failure modes similar HHBT. 1.4.4 MECHANICAL STRESS EFFECTS Thermal stress, which applied thermal cycling thermal shock, will result mechanical defects influence different thermal expansion coefficients chip resin. main phenomena slid broken aluminum layers, cracked passivation layers, broken corner parts chip. defects explained effect that resin will force chip center temperatures. stress exceeds stress passivation layer, cracks appear passivation layer plastic deformation aluminum layer occurs. Eventually aluminum layer torn silicon substrate.
Fig. 1-42: Damage through sliding aluminum layer
Countermeasures reach higher reliability device result material that applies lower stress chip. This might realized resin used encapsulation, increase strength passivation film, improved geometrical design aluminum layer, chip coating. Bonding Fails Conventional chips electrically connected with external leads thin gold aluminum wires. similar methods bonding used NEC: (nail head thermal compression) UNTC (ultrasonic NTC). Both methods apply bonding process mutual diffusion gold wire aluminum bond pad. Failures might happen misplacement wire direction, poor connections, broken wires. Most these failure modes sorted electrical test, latest. Even will found after thermal electrical stress. failure mode example,
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unsufficient pressure bonding itself. diffusion process will continue high temperatures, fact that there void between materials, different diffusion speed gold aluminum will create gap. Another failure mode might appear when wire supply smooth enough during bonding mechanical vibration applied afterwards. strength wire will reduced. wire neck breakage will occur. avoid such fails, precautions must taken until device encapsulation finished.
Fig. 1-43: Examples damaged ball bond
FAILURE RATE PREDICTION METHODS
requirement determine limits performance level well lifetime device essential. However, take data real time time consuming costly. Under these circumstances, various testing methods have been introduced past. Eyring Equation Especially, fast reliability tests should performed, precise model should describe acceleration effect each possible failure mode. Eyring equation based quantum theory. Basically stress parameters such temperature, humidity, voltage, mechanical stress defined energy levels. This will result equation: B/T)
where Failure rate Constants Function stress other than temperature Absolute temperature
Under certain conditions, formula seperated into Arrhenius formula plus additional term, describing interaction between temperature stress. Even complete formula more precise, difficult calculate, several constants have determined beforehand.
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Arrhenius Model Most failure mechanisms semiconductor devices depend, least some degree, temperature related effects. Therefore, relationship represented Arrhenius model, which describes dependence between temperature activation energy failure mechanism. Raising temperature will lead increased failure rate, which allows reduced test time practice. model expressed following equation:
where
Failure rate Constant Activation energy constant 8.61595 10-5 Absolute temperature
eV/°K
Acceleration Factor Based upon this formula, acceleration coefficient between temperatures calculated following manor.
where
Acceleration factor Failure rate temperature Failure rate temperature Activation energy constant 8.61595 10-5 Operating temperature Operating temperature
eV/°K
Calculating reliability integrated circuit application, necessary calculate acceleration junction temperature. general, junction temperature will depend ambient temperature, cooling, package type, power dissipation device itself. With these terms, junction temperature expressed
where junction temperature ambient temperature power dissipation thermal resistance (junction ambient) °C/W
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Thermal Activation Energy estimation failure rate very difficult. even more difficult define lifetime semiconductor device clearly, because these products influenced variety failure mechanisms very different thermal activation energies. Table 1-6: Activation Energy Failure Modes
Failure Mode Ionic Contamination Surface Charge Polarization Oxide Defects Silicon Defects Electromigration Oxide Defect Leakage Intermetallic Bond Failures Metal Corrosion Activation Energy 0.48 0.78 High Temperature Bias /Storage Detection High Temperature Bias
Fig. 1-44: Relation between temperature acceleration factor
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With evolution semiconductor technologies, main failure mechanisms have changed with used processes experiences. While Al-gate processes polarization ionic contamination have been problems, silicon well oxide defects were considered main failure mechanisms polysilicon processes thinner gate oxides shallow junction depth. single activation energy value representation failure mode provided accurately practise, semiconductor manufacturers well users estimate some average activation energy range quick first order approximation based long experience, applies average thermal activation energy calculations. Stress Strength Model Systems devices exposed stress whether they operation not. Therefore, stress might divided into functional stress environmental stress. Functional stress unavoidable when product will work. Environmental conditions defined application. Using product, stress parameters might overlay that difficult find clear correlation between accelerating test failure modes. Each element applied tests either multiply effect, therefore, vary range acceleration, i.e. time reaction. practise, quite important know, parameters will vary over product's life cycle. practical model, reliability tests need concentrate main failure mechanisms which dominate endurance. Either samples have stressed with different strengths group-vise with specific stress. Even elementary failure modes known, they might influence each other production process, design, test history, etc. most cases, failure mode cannot observed directly, like parameter drift single transistor integerated circuit. relation between real failure, observed some delayed effect related stress, will described stress model.
Strength distribution Strength deterioration
Stress strength
Safety margin
Failure
Stress distribution
time
Fig. 1-45: Stress Strength Model
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stress strength model failure occurs, stress exceeds strength device. avoid occurence failure, product must have some margin between stress strength level. Stress strength characterized Gauszian distribution parameter representing failure mechanism. check real stress correlating with predicted values, empirical analysis made, especially case accelerating tests representing stress levels. From another point view, stress strength model describes minimum requirements device concerning reliability. Knowing degradation parameters certain condition, device specification limits determined condition. device must have enough margin parameters that stress strength band will meet each other. Prediction Methods Failure Rate Characteristics Each forecast methods have pros cons. Basically data taken from reliability tests, market feedback, theoretical forecast assumptions. Looking single groups data, prediction results might differ strongly. merits special reliability tests controlled reproducable conditions. Attention must paid fact that accurate acceleration factor defined failure mode tested device might different real application. Also amount data limited, even tests performed groups, accumulate with time, only. feedback from field provides more data, which represent real applications, volume fluctuates with time. Data products available. quality data depend strongly feedback loop between customer supplier. Quite often only small market segment will covered. forecast based upon theoretical assumptions easy calculate. Systemization groups products possible. other hand quite difficult correlate results with real results, find right coefficient suitable reliability. Taking merits demerits into account, defined forecast methods. Further details will described later.(please refer chapter 3.4)
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IMPLEMENTATION QUALITY RELIABILITY
large-scale integration reached very high level density, reliabilty semiconductor devices imposes profound impact system reliability. According this, reliability become major factor satisfaction and, therefore, important issue quality. Commiting within company rules, that most important targets better products better services, implemented advanced system total quality control (TQC) jobs facilities across entire semiconductor business. adopting TQC, build quality into products thus assure higher reliabilty.This chapter will provide some idea about philosophy behind concept methodology applied fulfill high targets. ORGANIZATIONAL STRUCTURES
Basic Principles reliability quality control semiconductors based thorough integration reliable management steps design production process well reliability assurance customer services. Clear definition subjects close communication well cooperation main factors execution such system. Team work within small groups integration quality functions jobs practical results. same manor, close relations customers essential understand requirements market. also allows establish short communication path between knowledgeable people customer's supplier's side. This valid supplier well customer subcontractors. Close cooperation main target whole daily business, including continuous education people; regardless this executed operator trainings customer seminars workshops. achieve these targets following activities executed: Standardized designing practices build reliability into products Thorough examination potential failure sources during design stage Extensive evaluation characteristics reliability tests Automated manufacturing reduce distribution quality Continuous environmental monitoring production site Periodic calibration maintenance equipment tools Quality control each production step Feed-back learning processes through small group activities Product-specific screening, inspection, reliability tests Monitoring reliabilty assurance tests Analysis quality information, including field data, feed-back results Close cooperation with customers
these measures leading constant improvement process increasing quality adoption customer needs.To meet requirements increasing product quality, concentrates three points:
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Standardized design characteristics build quality reliability into product Elimination potential failures screening inspection
Role Management factor success, management takes leading role system NEC. This strategy driven several ideas. example, concept total quality control requires implementation company culture management. This also expressed main rules, fixed within management commitments. Giving priority customer satisfaction through relentless efforts provide better products better services Creating value usefulness society through active exploration frontiers areas science technology Tapping individual uniqueness each employee realizing his/her fullest potential Fulfilling responsibilities corporate citizen Increasing profitability facilitate dynamic growth internally contribute society large.
Based upon these guidelines, settled company structure since years. management commitments reflected hand organizational structures, other hand further activities promotive items, established guided management. multi-national activities NEC, structures applied worldwide, taylored local requirements. term "quality" understood perfection perform defined and, therefore, taken part daily business. Everyone member internal customer-supplier relation that basically applied actions. management contributes this philosophy promoting small group activities continuous training employees. Necessary actions management will based follow-up progress. Additionally, NEC's slogan "compute communicate human potential", close cooperation information exchange essential. role, management plays this extent, supply enough resources force establishment right tools. Being biggest computer communications companies world, obligation driving force this field.
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Example: ISO9000 actual activity certification according ISO9000, which standard describing global rules quality management system. cope with these standards, company must have least state-of-the-art quality management system, which conform general rules, certified independent organisation. running updating advanced quality system since decades, company adopting these standards. Regardless functions, started implement ISO9000 rules across locations subsidaries. Former historically grown rules, like internal audits, were modified extended, necessary. previous times, customers performed audits only their requirements. This quite cost time consuming procedure parties. Additionally, along with more more complex manufacturing processes, became difficult judge detail supplier's measures assure high level quality, therefore, check supplier's fabrication. Although requirements most issues were same, they were checked individually. implementation ISO9000 standards brings common structure into these subjects. ensures customer that every action performed done best from organizational point view. guideline everything quality customer satisfaction. Processes, tests, procedures documented. General internal guide lines accessable customer. Procedures responsibilities fixed proofed independent organization. role management been discovering advantage certification forcing implementation. Even being certified will mean advantage directly related product quality; equivalent better service more transparency. Company Structures understand NEC's quality reliability assurance, also important know, related functions organized. items guided management, each profit center basically responsible area. Targets company's head office. Also standardization activities whole company actions coordinated central division. same way, centre coordinates supports activities related semiconductor operations NEC. center structured like matrix organization. axis defined coordination tasks, like management activities, promotions, engineering services. other correlates with different user groups. Applying such structure, quite effective optimal skills each task. Within semiconductor operations each division subsidiary company takes responsibility certain issues. Each them have seperate department, which independent from other departments, reporting directly related management. Their main role perform testing checking, even more supervise manage assurance process.
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Corporate Management Customer Statisfaction Office
Promotion activities Reliability Quality Control whole company principles standardization
Semiconductor Group
Promotion activities within group
Semiconductor Group Division
Determination principles Standardization Support activities within group
Sales Section Sales Division
Information management from customer
Support issues Sales
Application Engineering Division
Quality Reliability Department
Preparation sales tools, like documents Reliability data supply Promotion quality contracts Customer specification reviews Quality meetings with customers Feedback customer requirements Quality control distribution stage Support mounting technologies Coordination failure analysis
Product Division
Quality assurance activities products Setting goals quality level Development reliability technology Evaluation product's reliability Examination product designs Creating quality maintenance programs dedicated products Problem solving
Reliability Quality Control Department Production Company (Factory)
Quality assurance production process Quality control parts materials Quality control production process Monitoriong reliability test Failure analysis
Reliability Quality Control Department
Fig. 2-1: Quality Reliability Structures Semiconductor Operations
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Checking actual work requires abilities itself. Nobody should more perfect than executing this. That includes also process measuring parameters functions. this sense, quality should measured independent person against settled target definition. Therefore, employee executing function represent mainly hypothetical "customer". product process engineering divisions responsible potential quality device, which settled during design phase. engineers define standards, evaluate capabilities process actual product, solve technical problems. Continuous quality control production process, materials, reliability testing main functions function production site. design process product proper enough, influence quality control production process will lead improvement process with target zero defects. application engineering section takes care related sales organization which seperate department. This section basically engineering brain sales companies. Beside global application support, which covers preparation documents well support common issues, like mounting technologies, information exchange feedback market requirements main job. engineering capabilities this section make possible judge whether problem based product application. conjunction with analysis capabilities factories, customers supported case manufacturing line problems. functions, sales sections interface customers. They keep communication with customer arrange direct communication between sources right know-how. DESIGN-IN QUALITY RELIABILITY
Design plays extremely important role determining product quality reliabilty. believes that fundament reliable product build design stage. This chapter describes what believes necessary done during design cycle product. 2.2.1 DESIGN METHODS Product Development basis product trends dedicate requirements from market. These will represented specification after additional technical studies. develop product from this global specification, standardized procedures were implemented NEC. decision design product based three criteria business, technology, quality. Management relevant engineers from areas constitute development council, decides about realization. result will fixed target specification, which contains device functions, technology, parameters well targets quality reliability. last ones mainly influenced assumptions made what customer expects suit final application.
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Fig. 2-2: product development flow
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Hierarchical design method Since produces many kinds integrated circuits, design standards standardized procedures have been implemented, taking quality reliability into consideration. make design process very efficient, splitted into following steps: system design circuit design process design mask pattern (layout) design package design.
Making such seperation modulization implemented certain parts, like process design package design, used other products, too. Each design process more less independent, design criteria well standardization taylored design step. This approach called "Hierarchical Design Method". Design standard Design plays important role generating design quality product. Since introduction automation design verification, influence computer based methods reduced amount time required product design. tools, previously requiring large mainframe computers, realized with software running engineering work stations, today. designers carry design products using tools each level hierarchical design. This will shorten development period diminish number mis-design cases. order increase level performance, design methods standardized, design manuals prepared, education system related product established, beforehand. Trial When design completed, prototype produced wafer factory. Evaluation checks made product and, case problems design appear, corrections design implemented. avoid delays caused changes during development phase well ensure that desired performance obtained final product, inspection design rules confirmation operation simulation carried each level development. understands, that availability related design environment support system essential order realize early delivery products, especially when required customers devices such ASICs. contradiction standard devices, which fully developed NEC, ASIC products require involvement customer final product. Therefore, offers wide range tools necessary engineering support generate customized products with basically same level design quality.
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2.2.2 DESIGN REVIEW After completion design first trial samples, product must reviewed against targets set. basic questions review must give answer are: Does product conform device specification? Does meet quality reliability targets settled? every action well product line with standards? product manufactured economically?
designed product inspected from checklist, based upon experiences made, like data from past problems, example. parallel, experts fields product design, production technology, reliability technology others together regularly, publish design criteria checking rules. Each related department evaluates every design from their technical point view contributes this respect improvement global targets, also. design criteria checking rules fundamental guidelines each designer follow creating devices. Using tools circuit simulation, device simulation others, checks made each action design. problem found, design will corrected immediately. practice, experts same areas define design rules, will build Design Examination Committee. They will inspect each item design from their technical point view. main items checked are: Confirmation mask design Process design Rated values Reliability design Product liability problems others.
Only those designs that have passed examination considered following test stage. design fails examination, examined again after appropriate modification.The modification process includes another trial run, identify changes sufficient. 2.2.3 TESTING VLSI DEVICES While standard logic tested with patterns generated manually automatic test equipment (ATE), generation test pattern VLSIs becomes difficult because high complexity. economical, huge external test routines test device possible functions. Taking this fact into account, hand important consider ease testing (testability) stage design, other, design product functions make test "simple". following example idea making electrical test VLSI devices simple shown.
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Designing simple test necessary consider design concept that makes test simple, right from design stage device. There important principles, namely, ease control ease observation, which have implemented reach goal. Ease control this extend means that test pattern arbitrarily applied primary input circuit being tested. Ease observation respectively means that response measured some special pins normal output terminals. practice, test mode will switched control device test signals normal input output pins. order design simple test, necessary optimize ease control ease observation time design. standard devices, achieves these goals following methods: Attaching control gate control terminal testing Attaching output terminal testing observe internal circuit Incorporating testability circuit intrinsic ability test itself. Applying scan path method sequential circuits.
Since these methods important, number them implemented VLSI devices spite constraints semiconductor package chip areas. Implementation test Automatic test equipment (ATE) used production process contains computer, which controls functions connections signal waveforms. Usually, equipment applies series predetermined test signals input pins, compares signals with output response, judges whether results correct. test program varies depending being tested product. test pattern compiled either manually dedicated software, using simulation results design. program testing VLSI products generally large number program steps. Because importance, program examined Quality Assurance Department. NEC, test programs standardized main items quality assurance, such measuring items conditions. Test patterns generated with tools. high level quality, appropriate detection rate must obtained. Therefore, test patterns used mass production tested detection rate fault simulation. 2.2.4 CONFIRMATION QUALITY PRODUCTS product that passed design examination enters next stage trial production. Evaluation electrical characteristics tests reliability carried trial product. evaluation results have confirm, quality level intended design. critical products which testability important, test programs test patterns examined, additionally. order fulfill criteria qualification, following data gathered Reliability Quality Control department production division. These based survey requirements quality market present level technology.
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Initial failure rate Failure rate market Items conditions evaluation reliability ESD/Latch limit Other
After being qualified product, test made mass production line. Potentialproblems that might occur during mass-production checked for. this stage, main point yield distribution parameters which might affect quality reliability product. After successful examination engineers responsible production technology, production control, well Reliability Quality Control Dept., product released mass-production. QUALITY ASSURANCE DURING PRODUCTION
realize that specification during production, production control system must established. This should guarantee bug-free devices, minimum variations during production, reliable products. Beside establishment right equipment optimal test methods, consciousness each operator create products with optimal quality important process. believes that only combination good equipment well trained people fulfill requirements market. 2.3.1 PROCESS QUALITY CONTROL Quality control each process required achieve quality intended during engineering. activities concerning quality assurance mass-production stage involve various procedures each step production process. This based principle that quality reliability which designed into product must secured each step production process. also purchase materials parts, management equipment, environmental control major issues controlled. Fig. provides example concerning production process flow semiconductor devices. Process Check each production line, process check specifications with detailed control items applied each process step. items process checks roughly divided into ones related operation conditions those directly related products. each control item, checking methods, checking frequency recording procedures determined precise control performed. description actions done accessable each operator related work bench. basic tests performed documented related operator. Quality assurance people, so-called "process checkers", observe results conjunction with environmental equipment conditions, will create feedback data used production control.
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Fig. 2-3: Production process flow (Example plastic QFP)
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Statistical Process Control; measure keep constant production quality statistical process control. Basis competent product specification understanding critical processes, addition utilization charts with statistical control limits possibility quick effective corrective actions. Standardization quality control specifications across factories assist operate system control charts, monitors parameters critical processes. stations production line data gathered system, data back operators production engineering. quality department traces results keep data base. data that exceed limits parameters well abnormality being found daily observations will cause corrective actions. These actions defined corrective action system which reviewed constantly. monitor effectiveness process checks, audits conducted monthly basis. same time interval, process capability tracking done. process capability values summarized processes reviewed engineering departments location. Setting smaller limits from time time, statistical process control good vehicle implement Zero-defect culture. Environmental control Reliability quality semiconductor device affected large extent environmental conditions production process. Especially important temperature, humidity, dust water. Strict environmental control necessary. Accordingly, stringent control these items carried clearly defining checking method, checking frequency recording procedures. Furthermore, regular, periodic checks equipment that maintains environment performed maintain stable environmental conditions. Control facilities equipment Concerning different production facilities, control specifications prepared each them time their start-up initiation mass production processes. specifications incorporated into production line. Daily improvement activities aimed create perfect production facilities through activity, Quality Circle groups, etc. Furthermore, control items determined production facilities, conditions checked daily. regular intervals overall maintenance inspections performed each facility. Measurement instruments meters controlled detailed specifications each instrument. order calibrate each measurement instrument meter, standard instruments that have been calibrated with those from public organization installed. equipment factory calibrated using standard instruments.A seperate technical organization within assures that measurement equipment calibrated accurately.
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Control Purchased Parts order achieve reliable quality final product, also important control quality parts, materials related items that purchased from outside vendors. Also these parts materials affect reliable quality final product strongly. Parts, materials related items such chemicals pure gases only purchased from certified vendors. inspection these parts performed when they received from supplier. quality purchased items will confirmed. Incoming inspection done mainly sampling according standards, like 9051. vendors, requires them control changes their products accepts changes only after confirmation required quality. large scale change production line occurs, inspects suppliers factory prevent accidents terms quality. Additionally, doing vendor audit meetings regarding quality technology, necessary. inspects suppliers factory advise them improve stabilize quality products purchased. Final Inspection Screening inspection process very important factor guaranteeing quality devices shipped. According philosophy regarding optimal product quality, especially case VLSIs, latent failures removed burn-in, general. Therefore, applies this process industrial devices.
Fig. 2-4: Example Final Inspection Process Flow
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Beside level zero-hours quality, level reliability same importance. Reliability tests mass-production stage regularly made monitor reliability actual production. Samples each process family taken standardized tests executed. Items conditions reliability test explained 5.2. Examples product inspection reject criteria VLSI product shown Table Table 2-2. Table 2-1: Example Product Inspection Reject Criteria Plastic Package Product
Classification Item Sampling Method LTPD Sample Size Max. Defects
Electrical characteristics Fatal faults appearance Slight faults appearance
Individual specification
Cracked resin, lead distortion, lead plating, marking Inadequate resin molding, broken pieces, faulty lead plating, unclear marking
Table 2-2: Example Product Inspection Reject Criteria Ceramic Package Product
Classification Item Sampling Method LTPD Sample Size Max. Defects
Electrical characteristics Fatal faults appearance Slight faults appearance
Individual specification
Case crack, lead distortion, broken lead wire, plating, marking Part missing from case, poor lead wire plating, unclear marking
Even after certain time storage, sampling tests made check rust terminals deterioration quality moisture absorption epoxy resin. Target these inspections assure high quality reliability level eliminating latent failure modes occurring during long storage periods before shipping products market. majority devices with latent failures removed selection process after assembly. even with stringent screening rules, statistically small amount possible defects might remain tested material. After some time, failures will become visible external stress (temperature, voltage, etc.). identify such devices, applies external stress and, therefore, accelerate time until device becomes defect.
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possible causes latent failures device numerous therefore, methods remove them diverse. However, most failures modes accelerated applying external stress like high temperature high voltage. actual failure achieved short time line with stress factors. other hand, precautions must taken that normal devices will failing applying excess stress. VLSIs, effective screening method apply maximum voltage limits operate devices high temperature (100 125°C). This called burn-in. After this process, defect devices removed electrical test. Dealing with Defective Devices Preventing their Reocurrence anything above limits control specifications found during production process, product found defective, quick analysis problem done countermeasures taken according regulation associated with problem. continuation irregular items their recurrence stopped. Specifications dealing with defective devices state that problems recorded. cause defect countermeasure taken will reported. serious defect occurs, sample describing failure will analysed thoroughly concerning root cause measures taken prevent their recurrence. same time, information distributed separate production locations. 2.3.2 CONTROL CHANGES apparent that customers able semiconductor devices with satisfaction, reliability quality must maintained high level. This level must stable should able achieve even higher levels according demand times.
Plan change
Trial production
Evaluation
Important change?
Notification customers Direction change Execute change, process capability check
Fig. 2-5: Steps Control Changes
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When design change production process change made purpose improving quality, flexible control practice performed according steps shown Fig. 2-5. This prevent problems quality that caused change. Also asks agreement customers beforehand, change important one. Standardization Distribution Information Standardization being carried work steps, content work, maintenance inspection equipment. This done order produce semiconductor devices with stable quality. such kind standardization, experience distribution information with regard failures inadequacies contributed greatly. distribution system shown Fig. 2-6.
Fig. 2-6: Information Flow System
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2.3.3 HUMAN FACTORS Education Training Within NEC, Deployment (OJD) considered basis development human resources. Accordingly, programs education training employees regardless different hierarchical level functional ability have been developed employees, managers directors. programs systematically used develop various abilities each member company. Starting NEC, employees educated obtain fundamental knowledge. They learn about special technologies used company, have understand quality control industrial engineering. employess trained improve their abilities manage tasks, develop their capabilities foreign languages. this purpose, programs prepared provide collective education within company, have employees attend outside seminars, train people job, provide chances self-education. Small Group Activities part quality management activities company whole, small group activities, like Zero Defect groups (ZD) Quality Circles (QC), used. high goals groups defined members. Cooperation communication most important tools solve problems improve actual status. strongly promotes these activities. following programs provided stimulate enlighten small groups toward recognition problems development desires improve quality. Proposal program There different proposal programs established NEC. Quite popular programs which cover improvement current problem, like modified working processes, well proposals covering ideas. Each proposal checked conscientiously. Once proposal excepted,the related groups established. Publication meetings Improvement ideas published within departments, divisions, sections factories. Reading papers throughout whole company will spread know-how quickly. Wall charts, visible employees certain location show targets status each working group, will, therefore, keep communication with whole community. This allows fast implementation continuous improvements creates again ideas. Award Reward system Running award /reward system achieving goals, proposing useful ideas useful effects, will motivate people participate continuous improvement process activities company.The best yearly competition will present their ideas improvements during company-wide congress fight award have best idea throughout entire company.
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Group Formation Improvement programs, carried small group activities, must essentially practiced each every employee. Such activities most efficient when targets evaluated related work force. Support management must provided, too, management must driving factor topics quality. golden rule small group activities that group must have target. Several groups contribute common target. group size will exceed people, basically. Specially educated supervisors assist group function consultant. Additionally, group selected represent their members takes responsibility. item group selected among improvement issues, found experiences from inspections, test results, execution specifications, etc. When detailed data past available, used prepare Pareto diagram, which consulted selction most effective quality improvements. problem cannot numbers, group evaluates those items which might solve problem their means, improvement targets settled item item. Group Meetings necessary that entire group meets schedules evaluate solutions make autonomous decisions. supervising person should attend meeting whenever possible. This necessary because consultant should motivate group members continued efforts promote cooperation communication within group make their program success. this way, entire group deepen understanding towards constant quality improvement, like programs, whole and, same time, maintain group's consciousness terms quality, optimization methods, cost reduction. Results Group Activities results group activities shown relation targets settled, continuously. Improvement activities which checked inspection results, i.e. statistical numbers, computed commonly displayed. least everybody related problem will conscious what going might identify influence improvements made, even made. detailed data group activities aggregated day, week, month written into control charts. continuity process data traced months. quite easy data control chart when data from quality control process taken. similar way, also "indirect" items, like quality documents, specifications, drawings, measured comparison between actual status targets, results judgement relative numbers computed traditional way. Anyhow, such method, full expert knowledge hugh experiences related items essential.
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Programs Quality Management Quality control once desk theory technicians and, such, only applied manufacturing processes. Today, required execute total quality control (TQC), aimed qualitative improvement kinds work company. fact that involves divisions enterprise such, practiced method management company culture, term also translated total quality culture total quality management (TQM). Everybody admits that indispensable. remains, however, that whoever starts TQC, which easy speak meets with difficulties that hard negotiate. like expecting much gain only little from quality control ideology. program, which starts from plain logic that work must done without error, reason arouse antipathy. Thus could have entire organization participating program without resistance against program therefore considered approach towards where achieved real sense. Where organizations were established, programs improve organizational structures quality level. There question that once program started, that existing quality control system might absorbed newly started program. case NEC, program founded quality control system which proceeds. More, program reached areas which quality control system could never permeate before. believes that such quality improvement programs strengthen position entire organization. this sense, interprets programs only spiritual campaign, even more challange remarkable improvements concentrating company-wide capabilities from management line worker. 2.3.4 DISTRIBUTING PRODUCTS Quality Control Activity Distributed Products realizes that maintaining quality assurance distribution stage indispensable maintaining improving quality final market. Based this fact, implemented system which identifies requirements divisions involved distribution. defines "distribution defect" defect "part" wrong action detected distribution stage customers. divisions involved circulate PDCA (Plan-Do-Check-Action) activity controlling this problem. Table shows some examples quality maintenance activities distribution area. Considering total activity distribution quality control, information defect distribution managed EDP, relayed back divisions involved then used index improvement activity.
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Fig. Distribution Flow Semiconductor Devices
Table 2-3: Examples Distribution Quality Maintenance Activities
Classification Storage environment Requirements Control temperature humidity storage place Environmental atmosphere, place storage First-in, first-out policy Management storage shelf Limiting stacking parts desk Control counters Standard operation Verification Controlling humidity workplace Preparation anti-static facilities
Storing
Shipping
Measures against
Efficient Distribution Procedures diversification semiconductor devices, increased variation market reqirements well products, smaller sizes product trend. They contribute deterioration efficiency distribution potential threat more human errors. cope with such change conditions distribution process, promoting efficient handling. Storage distribution materials organized system. Labour reduction automatization such jobs management storing shipping, automatic printing labels, distribution transfer systems main targets.
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example improvement made code system. Fig. shows range applications. Range distribution parts materials within NEC. code used transfer slips product labels linked with system. this way, basically possible check products each process, while omitting key-in operation thus avoiding fails.
Production Facility
Warehouse Distribution Center
Sales Company, Distributor
Customer
Range
Range
Fig. 2-8: Code Application Range
addition internal process, range takes relation between customer into consideration. prepared support code labels shipment high volume orders customized products. application EIAJ standards offered. RELIABILITY ASSURANCE
goes without saying that semiconductor devices purchased customers must satisfy requirements initial stage usage. cause ideally products should perform their defined functions through periods without problem. reliability means that product perform required functions under given condition given period, reliability testing measure check conformance this requirement, basically defined customer's application. practise, reliability testing means apply accelerated tests simulate stress during products life cycle. Standard Reliability Tests simulate conditions stress applied device phases usage, applies standardized reliability tests samples. available, test according national international standards, like MIL-STD 750, MIL-STD 883C C7022. mechanisms covered properly, defined company-wide internal standards. tests correlate certain failure mechanisms applied device qualifications well monitoring reliability tests.
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Table 2-4: Examples Reliability Test Integrated Circuits
Test Items Standard C7022 Method Condition 1010 Condition 1011 Condition 2007 Condition 2002 Condition Test Conditions MIL-883C Method 5°C, sec. Failure Criteria Min. Sample Size
Soldering Heat
Temperature Cycling Thermal Shock
cycles, 30min. each
spec according electrical characteristics standard gross leak, fine leak less than 10-8 [atm sec] (note1)
Condition A-10
cycles, 0°/100°C min. each 20-2000Hz, min., each direction (X,Y,Z) 1500G, 0.5ms, times, each direction (X,Y,Z)
Variable Oscillation
Mechanical Shock
Condition Condition
Constant Acceleration
2001 20000G, 1min., Conditition each directtion (X,Y,Z) 2003 sec., coverage
Solderability
Bending Strength
2004 3times, pins Condition 1008
breakage slackering
High Temperature Storage Life Test High Temperature Operating Life Test (note4) Intermittent Life Test (note2)
1005
125°C, 150°C, 175°C spec >1000 hours according electrical >125°C, >1000 hours characteristics load/voltage device standard On/off frequency individually 85°C, rel. humidity >1000 hours 125°C, 100% rel.humidity atm., hours
1006
High Temperature, High Humidity Life Test (note2) Condition Pressure Cooker Test (PCT) (note2) Temperature Cycling (note3) Electrostatic Discharge (note3) 1010
>100 cycles,30min. each
3015
C=200pF, C=100pF, R=1.5K
Note Note Note Note
Applied only hermetically sealed IC's Applied only plastic packaged IC's Applied only qualification tests Continious qualification intermittent operation chosen depending kind product
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Family Concept target tests verify reliability most efficient way. Therefore, tests carried product process families. test families defined certain rules, like design rules, semiconductor processes, etc. monitoring tests, most critical devices concerning certain parameters selected NEC's experience dominating failure mechanisms process target application, cover whole family. this sense, tested devices represent worst-case parameters process designs. Reliability Monitoring quality well reliability cannot tested into product, reliability tests only verify previous steps made. Testing checking during whole process from design final product test measure continuity process. Standardization design rules production processes assist such trend. this sense, continuously carried reliability tests, even done with small sample sizes, will represent overall quality better than incoming test data. basically performs monitoring reliability testing monthly basis. Data published quarterly. (Please refer also chapter 3.4) EXAMPLES PRODUCT IMPROVEMENTS
Constant improvement concerning real market application requirements well modification products changing environment important targets quality reliability policy. Beside constant improvements coming from experiences made products processes directly production process, application range specifies performance final product. Taking this fact into account, implements requirements final product constant improvement actions since long time. following will show some example which related application oriented improvements. 2.5.1 APPLICATION ORIENTED QUALITY GRADES quality assurance means guarantee that products will meet defined requirements, each quality assurance program related application target. Concerning semiconductor devices this will mean even more that product will operate reliable under specific conditions. target produce semiconductor devices that satisfactory customer every respect. Therefore, stages from planning design mass production shipping, determined points controlled conditions necessary keeping quality semiconductor devices. these steps together quality assurance programs. order cope with different requirements customer applications, implemented number different quality assurance programs past. Each program answer requirements specific application range. Actually, three different grades defined:
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Standard Level standard level defined normal operating conditions which represented fundamental quality assurance program. Most devices produced this grade. intention this grade cover applications used office automation, communication equipment, industrial control, consumer products. environmental conditions range, people call "normal". Special Level contrast standard level which prepared first, so-called "Special Level" developed satisfy higher requirements certain applications, requested customers. related quality assurance programs defined main items specially considered comparison standard level: Duration reliability test Conditions screening Conditions inspection Period storing production records similar data
details quality assurance program depend individual device, general comparison items above made Table LSIs such microcomputers, memories, ASIC, etc. Devices "special level" ones used equipment that require wide operational temperature range high endurance limits against environmental conditions. failure could endanger safety system itself, when devices used such equipment, measures such fail-safe design facility debugging taken conjunction with "special level" product. "standard level" devices considered used such equipment, asks customer spend more careful considerations. Specific Level most sensitive applications those where human life strongly affected malfunction system. Therefore, example, aerospace machines, submarine relays, atomic power control units, life sustaining equipment etc., require such very high reliability each device. normally does produce devices such purposes. customers wish devices such applications, prepared discuss quality assurance agreements, develop individual quality assurance program related target application. such cases, please contact before ordering. quality grade devices that require individual quality assurance program called "specific level."
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Table 2-5: Main Difference between Standard Level Special Level
Item Standard Grade Special Grades High Temperature Storage Test High Temperature Bias Test High Temperature High Humidity Test Pressure Cooker Test Temperature Cycling Test Quality control production process Screening Outgoing inspection Storage period production records
Note:
2000 hours 2000 hours 2000 hours hours >300 cycles
1000 hours 1000 hours 1000 hours hours >100 cycles Standard Standard burn-in
Special control when necessary Extended burn-in
Room temperature High temperature selection years years
means that related devices intended systems indirectly related control transportation machines (trains, automobiles) similar equipment means that related devices intended systems directly related control transportation machines (trains, automobiles), traffic signals, leakage detectors, other safety equipment.
2.5.2 GENERAL DESIGN PRECAUTIONS Latch-up Precautions Going down finer structures, latch-up must prevented each possible design step. step design devices. NEC, guard rings channel stoppers were mainly introduced catch carriers generated environment.
Fig. 2-9: Scheme guard ring against latch-up Cross section view CMOS chip
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Fig. shows briefly function guard ring. Assuming that trouble coming pins buffers strong enough resist their impedance, precautions must taken concerning inner circuitry. That where guard ring implemented. doped walls, each polarity, between buffers internal logic. Most carriers that induced interference will caught guard ring. Additionally, further preventions against latch-up problems external circuit design should made. When power supply turned sometimes overshoot voltage will induced impedance unit. filter capacitance about 0.1µF should attached between power supply lines ground near CMOS device. When input voltage higher than supply voltage less than ground, insert diode resistor between input terminal related power supply line, like shown fig. 2-10 below.
Fig. 2-10: Countermeasure against over-/under-shoots
When multiple supply voltages used, sure sequence power-up power-down properly. precaution, serial resistor should used between different devices limit current case trouble.
Fig. 2-11: Precaution multiple supply voltages
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Driving inductance (like relay motor) from CMOS device's output transistor, input voltage CMOS device might higher than actual This might happen fact that voltage drop generated switching current. Capacitors should inserted decrease power supply's impedance.
Fig. 2-12: Countermeasure against voltage drop inductive load
Precautions Beside latch-up effect CMOS devices, protection against electrostatic discharge important semiconductor devices. interface structure device, this extend, influences failure rate quite much. similar way, like described latch-up before, interface structure must limit current flow into device high voltages regardless polarity, certain limit. Several types protection circuits commonly used. output circuits impedance supply voltage nature, pure input circuitry must protected only. principle most popular state-of-the-art circuits shown below. usage each type depends kind circuitry protect. Depending process technology design rules, several derivates exist.
Fig. 2-13: Examples protection circuits: symmetric diodes asymm
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