QAMP VDDD VDDF VDDP IAMP VDDA IAmp QAmp SCAN Limiter DC

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QAMP VDDD VDDF VDDP IAMP VDDA IAmp QAmp SCAN Limiter DC

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Data Sheet XE1202
QAMP VDDD VDDF VDDP IAMP VDDA
IAmp
QAmp SCAN
Limiter DCLK Demod. Sync. DATAOUT
Limiter
Pattern Recognition Buff. Phase Shifter Prog. divider RSSI
PATTERN MODE MODE
Control Logic modulator Synthesizer Oscillator Clock
MODE
RFOUT
DATAIN
VSSD
VSSF
VSSF
VSSP
VSSP
CLKOUT
TSUPP
TVCO
VSSA
XE1202
433MHz 868MHz 915MHz Low-power, integrated transceiver
GENERAL DESCRIPTION
XE1202 single chip transceiver operating 433, 915MHz license free (Industry Scientific Medical) frequency bands. highly integrated architecture allows minimum external components while maintaining design flexibility. major communication parameters programmable most them dynamically set. XE1202 offers unique advantage narrow-band wide-band communication, this without need modify number parameters external components. XE1202 optimized power consumption while offering high output power channelized operation suited both European (ETSI-300-220) North American (FCC part regulatory standards
PRODUCT FEATURES
Programmable output power: +15dBm High reception sensitivity: down -113dBm power consumption: RX=14mA; 48mA output power Supply voltage down 2.7V Wide band operation: 400kHz channels data rates 76.8kbps, coding Narrow band operation: down 25kHz channels data rates 4.8kbps, coding On-chip frequency synthesizer with steps 500Hz Continuous phase 2-level modulation Incoming data pattern recognition Built-in Bit-Synchronizer incoming data clock synchronization recovery RSSI (Received Signal Strength Indicator) (Frequency Error Indicator)
APPLICATIONS
Narrow-band wide-band security systems Voice data over link Process building control Access control Home automation Home appliances interconnection
ORDERING INFORMATION
Part number XE1202I027 Temperature range -40°C +85° Package LQFP44
Solu tion eles
XEMICS e-mail: info@xemics.com web: www.xemics.com
VSSA
Data Sheet XE1202 Table Contents General Description. Applications product features Ordering information. Functional Block Diagram description Electrical Characteristics Absolute Maximum Operating Ranges. Specifications. 3.2.1 Operating Range 3.2.2 Electrical Specifications Description. Detailed description 4.1.1 Receiver. 4.1.2 High sensitivity high linearity: A-mode, B-mode. 4.1.3 RSSI. 4.1.4 Frequency Error Indicator 4.1.5 Transmitter. 4.1.6 Pattern recognition. 4.1.7 Clock Output external processor Interface definition, Principles operation Serial Control Interface Configuration Status registers 5.2.1 RTParam configuration register. 5.2.2 FSParam configuration register 5.2.3 DataOut register 5.2.4 ADParam configuration register 5.2.5 Pattern register Operating Modes 5.3.1 Standard power sequence receiver transmitter 5.3.2 Single step sequence receiver Transmitted Data Interface Received Data Interface Pattern Recognition Interface Clock Output Interface Default settings power-up. Application Information Matching network receiver. Matching network transmitter tank Loop filter frequency synthesizer. Reference crystal frequency synthesizer Decoupling capacitances. Packaging information.
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Data Sheet XE1202 XE1202 single-chip solution integrated circuit intended cost transceiver establish frequency-agile, half-duplex, bi-directional link, with non-return zero data coding. device available LQFP44 package designed provide fully functional multi-channel transceiver. intended applications 433- 868MHz European band North American 902-928MHz band. single chip transceiver operates down provides power consumption solutions battery-operated power sensitive applications. Thanks external components count, XE1202 ideal small size, lowcost links. reference board design tunable components, which facilitates high volume cost sensitive production. XE1202 easily interfaced controller such XEMICS' XE8000 Series ultra low-power microcontrollers. XE1202 serial control registers programmed manages communication protocol.
Functional Block Diagram
QAMP VDDD VDDF VDDP IAMP VDDA
IAmp
QAmp SCAN
Limiter DCLK Demod. Sync. DATAOUT
Limiter
Pattern Recognition Buff. Phase Shifter Prog. divider RSSI
PATTERN MODE MODE
Control Logic modulator Synthesizer Oscillator Clock
MODE
RFOUT
DATAIN
VSSD
VSSF
VSSF
VSSP
VSSP
CLKOUT
TSUPP
TVCO
VSSA
VSSA
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Data Sheet XE1202
description
NAME MODE(1) MODE(0) VSSF VSSP VSSP RFOUT VDDP TVCO VSSF VDDD VSSD TSUPP SCAN TMOD[0] TMOD[1] VSSA VSSA VDDA QAMP IAMP TMOD[2] TMOD[3] TIBIAS CLKOUT DCLK DATAOUT DATAIN PATTERN MODE(2) DESCRIPTION Transmit/Receive/Stand-by/Sleep Mode Select Transmit/Receive/Stand-by/Sleep Mode Select Chip Enable Analog Ground Input Input Power Amplifier Ground Power Amplifier Ground Output Power Amplifier Supply Voltage Test Input (connected normal operation) Analog Supply Voltage Tank Tank Analog Ground Loop Filter Digital Supply Voltage Digital Ground Test Circuit Supply Voltage (connected normal operation) Scan Test Input (connected normal operation) (connected normal operation) (connected normal operation) (connected normal operation) Analog Ground
Xtal Input external clock
Analog Ground Reference Xtal Analog Supply Voltage
Output low-pass filter Output low-pass filter
(connected normal operation) (connected normal operation) (connected normal operation) Digital Supply Voltage Configuration Register Serial Output Configuration Register Serial Input Configuration Register Serial Clock
Output clock reference frequency divided
Digital Ground Recovered Received Data Clock Received Data Transmit Data
Output pattern recognition block
Transmit/Receive/Stand-by/Sleep Mode Select
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Data Sheet XE1202
Electrical Characteristics
Absolute Maximum Operating Ranges
Stresses above those values listed below cause permanent device failure. Exposure absolute maximum ratings extended periods affect device reliability. Symbol VDDmr Description Supply voltage Storage temperature Min. -0.5 Max. Unit
3.2.1
Specifications
Operating Range Symbol VDDop TRop CLop Description Supply voltage Temperature Load capacitance digital ports Min. Max. Unit
3.2.2 Electrical Specifications table below gives electrical specifications transceiver under following conditions: Supply Voltage temperature 2-level without pre-filtering, MHz, kHz, rate kb/s, BWSSB kHz, output synchronizer), matched impedances, environment defined section unless otherwise specified. Symbol IDDSL IDDST IDDR IDDT Description Supply current sleep mode Supply current standby mode Supply current receiver mode Supply current transmitter mode sensitivity Frequency deviation 3.2.2.1 3.2.2.2 RFOP RFOP A-mode B-mode Quartz oscillator MHz) running Conditions funw A-mode B-mode 0.85 -113 -102 1.10 16.5 -110 Unit
Programmable
IIP3
Co-channel rejection Input intercept point (from input base-band filter output)
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Data Sheet XE1202 Symbol Description Receiver input level Base band filter bandwidth Programmable Conditions RFOP10 RFOP1 RFOP20 RFOP2 Synthesizer frequency range Programmable Each range with external components From quartz oscillator running From frequency synthesizer running From frequency synthesizer running "RTParam_WBB" From quartz oscillator running From frequency synthesizer running
RTParam_WBB=0
19.2 38.4 76.8
Unit kb/s kb/s kb/s kb/s kb/s
Adjacent channel rejection rate
funw Pw=-107 dBm, A-mode Programmable
RFOP
output power
Programmable
TS_BBR TS_TR TS_BB0
Receiver processing wake-up time (first step) Transmitter wake-up time Receiver Front-End wake-up time Frequency synthesizer wakeup time Receiver Front-End wake-up time Frequency synthesizer switching time RSSI wake-up time Quartz oscillator wake-up time wake-up time (RTParam_Fsel counting duration (RTParam_Fsel
TS_FS TS_BB2
TS_FSW TS_RS TS_OS TS_FE
Between channels from each other From whole receiver running mode From receiver running RTParam_Fsel RTParam_Fsel
20/BR 4/BR
XTAL FSTEP
Quartz oscillator frequency Frequency synthesizer step
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Data Sheet XE1202 Symbol VTHR Description Equivalent input thresholds RSSI Conditions A-mode,low range:VTHR1
VTHR2 VTHR3
-105 -100
Unit
A-mode,high range:VTHR1
VTHR2 VTHR3
FERR
Error threshold Spurious emission receiver mode Digital input level high Digital input level Digital output level high Digital output level
Pw=-100 dBm, A-mode RTParam_Fsel
Description
XE1202 direct conversion (0-IF) half-duplex data transceiver. includes receiver, transmitter, frequency synthesizer some service blocks. circuit operates frequency ranges (433MHz, 868MHz, 915MHz) uses 2-level modulation. typical application, XE1202 programmed microcontroller through 3-wire serial write read from configuration registers. circuit consists main functional blocks: receiver converts incoming 2-level modulated signal into synchronized stream. receiver composed low-noise amplifier, down-conversion mixers, baseband filters, baseband amplifiers, limiters, demodulator synchronizer. synchronizer transforms data output demodulator into glitch-free stream DATAOUT generates synchronized clock DCLK used easily sample DATAOUT signal without loading external processor with heavy signal processing. addition, receiver includes Received Signal Strength Indicator function (RSSI), Frequency Error Indicator function (FEI) that gives indication about frequency error local oscillator, pattern recognition function detect programmable reference word incoming stream. bandwidth base-band filters, frequency deviation expected incoming signal well bitrate this stream programmable. transmitter performs modulation carrier input stream transmission modulated signal. modulation made directly through frequency synthesizer. on-chip power amplifier then amplifies signal. output power programmable among possible values. frequency deviation rate transmit signal same those programmed receiver section. frequency synthesizer generates local oscillator (LO) signal receiver section well modulated signal transmitter section. core synthesizer implemented with structure. frequency programmable with step frequency bands, 433-, 868-, 915-MHz. This section includes crystal oscillator whose signal reference PLL. This reference frequency divided made available CLKOUT serve clock signal external processor. control block generates control signals according setting configuration registers. service block performs necessary functions circuit work properly, including internal voltage current sources.
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Data Sheet XE1202
Detailed description
4.1.1 Receiver outputs receiver signals DATAOUT DCLK. When "RTParam_Bits" (see Configuration register section below), synchronizer turned output signals respectively output stream sampling clock. function synchronizer remove glitches from stream DATAOUT provide output clock DCLK. value DATAOUT valid rising edge DCLK. proper behavior synchronizer, three conditions must satisfied: received data must start with preamble bits synchronization; this preamble must sequence sent alternatively, after that, incoming stream must have least transition from from every bits, accuracy rate must better than (assuming reference Xtal oscillator exactly MHz)
When "RTParam_Bits" "0", synchronizer turned off, signal DATAOUT output demodulator. this case DCLK used value "low". condition modulation index proper behavior demodulator where frequency deviation rate.
4.1.2 High sensitivity high linearity: A-mode, B-mode receiver operated different modes that provide highest sensitivity highest linearity. This programmable with register "RTParam_Rmode" (see Configuration register section below). A-mode: receiver highest sensitivity (see parameter) B-mode: receiver highest linearity (see IIP3 parameter)
4.1.3 RSSI When activated, this function provides Received Signal Strength Indication based signal output base-band filter. activate this function, "RTParam_RSSI" (see Configuration register section below) must "1". When activated, status 2-bits data stored register "DataOut_RSSI", which read through serial control interface. meaning this status information given table below, where VRFFIL differential amplitude equivalent input signal when receiver operated A-mode. thresholds VTHRi thresholds output base-band filter divided gain between input receiver this output. DataOut_RSSI Description VRFFIL VTHR1 VTHR1 VRFFIL VTHR2 VTHR2 VRFFIL VTHR3 VTHR3 VRFFIL
Table RSSI status description
ranges with three VTHRi defined selected with flag "RTParam_RSSR". time diagram RSSI measurement given next figure. When RSSI function been activated signal strength periodically measured result stored register "DataOut_RSSI" each rising edge DATAIN. TS_RS wake-up time required after function been activated valid result.
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Data Sheet XE1202
RTParam_RSSI
rssi_out
VAL1
VAL2
VAL3
VAL4
datain
DataOut_RSSI
VAL2
VAL4
TS_RS
Figure RSSI measurement timing diagram applications where time needed first right result from RSSI possible, this time minimized waking RSSI during mode instead which condition definition TS_RS page (for definition modes, pages 20). 4.1.4 Frequency Error Indicator When activated, this function provides information about frequency error local oscillator compared with input carrier frequency. condition modulation index proper behavior function where frequency deviation rate. There modes operation this function selected "RTParam_Fsel" (see Configuration register section below). IMPORTANT NOTE guarantee proper behavior FEI, frequency offset signal bandwidth (ssb) should lower than baseband filter bandwidth (single sided). That foffset SignalBW Baseband_filterBW where foffset difference between carrier frequency frequency, SignalBW signal bandwidth (single sided) equal bitrate divided frequency deviation (Bitrate/2 Frequency Deviation), Baseband_filterBW channel filter bandwidth defined RTParam_BW parameter (see Configuration Registers section below). 4.1.4.1 "RTParam_Fsel" activate function, "RTParam_FEI" must "1". When activated, function provides 2bits status stored register "DataOut_FEI". meaning this output given following table, where internal local oscillator frequency, carrier frequency received signal. DataOut_FEI Meaning fLO-fRF fERR (fLO-fRF) fERR (fLO-fRF) -fERR
Table status description
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Data Sheet XE1202 threshold fERR FERR where rate FERR ratio given electrical specifications. example, rate kb/s with FERR 0.5, fERR kHz. This function works properly only input signal preamble defined under Receiver section above frequency error detected lower than kHz. time diagram measurement quite similar RSSI measurement, given figure below. When activated frequency error periodically measured result stored register "DataOut_FEI" each rising edge DATAIN. TS_FE wake-up time required after function been activated valid result.
RTParam_FEI
fei_out
VAL1
VAL2
VAL3
VAL4
datain
DataOut_FEI
VAL2
VAL4
TS_FE
Figure measurement time diagram, RTParam_Fsel
4.1.4.2 "RTParam_Fsel" activate function, "RTParam_FEI" must "1". When activated rising edge DATAIN, function provides 8-bits status stored register "DataOut_FEI". timing diagram this measurement described figure below. function activated rising edge signal when RTParam_FEI "1". Then, internal counter activated rising edge DATAIN. After duration TS_FE (see Electrical Specifications), counter stopped content stored register DataOut_FEI. maximum delay between rising edge DATAIN first clock internal counter 1/(16*BR), where rate.
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Data Sheet XE1202
RTParam_FEI
Demodulated ffdemod_out data
B0+1
B0+2
B0+3
B0+4
datain
counter_out
DataOut_FEI
TS_FE
Figure Time diagram measurement when "RTParam_Fsel" (the number transitions "counter_out" illustration only)
4.1.5 Transmitter output power power amplifier programmable four values with register "RTParam_Tpow" (see Configuration register section below), shown table below, where RFOPi given Electrical Specifications section RTParam_Tpow Output power RFOP10 RFOP1 RFOP20 RFOP2
type modulation frequency modulating stream programmable through RTParam_Filter: input stream directly applied frequency synthesizer without pre-filtering (RTParam_Filter=0) input stream pre-filtered before being applied frequency synthesizer; with this filtering, each edge stream linearly smoothed with staircase transition (RTParam_Filter=1) This illustrated next page where DATAIN input stream transmitted.
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Data Sheet XE1202
tbit
datain
filtering freq_synth
staircase filtering freq_synth
trise
Figure Modulation without with pre-filtering
characteristic smoothing filter ratio trise/tbit. value this ratio programmable with register "RTParam_Stair", shown following table. FSParam_Stair trise/tbit
4.1.6 Pattern recognition XE1202 includes pattern recognition function. When "ADParam_Pattern" (see Configuration register section below) this feature turned provided synchronizer turned (the pattern recognition feature doesn't work synchronizer turned off). this case, incoming stream compared with pattern stored "Pattern" register. length this pattern bits, defined "ADParam_Psize". When comparing streams errors, defined "ADParam_Psize" allowed detect match. PATTERN output driven output this comparator. "high" when match detected, otherwise "low". When feature disabled, PATTERN output "low"
4.1.7 Clock Output external processor When "RTParam_Clkout" high, frequency divider depending "ADParam_Clkfreq" (see Configuration register section below), embedded XE1202 provides CLKOUT clock signal external circuitry. input frequency 39.0 reference frequency, possible clocks available CLKOUT 1.22, 2.44, 4.87, 9.75 MHz. When XE1202 Sleep Mode (MODE[2:0] 000), this clock stopped. D0211-105
Data Sheet XE1202
Interface definition, Principles operation
Serial Control Interface
3-wire bi-directional (SCK, used program XE1202 read data from input signals, example generated microcontroller. output signal controlled XE1202. write mode, falling edge signal, logic data line written into internal shift register. read mode, rising edge signal, data line become valid should sampled next falling edge SCK. signal must during whole write read sequences. write mode actual content configuration register updated rising edge signal. Before this, data stored temporary registers whose content does affect transceiver settings. time diagram write sequence given figure below. sequence initiated when Start condition detected, that when signal during period SCK. next read/write (R/W) which should indicate write operation. next bits address control register A[4:0] accessed, first. Then, next bits data written register. sequence ends with stop bits "1". data should change rising edges SCK, sampled falling edge SCK. After stop bits, data transfer terminated, even line stays "1". After this line should least clock cycle before write read sequence start. doing this, users write multiple registers raw, there need raise signal between. duty cycle must between maximum frequency this signal MHz. Over operating supply temperature range, set-up hold time falling edge 200ns.
Figure Write sequence into configuration register
START
A(4)
A(1)
A(0)
D(7)
D(6)
D(3)
D(2)
D(1)
D(0)
STOP
STOP
time diagram read sequence given figure below. sequence initiated when Start condition detected, that when signal during period SCK. next read/write (R/W) which should indicate read operation. next bits address control register A[4:0] accessed, first. Then data from register transmitted pin. data become valid rising edges should sampled falling edge SCK. After this data transfer terminated. line must stay high least clock cycle start write read sequence. maximum current drive 2.7V, maximum load CLop.
START
A(4)
A(0)
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
Figure Read sequence into configuration register
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Data Sheet XE1202 When serial interface used read write operations, both should "1". Except read mode, "0".
Configuration Status registers
XE1202 series configuration registers programmable through serial control interface described above. Their name, size, address description listed table below. size these registers bytes. Their byte address address, A[4:0]. addition, there register, DataOut, from which users read various transceiver status information. Name RTParam FSParam Size Byte Address 00000 00001 00010 00011 00100 00101 00110 01000 01001 01010 01011 Description Receiver transmitter parameters registers Frequency parameters
DataOut ADParam Pattern
Transceiver data register Additional parameters Reference pattern "pattern recognition" function
addition, bytes addresses A[4:0] 10000 11111 reserved test purpose Name Test Size Byte Address 10000 11111 Description Test registers (reserved)
bits that referred "reserved" this section should "0". 5.2.1 RTParam configuration register Name RTParam_Rmode Bits Byte Address 00000 Description Receiver modes: A-mode (high sensitivity) B-mode (high linearity) synchronizer on/off: off; RSSI on/off: off; on/off: off; Bandwidth filter:
RTParam_Bits RTParam_RSSI RTParam_FEI RTParam_BW
00000 00000 00000 00000
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Data Sheet XE1202 Name RTParam_Tpow Bits Byte Address 00000 Description Transmitter output power: Source reference frequency: on-chip crystal oscillator external signal Receiver wake-up type selection "Boost" power sequence Standard power-up sequence Pre-filtering stream transmitter mode: filtering; filtering Selection block: uses demodulator uses correlators Rise fall time when RTParam_Filter duration duration Inhibition modulation transmitter mode: modulation; modulation Range RSSI: range; high range Enable CLKOUT output: signal CLKOUT clock signal available CLKOUT 9.75 down 1.22 (39MHz divided
RTParam_Osc
00001
RTParam_WBB
00001
RTParam_Filter
00001
RTParam_Fsel
00001
RTParam_Stair
00001
RTParam_Modul
00001
RTParam_RSSR RTParam_Clkout
00001 00001
5.2.2
FSParam configuration register Name FSParam_Band Bits Byte Address 00010 Description Frequency band: valid Frequency deviation: D0211-105
FSParam_Dev
00010
Data Sheet XE1202 Name FSParam_BR Bits Byte Address 00010 Description rate: kb/s kb/s 19.2 kb/s 38.4 kb/s 76.8 kb/s others valid frequency 2's-complement representation: 00.0 middle range 0X.X higher than middle range 1X.X lower than middle range byte pos. 00011 byte pos. 00100
example below
FSParam_Freq
00011 00100
Example frequency setting FSParam_Freq Byte Address 00011 Byte Address 00100 Resulting setting
Note: reference frequency 39.0
00000000
00000000
where depends selected frequency band (see FSParam_Band 434.0 433-435 band 869.0 868-870 band 915.0 902-928 band
00000000 00000000 11111111 11111111 5.2.3 DataOut register Name DataOut_RSSI Bits
00000001 00000010 11111111 11111110
Byte Address 00101
Description RSSI output: lowest level level level highest level output: Output up/down counter 2's-complement representation
DataOut_FEI When RTParam_Fsel
00101
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Data Sheet XE1202 Name DataOut_FEI When RTParam_Fsel Bits Byte Address 00101 Description output: frequency frequency frequency high
5.2.4
ADParam configuration register Name ADParam_Pattern Bits Byte Address 00110 Description Pattern recognition on/off: Size reference pattern recognition: bits bits bits bits Number tolerated errors pattern recognition: error error errors errors Frequency CLKOUT: 1.22 (div. ratio: 2.44 (div. ratio: 4.87 (div. ratio: 9.75 (div. ratio: amplifiers on/off: Reserved. Should Inversion output data receiver: non-inverted data inverted data Regulation bandwidth base-band filter on/off: Periodicity regulation bandwidth base-band filter: only start-up receiver each minute long receiver
ADParam_Psize
00110
ADParam_Ptol
00110
ADParam_Clkfreq
00110
ADParam_IQA
00110
ADParam_Res1 ADParam_Invert
00111 00111
ADParam_RegBW
00111
ADParam_Regfreq
00111
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Data Sheet XE1202 Name ADParam_Regcond Bits Byte Address 00111 Description Regulation process bandwidth base-band filter according selected bandwidth: regulation restarted each time bandwidth changed regulation started when bandwidth changed Boosting process base-band filter according selected bandwidth: boosting restarted each time bandwidth changed boosting started when bandwidth changed Selection XOSC modes: lower current consumption mode Reserved
ADParam_WBBcond
00111
ADParam_Xsel
00111
ADParam_Res2
00111
5.2.5 Pattern register this register, users store reference pattern bits (see ADParam_Psize parameter). first byte this pattern always stored byte address A[4:0] 01000. used, byte stored address A[4:0] 01001, reference pattern always address 01000 address 01000, 01001, 01010, 01011 pattern length resp. bits. When compared demodulated stream, last received compared Pattern register. "oldest" received (the first last received bits, depending ADParam_Psize) compared with byte address 01000 (the MSB). Name Pattern Bits Byte Address 01000 01001 01010 01011 Description byte reference pattern byte byte byte
Example pattern recognition with 32-bit pattern Byte Address 01000 10010011 10010011 Byte Address 01001 10101010 10101010 previous bits from demodulator Byte Address 01010 10010011 10010011 Byte Address 01011 10101010 10101010 last received
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Data Sheet XE1202 Example pattern recognition with 8-bit pattern Byte Address 01000 10010011 10010011 previous bits from demodulator last received Byte Address 01001 xxxxxxxx Byte Address 01010 xxxxxxxx Byte Address 01011 xxxxxxxx
Operating Modes
XE1202 main operating modes MODE[2:0] inputs illustrated table below. switch between modes, value inputs MODE[2:0] should modified when signal low. actual change will applied transceiver upon rising edge signal. Over operating supply temperature range, set-up hold time MODE[2:0] rising edge 200ns, while negative pulse duration minimum.
MODE[2:0]
Transceiver Mode Transceiver Mode
Name Sleep mode Standby mode Receiver mode Transmitter mode
MODE(2:0)
Description Reference Xtal oscillator running Xtal oscillator, Frequency synthesizer, Receiver running Xtal oscillator, Frequency synthesizer, Transmitter running
Table XE1202 Main operating modes
5.3.1 Standard power sequence receiver transmitter additional operating modes defined should used when transceiver switched from standby mode receiver transmitter mode. These additional operating modes illustrated Table below Name Receiver mode MODE(2:0) Transmitter mode Description Xtal oscillator, Baseband running (first step) Xtal oscillator, Frequency synthesizer, Baseband running (first step) Xtal oscillator, Frequency synthesizer running
Table XE1202 Additional operating modes
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Data Sheet XE1202
standard power sequence from sleep receiver mode uses "boost" procedure; this "boost" sequence selected setting RTParam_WBB parameter "0". sequence described Figure below Mode Sleep Mode Xtal oscillator running Mode Baseband Xtal oscillator running TS_BBR RTParam_WBB Mode Frequency synthesizer Baseband Xtal oscillator running TS_FS Received data valid Mode Front Frequency synthesizer Baseband Xtal oscillator running TS_BB2 Mode=001 Xtal oscillator running
TS_OS
Figure Standard "boosted" power sequence from Stand Receiver Mode
typical current consumption values during standard power-up sequence from Stand-by Receiver Mode following RTParam_WBB 14.0 11.5 0.85 Mode= Mode= TS_OS Mode=010 TS_BBR Mode =011 TS_FS Mode TS_BB2
Figure Typical current consumption profile during standard "boosted" power sequence from Stand Receiver Mode
standard power sequence from sleep transmit mode described Figure below Transmission Mode Sleep Mode Xtal oscillator running Mode Frequency synthesizer Xtal oscillator running TS_FS Mode =111 Power Amplifier Frequency synthesizer Xtal oscillator running TS_TR Mode=001 Xtal oscillator running
TS_OS
Figure Standard power sequence from Stand Transmit Mode
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Data Sheet XE1202
5.3.2 Single step sequence receiver programming RTParam_WBB "1", boost procedure inhibited. this case, wake-up time longer (TS_BB2
replaced TS_BB0 whose value given electrical specifications).
Transmitted Data Interface
When transmit mode (MODE[2:0] 111), DATAIN signal used input on-chip modulator. DATAIN sampled, duration should match rate setting receiver. Whenever XE1202 used both sides communication link, rate should those defined specifications table (BR). this case rate error should less than compared specified value.
DATAIN (NRZ)
1/BR
Received Data Interface
outputs receiver signals DATAOUT DCLK. When "RTParam_Bits" "1", synchronizer turned output signals respectively output stream sampling clock. value DATAOUT valid rising edge DCLK (see below).
DATAOUT (NRZ) DCLK
When "RTParam_Bits" "0", synchronizer turned off, signal DATAOUT output demodulator. this case DCLK used value "low". maximum current drive DATAOUT DCLK 2.7V, maximum load Clop.
Pattern Recognition Interface
When this feature turned incoming stream compared with pattern stored "Pattern" register. PATTERN output driven output this comparator synchronized DCK. "high" when match detected, otherwise "low". Changes occur rising edge
DATAOUT (NRZ) DCLK PATTERN
N-x=PATTERN[x] N-1=PATTERN[1] N=PATTERN[0]
When feature disabled, PATTERN output "low". maximum current drive PATTERN 2.7V, maximum load Clop.
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Data Sheet XE1202
Clock Output Interface
CLKOUT clock signal 1.22, 2.44, 4.87, 9.75 MHz, depending programming. When XE1202 Sleep Mode (MODE[2:0] 000) when "RTParam_Clkout" low, this clock stopped.
Default settings power-up
Upon power-up RTParam, FSParam, ADParam Pattern registers 00hex power-up, XE1202 Stand-by mode, which means that Xtal oscillator running; furthermore, signal 1.22 (reference frequency divided present CLKOUT. However, internally, RTParam_Clkout low, which means that, nothing changed configuration register, signal CLKOUT will disappear first rising edge furthermore, this first rising edge circuit will mode corresponding signals pins MODE(2:0) this moment. Thus, keep circuit Standy-by mode clock signal present CLKOUT, RTParam_Clkout high during first communication through 3-wire bus, MODE(0) high before first rising edge strongly recommended initialize XE1202 registers right after power-up according application needs.
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Data Sheet XE1202
Application Information
Matching network receiver
schematic matching network input receiver given below
SOURCE
EAGLE ASIC XE1202
components network have satisfy conditions given following table. Name (optional) Min. value Typ. value Min. Q-factor selected frequency range Tolerance
Matching network transmitter
schematic matching network output transmitter given below.
XE1202
OUTPUT
RFOUT
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Data Sheet XE1202 components network have satisfy following conditions: Name (optional) Min. value Typ. value Min. Q-factor selected frequency range Tolerance
tank
tank will implemented with inductor parallel with capacitor. characteristics these components must follows: Name Min. value Typ. value Min. Q-factor selected frequency range Tolerance
Loop filter frequency synthesizer
loop filter frequency synthesizer shown below.
EAGLE ASIC XE1202
components filter have satisfy following conditions: Name Min. value Typ. value Min. Q-factor selected frequency range Tolerance
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Data Sheet XE1202
Reference crystal frequency synthesizer
narrow band applications, where users select lowest frequency deviation narrowest baseband filter, crystal reference oscillator frequency synthesizer must have following characteristics: Name fs(0) fs(T) fs(t) Description Nominal frequency Load capacitance (on-chip) Motional resistance Motional capacitance Shunt capacitance Calibration tolerance Stability over temperature range (-40 Aging tolerance first years Min. value Typ. value 39.0 (fundamental) Max. value
Table Crystal characteristics on-chip oscillator implemented selectable versions: first second latter will allow higher amplitude internal signal with slightly lower consumption. electrical specifications given section 3.2.2 valid provided crystal satisfies specifications given table less demanding applications term signal bandwidth and/or temperature range, possible crystal with larger values fs(0), fs(T), and/or fs(t). this case foffset BWssb should lower than BWfilter, where foffset offset (error) carrier frequency (the fs(0), fs(T), and/or fs(t)), BWssb single side-band bandwidth signal, BWfilter single side-band bandwidth base-band filter. XE1202 used with reference crystal operating harmonic 39.00 MHz. This consequences: oscillator start-up time higher than fundamental mode; extra 1.5k external resistor placed parallel crystal. this case, crystal should have Cload 10pF, ohm, 7pF.
Decoupling capacitances
decoupling capacitance will placed between each pins ground VSS. These five capacitances must have following characteristics: Name Typ. value Tolerance
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Data Sheet XE1202
Packaging information
XE1202 comes 44-lead LQFP package
DATAOUT MODE(2) PATTERN DATAIN DCLK CLKOUT
MODE(1) MODE(0) VSSF VSSP VSSP RFOUT VDDP TVCO
IAMP VDDA VSSA VSSA
TSUPP
VDDF
VSSF
VDDD
VSSD
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SCAN
D0211-105

QAMP VDDD VDDF VDDP IAMP VDDA IAmp QAmp SCAN Limiter DC

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