independent wideband processing channels Processes wideband carriers (
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MSPS Wideband Digital Down-Converter (DDC) AD6636
independent wideband processing channels Processes wideband carriers (UMTS, CDMA2000) single-ended LVDS parallel input ports linear plus 3-bit exponent) running Supports MSPS input using external interface logic 16-bit parallel output ports operating Real complex input ports Quadrature correction correction complex inputs Supports output rate MSPS channel RMS/peak power monitoring input ports Programmable attenuator control external gain ranging programmable coefficient filters channel decimating half-band filters channel programmable digital loops with range Synchronous serial operation (SPI®-, SPORT-compatible) Supports 8-bit 16-bit microport modes I/O, CMOS core User-configurable built-in self-test (BIST) capability JTAG boundary scan
Multicarrier, multimode digital receivers GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA Micro pico cell systems, software radios Broadband data applications Instrumentation test equipment Wireless local loop In-building wireless telephony
FUNCTIONAL BLOCK DIAGRAM
CLKA CIC5 1-32 FIR1 Byp, FIR2 Byp, MRCF DRCF 1-16 CRCF 1-16 Byp,
INPUT MATRIX
A/AI
EXPA [2:0]
CIC5 1-32
CLKB
FIR1 Byp,
FIR2 Byp,
MRCF DRCF 1-16
CRCF 1-16
Byp,
DATA ROUTING
EXPB [2:0] CMOS REAL PORTS
CIC5 1-32
FIR1 Byp,
FIR2 Byp,
DATA ROUTER MATRIX
B/AQ
MRCF DRCF 1-16
CRCF 1-16
Byp,
CLKC
C/CI
CMOS EXPC [2:0] COMPLEX PORTS (AI, CLKD (BI, LVDS PORTS PEAK/ MEAS. CORR.
CIC5 1-32
FIR1 Byp,
FIR2 Byp,
MRCF DRCF 1-16
CRCF 1-16
Byp,
PARALLEL PORTS
D/CQ
CIC5 1-32
FIR1 Byp,
FIR2 Byp,
MRCF DRCF 1-16
CRCF 1-16
Byp,
EXPD [2:0] RESET
CIC5 1-32
FIR1 Byp,
FIR2 Byp,
MRCF DRCF 1-16
CRCF 1-16
Byp,
SYNC [3:0]
NOTE: CHANNELS RENDERED
AVAILABLE ONLY 6-CHANNEL PART
DECIMATION
INTERPOLATION
Figure Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2004 Analog Devices, Inc. rights reserved.
04998-0-001
CLOCK MULTIPLIER
16-BIT MICROPORT INTERFACE
SPORT/SPI INTERFACE
JTAG
AD6636 TABLE CONTENTS
Product Description. Product Highlights Specifications. Electrical Characteristics General Timing Characteristics Microport Timing Characteristics Serial Port Timing Characteristics Explanation Test Levels Specifications. Absolute Maximum Ratings. Thermal Characteristics Caution. Configuration Function Descriptions. Listing Power, Ground, Data Address Buses Timing Diagrams. Theory Operation Input Port Clock Multiplier Gain Control Input Port Monitor Function. Quadrature Correction Block. Input Crossbar Matrix Numerically Controlled Oscillator (NCO) Fifth-Order Filter Half-Band Block. Intermediate Data Router Mono-Rate Coefficient Filter (MRCF) Decimating Coefficient Filter (DRCF) Channel Coefficient Filter (CRCF) Interpolating Half-Band Filter. Output Data Router Automatic Gain Control. Parallel Port Output User-Configurable Built-In Self-Test (BIST) Chip Synchronization Serial Port Control Microport JTAG Boundary Scan. Memory Reading Memory Table. Global Register Input Port Register Channel Register Output Port Register Design Notes Outline Dimensions Ordering Guide
REVISION HISTORY
8/04-Revision Initial Version
Rev. Page
AD6636 PRODUCT DESCRIPTION
AD6636 digital down-converter intended sampling oversampled baseband radios requiring widebandwidth input signals. Optimized demanding filtering requirements wideband standards, such CDMA2000, UMTS, TD-SCDMA, AD6636 designed radio systems that either sampling baseband sampling ADC. AD6636 channels have following signal processing stages: frequency translator, fifth-order cascaded integrated comb filter, sets cascaded fixed-coefficient halfband filters, three cascaded programmable coefficient sum-ofproduct filters, interpolating half-band filter (IHB), digital automatic gain control (AGC) block. Multiple modes supported clocking data into chip provide flexibility interfacing wide variety digitizers. Programming control accomplished serial microport interfaces. Input ports take input data MSPS. MSPS input data supported using input ports (some external interface logic required) internal channels processing tandem. Biphase filtering output data router selected complete combined filtering mode. four input ports operate CMOS mode, ports combined LVDS input mode. maximum input data rate each input port MHz. Frequency translation accomplished with 32-bit complex numerically controlled oscillator (NCO). greater than SDFR. This stage translates either real complex input signal from (intermediate frequency) baseband complex digital output. Phase amplitude dither enabled on-chip improve spurious performance NCO. 16-bit phase-offset word available create known phase relationship between multiple AD6636 chips channels. also bypassed that baseband inputs provided directly from baseband sampling through input ports. Following frequency translation fifth-order filter with programmable decimation between This filter used lower sample rate efficiently, while providing sufficient alias rejection frequencies with higher frequency offsets from signal interest. Following CIC5 sets filters. Each nondecimating filter decimate-by-2 half-band filter. FIR1 filter provides about rejection, while filter provides about rejection. They used together achieve stopband alias rejection, they individually bypassed save power. FIR2 filter provides about rejection, while filter provides about rejection. filters used either together achieve more than stopband alias rejection, individually bypassed save power. FIR1 filters with maximum input rate MSPS. contrast, FIR2 with maximum input rate MSPS (input rate FIR2 filters). programmable filtering divided into three cascaded coefficient filters (RCFs) flexible power efficient filtering. first filter cascade MRCF, consisting programmable nondecimating FIR. followed programmable filters (DRCF) with decimation from They used either together provide high rejection filters, independently save power. maximum input rate MRCF one-fourth clock rate. CRCF (Channel RCF) last programmable filter with programmable decimation from typically used meet spectral mask requirements standard interest. This could RRC, anti-aliasing filter other real data filter. Decimation preceding blocks used keep input rate this stage possible best filter performance. last filter stage chain interpolate-by-2 half-band filter, which used up-sample CRCF output produce higher output oversampling. Signal rejection requirements this stage relaxed because preceding filters already have filtered blockers adjacent carriers. Each input port AD6636 clock used latching onto input data, Input Port clock (CLKA) used also input on-board clock multiplier. output clock used processing filters processing blocks beyond data router following filter. clock programmed have maximum clock rate MHz. data routing block (DR) used distribute data from CICs various channel filters. This block allows multiple back filter chains work together process high bandwidth signals make even sharper filter transitions than single channel perform. also allow complex filtering operations achieved programmable filters. digital provides user with scaled digital outputs based level signal present output digital filters. user requested level time constant loop optimum performance postprocessor. This critical function base station CDMA applications where power level must well controlled going into RAKE receivers. programmable clipping rounding control provide different output resolutions.
Rev. Page
AD6636
overall filter response AD6636 composite combined filter stages. Each successive filter stage capable narrower transition bandwidths, requires greater number cycles calculate output. More decimation first filter stage minimizes overall power consumption. Data from device interfaced DSP/FPGA/baseband processor either high speed parallel ports (preferred) DSP-compatible microprocessor interface. AD6636 available both 4-channel 6-channel versions. data sheet primarily discusses 6-channel part. only difference between 6-channel 4-channel devices that 4-channel version, Channels available (see Figure 4-channel device still same input ports, output ports, memory map. memory section Channels programmed read back, serves purpose.
PRODUCT HIGHLIGHTS
independent digital filtering channels noise performance, spurious performance Four input ports capable MSPS input data rates RMS/peak power monitoring input ports range AGCs before output ports Three programmable coefficient filters, three halfband filters, fixed coefficient filters, fifth-order filter channel Complex filtering biphase filtering (300 MSPS input) combining filtering capability multiple channels Three 16-bit parallel output ports operating clock Blackfin®- TigerSHARC®-compatible 16-bit microprocessor port Synchronous serial communications port compatible with most serial interface standards, SPORT, SPI,
Rev. Page
AD6636 SPECIFICATIONS
Table Recommended Operating Conditions
Parameter VDDCORE VDDIO TAMBIENT Temp Full Full Full Test Level Unit
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics1
Parameter LOGIC INPUTS (NOT TOLERANT) Logic Compatibility Logic Voltage Logic Voltage Logic Current Logic Current Input Capacitance LOGIC OUTPUTS Logic Compatibility Logic Voltage (IOH 0.25 Logic Voltage (IOL 0.25 SUPPLY CURRENTS WCDMA (61.44 MHz) Example1 IVDDCORE IVDDIO CDMA 2000 (61.44 MHz) Example1 IVDDCORE IVDDIO TDS-CDMA (76.8 MHz) Example1, IVDDCORE IVDDIO MHz) Example1, IVDDCORE IVDDIO TOTAL POWER DISSIPATION WCDMA (61.44 MHz)1 CDMA 2000 (61.44 MHz)1 TDS-CDMA, (76.8 MHz)1, GSM, MHz)1, Temp Full Full Full Full Full 25°C Full Full Full Test Level -0.3 Unit CMOS CMOS
+0.8
VDDIO
25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C
input port, channels, relevant signal processing blocks active. turned power savings.
Rev. Page
AD6636
GENERAL TIMING CHARACTERISTICS
Table General Timing Characteristics1,
Parameter TIMING REQUIREMENTS tCLK CLKx Period tCLKL CLKx Width tCLKH CLKx Width High tCLKSKEW CLKA CLKx Skew INPUT WIDEBAND DATA TIMING REQUIREMENTS [15:0] CLKx Setup Time [15:0] CLKx Hold Time tSEXP EXPx [2:0] CLKx Setup Time tHEXP EXPx [2:0] CLKx Hold Time tDEXP CLKx EXPx[2:0] Delay PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER) tDPREQ PCLK Delay tDPP PCLK [15:0] Delay tDPIQ PCLK Delay tDPCH PCLK CH[2:0] Delay tDPGAIN PCLK Gain Delay tSPA PCLK Setup Time tHPA PCLK Hold Time PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE) tPCLK PCLK Period tPCLKL PCLK Period tPCLKH PCLK High Period tDPREQ PCLK Delay tDPP PCLK [15:0] Delay tDPIQ PCLK Delay tDPCH PCLK CH[2:0] Delay tDPGAIN PCLK Gain Delay tSPA PCLK Setup Time tHPA PCLK Hold Time MISC PINS TIMING REQUIREMENTS tRESET RESET Width tDIRP CPUCLK/SCLK Delay SYNC(0, CLKA Setup Time SYNC(0, CLKA Hold Time Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level 6.66 1.71 1.70 tCLK 0.75 1.13 3.37 1.11 5.98 1.77 2.07 0.48 0.38 0.23 4.59 0.90 4.72 4.83 4.88 5.08 6.09 0.87 0.67 Unit
tCLK tCLK
10.74 3.86 5.29 5.49 5.35 4.95
tPCLK tPCLK 8.87 8.48 10.94 10.09 11.49
timing specifications valid over VDDCORE range VDDIO range CLOAD outputs, unless otherwise noted.
Rev. Page
AD6636
MICROPORT TIMING CHARACTERISTICS
Table Microport Timing Characteristics1,
Parameter MICROPORT CLOCK TIMING REQUIREMENTS tCPUCLK CPUCLK Period tCPUCLKL CPUCLK Time tCPUCLKH CPUCLK High Time MODE WRITE TIMING (MODE Control3 CPUCLK Setup Time Control3 CPUCLK Hold Time tSAM Address/Data CPUCLK Setup Time tHAM Address/Data CPUCLK Hold Time tDRDY CPUCLK (DTACK) Delay tACC Write Access Time MODE READ TIMING (MODE Control3 CPUCLK Setup Time Control3 CPUCLK Hold Time tSAM Address CPUCLK Setup Time tHAM Address CPUCLK Hold Time CPUCLK Data Delay tDRDY CPUCLK (DTACK) Delay tACC Read Access Time MODE WRITE TIMING (MODE Control3 CPUCLK Setup Time Control3 CPUCLK Hold Time tSAM Address/Data CPUCLK Setup Time tHAM Address/Data CPUCLK Hold Time tDDTACK CPUCLK DTACK (RDY) Delay tACC Write Access Time MODE READ TIMING (MODE Control3 CPUCLK Setup Time Control3 CPUCLK Hold Time tSAM Address CPUCLK Setup Time tHAM Address CPUCLK Hold Time CPUCLK Data Delay tDDTACK CPUCLK DTACK (RDY) Delay tACC Read Access Time Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level 10.0 1.53 1.70 0.80 0.09 0.76 0.20 3.51 tCPUCLK 1.00 0.03 0.80 0.20 4.50 tCPUCLK 1.00 0.00 0.00 0.57 4.10 tCPUCLK 1.00 0.00 0.00 0.57 4.20 tCPUCLK 6.03 tCPUCLK 6.72 tCPUCLK Unit
tCPUCLK tCPUCLK
6.72 tCPUCLK
5.72 tCPUCLK
timing specifications valid over VDDCORE range VDDIO range CLOAD outputs, unless otherwise noted. Specification pertains control signals: (WR), (RD),
Rev. Page
AD6636
SERIAL PORT TIMING CHARACTERISTICS
Table Serial Port Timing Characteristics1,
Parameter SERIAL PORT CLOCK TIMING REQUIREMENTS tSCLK SCLK Period tSCLKL SCLK Time tSCLKH SCLK High Time PORT CONTROL TIMING REQUIREMENTS (MODE tSSI SCLK Setup Time tHSI SCLK Hold Time tSSCS SCLK Setup Time tHSCS SCLK Hold Time SCLK Delay Time SPORT MODE CONTROL TIMING REQUIREMENTS (MODE tSSI SCLK Setup Time tHSI SCLK Hold Time tSSRFS SRFS SCLK Setup Time tHSRFS SRFS SCLK Hold Time tSSTFS STFS SCLK Setup Time tHSTFS STFS SCLK Hold Time tSSCS SCLK Setup Time tDSDO tHSCS tDSDO SCLK Hold Time SCLK Delay Time Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level 10.0 1.60 1.60 1.30 0.40 4.12 -2.78 4.28 0.80 0.40 1.60 -0.13 1.60 -0.30 4.12 -2.76 4.29 7.95 7.96 Unit
tSCLK tSCLK
timing specifications valid over VDDCORE range VDDIO range CLOAD outputs, unless otherwise noted.
EXPLANATION TEST LEVELS SPECIFICATIONS
100% production tested. 100% production tested 25°C, sample tested specified temperatures. Sample tested only. Parameter guaranteed design analysis. Parameter typical value only. 100% production tested 25°C, sampled tested temperature extremes.
Rev. Page
AD6636 ABSOLUTE MAXIMUM RATINGS
Table
Parameter ELECTRICAL VDDCORE Supply Voltage (Core Supply) VDDIO Supply Voltage (Ring Supply) Input Voltage Output Voltage Load Capacitance ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature under Bias Storage Temperature Range (Ambient) Rating -0.3 +3.6 (not tolerant) -0.3 VDDIO -40°C +85°C 125°C -65°C +150°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL CHARACTERISTICS
256-ball CSP_BGA package: 25.4°C airflow 23.3°C airflow 22.6°C airflow 21.9°C airflow Thermal measurements made horizontal position 4-layer board with vias.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD6636 CONFIGURATION FUNCTION DESCRIPTIONS
INC3
IND4
IND7
CLKD
CLKC
IND11
VDDCORE
IND14
IND15
SYNC1
PBGAIN
PB11
IND0
VDDIO
INC2
IND5
IND6
IND8
IND10
IND12
IND13
INC14
SYNC3
SYNC0
TRST
PBCH2
VDDIO
PB12
EXPA1
EXPD1
INC0
INC1
IND3
INC5
IND9
INC10
INC13
SYNC2
TCLK
PBCH0
PB15
PB10
EXPB0
EXPC2
EXPC1
EXPD0
IND2
INC4
INC7
INC9
INC12
PBCH1
PBIQ
PB14
PB13
PACH1
INA14
INA15
EXPA0
LVDS_RSET
IND1
INC6
INC8
INC11
INC15
PBREQ
PBACK
PCLK
INA12
INA13
EXPB1
EXPC0
EXPD2
VDDIO
VDDIO
VDDIO
VDDIO
PAREQ
INA11
INB13
INB15
EXPB2
EXPA2
VDDCORE
VDDCORE
PAGAIN
PACH0
VDDCORE
INA10
INB12
INB11
INB14
VDDCORE
VDDCORE
PACH2
PAIQ
PAACK
INA9
INB10
INB8
INB9
VDDCORE
VDDCORE
VDDCORE
CLKA
INA8
INA7
INB6
INB7
VDDCORE
VDDCORE
PA12
PA15
CLKB
INA6
INB4
INB1
INB3
DTACK (RDY, SDO) CHIPID2
VDDIO
VDDIO
VDDIO
VDDIO
PCACK
PCCH1
PA13
PA10
INA5
INB5
INB2
INB0 (WR, STFS) (RD, SRFS) EXT_ FILTER CHIPID0
PC12
PCCH0
PA11
INA4
INA3
INA0
(SCS)
(SDI)
PC15
PCCH2
PA14
INA2 CPUCLK (SCLK)
INA1
RESET MSB_ FIRST MODE
SMODE
CHIPID3
PC11
PC10
PCIQ
PCGAIN
VDDIO
CHIPID1
VDDIO
PCREQ
VDDCORE
PC14
PC13
VDDCORE
VDDIO
04998-0-002
GROUND
Figure CSP_BGA Configuration
Table Names Functions
Name Type POWER SUPPLY VDDCORE Power VDDIO Power Ground INPUT (ADC) PORTS (CMOS/LVDS) CLKA Input CLKB CLKC CLKD INA[0:15] INB[0:15] INC[0:15] IND[0:15] EXPA[0:2] EXPB[0:2] EXPC[0:2] EXPD[0:2] CLKA, CLKB Input Input Input Input Input Input Input Bidirectional Bidirectional Bidirectional Bidirectional Input Table Table Table Table Table Table Table Function Digital Core Supply. Digital Supply. Digital Core Ground. Clock Input Port Used clock INA[15:0] EXPA[2:0] data. Additionally, this clock used drive internal circuitry clock multiplier. Clock Input Port Used clock INB[15:0] EXPB[2:0] data. Clock Input Port Used clock INC[15:0] EXPC[2:0] data. Clock Input Port Used clock IND[15:0] EXPD[2:0] data. Input Port (Parallel). Input Port (Parallel). Input Port (Parallel). Input Port (Parallel). Exponent Input Port Gain control output. Exponent Input Port Gain control output. Exponent Input Port Gain control output. Exponent Input Port Gain control output. LVDS Differential Clock LVDS_A Input Port (LVDS_CLKA+, LVDS_CLKA-).
Rev. Page
AD6636
Name CLKC, CLKD INA[0:15], INB[0:15] INC[0:15], IND[0:15] OUTPUT PORTS PCLK PA[0:15] PACH[0:2] PAIQ PAGAIN PAACK PAREQ PB[0:15] PBCH[0:2] PBIQ PBGAIN PBACK PBREQ PC[0:15] PCCH[0:2] PCIQ PCGAIN PCACK PCREQ MISC PINS RESET SYNC[0:3] Type Input LVDS Input LVDS Input Table Table Function LVDS Differential Clock LVDS_C Input Port (LVDS_CLKC+, LVDS_CLKC-). LVDS input mode, INA[0 :15] INB[0 :15] form differential pair LVDS_A+[0:15] (positive node) LVDS_A-[0:15] (negative node), respectively. LVDS input mode, INC[0 :15] IND[0 :15] form differential pair LVDS_C+[0:15] (positive node) LVDS_C-[0:15] (negative node), respectively. Parallel Output Port Clock. Master mode output, Slave mode input. Parallel Output Port Data Bus. Channel Indicator Output Port Parallel Port Data Indicator. Logic indicates data data bus. Parallel Port Gain Word Output Indicator. Logic indicates gain word data bus. Parallel Port Acknowledge (Active High). Parallel Port Request (Active High). Parallel Output Port Data Bus. Channel Indicator Output Port Parallel Port Data Indicator. Logic indicates data data bus. Parallel Port Gain Word Output Indicator. Logic indicates gain word data bus. Parallel Port Acknowledge (Active High). Parallel Port Request (Active High). Parallel Output Port Data Bus. Channel Indicator Output Port Parallel Port Data Indicator. Logic indicates data data bus. Parallel Port Gain Word Output Indicator. Logic indicates gain word data bus. Parallel Port Acknowledge (Active High). Parallel Port Request (Active High). Master Reset (Active Low). Interrupt Pin. Synchronization Inputs. SYNC pins independent channels input ports independent each other. LVDS Resistor (Analog Pin). Design Notes. Loop Filter (Analog Pin). Design Notes. Bidirectional Microport Data. This three-stated when high. Microport Address Bus. Active Data Strobe when MODE Active Read Strobe when MODE Active Data Acknowledge when MODE Microport Status when MODE Read/Write Strobe when MODE Active Write Strobe when MODE Mode Select Pin. When SMODE Logic Intel mode; Logic Motorola mode. When SMODE Logic mode; Logic SPORT mode. Active Chip Select. Logic three-states microport data bus. Microport Input (Input Only). Chip Input Pins.
Bidirectional Output Output Output Output Input Output Output Output Output Output Input Output Output Output Output Output Input Output Input Output Input
Table G15, D16, Table C13, D11, Table M15, L14, B12, A12, C10, Table Table
LVDS_RSET Input EXT_FILTER Input MICROPORT CONTROL D[0:15] Bidirectional A[0:7] Input Input DS(RD) DTACK (RDY)1 (WR) MODE Output Input Input
CPUCLK CHIPID[0:3]
Input Input Input
Rev. Page
AD6636
Name Type SERIAL PORT CONTROL SCLK Input Output SDI2 Input STFS Input SRFS Input Input MSB_FIRST Input SMODE JTAG TRST1 TCLK2 TMS1 TDI1 Input Function Serial Clock. Serial Port Data Output. Serial Port Data Input. Serial Transmit Frame Sync. Serial Receive Frame Sync. Serial Chip Select. Select First into First Pin. Logic first; Logic first. Serial Mode Select. Pull high when serial port used when microport used. Test Reset Pin. Pull when JTAG used. Test Clock. Test Mode Select. Test Data Output. Three-stated when JTAG reset. Test Data Input.
Input Input Input Output Input
with pull-up resistor nominal with pull-down resistor nominal
LISTING POWER, GROUND, DATA ADDRESS BUSES
Table
Name VDDCORE VDDIO INA[0:15] INB[0:15] INC[0:15] IND[0:15] PA[0:15] PB[0:15] PC[0:15] D[0:15] A[0:7] G11, H11, J11, J16, K11, B15, F10, L10, A16, F11, G10, H10, H16, J10, K10, L11, T10, T15, B10, A10, F16, H15, G16, J12, J15, J14, K16, J13, K15, K14, L16, M16, K12, L15, N16, F13, E15, G14, G12, E13, E14, F12, F14, C14, D14, C16, A15, B16, D15, D13, M14, N14, M13, L12, P14, N13, R14, M12, T14, R13, P13, P12, M11, T13, T12, R10, N11, R12, P11, R11, N10, M10, P10,
Rev. Page
AD6636 TIMING DIAGRAMS
04998-0-003
RESET
tRESL
Figure Reset Timing Requirements
tCLKH
04998-0-004
CLKx
tCLKL
Figure Switching Characteristics Individual Input Ports)
tCLK tCLKL
CLKA
tCLKH
tCLKSKEW
CLKx
04998-0-005
Figure Skew Characteristics Individual Input Ports)
tCPUCLKH
CPUCLK
tCPUCLKL
Figure CPUCLK Switching Characteristics
tSCLKH
SCLK
04998-0-007
tSCLKL
Figure SCLK Switching Characteristics
CLKA
tSSYNC
SYNC [3:0]
tHSYNC
04998-0-008
Figure SYNC Timing Inputs
Rev. Page
04998-0-006
AD6636
tCLK tCLKL
CLKx
tCLKH tDEXP
EXPx[2:0]
04998-0-009
Figure Gain Control Word Output Switching Characteristics Individual Input Ports)
CLKx
INx[15:0]
tSEXP
EXPx[15:0]
tHEXP
04998-0-010
Figure Input Port Timing Data Individual Input Ports)
PCLK
tSPA
PxACK
tHPA
tDPREQ
PxREQ
tDPP
[15:0] [15:0]
tDPP
[15:0]
tDPP
RSSI [11:0]
tDPP
[15:0]
tDPP
[15:0]
tDPP
RSSI [11:0]
PxIQ
tDPIQ tDPCH
tDPIQ tDPCH
PxCH [2:0] CHANNEL PxCH [2:0] CHANNEL
PxCH [2:0]
tDPGAIN
PxGAIN
tDPGAIN
Figure Master Mode PxACK PCLK Switching Characteristics Individual Output Ports)
Rev. Page
04998-0-011
AD6636
PCLK PxACK
tDPREQ
PxREQ
TIED LOGIC HIGH TIME
tDPP
[15:0] [15:0]
tDPP
[15:0]
tDPP
RSSI [11:0]
tDPP
[15:0]
tDPP
[15:0]
tDPP
RSSI [11:0]
PxIQ
tDPIQ tDPCH
tDPIQ tDPCH
PxCH [2:0] CHANNEL PxCH [2:0] CHANNEL
PxCH [2:0]
tDPGAIN
PxGAIN
tDPGAIN
Figure Master Mode PxREQ PCLK Switching Characteristics
CPUCLK
tSAM
[7:0] VALID ADDRESS
tHAM
tSAM
[15:0] VALID DATA
tHAM
tDRDY
04998-0-013
tACC
NOTE: tACC ACCESS TIME DEPENDS ADDRESS ACCESSED. VARY FROM CPUCLK CYCLES.
Figure Microport Write Timing Requirements
Rev. Page
04998-0-012
AD6636
CPUCLK
tSAM
[7:0] VALID ADDRESS
tHAM
[15:0] VALID DATA
tDRDY
04998-0-014
tACC
NOTE: tACC ACCESS TIME DEPENDS ADDRESS ACCESSED. VARY FROM CPUCLK CYCLES.
Figure Microport Read Timing Requirements
CPUCLK
tSAM
[7:0] VALID ADDRESS
tHAM
tSAM
[15:0] VALID DATA
tHAM
tDDTACK
DTACK
04998-0-015
tACC
NOTE: tACC ACCESS TIME DEPENDS ADDRESS ACCESSED. VARY FROM CPUCLK CYCLES.
Figure Microport Write Timing Requirements
Rev. Page
AD6636
CPUCLK
tSAM
[7:0] VALID ADDRESS
tHAM
[15:0] VALID DATA
tDDTACK
DTACK
tACC
04998-0-016
NOTE: tACC ACCESS TIME DEPENDS ADDRESS ACCESSED. VARY FROM CPUCLK CYCLES.
Figure Microport Read Timing Requirements
SCLK
tSSCS
tHSCS
SMODE LOGIC
tHSI tSSI
tSSRFS
SRFS
tHSRFS
MODE LOGIC
Figure SPORT Mode Write Timing Characteristics
Rev. Page
04998-0-017
AD6636
SCLK
tSSCS
tHSCS
SMODE LOGIC
tDSDO
tSSTFS
STFS
tHSTFS
MODE LOGIC
Figure SPORT Mode Read Timing Characteristics
SCLK
tSSCS
tHSCS
SMODE LOGIC
tHSI tSSI
MODE LOGIC
Figure Mode Write Timing Characteristics
SCLK
tSSCS
tHSCS
SMODE LOGIC
tDSDO
04998-0-020
LOGIC MODE
Figure Mode Read Timing Characteristics
Rev. Page
04998-0-019
04998-0-018
AD6636 THEORY OPERATION
INPUT PORT
AD6636 features four identical, independent high speed input ports named These input ports have flexibility allow independent inputs, diversity inputs, complex inputs. input ports routed tuner channels; that AD6636 channels receive input data from input ports. Time-multiplexed inputs single port supported AD6636. These four input ports operate MSPS. Each input port clock (CLKA, CLKB, CLKC, CLKD) used registering input data into AD6636. allow slow input rates while providing fast processing clock rates, AD6636 contains internal clock multiplier that supplies internal signal processing clock. CLKA used input clock multiplier. Additional programmability allows input data clocked into part either rising edge falling edge input clock. addition, front AD6636 contains circuitry that enables high speed signal-level detection, gain control, quadrature correction. This accomplished with unique high speed level-detection circuit that offers minimal latency maximum flexibility control four input signals (typically inputs) individually. input ports also provide input power-monitoring functions various modes, magnitude phase correction blocks. Quadrature Correction Block section details. Each individual processing channel receive input data from four input ports individually. This controlled using 3-bit crossbar mux-select words input control register. Each individual channel similar 3-bit selection. addition four input ports, internal test signal (PN- pseudorandom noise sequence) also selected. This internal test signal discussed User-Configurable BuiltIn Self-Test (BIST) section. Input Data Format Each input port consists 16-bit mantissa 3-bit exponent floating-point input, 16-bit fixedpoint input). When interfacing standard fixed-point ADCs, exponent should either connected ground programmed outputs gain control output. connected floating-point (also called gain ranging ADC), exponent bits from connected input exponent bits AD6636. mantissa data format twos complement, exponent unsigned binary. 3-exponent bits shared with gain range control bits hardware. When floating-point ADCs used, these three pins each input port used gain range control output bits. Input Timing data from each high speed input port latched either rising edge falling edge port's individual CLKx (where stands input ports). clock invert clock control register selects edge clock (rising falling) used register input data into AD6636.
CLKx
[15:0] EXPx [2:0]
DATA
DATA
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Figure Input Data Timing Requirements (Rising Edge Clock, Four Input Ports)
CLKx
[15:0] EXPx [2:0]
DATA
DATA
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Figure Input Data Timing Requirements (Falling Edge Clock, Four Input Ports)
clock signals (CLKA, CLKB, CLKC, CLKD) operate MHz. applications using high speed ADCs, sample clock, data valid, data ready strobe typically used clock AD6636. Connection Fixed-Point fixed-point ADCs, AD6636 exponent inputs, EXP[2:0], typically used should tied low. Alternatively, because these pins shared with gain range control bits, gain ranging block used, these pins used outputs gain range control block. outputs tied directly AD6636 inputs, MSB-justified. Therefore, fixed-point ADCs, exponents typically static input scaling used AD6636. Figure shows typical interconnection.
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AD6636
(MSB) IN15
Input Ports then select bits should indicate Input Port complex input should selected. When input ports paired complex input operation, only exponent bits driven externally with gain control output. when Input Ports form complex input, then EXPA[2:0] output and, similarly, Input Ports EXPC[2:0] output. LVDS Input Ports AD6636 input ports configured different modes: CMOS LVDS. CMOS input mode, four input ports configured complex input ports. LVDS mode, CMOS input ports each combined form LVDS input port. CMOS Input Ports INA[15:0] INB[15:0] form positive negative differential nodes, LVDS_A+[15:0] LVDS_A-[15:0], respectively. Similarly, INC[15:0] IND[15:0] form positive negative differential nodes, LVDS_C+[15:0] LVDS_C- [15:0], respectively. CLKA CLKB form differential pair, LVDS_CLKA+ LVDS_CLKA- pins. Similarly, CLKC CLKD form differential pair LVDS_CLKC+ LVDS_CLKC- pins. default, AD6636 powers CMOS mode programmed CMOS mode using CMOS mode (Bit LVDS control register). Writing Logic LVDS control register enables autocalibrate routine that calibrates impedance LVDS pads match output impedance LVDS signal source impedance. LVDS pads AD6636 have internal impedance across differential signals; therefore, external resistor required.
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AD6645
14-BIT
AD6636
(LSB)
EXP2 EXP1 EXP0
GAIN RANGING CONTROL BITS GROUNDED EXPONENT BITS
Figure Typical Interconnection AD6645 Fixed-Point AD6636
Scaling with Floating-Point example exponent control feature combines AD6600 AD6636. AD6600 11-bit with three bits gain ranging. effect, 11-bit provides mantissa, three bits relative signal strength indicator (RSSI) exponent. Only five eight available steps used AD6600. AD6600 data sheet details. Table Weighting Factors Different Exp[2:0] Values
Input Level Largest AD6636 Exp[2:0] Data Divide-By (>>1) (>>2) (>>3) /128(>> Signal Attenuation (dB)
Smallest
CLOCK MULTIPLIER
AD6636, input clock rate must same input data rate. typical digital down-converter architecture, clock rate limitation number filter taps that calculated programmable coefficient filters (MRCF, DRCF, CRCF). slower clock rates clock rate), this limitation overcome using clock multiplier provide higher clock rate filters. Using this clock multiplier, internal signal processing clock rate increased MHz. CLKA signal used input clock multiplier.
CLOCK GENERATION CLKA DIVIDE CLOCK MULITPLIER 20x) ADC_CLK
Complex (I/Q) Input Ports four individual input ports AD6636 configured function complex input ports. Additionally, required, only input ports made function complex port, while remaining input ports function real individual input ports. complex mode, Input Port paired with Input Port receive data, respectively. Similarly, Input Port paired with Input Port receive data, respectively. These pairings controlled individually using Bits input control register. explained previously, each individual channel receive input signals from four input ports using crossbar select bits input control register. addition three bits, 1-bit selection provided choosing complex input port option individual channel. example, Channel needs receive complex input from
PLL_CLK
BYPASS_PLL BYPASS
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Figure Clock Generation
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clock multiplier programmable uses input clock rates between give system clock rate (output) high MHz. output clock rate given Function
where:
CLKA
CLKA Input Port clock rate. 5-bit programmable multiplication factor. predivide factor. 5-bit number between (both values included). (predivide) multiplication factor programmed using 5-bit clock multiplier word clock control register. value outside valid range bypasses clock multiplier and, therefore, clock same input clock. predivide factor programmed using 2-bit pre-PLL clock divider word clock control register, listed Table Table Clock Generation Predivider Control
Predivide Word [1:0] Divide-by Value Clock Divide-by-1, bypass Divide-by-2 Divide-by-4 Divide-by-8
gain-control block features programmable upper threshold register lower threshold register. input data compared both these registers. input data larger than upper threshold register, then gain control output decremented input data smaller than lower threshold register, then gain control output incremented When decrementing gain control output, change immediate. when incrementing output, dwell-time register used delay change. input larger than upper threshold register value, gaincontrol output decremented immediately prevent overflow. When input lower than lower threshold register, dwell timer loaded with value programmable 20-bit dwell-time register. counter decrements once every input clock cycle, long input signal remains below lower threshold register value. counter reaches gain control output incremented signal goes above lower threshold register value, gain adjustment made, normal comparison lower upper threshold registers initiated once again. Therefore, dwell timer provides temporal hysteresis prevents gain from switching continuously. typical application, signal goes below lower threshold time greater than dwell time, then gain control output incremented Gain control bits control gain ranging block, which appears before signal chain. With each increment gain control output, gain gain-ranging block increased 6.02 This increases dynamic range input signal into 6.02 This gain compensated AD6636 relinearizing, explained Relinearization section. Therefore, AD6636 increase dynamic range provided that gain-ranging block support
Relinearization
best signal processing advantage, user should program clock multiplier give system clock output close possible exceeding, MHz. internal blocks AD6636 that clock rated maximum MHz. default power-up state clock multiplier bypass state, where CLKA passed clock.
GAIN CONTROL
Each input port individual, high speed gain-control logic circuitry. Such gain-control circuitry useful applications that involve large dynamic-range inputs which gain-ranging ADCs employed. AD6636 gain-control logic allows programmable upper lower thresholds programmable dwell-time counter temporal hysteresis. Each input port 3-bit output from gain control block. These three output pins shared with 3-bit exponent input pins each input port. operation controlled gain control enable gain control register individual input ports. Logic this programs EXP[2:0] pins gain-control outputs, Logic configures pins input exponent pins. avoid contention, these pins set, default, input exponent pins.
gain gain-ranging block (external) compensated relinearizing, using exponent bits EXP[2:0] input port. this purpose, gain control bits connected EXP[2:0] bits, providing attenuation 6.02 every increase gain control output. After gain external gain-ranging block attenuation AD6636 (using bits), signal gain essentially unchanged. only change increase dynamic range ADC. External gain-ranging blocks gain-ranging ADCs have delay associated with changing gain signal. Typically, these delays clock cycles. gain change AD6636 (via EXP[2:0]) must synchronized with gain change gain-ranging block (external). This allowed AD6636 providing flexible delay, programmable 6-bit word gain control register. value this 6-bit word gives delay input clock cycles. programmable pipeline
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delay given 6-bit value (maximum delay clock cycles) placed between gain control output EXP[2:0] input. Therefore, external gain-ranging block's settling delays compensated AD6636. Note that gain changes that initiated during relinearization period ignored. example, AD6636 detects that gain adjustment required during relinearization period previous gain adjustment, then adjustment ignored.
Setting Gain Control Block
INPUT PORT MONITOR FUNCTION
AD6636 provides power-monitor function that monitor gather statistics about received signal signal chain. Each input port equipped with individual power-monitor function that operate both real complex modes input port. This function block operate three modes, which measure following over programmable period time: Peak power Mean power Number samples crossing threshold
gain control block individual input ports, individual upper threshold registers lower threshold registers should written with appropriate values. 10-bit values written into upper lower threshold registers compared bits absolute magnitude calculated using input port data. 20-bit dwell timer register should have appropriate number clock cycles provide temporal hysteresis. 6-bit relinearization pipeline delay word synchronize with settling delay external gain ranging circuitry. Finally, gain control enable written with Logic activate gain control block. enabling, gain control output bits made (output EXP[2:0] pins), which represent minimum gain external gain-ranging circuitry corresponding minimum attenuation during relinearization. normal functioning takes over, explained previously this section.
Complex Inputs
These functions controlled 2-bit power-monitor function select bits power monitor control register each individual input port. input ports different modes, only function active time given input port. three modes operation function continuously over programmable time period. This time period programmed number input clock cycles 24-bit monitor period register (AMPR). This register separate each input port. internal magnitude storage register (MSR) used monitor, accumulate, count, depending mode operation.
Peak Detector Mode (Control Bits
complex inputs (formed pairing input ports), only EXP[2:0] pins should used gain control output. pair Input Ports gain control circuitry Input Port active, EXPA[2:0] should connected externally gain control output. gain control circuitry Input Port activated (shut down), EXPB[2:0] forced equal EXP[2:0].
FROM MEMORY LOWER THRESHOLD REGISTER FROM INPUT PORTS COMPARE
magnitude input port signal monitored over programmable time period (given AMPR) give peak value detected. This mode programming Logic power-monitor function select bits power-monitor control register each individual input port. 24-bit AMPR must programmed before activating this mode. After enabling this mode, value AMPR loaded into monitor period timer countdown started. magnitude input signal compared MSR, greater updated back into MSR. initial value current input signal magnitude. This comparison continues until monitor period timer reaches count When monitor period timer reaches count value transferred power-monitor holding register, which read through microport serial port. monitor period timer reloaded with value AMPR, countdown started. Also, first input sample's magnitude updated MSR, comparison update procedure, explained above, continues. interrupt enabled, interrupt generated, interrupt status register updated when AMPR reaches count
DECREASE EXTERNAL GAIN [2:0] INCREASE EXTERNAL GAIN
FROM MEMORY LOWER THRESHOLD REGISTER COMPARE
DWELL TIMER
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Figure AD6636 Gain Control Block Diagram
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Figure block diagram peak detector logic. contains absolute magnitude peak detected peak detector logic.
FROM MEMORY POWER MONITOR PERIOD REGISTER INTERRUPT CONTROLLER COUNT
FROM MEMORY POWER MONITOR PERIOD REGISTER DOWN COUNTER LOAD FROM INPUT PORTS CLEAR ACCUMULATOR LOAD POWER MONITOR HOLDING REGISTER MEMORY INTERRUPT CONTROLLER COUNT
LOAD FROM INPUT PORTS CLEAR MAGNITUDE STORAGE REGISTER LOAD POWER MONITOR HOLDING REGISTER LOAD
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MEMORY
Figure Input Mean Power-Monitoring Block Diagram
Threshold Crossing Mode (Control Bits
COMPARE
Figure Input Peak Detector Block Diagram
Mean Power Mode (Control Bits
this mode, magnitude input port signal integrated adding accumulator) over programmable time period (given AMPR) give integrated magnitude input signal. This mode programming Logic power monitor function select bits power monitor control register each individual input port. 24-bit AMPR, representing period over which integration performed, must programmed before activating this mode. After enabling this mode, value AMPR loaded into monitor period timer, countdown started immediately. 15-bit magnitude input signal rightshifted nine bits give 6-bit data. This 6-bit data added contents 24-bit holding register, thus performing accumulation. integration continues until monitor period timer reaches count When monitor period timer reaches count value transferred power-monitor holding register (after some formatting), which read through microport serial port. monitor period timer reloaded with value AMPR, countdown started. Also, first input sample signal magnitude updated MSR, accumulation continues with subsequent input samples. interrupt enabled, interrupt generated, interrupt status register updated when AMPR reaches count Figure illustrates mean power-monitoring logic. value floating-point number with MSBs LSBs. MSBs LSBs MAG, value dBFS decoded using following equation:
Mean Power
this mode operation, magnitude input port signal monitored over programmable time period (given AMPR) count number times crosses certain programmable threshold value. This mode programming Logic (where don't care bit) power-monitor function select bits power monitor control register each individual input port. Before activating this mode, user needs program 24-bit AMPR 10-bit upper threshold register each individual input port. same upper threshold register used both power monitoring gain control (see Gain Control section). After entering this mode, value AMPR loaded into monitor period timer, countdown started. magnitude input signal compared upper threshold register (programmed previously) each input clock cycle. input signal magnitude greater than upper threshold register, then register incremented initial value zero. This comparison increment register continues until monitor period timer reaches count When monitor period timer reaches count value transferred power monitor holding register, which read through microport serial port. monitor period timer reloaded with value AMPR, countdown started. register also cleared value zero. interrupts enabled, interrupt generated, interrupt status register updated when AMPR reaches count Figure illustrates threshold crossing logic. value number samples that have amplitude greater than threshold register.
FROM MEMORY POWER MONITOR PERIOD REGISTER INTERRUPT CONTROLLER COUNT
DOWN COUNTER LOAD
FROM INPUT PORTS FROM MEMORY
CLEAR COMPARE UPPER THRESHOLD REGISTER COMPARE
LOAD POWER MONITOR HOLDING REGISTER
MEMORY
Figure Input Threshold Crossing Block Diagram
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DOWN COUNTER
AD6636
Additional Control Bits
additional flexibility power monitoring process, control bits provided power-monitor control register. control bits disable monitor period timer clear-on-read bit. These options have same function three modes operation.
Disable Monitor Period Timer
clear-on-read Logic read operation microport serial port does clear value after transferred into holding register. value from previous monitor time period persists, continues compared, accumulated, incremented, based input signal magnitude values.
QUADRATURE CORRECTION BLOCK
When paths digitized using separate ADCs, quadrature down-conversion, mismatch often occurs between variations ADCs from manufacturing process. AD6636 equipped with quadrature correction blocks that used correct mismatch errors complex baseband input stream. These mismatches result spectral distortions, removing them useful. such blocks present, each signal formed combining inputs inputs, respectively. correction block enabled when Port Port complex data active enabled input control register. This block bypassed when real input data present input ports, because there possibility mismatch real data. quadrature correction block consists three independent subblocks: correction, phase correction, amplitude correction. Three individual bits correction control registers used enable disable each these subblocks independently. Figure shows contents definitions registers related quadrature correction block.
[15:0] FROM INPUT PORT PHASE ESTIMATE [13:0] MAGNITUDE MAGNITUDE ERROR ESTIMATE [13:0] ESTIMATION [15:0] FROM INPUT PORT PHASE ERROR ESTIMATION ESTIMATE I_OUT [15:0] NEXT BLOCK
When disable monitor period timer written with Logic timer continues does cause contents transferred holding register when count reaches This function transferring power monitor holding register resetting controlled read operation microport serial port. When microport serial port read performed power monitor holding register, value transferred holding register. After read operation, timer reloaded with AMPR value. timer reaches before microport serial port read, value transferred holding register, normal operation. timer still generates interrupt AD6636 interrupt updates interrupt status register. interrupt appears pin, interrupts enabled interrupt enable register.
Clear-on-Read
This control valid only when disable monitor period timer Logic When both these bits set, read operation either microport serial port reads value monitor period timer reloaded with AMPR value. cleared (written with current input signal magnitude peak power mean power mode; written with zero threshold crossing mode), normal operation continues. When monitor period timer disabled clear-onread set, read operation power monitor holding register clears contents and, therefore, power monitor loop restarts.
PHASE ESTIMATE [13:0]
Q_OUT [15:0] NEXT BLOCK
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ESTIMATE
Figure Quadrature Correction Block Diagram
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Table Correction Control Registers
Register Correction Control Bits 15-12 11-8 31-16 15-0 31-16 15-0 Decription Amplitude Loop Phase Loop Loop Reserved (Logic Amplitude Correction Enable Phase Correction Enable Correction Enable Offset Offset Amplitude Correction Phase Correction
Phase Correction
When using complex input, datapaths typically have phase offset, caused mainly local oscillator demodulator AD6636 phase-offset correction circuit used compensate this phase offset. When phase correction enable Logic phase error between estimated (ideally, phase should 90°). phase mismatch estimated over period time determined integrator loop bandwidth. This integrator implemented first-order decimating filter, whose decimation value vary between powers Phase loop (Bits [11:8]) correction control register determine this decimation value. When phase loop equals decimation value 212, when phase loop decimation value 224. While phase offset correction circuit enabled, tan(phase_mismatch) estimated continuously. This value multiplied with path data added path data continuously. estimated value also updated phase offset correction register. tan(phase_mismatch) ±0.125 with 14-bit resolution. This converts phase mismatch about ±7.125°. When phase offset correction circuit disabled, value phase correction register multiplied with path data added path data continuously. This method used manually phase offset instead using automatic phase offset correction circuit.
Amplitude Correction
Offset Correction Offset Correction Amplitude Offset Correction Phase Offset Correction
Correction
ADCs have nominal offset related them. ADCs path have different offsets variations manufacturing process, correction circuit used compensate these offsets. Writing Logic into correction enable correction control register enables correction block. estimation blocks used, each paths. estimated value subtracted from paths. Therefore, signal removed independently from path signals. cascade low-pass decimating filters estimates offset feedback loop. decimating first-order filter followed interpolating second-order filter. decimation interpolation values filters same programmable between powers 4-bit loop word correction control register used program this decimation (interpolation) value. When loop decimation 212, when loop decimation 224. When correction circuit enabled, correction values estimated. values, which estimated independently paths, subtracted independently from their respective datapaths. These correction values also available output continuously through correction correction registers. These registers contain register 16-bit offset values whose MSB-justified values subtracted directly from MSB-justified inputs paths. When correction circuit disabled, value correction register used continuously subtracting offset from datapaths. This method used manually offset instead using automatic correction circuit.
When using complex input, datapaths typically have amplitude offset, caused mainly local oscillator demodulator AD6636 amplitude offset correction circuit used compensate this amplitude offset. When amplitude correction enable Logic amplitude error between datapaths estimated. amplitude mismatch estimated over period time determined integrator loop bandwidth. This integrator implemented first-order decimating filter, whose decimation value vary between powers Phase loop (Bits [11:8]) correction control register determines this decimation value. When phase loop equals decimation value 212, when phase loop decimation value 224. While amplitude offset correction circuit enabled, difference (MAG(Q) MAG(I)) estimated continuously. This value multiplied with path data added path data continuously. estimated value also updated phase offset correction register. difference (MAG(Q) MAG(I)) between 1.125 0.875 with 14-bit resolution.
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When amplitude offset correction circuit disabled, value amplitude offset correction register multiplied with path data added path data continuously. This method used manually amplitude offset instead using automatic amplitude offset correction circuit. amplitude sine cosine represented using bits. worst-case spurious signal from better than -100 output frequencies. Because filtering AD6636 low-pass filtering, carrier interest tuned down (frequency Hz). This illustrated Figure Once signal interest tuned down unwanted adjacent carriers rejected using low-pass filtering that follows.
Frequency
INPUT CROSSBAR MATRIX
AD6636 four input ports channels. input ports paired support complex input ports. Crossbar selection allows each channel select input signal from following sources: four real input ports, complex input ports, internally generated pseudorandom sequence (referred sequence, which either real complex). Each channel input crossbar matrix select from above-listed input signal choices. selection input signal particular channel made using 3-bit crossbar select word 1-bit complex data input selection input control register. Each channel separate selection individual control. Table lists valid combinations crossbar select word, complex data input values, corresponding input signal selections.
frequency value given 32-bit twos complement number entered frequency register. Frequencies between -CLK/2 CLK/2 (CLK/2 excluded) represented using this frequency word: 0x8000 0000 represents frequency given -CLK/2. 0x0000 0000 represents (frequency Hz). 0x7FFF FFFF represents CLK/2 CLK/232. frequency word calculated using following equation:
FREQ mod(
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
Each channel consists independent complex complex mixer. This processing stage comprises digital tuner consisting three multipliers 32-bit complex NCO. serves quadrature local oscillator capable producing frequency between -CLK/2 +CLK/2 with resolution CLK/232 complex mode, where input clock frequency. frequency word used generating 32-bit word. This word used generate 20-bit phase word. 16-bit phase offset word added this phase word. bits this phase word used generate sine cosine required frequency. where:
NCO_FREQ 32-bit twos complement number representing frequency register. desired carrier frequency. fclk clock rate channel under consideration. mod( remainder function. example, mod(110, 100) and, negative numbers, mod(-32, Note that this equation applies aliasing signals digital domain (that aliasing introduced when digitizing analog signals).
Table Crossbar Selection Channel Input Signal
Complex Input Crossbar Select Input Signal Selection Input Port magnitude exponent pins drive channel. Input Port magnitude exponent pins drive channel. Input Port magnitude exponent pins drive channel. Input Port magnitude exponent pins drive channel. Internal sequence's magnitude exponent bits drive channel. Input Ports form pair drive paths channel, respectively. Input Port exponent pins drive channel exponent bits. Input Ports form pair drive paths channel, respectively. Input Port exponent pins drive channel exponent bits. Internal sequence's magnitude exponent bits drive channel.
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WIDEBAND INPUT SPECTRUM (-fsamp/2 fsamp/2)
SIGNAL INTEREST IMAGE SIGNAL INTEREST
-fs/2
-7fs/8
-3fs/8
-5fs/16
-fs/4
-3fs/16
-fs/8
-fs/16
fs/16
fs/8
3fs/16
fs/4
5fs/16
3fs/8
7fs/8
fs/2
WIDEBAND INPUT SPECTRUM (30MHz FROM HIGH SPEED ADC) TUNES SIGNAL SIGNAL INTEREST AFTER FREQUENCY TRANSLATION SIGNAL INTEREST IMAGE
-fs/2
-7fs/8
-3fs/8
-5fs/16
-fs/4
-3fs/16
-fs/8
-fs/16
fs/16
fs/8
3fs/16
fs/4
5fs/16
3fs/8
7fs/8
fs/2
FREQUENCY TRANSLATION (SINGLE 1MHz CHANNEL TUNED BASEBAND)
Figure Frequency Translation Principle Using Mixer
example, carrier frequency clock frequency MHz,
mod( 0.25
useful baseband sampling applications, which input Port connected signal path within filter Input Port connected signal path. This might desired, digitized signal already been converted baseband prior analog stages other digital preprocessing.
Clear Phase Accumulator
This, turn, converts 0x4000 0000 32-bit twos complement representation NCO_FREQ. carrier frequency clock frequency MHz,
mod( 0.125
This, turn, converts 0xE000 0000 twos complement 32-bit representation.
Mixer
When clear accumulator control register (Logic phase accumulator cleared prior frequency hop. Refer Chip Synchronization section details frequency hopping. This ensures consistent phase each hop. phase offset unaffected this setting still effect. phase-continuous hopping needed, this should cleared (NCO accumulator cleared). last phase phase register initiating point frequency.
Phase Dither
accompanied mixer. operation similar analog mixer. does down-conversion input signals (real complex) using frequency local oscillator. real input signals, this mixer performs real mixer operation (with multipliers). complex input signals, mixer performs complex mixer operation (with four multipliers). mixer adjusts operation based input signal (real complex) provided each individual channel.
Bypass
AD6636 provides phase dither option improving spurious performance NCO. Writing Logic phase dither enable control register individual channels enables phase dither. When phase dither enabled, random phase added LSBs phase accumulator NCO. When phase dither enabled, spurs phase truncation randomized. energy from these spurs spread into noise floor spurious free dynamic range increased expense very slight decrease SNR. choice whether phase dither system ultimately decided system goals. lower spurs desired expense slightly raised noise floor, phase dither should employed. noise floor desired higher spurs tolerated filtered subsequent stages, then phase dither needed.
mixer bypassed individually each channel writing Logic bypass control register channel under consideration. When bypassed, down-conversion performed AD6636 channel functions simply real filter complex data. This
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Amplitude Dither
Amplitude dither used improve spurious performance NCO. Amplitude dither enabled writing Logic amplitude dither enable control register channel under consideration. Random amplitude added LSBs sine cosine amplitudes, when this feature enabled. Amplitude dither improves performance randomizing amplitude quantization errors within angular-to-Cartesian conversion NCO. This option might reduce spurs expense slightly raised noise floor. Amplitude dither phase dither used together, separately, all.
Frequency Hold-Off Register
register used decimation factor. binary value less than decimation factor written into this register. decimation ratio achieved bypassing filter stage. frequency response filter given following equations. gain pass-band droop should calculated these equations. Both parameters offset stage.
(SCIC MCIC
When frequency registers written microport serial port, data passed shadow register. Data moved main registers when channel comes sleep mode, when sync occurs. either event, counter loaded with frequency holdoff register value. 16-bit unsigned integer counter starts counting down, clocked input port clock selected crossbar mux. When counter reaches frequency value shadow register written frequency register. Writing this hold-off register updates frequency register soon start sync sync occurs. Chip Synchronization section details.
Phase Offset
(SCIC
where: data input rate channel under consideration. SCIC, scale factor, programmable unsigned integer between attenuation data into stage should controlled increments. best dynamic range, SCIC should smallest value possible (lowest attenuation possible) without creating overflow condition. This accomplished safely using following equation, where input_level largest possible fraction full-scale value input port. This value output from stage pipelined into filter.
SCIC ceil log2 MCIC5 input level
phase offset register written with value that added offset phase accumulator NCO. This 16-bit register interpreted 16-bit unsigned integer. 0x0000 this register corresponds radian offset 0xFFFF corresponds offset 1/216) radians. This register allows multiple NCOs (multiple channels) synchronized produce complex sinusoids with known steady phase difference.
Sync
OLCIC
input level
SCIC
sync should issued channel, when channel's frequency needs changed from frequency different frequency. This feature discussed detail Chip Synchronization section.
Bypass
FIFTH-ORDER FILTER
signal processing stage immediately after filter stage. This stage implements fixed-coefficient, decimating, cascade integrated comb filter. input rate this filter same data rate input port; output rate from this stage dependent decimation factor.
fifth-order filter bypassed when decimation required When bypassed, scaling operation performed. bypass mode, output filter same input filter.
Rejection
Table illustrates amount bandwidth percentage data rate into stage, which protected with various decimation rates alias rejection specifications. maximum input rate into (the same maximum input port data rate). data scaled other allowable sample rate.
decimation ratio, MCIC, programmed from (only integer values). 5-bit word decimation
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Table used decide minimum decimation required stage preserve certain bandwidth. CIC5 stage protect much wider bandwidth given rejection, when decimation ratio lower than that identified table used. table helps calculate upper boundary decimation, MCIC, given desired filter characteristics.
Table CIC5 Alias Rejection Table (fin
MCIC5 8.078 6.367 5.022 4.107 3.463 2.989 2.627 2.342 2.113 1.924 1.765 1.631 1.516 1.416 1.328 1.25 1.181 1.119 1.064 1.013 0.967 0.925 0.887 0.852 0.819 0.789 0.761 0.734 0.71 0.687 0.666 6.393 5.11 4.057 3.326 2.808 2.425 2.133 1.902 1.716 1.563 1.435 1.326 1.232 1.151 1.079 1.016 0.96 0.91 0.865 0.824 0.786 0.752 0.721 0.692 0.666 0.641 0.618 0.597 0.577 0.559 0.541 5.066 4.107 3.271 2.687 2.27 1.962 1.726 1.54 1.39 1.266 1.162 1.074 0.998 0.932 0.874 0.823 0.778 0.737 0.701 0.667 0.637 0.61 0.584 0.561 0.54 0.52 0.501 0.484 0.468 0.453 0.439 4.008 3.297 2.636 2.17 1.836 1.588 1.397 1.247 1.125 1.025 0.941 0.87 0.809 0.755 0.708 0.667 0.63 0.597 0.568 0.541 0.516 0.494 0.474 0.455 0.437 0.421 0.406 0.392 0.379 0.367 0.355 -100 3.183 2.642 2.121 1.748 1.48 1.281 1.128 1.007 0.909 0.828 0.76 0.703 0.653 0.61 0.572 0.539 0.509 0.483 0.459 0.437 0.417 0.399 0.383 0.367 0.353 0.34 0.328 0.317 0.306 0.297 0.287
-100 column Table find value greater than equal pass-band percentage clock rate. Then find corresponding rate decimation factor (MCIC). MCIC frequency that -100 alias rejection 1.48%, which slightly larger than 1.4% calculated. Therefore, this example, maximum bound decimation rate higher MCIC means less alias rejection than required.
HALF-BAND BLOCK
output filter pipelined into (halfband) block. Each channel sets cascading fixedcoefficient fixed-coefficient half-band filters. halfband filters decimate Each these filters (FIR1, HB1, FIR2, HB2) described following sections.
3-Tap Fixed-Coefficient Filter (FIR1)
3-tap filter useful certain filter configurations which extra alias protection needed decimating filter. simple sum-of-products filter with three filter taps 2-bit fixed coefficients. Note that this filter does decimate. coefficients this symmetric filter normalized coefficients used implementation {0.25, 0.5, 0.25}. user either bypass this filter. Writing Logic FIR1 enable FIR-HB control register bypasses this fixed-coefficient filter. filter useful only certain filter configurations bypassing other applications results power savings.
-8.33 FIR1 RESPONSE -16.67 -25.00 -33.33 -41.67
0.34
0.66
-50.00 -58.33 -66.67 -75.00 -83.33 -91.67
-100.00
Goal: Implement filter with input sample rate requiring alias rejection pass band. Solution: First determine percentage sample rate that represented pass band.
FRACTION FIR1 INPUT SAMPLE RATE
Figure FIR1 Filter Response Input Rate Filter
fraction
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Example Calculations
AD6636
This filter runs same sample rate filter output rate given FIR1 where: input rate channel. MCIC decimation ratio filter stage. maximum input output rates this filter MHz.
Decimate-by-2 Half-Band Filter (HB1)
RESPONSE
0.43
0.57
FRACTION INPUT SAMPLE RATE
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next stage FIR-HB block decimate-by-2 halfband filter. 11-tap, symmetrical, fixed-coefficient filter power consumption polyphase implementation. filter bits input output data with 10-bit coefficients. Table lists coefficients half-band filter. normalized coefficients used implementation 10-bit decimal equivalent value coefficients also listed. Other coefficients zeros.
Table Fixed Coefficients Filter
Coefficient Number Normalized Coefficient 0.013671875 -0.103515625 0.58984375 Decimal Coefficient (10-Bit)
Figure Filter Response Input Rate Filter
filter maximum input sample rate and, when filter bypassed, maximum output rate MHz. filter ripple 0.0012 rejection alias rejection alias-protected bandwidth filter input sample rate. bandwidth filter ripple 0.00075 also same alias-protected bandwidth, nature half-band filters. bandwidth this filter filter input sample rate. example, sample rate into filter MHz, then alias-protected bandwidth filter MHz. bandwidth required carrier greater than MHz, then might useful.
0.43
0.57
Similar FIR1 filter, this filter used bypassed. Writing Logic enable FIR-HB control register bypasses this fixed-coefficient filter. filter useful only certain filter configurations bypassing other applications results power savings. example, useful narrow-band wideband output applications which more filtering required compared very wide bandwidth applications which higher output rate might prohibit decimating filter. response filter shown Figure input sample rate this filter same filter output rate given where: input rate channel. MCIC decimation ratio filter stage.
FIR1 RESPONSE -100 -110 -120 FRACTION INPUT SAMPLE RATE -107
Figure Composite Response FIR1 Filters Their Input Rate
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6-Tap Fixed Coefficient Filter (FIR2) Decimate-by-2 Half-Band Filter (HB2)
Following first cascade FIR1 filters second cascade FIR2 filters. 6-tap, fixedcoefficient FIR2 filter useful providing extra alias protection decimating filter certain filter configurations. simple sum-of-products filter with filter taps 5-bit fixed coefficients. Note that this filter does decimate. normalized coefficients used implementation 5-bit decimal equivalent value coefficients listed Table
Table 6-Tap FIR1 Filter Coefficients
Coefficient Number Normalized Coefficient -0.125 0.1875 0.9375 Decimal Coefficient (5-Bit)
second stage second cascade FIR-HB block decimate-by-2 half-band filter. 27-tap, symmetric, fixedcoefficient filter power consumption polyphase implementation. filter bits input output data with 12-bit coefficients. normalized coefficients used implementation 10-bit decimal equivalent value coefficients listed Table Other coefficients zeros.
Table Filter Fixed Coefficients
Coefficient Number C11, C13, Normalized Coefficient 0.00097656 -0.00537109 0.015 -0.0380859 0.0825195 0.1821289 0.6259766 Decimal Coefficient (12-Bit) -373 1282 2048
user either bypass this filter. Writing Logic FIR2 enable FIR-HB control register bypasses this fixed-coefficient filter. filter useful only certain filter configurations bypassing other applications results power savings. filter especially useful increasing stop-band attenuation filter that follows. Therefore, optimal both FIR2 configuration. This filter runs sample rate given following equations: fFIR2 fHB1, bypassed fFIR2
bypassed
Similar filter, user either bypass this filter. Writing Logic enable FIR-HB control register bypasses this fixed-coefficient filter. filter useful only certain filter configurations bypassing other applications results power savings. example, filter useful narrow-band applications which more filtering required, compared wide-band applications, which higher output rate might prohibit decimating filter. response filter shown Figure
0.01 -9.99 -19.99 0.34 0.66
where fHB1 input rate filter. maximum input output rate this filter MHz. response FIR2 filter shown Figure
-8.33 -16.67 -25.00 -33.33 -41.67 FIR2 RESPONSE
-29.99 -39.99 -49.99
0.39
0.61
-60.00 -70.00 -80.00 -90.00
RESPONSE
-100.00 -110.00 -120.00 FRACTION INPUT SAMPLE RATE
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-50.00 -58.33 -66.67 -75.00 -83.33 -91.67
Figure Filter Response Input Rate Filter
-100.00 FRACTION FIR2 INPUT SAMPLE RATE
Figure FIR2 Filter Response Input Rate Filter
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AD6636
filter input sample rate same FIR2 filter output rate given following equations: fHB2 fFIR2 fHB1, bypassed fHB2 fFIR2 where: fFIR1 input rate FIR1 filter. fHB1 input rate filter. input filter maximum MHz. maximum output rate when bypassed 37.5 MHz. filter ripple 0.00075 rejection alias rejection alias-protected bandwidth filter input sample rate. bandwidth filter ripple 0.00075 same alias-protected bandwidth, nature half-band filters. bandwidth this filter filter input sample rate. example, sample rate into filter MHz, then aliasprotected bandwidth filter 8.25 (33% MHz). bandwidth required carrier greater than 8.25 MHz, then might useful.
0.01 -9.99 -19.99 -29.99 -39.99 -49.99 0.34 0.66
Table Data Router Select Settings
MRCF Data Select [2:0] Data Source Channel Channel Channel Channel Channel Channel
bypassed
Allowing different channel back ends select different channel front ends useful polyphase implementation filters. When multiple AD6636 channels used process single carrier, single-channel front feeds more than channel back end. After processing through channel back ends (RCF filters), data interleaved back from polyphased channels.
MONO-RATE COEFFICIENT FILTER (MRCF)
MRCF programmable sum-of-products filter. This filter block comes after first data router before DRCF CRCF programmable filters. consists maximum eight taps with 6-bit programmable coefficients. Note that this block does decimate used helper filter DRCF CRCF filters that follow signal chain. number filter taps that calculated programmable using 3-bit number-of-taps word MRCF control register channel under consideration. 3-bit word programmed less than number filter taps. coefficients themselves programmed eight MRCF coefficient memory registers individual channels. input output data block both 20-bit.
-60.00 -70.00 -80.00 -90.00 FIR2 RESPONSE
Symmetry
-100.00 -110.00 -120.00 FRACTION INPUT SAMPLE RATE
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Figure Composite Response FIR1 filters Their Input Rates
INTERMEDIATE DATA ROUTER
Following FIR-HB cascade filters intermediate data router. This data router consists muxes that allow data from channel front (input port FIR-HB) processed channel back (MRCF DRCF CRCF). choice channel front made programming 3-bit MRCF data select word MRCF control register. valid values this word their corresponding settings listed Table
Though MRCF filter does require symmetrical filters, filter symmetrical, then symmetry MRCF control register should set. When this set, only half impulse response needs programmed into MRCF coefficient memory registers. example, number filter taps equal five filter symmetrical, then only three coefficients need written into coefficient memory. both symmetrical asymmetrical filters, number filter taps limited eight.
Clock Rate
MRCF filter runs internal high speed clock. This clock rate high MHz. half clock rate MRCF control register set, then only half clock rate used (maximum MHz). This results power savings, only used certain conditions met.
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Because this filter nondecimating, input output rates both same equal following: fMRCF fHB2, bypassed fMRCF
bypassed
decimation rate programmable using 4-bit DRCF decimation rate word DRCF control register. Again, value written decimation rate minus one.
Bypass
fPLLCLK clock
MRCF TAPS PLLCLK
DRCF filter used normal operation bypassed using DRCF bypass DRCF control register. When DRCF filter bypassed, scaling applied output filter same input DRCF filter.
Scaling
then half clock used processing (power savings). Otherwise, clock should used.
Bypass
output DRCF filter scaled using 2-bit DRCF scaling word DRCF control register. Table lists valid values 2-bit word their corresponding settings.
Table DRCF Scaling Factor Settings
DRCF Scale Word [1:0] Scaling Factor 18.06 attenuation 12.04 attenuation 6.02 attenuation scaling,
MRCF filter used normal operation bypassed using MRCF bypass MRCF control register. When filter bypassed, output filter same input filter. Bypassing MRCF filter when required results power savings.
Scaling
output MRCF filter scaled using 2-bit MRCF scaling word MRCF control register. Table shows valid values 2-bit word their corresponding settings.
Table MRCF Scaling Factor Settings
MRCF Scale Word [1:0] Scaling Factor 18.06 attenuation 12.04 attenuation 6.02 attenuation scaling,
Symmetry
DRCF filter does require symmetrical filters. However, filter symmetrical, then symmetry DRCF control register should set. When this set, only half impulse response needs programmed into DRCF coefficient memory registers. example, number filter taps equal filter symmetrical, then only eight coefficients need written into coefficient memory. Because total taps written into memory registers, DRCF perform asymmetrical filter taps symmetrical filter taps.
Coefficient Offset
DECIMATING COEFFICIENT FILTER (DRCF)
Following MRCF programmable DRCF filter. This filter calculate asymmetrical filter taps symmetrical filter taps. filter also capable programmable decimation rate from flexible coefficient offset feature allows loading multiple filters into coefficient changing filters fly. decimation phase feature allows polyphase implementation, where multiple AD6636 channels used processing single carrier. DRCF filter 20-bit input output data 14-bit coefficient data. number filter taps calculate programmable DRCF taps register. value number taps minus written this register. example, value register corresponds filter taps.
More than filter coefficients loaded into coefficient given time (given sufficient space). coefficient offset used this case access more different filters. changing coefficient offset, filter coefficients being accessed changed fly. This decimal offset value programmed DRCF coefficient offset register. When this value changed during calculation particular output data sample, sample calculation completed using coefficients, coefficient offset from next data sample calculation used.
Decimation Phase
When more than channel AD6636 used process carrier, polyphase implementation corresponding channels' DRCF CRCF possible using decimation phase feature. This feature used only under certain conditions. decimation phase programmed using 4-bit DRCF decimation phase word DRCF control register.
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Maximum Number Taps Calculated
output rate DRCF filter given DRCF where: fMRCF data rate MRCF filter into DRCF filter. MDRCF decimation rate DRCF filter. DRCF filter consists multipliers (one each paths). Each multiplier, working high speed clock rate (PLL clock), multiply tap) high speed clock cycle. Therefore, maximum number filter taps that calculated (symmetrical asymmetrical filter) given
Maximum Number Taps ceil PLLCLK DRCF
MRCF DRCF
After each write access DRCF coefficient memory register, internal address incremented starting with start address ending with stop address.
Note that each write read access increments internal address. Therefore, coefficients should read first before reading them back. Also, debugging purposes, each address written individually making start address stop addresses same. Therefore, program location, user writes address location both start stop address registers, then writes coefficient memory register.
Programming DRCF Registers Symmetric Filter
program DRCF registers symmetrical filter: Write NTAPS DRCF taps register, where NTAPS number filter taps. absolute maximum value NTAPS symmetric filter mode. Write ceil(64 NTAPS/2) DRCF coefficient offset register, where ceil function takes closest integer greater than equal argument. Write symmetrical filter DRCF control register. Write start address coefficient RAM, typically equal coefficient offset register, DRCF start address register. Write stop address coefficient RAM, typically equal ceil(NTAPS/2) DRCF stop address register. Write coefficients DRCF coefficient memory register, starting with middle filter working towards filter. When coefficients numbered NTAPS middle coefficient given coefficient number ceil(NTAPS/2). 8-bit microport mode serial port mode, write lower byte memory register first then higher byte. After each write access DRCF coefficient memory register, internal address incremented starting with start address ending with stop address.
where: fPLLCLK high speed internal processing clock generated clock multiplier. fDRCF output rate DRCF filter calculated above.
Programming DRCF Registers Asymmetrical Filter
program DRCF registers asymmetrical filter: Write NTAPS DRCF taps register, where NTAPS number filter taps. absolute maximum value NTAPS asymmetrical filter mode. Write DRCF coefficient offset register. Write symmetrical filter DRCF control register. Write start address coefficient RAM, typically equal coefficient offset register DRCF start address register. DRCF stop address register, write stop address coefficient RAM, typically equal following: Coefficient Offset NTAPS Write coefficients reverse order (start with last coefficient) DRCF coefficient memory register. 8-bit microport mode serial port mode, write lower byte memory register first then higher byte.
Note that each write read access increments internal address. Therefore, coefficients should read first before reading them back. Also, debugging purposes, each address written individually making start stop addresses same. Therefore, program location, user writes address location both start stop address registers, then writes coefficient memory register.
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CHANNEL COEFFICIENT FILTER (CRCF)
Following DRCF programmable decimating CRCF filter. only difference between DRCF CRCF filters coefficient width. DRCF 14-bit coefficients, while DRCF 20-bit coefficients. This filter calculate asymmetrical filter taps symmetrical filter taps. filter capable programmable decimation rate from flexible coefficient offset feature allows loading multiple filters into coefficient changing filters fly. decimation phase feature allows polyphase implementation which multiple AD6636 channels used process single carrier. CRCF filter 20-bit input output data 14-bit coefficient data. number filter taps calculate programmable CRCF taps register. value number taps minus written this register. example, value register corresponds filter taps. decimation rate programmable using 4-bit CRCF decimation rate word CRCF control register. Again, value written decimation rate minus one.
Bypass Coefficient Offset
More than filter coefficients loaded into coefficient time (given sufficient space). coefficient offset used this case access more different filters. changing coefficient offset, filter coefficients being accessed changed fly. This decimal offset value programmed CRCF coefficient offset register. When this value changed during calculation particular output data sample, sample calculation completed using coefficients coefficient offset brought into effect from next data sample calculation.
Decimation Phase
When more than channel AD6636 used process carrier, polyphase implementation corresponding channels' DRCF CRCF possible using decimation phase feature. This feature used only under certain conditions. decimation phase programmed using 4-bit CRCF decimation phase word CRCF control register.
Maximum Number Taps Calculated
output rate CRCF filter given CRCF where: fDRCF data rate DRCF filter into CRCF filter. MCRCF decimation rate CRCF filter. CRCF filter consists multipliers (one each paths). Each multiplier, working high speed clock rate (PLL clock), multiply once). Therefore, maximum number filter taps that calculated (symmetrical asymmetrical filter) given
Maximum Number Taps ceil PLLCLK CRCF
CRCF filter used normal operation bypassed using CRCF bypass CRCF control register. When CRCF filter bypassed, scaling applied output filter same input CRCF filter.
Scaling output CRCF filter scaled using 2-bit CRCF scaling word CRCF control register. Table shows valid values 2-bit word corresponding settings. COEFF coefficients normalized form) used calculate filter. Table CRCF Scaling Factor Settings
CRCF Scale Word [1:0] Scaling Factor 18.06 attenuation 12.04 attenuation 6.02 attenuation scaling,
DRCF CRCF
where:
Symmetry
CRCF filter does require symmetrical filters. However, filter symmetrical, then symmetry CRCF control register should set. When this set, only half impulse response needs programmed into CRCF coefficient memory registers. example, number filter taps equal filter symmetric, then only eight coefficients need written into coefficient memory. Because total taps written into memory registers, CRCF perform asymmetrical filter taps symmetrical filter taps.
fPLLCLK high speed internal processing clock generated clock multiplier. fCRCF output rate CRCF filter calculated previously.
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Programming CRCF Registers Asymmetrical Filter
program CRCF registers asymmetrical filter: Write NTAPS CRCF taps register, where NTAPS number filter taps. absolute maximum value NTAPS asymmetrical filter mode. Write CRCF coefficient offset register. Write symmetrical filter CRCF control register. CRCF start address register, write start address coefficient RAM, typically equal coefficient offset register. CRCF stop address register, write stop address coefficient RAM, typically equal following: Coefficient Offset NTAPS Write coefficients reverse order (start with last coefficient) CRCF coefficient memory register. 8-bit microport mode serial port mode, write lower byte memory register first then higher byte. 16-bit microport mode, write lower 16-bits CRCF memory register first then high four bits. After each write access CRCF coefficient memory register, internal address incremented starting with start address ending with stop address.
CRCF stop address register, write stop address coefficient RAM, typically equal ceil(NTAPS/2) Write coefficients CRCF coefficient memory register, starting with middle filter working towards filter. When coefficients numbered NTAPS middle coefficient given coefficient number ceil(NTAPS/2). 8-bit microport mode serial port mode, write lower byte memory register first then higher byte. 16-bit microport mode, write lower 16-bits CRCF memory register first then high four bits. After each write access CRCF coefficient memory register, internal address incremented starting with start address ending with stop address.
Note that each write read access increments internal address. Therefore, coefficients should read first before reading them back. Also, debugging purposes, each address written individually making start stop addresses same. Therefore, program location, user writes address location both start stop address registers, then writes coefficient memory register.
INTERPOLATING HALF-BAND FILTER
AD6636 interpolating half-band filters that immediately follow CRCF programmable filters precede second data router. Each interpolating half-band filter takes 22-bit 22-bit data from preceding CRCF outputs rounded 22-bit 22-bit data second data router. 10-tap fixed-coefficient filter implemented this stage. maximum input rate into this block MHz. Consequently, maximum output constrained MHz. normalized coefficients used implementation 10-bit decimal equivalent value coefficients listed Table Other coefficients
Table Interpolating Filter Fixed Coefficients
Coefficient Number Normalized Coefficient 0.02734375 -0.12890625 0.603515625 Decimal Coefficient (10-Bit)
Note that each write read access increments internal address. Therefore, coefficients should read first before reading them back. Also, debugging purposes, each address written individually making start stop addresses same. Therefore, program location, user writes address location both start stop address registers, then writes coefficient memory register.
Programming CRCF Registers Symmetrical Filter
program CRCF registers symmetrical filter: Write NTAPS CRCF taps register, where NTAPS number filter taps. absolute maximum value NTAPS symmetrical filter mode. Write ceil(64 NTAPS/2) CRCF coefficient offset register, where ceil function takes closest integer greater than equal argument. Write symmetrical filter CRCF control register. CRCF start address register, write start address coefficient RAM, typically equal coefficient offset register.
half-band filters interpolate incoming data channel running chip rate, half-band used output channel data chip rate. interpolation operation creates image baseband signal, which filtered half-band filter.
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image rejection this filter about still sufficient, because image from desired signal, interfering signal. Note that interpolating half-band filter enabled writing Logic MRCF control registers. frequency response interpolating half-band shown Figure with respect chip rate. input rate this filter chip rate, output rate chip rate.
0.75 1.25
second subblock perform special functions, either complex filter completion biphase filtering. combined data passed AGCs.
Interleaving Data
some cases, filtering using single channel insufficient. such setups, advantageous combine filtering resources more than channel. Multiple channels work input port data with same filter setups. decimation phase values filters such that channel filters exactly phase with each other. data router, these multiple channels interleaved (combined) form single stream data. Because each individual channel decimated more than would single channel were filtering, larger number filter taps calculated. example, channels need work together produce filter output rate when input rate MHz. Each channel decimated factor (total decimation) achieve desired output rate each. This compares decimation single channel were filtering. same coefficients programmed both channels' filters, decimation phases decimation phases channel, second channel pair. This causes first channel produce even outputs, second produce outputs filter. streams then recombined (interleaved) produce desired output rate. benefit that each channel's time calculate twice many taps, because lower output rate.
AGC0 AGC0
INTERPOLATING HALFB FILTER RESPONSE
-100 FREQUENCY FRACTION INPUT RATE
Figure Interpolating Half-Band Frequency Response
OUTPUT DATA ROUTER
output data router circuit precedes AGCs final output block immediately follows interpolating halfband filters. This block consists subblocks. first subblock responsible combining (interleaving) data from more than channel into single stream data.
STR0
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STR1
AGC1 AGC1 PARALLEL PORT
STREAM CONTROL
STR2 COMPLEX FILTER COMPLETION STR3
AGC2 AGC2 PARALLEL PORT AGC3 AGC3
STR4
AGC4 AGC4
PARALLEL PORT
AGC5
Figure Output Data Router Block Diagram
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STR5
AGC5
AD6636
interleaving function simple time-multiplexing function, with lower data rate input side higher data rate output side. output data rate input stream data rates that combined. channels that need combined programmable with sufficient flexibility. Table gives combinations that possible using 4-bit word (stream control bits) Parallel Port Control register. After interleaving data (see Output Data Router section), data passed second subblock, which either complex filter completion biphase filtering performed.
Complex Filter Completion
terms calculated follows: (ICi, QCi) from first channel (Icq, QCq) from second channel
Using these terms, complex filter completed applying following formula: jCq) (ICi QCq) j(ICq QCi) channels combined programmed using 3-bit complex control word Parallel Output Control register. values 3-bit control word corresponding settings listed Table These outputs available AGCs. AGCs need used different applications, unused AGCs bypassed output data streams ignored parallel output ports. example, Streams combined complex filter, bypassed, because Stream already combined into Stream sent
normal operation, each individual channel's filter performs real coefficient, complex data filtering. channels used perform complex coefficient data filtering. channel loaded with real part (in-phase) coefficients; other channel loaded with imaginary part (quadrature) coefficients.
Table Stream Control Combinations
Stream Control Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 other state
Output Streams combined, independent 0/1/2 combined, independent 0/1/2/3 combined; independent 0/1/2/3/4 combined; independent 0/1/2/3/4/5 combined 0/1/2 combined, 3/4/5 combined combined, combined, combined combined, combined, independent 0/1/2 combined, combined, independent 0/1/2/3 combined, combined. Independent channels
Streams
Table Definitions Complex Control Register Selections
Complex Control Word Data Routing complex filters Stream combined Stream combined, Stream combined Stream combined, Stream combined, Stream combined Stream Combined Stream combined, Stream combined Stream combined, Stream combined, Stream combined Comments Stream control register controls usage. Allows form complex filter. Allows form complex filter form complex filter. Allows form complex filter, form complex filte,r form complex filter. Allows form biphase filter. Allows form biphase filter, form biphase filter. Allows form biphase filter, form biphase filter, form biphase filter.
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Biphase Filtering Option
second special function that performed second subblock output data router called biphase filtering option. With this option, AD6636 used process data from ADCs that faster than input clock frequency using channels streams form biphase filter. example, used with clock rate driving ADC. data decimated produce even data streams data. even stream clocked into Input Port stream clocked into Input Port These input ports drive separate channels separate groups channels. filters designed place sample time difference (1/300 between even path filters. After channel-filter coefficients have appropriate delay, complex addition even sample channels performed create single filter. This equivalent filter looks like single channel with input rate, even though clock rate chip runs only MHz. biphase filter summation implemented following equation: Output j(Qe where: even in-phase quadrature-phase samples from stream. in-phase quadrature-phase samples from other stream. even coefficients, which differ high speed sample time (300 previous example). Users program certain streams summed using biphase filtering option. This option programmed using same 3-bit complex control word Parallel Output Control register. values 3-bit control word their corresponding settings listed Table
bits. Because small signals from lower bits pushed higher bits adding gain, clipping lower bits does compromise signal interest. maintains constant mean power output despite level signal interest, allowing operation environments where dynamic range signal exceeds dynamic range output resolution. output width writing 3-bit word length word control register individual channel's memory map. bypassed, needed, and, when bypassed, 24-bit complex input word still truncated 16-bit value that output through parallel port output. AGCs available AD6636 programmable through channel memory maps. AGCs corresponding individual channels bypassed writing Logic bypass control register. Three sources error introduced function: underflow, overflow, modulation. Underflow caused truncation bits below output range. Overflow caused clipping errors when output signal exceeds output range. Modulation error occurs when output gain varies while receiving data. desired signal level should based probability density function signal, that errors underflow overflow balanced. gain damping values loop filter should set, that fast enough track long-term amplitude variations signal that might cause excessive underflow overflow, slow enough avoid excessive loss amplitude information modulation signal.
Loop
loop implemented using log-linear architecture. contains four basic operations: power calculation, error calculation, loop filtering, gain multiplication. configured operate either desired signal level mode desired clipping level mode. mode clipping error control register. adjusts gain incoming data according from given desired signal level desired clipping level, depending selected mode operation. datapaths loop provided: before clipping circuitry after clipping circuitry, shown Figure desired signal level mode, only path from before clipping used. desired clipping level mode, difference signals from before after clipping circuitry used.
AUTOMATIC GAIN CONTROL
AD6636 equipped with independent automatic gain control (AGC) loops that directly follow second data router immediately precede parallel output ports. Each circuit range. important that decimating filters AD6636 preceding reject unwanted signals, that each loop operating only carrier interest, carriers other frequencies affect ranging loop. compresses 24-bit complex output from second data router into programmable word size
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BITS CLIP GAIN MULTIPLIER CLIP PROGRAMMABLE WIDTH USED ONLY DESIRED CLIPPING LEVEL MODE
POWER
MEAN SQUARE AVERAGE 16384 SAMPLES DECIMATE 4096 SAMPLES SQUARE ROOT log2(x) ERROR THRESHOLD ERROR GAIN GAIN POLE DESIRED
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Figure Block Diagram
Desired Signal Level Mode
this mode operation, strives maintain output signal programmable level. desired signal level mode selected writing Logic into clipping error enable control register. loop finds square power) incoming complex data signal squaring adding them. loop average decimate block. This average decimate operation takes place power samples before square root operation. This block programmed average from 16,384 power samples, decimate section programmed update once every 4,096 samples. limitation averaging operation that number averaged power samples should multiple decimation value averaging decimation effectively means that operate over averaged power 16,384 output samples. Updating once every 4,096 samples operating average power facilitates implementation loop filter with slow time constants, where error converges slowly makes infrequent gain adjustments. also useful when user wants keep gain scaling constant over frame data stream symbols. limitation that number average samples must multiple decimation value, only multiple numbers programmed. This using average samples word average sample register. These averaged samples then decimated with decimation ratios programmable from 4,096. This decimation ratio defined 12-bit update decimation register. average decimate operations tied together implemented using first-order filter FIFO registers. Gain growth associated with filters depend decimation ratio. compensate gain associated
with these operations, attenuation scaling provided before filter. This scaling operation accounts division associated with averaging operation well traditional growth filters. Because this scaling implemented bit-shift operation, only coarse scaling possible. Fine scaling implemented offset request level, explained later this section. attenuation scaling SCIC programmable from using 4-bit scale word average samples register given
SCIC ceil
where: MCIC decimation ratio 4,096). NAVG number averaged samples programmed multiple decimation ratio example, decimation ratio Mcic 1,000 Navg (decimation 1,000 averaging 3,000 samples), then actual gain averaging decimation 3,000 69.54 (log2 (3000)). Because attenuation implemented bitshift operation, only multiples 6.02 attenuations possible. SCIC this case corresponding 72.24 This way, SCIC scaling always attenuates more than sufficient compensate gain average decimate sections and, therefore, prevents overflows loop. also evident that SCIC scaling induces gain error (the difference between gain attenuation provided scaling) 6.02 This error should compensated request signal level, explained later this section. logarithm Base applied output from average decimate section. These decimated power samples converted signal samples applying square root operation. This square root implemented using simple shift
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operation logarithmic domain. samples obtained subtracted from request signal level specified desired level register, leaving error term processed loop filter, G(z). user sets this programmable request signal level according output signal level that desired. request signal level programmable from -23.99 steps 0.094 request signal level should also compensate errors, any, scaling, explained previously this section. Therefore, request signal level offset amount error induced CIC, given Offset log(MCIC Navg) SCIC 3.01 where Offset Continuing previous example, this offset given Offset 72.24 69.54 request signal level given (DSL Offset -ceil 0.094 dBFS 0.094 where: request signal level. (desired signal level) output signal level that user desires. Therefore, previous example, desired signal level -13.8 request level programmed -16.54 compensating offset. This request signal level programmed 8-bit desired level register. This register floating-point representation, where MSBs exponent bits LSBs mantissa bits. exponent steps 6.02 mantissa steps 0.094 example, value 10'100101 represents 6.02 0.094 15.518 provides programmable second-order loop filter. programmable parameters gain (K1), gain (K2), error threshold pole completely define loop filter characteristics. error term after subtracting request signal level processed loop filter, G(z). open loop poles second-order loop filter respectively. loop filter parameters, pole gain allow adjustment filter time constant that determines window calculating peak-to-average ratio. Depending value error term that obtained after subtracting request signal level from actual signal level, either gain value, used. error less than
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programmable threshold used. This allows fast loop when error term high (large convergence steps required) slower loop function when error term smaller (almost converged). open-loop gain used second-order loop G(z) given following equations: Error Error Threshold Error Error Threshold open-loop transfer function filter, including gain parameter,
properly configured terms offset request level, then there gains loop except filter gain Under these circumstances, closed-loop expression loop given
closed
gain parameters pole programmable through loop gain pole location registers from 0.996 steps 0.0039 using 8-bit representation. example, 1000 1001 represent (137/256 0.535156). error threshold value programmable between 96.3 steps 0.024 This value programmed 12-bit error threshold register, using floating-point representation. consists four exponent bits eight mantissa bits. Exponent bits steps 6.02 mantissa bits steps 0.024 example, 0111'10001001 represents 6.02 0.024 45.428 user defines open-loop pole gain which also directly impact placement closed-loop poles filter characteristics. These closed-loop poles, roots denominator previous closed-loop transfer function given
Typically, loop performance defined terms time constant settling time. this case, closed-loop poles should meet time constants required loop.
AD6636
relationship between time constant closed-loop poles that used this purpose
Sample Rate where time constants corresponding poles time constants also derived from settling times given signal level more slowly compared averaging. same applies manner which addresses sudden decrease signal level.
Desired Clipping Level Mode
settling time
settling time
MCIC (CIC decimation from 4,096), either settling time time constant chosen user. sample rate sample rate stream coming into AGC. channels were interleaved output data router, then combined sample rate into should considered. This rate should used calculation poles previous equation, where sample rate mentioned. loop filter output corresponds signal gain that updated AGC. Because computation loop filter done logarithmic domain Base samples, signal gain generated using exponent (power loop filter output. gain multiplier gives product signal gain with both data entering section. This signal gain applied coarse 4-bit scaling then fine scale 8-bit multiplier. Therefore, applied signal gain from 96.3 steps 0.024 initial signal gain programmable using signal gain register. This register again exponent mantissa floating-point representation similar error threshold. This taken initial gain value before loop starts operating. products gain multiplier scaled outputs with 19-bit representation. These turn used calculating power, error loop filtered produce signal gain next samples. These scaled outputs programmed have 10-, 12-, 16-bit widths using output word length word control register. scaled outputs truncated required widths using clipping circuitry, shown Figure
Average Samples Setting
Each configured that loop locks onto desired clipping level desired signal level. Desired clipping level mode selected writing Logic clipping error mode control register. signals that tend exceed bounds peak-to-average ratio, desired clipping level option provides prevent truncating those signals still provide that attacks quickly settles desired output level. signal path this mode operation shown with dotted lines Figure operation similar desired signal level mode. First, data from gain multiplier truncated lower resolution bits) output word length word control register. error term (for both generated that difference between signals before after truncation. This term passed complex squared magnitude block, averaging decimating update samples taking their square root find samples desired signal level mode. place request desired signal level, desired clipping level subtracted, leaving error term processed secondorder loop filter. rest loop operates same desired signal level mode. This way, truncation error calculated loop operates maintain constant truncation error level. only register setting that different from desired signal level mode settings that desired clipping level stored desired level registers instead request signal level.
Synchronization
When output connected RAKE receiver, RAKE receiver synchronize average update section update average power error calculation loop filtering. This external sync signal synchronizes changes RAKE receiver makes sure that gain word does change over symbol period, which, therefore, provides more accurate estimation. This synchronization accomplished setting appropriate bits control register.
Sync Select Alternatives
receive sync follows: Channel sync: sync signal used synchronize channel under consideration. sync: Select four SYNC pins. Sync bit: Through control register.
Though complicated express exact effect number averaging samples using equations, intuitively smoothing effect loop addresses sudden increase spike signal level. averaging four samples used, addresses sudden increase
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AD6636
When channel sync select control register Logic receives SYNC signal used corresponding channel start. When this Logic sync defined 2-bit SYNC select word control register used provide sync AGC. Apart from these methods, control register also sync that used provide sync writing this register through microport serial port.
Sync Process
PARALLEL PORT OUTPUT
AD6636 incorporates three independent 16-bit parallel ports output data transfer. three parallel output ports share common clock, PCLK. Each port consists 16-bit data bus, REQuest signal, ACKnowledge signal, three channel indicator pins, indicator pin, gain word indicator pin, common shared PCLK pin. parallel ports configured function master mode slave mode. default, parallel ports slave mode power-up. Each parallel port output data from AGCs, using 1-bit enable each parallel port control register. Even when required certain channel, bypassed, data still received from bypassed AGC. parallel port functionality programmable through parallel port control registers. Each parallel port programmed individually operate either interleaved mode parallel mode. mode selected using 1-bit data format parallel port control register. both modes, gain word output enabled using 1-bit append gain parallel port control register individual output ports. There enable bits output port, each corresponding parallel port.
Interleaved Mode
Regardless sync signal received, syncing process same. When sync received, start hold-off counter loaded with 16-bit value hold-off register, which initiates countdown. countdown based input clock. When count reaches sync initiated. When sync initiated, decimation filter dumps current value square root, error estimation, loop filter blocks. After dumping current value, starts working toward next update value. Additionally sync, initialized initialize sync control register. During initialization, accumulator cleared values decimation, number averaging samples, scale, signal gain, open-loop gains pole parameter loaded from their respective registers. When initialize sync cleared, these parameters loaded from registers. This sync process also initiated when channel comes sleep using start sync NCO. additional feature first sync only control register. When this set, only first sync initiates process remaining sync signals ignored. This useful when syncing using sync. sync required only first pulse this pin. These additional features make synchronization more flexible applicable varied circumstances.
Parallel port channel mode selected writing data format parallel port consideration. this mode, words from output same 16-bit data time-multiplexed basis. 16-bit word output followed 16-bit word. specific AGCs output port selected setting individual bits each AGCs parallel port control register. Figure shows timing diagram interleaved mode.
PCLKn
PxACK
tDPREQ
PxREQ
tDPP
[15:0] [15:0] [15:0]
tDPIC
PxIQ
tDPCH
PxCH [2:0] PxCH [2:0] CHANNEL
04998-0-040
LOGIC PxGAIN
Figure Interleaved Mode without Gain Word
Rev. Page
AD6636
When output data sample available output from AGC, parallel port initiates transfer pulling PxREQ signal high. response, processor receiving data needs pull PxACK signal high, acknowledging that ready receive signal. Figure PxACK already pulled high and, therefore, 16-bit data output data next PCLK rising edge after PxREQ driven logic high. PxIQ signal also goes high indicate that data available data bus. next PCLK cycle brings data onto data bus. this cycle, PxIQ signal driven low. When data data output, channel indicator pins PxCH[2:0] indicate data source (AGC number). Figure timing diagram interleaved mode with gain word disabled. Figure similar timing diagram with gain word. data explained Figure PCLK cycle after data, gain word output data PxGAIN signal pulled high indicate that gain word available parallel port. Therefore, minimum three four PCLK cycles required output sample output data parallel port without with gain word, respectively.
Parallel Mode
this mode, eight bits data eight bits data output data simultaneously during PCLK cycle. byte most significant byte port, while byte least significant byte. PAIQ PBIQ output indicator pins high during PCLK cycle. Note that data from multiple AGCs output consecutively, PAIQ PBIQ output indicator pins remain high until data from channels output. PACH[2:0] PBCH[2:0] pins provide 3-bit binary value indicating source (AGC number) data currently being output. Figure timing diagram parallel mode.
PCLKn
PxACK
tDPREQ
PxREQ
tDPP
[15:0] I[15:0] Q[15:0] GAIN [11:0] 0000
tDPIQ
PxIQ
tDPCH
PxCH [2:0] PxCH [2:0] CHANNEL
04998-0-041
tDPGAIN<b
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