Preliminary Technical DatHigh performance 32-bit/40-bit floating point
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SUMMARY
Preliminary Technical DatHigh performance 32-bit/40-bit floating point processor optimized professional audio processing MHz/2 GFLOPs, with unique audio centric peripherals such Digital Audio Interface that includes highprecision 8-channel asynchronous sample rate converter among others, ADSP-21364 SHARC processor ideal applications that require industry leading equalization, reverberation other effects processing Single-Instruction Multiple-Data (SIMD) computational architecture 32-bit IEEE floating-point/32-bit fixed-point/40-bit extended precision floating-point computational units, each with multiplier, ALU, shifter, register file
SHARC® Processor ADSP-21364
On-chip memory-3M on-chip SRAM dedicated on-chip mask-programmable Code compatible with other members SHARC family ADSP-21364 available with core instruction rate unique audio centric peripherals such Digital Audio Interface, S/PDIF transceiver, serial ports, 8channel asynchronous sample rate converter, precision clock generators more. complete ordering information, Ordering Guide Page
CORE PROCESSOR
TIMER INSTRUCTION CACHE 48-BIT
BLOCKS ON-CHIP MEMORY
BLOCK SRAM BLOCK SRAM BLOCK SRAM 0.5M BLOCK SRAM 0.5M
DAG1 8X4X32
DAG2 8X4X32
PROGRAM SEQUENCER
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDRESS ADDRESS DATA
DATA
REGISTER PROCESSING ELEMENT (PEX) PROCESSING ELEMENT (PEY)
REGISTERS (MEMORY MAPPED)
SPORTS TIMERS SPDIF
SIGNAL ROUTING UNIT
JTAG TEST EMULATION
Figure Functional Block Diagram Processor Core
SHARC SHARC logo registered trademarks Analog Devices, Inc.
PROCESSOR PERIPHERALS
"ADSP-21364 MEMORY INTERFACE FEATURES" SECTION DETAILS
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106 U.S.A. Tel:781.329.4700 www.analog.com Fax:781.326.8703 2004 Analog Devices, Inc. rights reserved.
ADSP-21364
FEATURES PROCESSOR CORE
(3.0 core instruction rate, ADSP-21364 performs GFLOPS/666 MMACS on-chip single-ported SRAM blocks 0.50M blocks simultaneous access core processor on-chip single-ported mask-programmable block block Dual Data Address Generators (DAGs) with modulo bit-reverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single Instruction Multiple Data (SIMD) architecture provides: computational processing elements Concurrent execution Code compatibility with other SHARC family members assembly level Parallelism busses computational units allows single cycle execution (with without SIMD) multiply operation, dual memory read write, instruction fetch Transfers between memory core sustained Gbytes/s bandwidth core instruction rate
Preliminary Technical DatUp stream support, each with channels frame Companding selection channel basis mode Input data port provides additional input path SHARC core, configurable eight channels serial data seven channels serial data single channel 20-bit wide parallel data Signal routing unit provides configurable flexible connections between components-six serial ports, precision clock generators, input data port with data acquisition port, port, eight channels asynchronous sample rate converters, three timers, interrupts, flag inputs, flag outputs, pins (DAI_Px) Serial Peripheral Interfaces (SPI): primary dedicated pins, secondary pins provide: Master slave serial boot through primary Full-duplex operation Master-Slave mode multi-master support Open drain outputs Programmable baud rates, clock polarities phases Muxed Flag/IRQ lines Muxed Flag/Timer expired line
DEDICATED AUDIO COMPONENTS
S/PDIF Compatible Digital Audio receiver/transmitter supports: EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards Left justified, right justified serial data input with word widths (transmitter) channel mode Single Channel Double Frequency (SCDF) mode Sample Rate Converter (SRC) Contains Serial Input Port, Deemphasis Filter providing -140db performance, Sample Rate Converter (SRC) Serial Output Port Supports Left Justified, I2S, Right Justified serial formats (input) Pulse Width Modulation provides: outputs configured four groups four outputs Supports center-aligned edge-aligned waveforms generate complementary signals outputs paired mode independent signals nonpaired mode wide variety software hardware multiplier/divider ratios Dual voltage: I/O, core Available 136-ball Mini-BGA 144-lead LQFP Packages
INPUT/OUTPUT FEATURES
Controller supports: channels transfers between ADSP-21364 internal memory variety peripherals 32-bit transfers core clock speed, parallel with fullspeed processor execution Asynchronous parallel port provides access asynchronous external memory multiplexed address/data lines support 24-bit address external address range with 8-bit data 16-bit address external address range with 16-bit data Mbyte transfer rate External memory access dedicated channel 32-bit packing options Programmable data cycle duration: CCLK Digital audio interface (DAI) includes serial ports, Precision Clock Generators, Input Data Port, three timers, eight-channel asynchronous sample rate converter, Signal routing unit dual data line serial ports that operate bit/s each data line-each clock, frame sync data lines that configured either receiver transmitter pair Left-justified Sample Pair Support, programmable direction simultaneous receive transmit channels using compatible stereo devices serial port support telecommunications interfaces including channel support newer telephony interfaces such H.100/H.110
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Preliminary Technical DatGENERAL DESCRIPTION
ADSP-21364 SHARC processor member SIMD SHARC family DSPs that feature Analog Devices' Super Harvard Architecture. ADSP-21364 source code compatible with ADSP-2126x, ADSP-2116x DSPs well with first generation ADSP-2106x SHARC processors SISD (Single-Instruction, Single-Data) mode. ADSP-21364 32bit/40-bit floating point processor optimized professional audio applications with large on-chip SRAM, multiple internal buses eliminate bottlenecks, innovative Digital Audio Interface (DAI). shown functional block diagram Page ADSP-21364 uses computational units deliver significant performance increase over previous SHARC processors range signal processing algorithms. Fabricated state-ofthe-art, high speed, CMOS process, ADSP-21364 processor achieves instruction cycle time MHz. With SIMD computational hardware, ADSP-21364 perform GFLOPS running MHz. Table shows performance benchmarks ADSP-21364. Table ADSP-21364 Benchmarks MHz)
Speed MHz) 1024 Point Complex (Radix with reversal) 27.9 Filter (per tap)1 Filter (per biquad)1 Matrix Multiply (pipelined) [3x3] [3x1] 13.5 [4x4] [4x1] 23.9 Divide 10.5 Inverse Square Root 16.3
ADSP-21364
16-bit Parallel port that supports interfaces off-chip memory peripherals JTAG test access port block diagram ADSP-21364 Page illustrates following architectural features: controller full duplex serial ports SPI-compatible interface ports-primary dedicated pins secondary pins Digital Audio Interface that includes precision clock generators (PCG), input data port (IDP), S/PDIF receiver/transmitter, eight channels asynchronous sample rate converters, serial ports, eight serial interfaces, 20bit parallel input port, interrupts, flag outputs, flag inputs, three timers, flexible signal routing unit (SRU) Figure Page shows sample configuration SPORT using precision clock generators interface with with much lower jitter clock than serial port would generate itself. Many other configurations possible.
Benchmark Algorithm
ADSP-21364 FAMILY CORE ARCHITECTURE
ADSP-21364 code compatible assembly level with ADSP-2126x, ADSP-21160 ADSP-21161, with first generation ADSP-2106x SHARC DSPs. ADSP-21364 shares architectural features with ADSP-2126x ADSP-2116x SIMD SHARC processors, detailed following sections.
SIMD Computational Engine
ADSP-21364 contains computational processing elements that operate Single-Instruction Multiple-Data (SIMD) engine. processing elements referred each contains ALU, multiplier, shifter register file. always active, enabled setting PEYEN mode MODE1 register. When this mode enabled, same instruction executed both processing elements, each processing element operates different data. This architecture efficient executing math intensive signal processing algorithms. Entering SIMD mode also effect data transferred between memory processing elements. When SIMD mode, twice data bandwidth required sustain computational operation processing elements. Because this requirement, entering SIMD mode also doubles bandwidth between memory processing elements. When using DAGs transfer data SIMD mode, data values transferred with each access memory register file.
Assumes files multichannel SIMD mode
ADSP-21364 continues SHARC's industry leading standards integration DSPs, combining high performance 32-bit core with integrated, on-chip system features. block diagram ADSP-21364 Page illustrates following architectural features: processing elements, each which comprises ALU, Multiplier, Shifter Data Register File Data Address Generators (DAG1, DAG2) Program sequencer with instruction cache buses capable supporting four 32-bit data transfers between memory core every core processor cycle Three Programmable Interval Timers with Generation, Capture/Pulse width Measurement, External Event Counter Capabilities On-Chip SRAM bit) On-Chip mask-programmable bit)
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ADSP-21364
ADSP-21364
CLKOUT CLOCK CLKIN XTAL CLK_CFG1-0 BOOTCFG1-0 FLAG3-1 FLAG0 (OPTIONAL) SDAT AD15-0 LATCH
Preliminary Technical
ADDR DATA
PARALLEL PORT RAM, DEVI
CONTROL
DATA
ADDRESS
DAI_P1 DAI_P2 DAI_P3 DAI_P18 DAI_P19 DAI_P20 SCLK0 SFS0 SD0A SD0B SPORT0-5 TIMERS SPDI
(OPTIONAL) SDAT
RESET
PCGA
JTAG
Figure ADSP-21364 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element computational units. computational units consist arithmetic/logic unit (ALU), multiplier, shifter. These units perform operations single cycle. three units within each processing element arranged parallel, maximizing computational throughput. Single multifunction instructions execute parallel multiplier operations. SIMD mode, parallel multiplier operations occur both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, 32-bit fixed-point data formats.
Single-Cycle Fetch Instruction Four Operands
ADSP-21364 features enhanced Harvard architecture which data memory (DM) transfers data program memory (PM) transfers both instructions data (see Figure Page With ADSP-21364's separate program data memory buses on-chip instruction cache, processor simultaneously fetch four operands (two over each data bus) instruction (from cache), single cycle.
Instruction Cache
ADSP-21364 includes on-chip instruction cache that enables three-bus operation fetching instruction four data values. cache selective-only instructions whose fetches conflict with data accesses cached. This cache allows full-speed execution core, looped operations such digital filter multiply-accumulates, butterfly processing.
Data Register File
general-purpose data register file contained each processing element. register files transfer data between computation units data buses, store intermediate results. These 10-port, 32-register primary, secondary) register files, combined with ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units internal memory. registers referred R0-R15 S0-S15.
Data Address Generators With Zero-Overhead Hardware Circular Buffer Support
ADSP-21364's data address generators (DAGs) used indirect addressing implementing circular data buffers hardware. Circular buffers allow efficient programming delay lines other data structures required digital
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Preliminary Technical Datsignal processing, commonly used digital filters Fourier transforms. DAGs ADSP-21364 contain sufficient registers allow creation circular buffers primary register sets, secondary). DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, simplify implementation. Circular buffers start memory location.
ADSP-21364
On-Chip Memory
ADSP-21364 contains three megabits internal SRAM. Each block configured different combinations code data storage (see Table Page Each memory block supports single-cycle, independent accesses core processor processor. ADSP-21364 memory architecture, combination with separate on-chip buses, allow data transfers from core from processor, single cycle. ADSP-21364's, SRAM configured maximum words 32-bit data, 192K words 16-bit data, words 48-bit instructions 40-bit data), combinations different word sizes three megabits. memory accessed 16-bit, 32-bit, 48-bit, 64-bit words. 16-bit floating-point storage format supported that effectively doubles amount data that stored on-chip. Conversion between 32-bit floating-point 16-bit floating-point formats performed single instruction. While each memory block store combinations code data, accesses most efficient when block stores data using transfers, other block stores instructions data using transfers.
Flexible Instruction
48-bit instruction word accommodates variety parallel operations, concise programming. example, ADSP-21364 conditionally execute multiply, add, subtract both processing elements while branching fetching four 32-bit values from memory-all single instruction.
ADSP-21364 MEMORY INTERFACE FEATURES
ADSP-21364 adds following architectural features SIMD SHARC family core.
Table ADSP-21364 Internal Memory Space
Registers 0x0000 0000 0003 FFFF Long Word bits) BLOCK 0x0004 0000- 0x0004 7FFF Reserved 0x0004 8000-0x0004 BFFF BLOCK 0x0004 C000-0x0004 FFFF BLOCK 0x0005 0000-0x0005 7FFF Reserved 0x0005 8000-0x0005 BFFF BLOCK 0x0005 C000-0x0005 FFFF BLOCK 0x0006 0000-0x0006 1FFF Reserved 0x0006 2000-0x0006 FFFF BLOCK 0x0007 0000-0x0007 1FFF Reserved 0x0007 2000-0x0007 FFFF BLOCK 0x000E 0000-0x000E 2AAA BLOCK 0x000B 0000-0x000B 5555 BLOCK 0x000C 0000-0x000C 2AAA BLOCK 0x0009 0000-0x0009 5555 BLOCK 0x000A 0000-0x000A AAAA Extended Precision Normal Normal Word bits) Instruction Word bits) BLOCK 0x0008 0000-0x0008 AAAA BLOCK 0x0008 0000- 0x0008 FFFF Reserved 0x0009 0000-0x0009 7FFF BLOCK 0x0009 8000-0x0009 FFFF BLOCK 0x000A 0000- 0x000A FFFF Reserved 0x000B 0000-0x000B 7FFF BLOCK 0x000B 8000-0x000B FFFF BLOCK 0x000C 0000-0x000C 3FFF Reserved 0x000C 4000- 0x000D FFFF BLOCK 0x000E 0000-0x000E 3FFF Reserved 0x000E 4000-0x000F FFFF Short Word bits) BLOCK 0x0010 0000-0x0011 FFFF Reserved 0x0012 0000-0x0012 FFFF BLOCK 0x0013 0000-0x0013 FFFF BLOCK 0x0014 0000-0x0015 FFFF Reserved 0x0016 0000-0x0016 FFFF BLOCK 0x0017 0000-0x0017 FFFF BLOCK 0x0018 0000-0x0018 7FFF Reserved 0x0018 8000-0x001B FFFF BLOCK 0x001C 0000-0x001C 7FFF Reserved 0x001C 8000-0x001F FFFF Reserved 0x0020 0000-0xFFFF FFFF
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ADSP-21364
Using buses, with dedicated each memory block assures single-cycle execution with data transfers. this case, instruction must available cache.
Preliminary Technical DatDigital Audio Interface (DAI)
Digital Audio Interface (DAI) provides ability connect various peripherals SHARCs pins (DAI_P20-1). Programs make these connections using Signal Routing Unit (SRU, shown Figure matrix routing unit group multiplexers) that enables peripherals provided interconnected under software control. This allows easy associated peripherals much wider variety applications using larger algorithms than possible with nonconfigurable signal paths. also includes serial ports, precision clock generators (PCGs), eight channels asynchronous sample rate converters, input data port (IDP), port, flag outputs flag inputs, three timers. provides additional input path ADSP-21364 core, configurable either eight channels serial data seven channels plus single 20-bit wide synchronous parallel data acquisition port. Each data channel channel that independent from ADSP-21364's serial ports. complete information using DAI, ADSP2136x SHARC Processor Hardware Reference.
Controller
ADSP-21364's on-chip controller allows data transfers without processor intervention. controller operates independently invisibly processor core, allowing operations occur while core simultaneously executing program instructions. transfers occur between ADSP-21364's internal memory serial ports, SPI-compatible (Serial Peripheral Interface) ports, (Input Data Port), Parallel Data Acquisition Port (PDAP), parallel port. Twenty-five channels available ADSP-21364-two interface, memory-to-memory transfers, twelve serial ports, eight Input Data Port, processor's parallel port. Programs downloaded ADSP-21364 using transfers. Other features include interrupt generation upon completion transfers, chaining automatic linked transfers.
PROCES BUSS
DATA
Serial Ports
ADDRE
FLAGS/I RQ/TIMEXP CONTROLLER
ADSP-21364 features synchronous serial ports that provide inexpensive interface wide variety digital mixed-signal peripheral devices such Analog Devices' AD183x family audio codecs, ADCs, DACs. serial ports made data lines, clock frame sync. data lines programmed either transmit receive each data line dedicated channel. Serial ports enabled programmable simultaneous receive transmit pins that support transmit receive channels audio data when SPORTS enabled, full duplex streams channels frame. serial ports operate maximum data rate bits/s. Serial port data automatically transferred from on-chip memory dedicated channels. Each serial ports work conjunction with another serial port provide support. SPORT provides transmit signals while other SPORT provides receive signals. frame sync clock shared. Serial ports operate four modes: Standard serial mode Multichannel (TDM) mode mode Left-justified sample pair mode Left-justified sample pair mode mode where each frame sync cycle samples data transmitted/received-one sample high segment frame sync, other segment frame sync. Programs have control over various attributes this mode.
ARALLEL
PORT
Figure ADSP-21364 Processor Peripherals Block Diagram
CONTROL, STAT DATA BUFFERS
REGISTERS (MEMO MAPPED)
ERIAL PORTS
SIGNAL UTING UNIT
INPUT DATA ORTS
RECI CLOCK GENERATORS
SPDIF (RX/
CHANNELS)
DIGITAL AUDIO INTERFACE PROCESSOR
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Preliminary Technical DatEach serial ports supports left-justified sample pair protocols (I2S industry standard interface commonly used audio codecs, ADCs DACs such Analog Devices AD183x family), with data pins, allowing four left-justified sample pair channels (using stereo devices) serial port, with maximum channels. serial ports permit little-endian big-endian transmission formats word lengths selectable from bits bits. left-justified sample pair modes, dataword lengths selectable between bits bits. Serial ports offer selectable synchronization transmit modes well optional µ-law A-law companding selection channel basis. Serial port clocks frame syncs internally externally generated.
ADSP-21364
S/PDIF Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter
S/PDIF transmitter separate channels. receives audio data serial format converts into biphase encoded signal. serial data input transmitter formatted left justified, right justified with word widths bits. serial data, clock, frame sync inputs S/PDIF transmitter routed through Signal Routing Unit (SRU). They come from variety sources such SPORTs, external pins, precision clock generators (PCGs), sample rate converters (SRC) controlled control registers. sample rate converter (SRC) contains four blocks same core that used AD1896 Stereo Asynchronous Sample Rate Converter providing 140dB SNR. block used perform synchronous asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. four blocks also configured operate together convert multichannel audio data without phase mismatches. Finally, used clean audio data from jittery clock sources such S/PDIF receiver.
Parallel Port
Parallel Port provides interfaces SRAM peripheral devices. multiplexed address data pins (AD15-0) access 8-bit devices with bits address, 16-bit devices with bits address. either mode, 16bit, maximum data transfer rate bytes/sec. transfers used move data from internal memory. Access core also facilitated through parallel port register read/write functions. (Address Latch Enable) pins control pins parallel port.
Pulse Width Modulation
module flexible, programmable, waveform generator that programmed generate required switching patterns various applications related motor engine control audio power control. generator generate either center-aligned edge-aligned waveforms. addition, generate complementary signals outputs paired mode independent signals nonpaired mode (applicable single group four waveforms). entire module four groups four outputs each. Therefore this module generates outputs total. Each group produces pairs signals four outputs. generator capable operating distinct modes while generating center-aligned waveforms: single update mode, double update mode. single update mode duty cycle values programmable only once period. This results patterns that symmetrical around mid-point period. double update mode, second updating registers implemented mid-point period. this mode, possible produce asymmetrical patterns that produce lower harmonic distortion three-phase inverters.
Serial Peripheral (Compatible) Interface
ADSP-21364 SHARC processor contains Serial Peripheral Interface ports (SPIs). industry standard synchronous serial link, enabling ADSP-21364 compatible port communicate with other compatible devices. consists data pins, device select pin, clock pin. full-duplex synchronous serial interface, supporting both master slave modes. port operate multimaster environment interfacing with four other compatible devices, either acting master slave device. ADSP-21364 compatible peripheral implementation also features programmable baud rate clock phase polarities. ADSP-21364 compatible port uses open drain drivers support multimaster configuration avoid data contention. sample rate converter (SRC) contains four blocks same core that used AD1896 Stereo Asynchronous Sample Rate Converter providing 140dB SNR. block used perform synchronous asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. four blocks also configured operate together convert multichannel audio data without phase mismatches. Finally, used clean audio data from jittery clock sources such S/PDIF receiver.
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ADSP-21364
Timers
ADSP-21364 total four timers: core timer able generate periodic software interrupts three general purpose timers that generate periodic interrupts independently operate three modes: Pulse Waveform Generation mode Pulse Width Count /Capture mode External Event Watchdog mode core timer configured FLAG3 Timer Expired signal, each general-purpose timer bidirectional four registers that implement mode operation: 6-bit configuration register, 32-bit count register, 32-bit period register, 32-bit pulse width register. single control status register enables disables three general purpose timers independently.
VDDINT
Preliminary Technical Dat10 AVDD 0.01
AVSS
Figure Analog Power (AVDD) Filter Circuit
inspection modification memory, registers, processor stacks. processor's JTAG interface ensures that emulator will affect target system loading timing. complete information Analog Devices' SHARC Tools product line JTAG emulator operation, appropriate "Emulator Hardware User's Guide".
DEVELOPMENT TOOLS
ADSP-21364 supported with complete CROSSCORE® software hardware development tools, including Analog Devices emulators VisualDSP++® development environment. same emulator hardware that supports other SHARC processors also fully emulates ADSP-21364. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler (which based algebraic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code assembly. SHARC architectural features that improve efficiency compiled C/C++ code. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow complexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer intrusively poll processor running program. This feature, unique VisualDSP++, enables software developer passively gather important code execution metrics without interrupting real-time characteristics program. Essentially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert breakpoints
Program Booting
internal memory ADSP-21364 boots system power-up from 8-bit EPROM parallel port, master, slave internal boot. Booting determined Boot Configuration (BOOTCFG1-0) pins (see Table Page 14). Selection boot source controlled either master slave device.
Phase-Locked Loop
ADSP-21364 uses on-chip Phase-Locked Loop (PLL) generate internal clock core. power CLKCFG1-0 pins used select ratios 32:1, 16:1, (see Table Page 14). After booting, numerous other ratios selected software control. ratios made software configurable numerator values from software configurable divisor values
Power Supplies
ADSP-21364 separate power supply connections internal (VDDINT), external (VDDEXT), analog (AVDD/AVSS) power supplies. internal analog supplies must meet requirement. external supply must meet requirement. external supply pins must connected same power supply. Note that analog supply (AVDD) powers ADSP-21364's clock generator PLL. produce stable clock, programs should provide external circuit filter power input AVDD pin. Place filter close possible pin. example circuit, Figure prevent noise coupling, wide trace analog ground (AVSS) signal install decoupling capacitor close possible pin. Note that AVSS AVDD pins specified Figure inputs processor analog ground plane board.
Target Board JTAG Emulator Connector
Analog Devices Tools product line JTAG emulators uses IEEE 1149.1 JTAG test access port ADSP-21364 processor monitor control target board processor during emulation. Analog Devices Tools product line JTAG emulators provides emulation full processor speed, allowing
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Preliminary Technical conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Perform source level debugging Create custom debugger windows VisualDSP++ IDDE lets programmers define manage software development. dialog boxes property pages programmers configure manage SHARC development tools, including color syntax highlighting VisualDSP++ editor. This capability permits programmers Control development tools process inputs generate outputs Maintain one-to-one correspondence with tool's command line switches VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include Threads, Critical Unscheduled regions, Semaphores, Events, Device flags. also supports Priority-based, Preemptive, Cooperative, Time-Sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard command line tools. When used, development environment assists developer with many error-prone tasks assists managing system resources, automating generation various based objects, visualizing system state, when debugging application that uses VDK. VisualDSP++ Component Software Engineering (VCSE) Analog Devices' technology creating, using, reusing software components (independent modules substantial functionality) quickly reliably assemble software applications. Download components from drop them into application. Publish component archives from within VisualDSP++. VCSE supports component implementation C/C++ assembly language. Expert Linker visually manipulate placement code data embedded system. View memory utilization color-coded graphical form, easily move code data different areas processor external memory with drag mouse, examine time stack heap usage. Expert Linker fully compatible with existing Linker Definition File (LDF), allowing developer move between graphical textual environments.
ADSP-21364
addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting SHARC processor family. Hardware tools include SHARC processor plug-in cards. Third party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Board (Target)
Analog Devices family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG DSP. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. emulator uses access internal features processor, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. processor must halted send data commands, once operation been completed emulator, processor system running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website (www.analog.com)- site search "EE-68." This document updated regularly keep pace with improvements emulator support.
Evaluation
Analog Devices offers range EZ-KIT Lite evaluation platforms cost effective method learn more about developing prototyping applications with Analog Devices processors, platforms, software tools. Each EZ-KIT Lite includes evaluation board along with evaluation suite VisualDSP++ development debugging environment with C/C++ compiler, assembler, linker. Also included sample application programs, power supply, cable. evaluation versions software tools limited only with EZ-KIT Lite product. controller EZ-KIT Lite board connects board port user's enabling VisualDSP++ evaluation suite emulate on-board processor incircuit. This permits customer download, execute, debug programs EZ-KIT Lite system. also allows incircuit programming on-board Flash device store userspecific boot code, enabling board standalone unit without being connected With full version VisualDSP++ installed (sold separately), engineers develop software EZ-KIT Lite custom defined system. Connecting Analog Devices JTAG emulators EZ-KIT Lite board enables high-speed, nonintrusive emulation.
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ADSP-21364
ADDITIONAL INFORMATION
This data sheet provides general overview ADSP-21364 architecture functionality. detailed information ADSP-2136x Family core architecture instruction set, refer ADSP-2136x SHARC Processor Hardware Reference ADSP-2136x SHARC Processor Programming Reference.
Preliminary Technical
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Preliminary Technical DatPIN FUNCTION DESCRIPTIONS
ADSP-21364 definitions listed below. Inputs identified synchronous must meet timing requirements with respect CLKIN with respect TDI). Inputs identified asynchronous asserted asynchronously CLKIN TRST). pull unused inputs VDDEXT GND, except following: Table Descriptions
AD15-0 Type I/O/T (pu) State During After Reset Three-state with pullup enabled Function
ADSP-21364
DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, AD15-0 (NOTE: These pins have pullup resistors.) following symbols appear Type column Table Asynchronous, Ground, Input, Output, Power Supply, Synchronous, (A/D) Active Drive, (O/D) Open Drain, Three-State, (pd) pulldown resistor, (pu) pullup resistor.
(pu) (pu) (pd)
Three-state, driven high1 Three-state, driven high1 Three-state, driven low1
FLAG3-0
I/O/A
Three-state
Parallel Port Address/Data. ADSP-21364 parallel port corresponding unit output addresses data peripherals these multiplexed pins. multiplex state determined pin. parallel port operate either 8-bit 16-bit mode. Each 22.5 internal pullup resistor. Address Data Modes Page details operation. 8-bit mode: automatically asserted whenever change occurs upper external address bits, A23-8; used conjunction with external latch retain values A23-8. 16-bit mode: automatically asserted whenever change occurs address bits, A15-0; used conjunction with external latch retain values A15-0. these pins flags (FLAGS15-0) PWMs (PWM15-0), (=1) SYSCTL register disable parallel port, (=1) bits 22-25 SYSCTL register enable FLAGS groups four (bit FLAGS3-0, FLAGS7-4 etc.) (=1) bits 26-29 SYSCTL register enable PWMs groups four (bit PWM0-3, PWM4-7, on). When used input, Channel0 these pins parallel input data. Parallel Port Read Enable. asserted whenever processor reads 8-bit 16-bit data from external memory device. When AD15-0 flags, this remains deasserted. 22.5 internal pullup resistor. Parallel Port Write Enable. asserted whenever processor writes 8-bit 16-bit data external memory device. When AD15-0 flags, this remains deasserted. 22.5 internal pullup resistor. Parallel Port Address Latch enable. asserted whenever processor drives address parallel port address pins. reset, active high. However, reconfigured using software active low. When AD15-0 flags, this remains deasserted. internal pulldown resistor. Flag Pins. Each flag configured control bits either input output. input, tested condition. output, used signal external peripherals. These pins used interface slave select output during mastering. These pins also multiplexed with IRQx TIMEXP signals. master boot mode, FLAG0 slave select that must connected EPROM. FLAG0 configured slave select during master boot. When (=1) SYSCTL register, FLAG0 configured IRQ0. When (=1) SYSCTL register, FLAG1 configured IRQ1. When (=1) SYSCTL register, FLAG2 configured IRQ2. When (=1) SYSCTL register, FLAG3 configured TIMEXP which indicates that system timer expired.
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Table Descriptions (Continued)
DAI_P20-1 Type I/O/T (pu) State During After Reset Three-state with programmable pullup Function
Preliminary Technical
SPICLK
(pu)
Three-state with pullup enabled
SPIDS
Input only
MOSI
(O/D) (pu)
Three-state with pullup enabled
MISO
(O/D) (pu)
Three-state with pullup enabled
BOOTCFG1-0
Input only
Digital Audio Interface Pins. These pins provide physical interface SRU. configuration registers define combination on-chip peripheral inputs outputs connected pin's output enable. configuration registers these peripherals then determines exact behavior pin. input output signal present routed these pins. provides connection from Serial ports, Input data port, precision clock generators timers, sample rate converters DAI_P20-1 pins These pins have internal 22.5 pullup resistors which enabled reset. These pullups disabled DAI_PIN_PULLUP register. Serial Peripheral Interface Clock Signal. Driven master, this signal controls rate which data transferred. master transmit data variety baud rates. SPICLK cycles once each transmitted. SPICLK gated clock that active during data transfers, only length transferred word. Slave devices ignore serial clock slave select input driven inactive (HIGH). SPICLK used shift shift data driven MISO MOSI lines. data always shifted clock edge sampled opposite edge clock. Clock polarity clock phase relative data programmable into SPICTL control register define transfer format. SPICLK 22.5 internal pullup resistor. Serial Peripheral Interface Slave Device Select. active signal used select processor slave device. This input signal behaves like chip select, provided master device slave devices. multimaster mode DSPs SPIDS signal driven slave device signal processor master) that error occurred, some other device also trying master device. asserted when device master mode, considered multimaster error. single-master, multiple-slave configuration where flag pins used, this must tied pulled high VDDEXT master device. ADSP-21364 ADSP-21364 interaction, master ADSP-21364's flag pins used drive SPIDS signal ADSP-21364 slave device. Master Slave ADSP-21364 configured master, MOSI becomes data transmit (output) pin, transmitting output data. ADSP-21364 configured slave, MOSI becomes data receive (input) pin, receiving input data. ADSP-21364 interconnection, data shifted from MOSI output master shifted into MOSI input(s) slave(s). MOSI 22.5 internal pullup resistor. Master Slave Out. ADSP-21364 configured master, MISO becomes data receive (input) pin, receiving input data. ADSP-21364 configured slave, MISO becomes data transmit (output) pin, transmitting output data. ADSP-21364 interconnection, data shifted from MISO output slave shifted into MISO input master. MISO 22.5 internal pullup resistor. MISO configured setting SPICTL register. Note: Only slave allowed transmit data given time. enable broadcast transmission multiple SPI-slaves, processor's MISO disabled setting (=1) (DMISO) SPICTL register. Boot Configuration Select. This used select boot mode processor. BOOTCFG pins must valid before reset asserted. Table description boot modes.
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Preliminary Technical DatTable Descriptions (Continued)
CLKIN Type State During After Reset Input only Function
ADSP-21364
XTAL CLKCFG1-0
Output only2 Input only
RSTOUT/CLKOUT
Output only
RESET
Input only
TRST
(pu) (pu) (pu) (O/D) (pu)
Input only3 Three-state with pullup enabled Three-state with pullup enabled Three-state4 Three-state with pullup enabled Three-state with pullup enabled
VDDINT VDDEXT AVDD
AVSS
Local Clock Used conjunction with XTAL. CLKIN ADSP-21364 clock input. configures ADSP-21364 either internal clock generator external clock source. Connecting necessary components CLKIN XTAL enables internal clock generator. Connecting external clock CLKIN while leaving XTAL unconnected configures ADSP-21364 external clock source such external clock oscillator. core clocked either output this clock input depending CLKCFG1-0 settings. CLKIN halted, changed, operated below specified frequency. Crystal Oscillator Terminal. Used conjunction with CLKIN drive external crystal. Core/CLKIN Ratio Control. These pins start clock frequency. Table description clock configuration modes. Note that operating frequency changed programming multiplier divider PMCTL register time after core comes reset. Local Clock Out/ Reset Out. Drives core reset signal external device. CLKOUT also configured reset pin.The functionality switched between output clock reset setting PMCTREG register. default reset out. Processor Reset. Resets ADSP-21364 known state. Upon deassertion, there 4096 CLKIN cycle latency lock. After this time, core begins program execution from hardware reset vector address. RESET input must asserted (low) power-up. Test Clock (JTAG). Provides clock JTAG boundary scan. must asserted (pulsed low) after power-up held proper operation ADSP-21364. Test Mode Select (JTAG). Used control test state machine. 22.5 internal pullup resistor. Test Data Input (JTAG). Provides serial data boundary scan logic. 22.5 internal pullup resistor. Test Data Output (JTAG). Serial scan output boundary scan path. Test Reset (JTAG). Resets test state machine. TRST must asserted (pulsed low) after power-up held proper operation ADSP-21364. TRST 22.5 internal pullup resistor. Emulation Status. Must connected ADSP-21364 Analog Devices processor Tools product line JTAG emulators target board connector only. 22.5 internal pullup resistor. Core Power Supply. Nominally +1.2 supplies processor's core processor pins Mini-BGA package, pins LQFP package). Power Supply. Nominally +3.3 pins Mini-BGA package, pins LQFP package). Analog Power Supply. Nominally +1.2 supplies processor's internal (clock generator). This same specifications VDDINT, except that added filtering circuitry required. more information, Power Supplies Page Analog Power Supply Return. Power Supply Return. pins Mini-BGA package, pins LQFP package).
three-stated (and driven) only when RESET active. Output only three-state driver with output path always enabled. Input only three-state driver with both output path pullup disabled. Three-state three-state driver with pullup disabled.
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ADSP-21364
ADDRESS DATA PINS FLAGS
these pins flags (FLAGS15-0) (=1) SYSCTL register disable parallel port. Then (=1) bits SYSCTL register accordingly. Table AD15-0 Flag Mapping
Flag FLAG8 FLAG9 FLAG10 FLAG11 FLAG12 FLAG13 FLAG14 FLAG15 AD10 AD11 AD12 AD13 AD14 AD15 Flag FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7
Preliminary Technical DatBOOT MODES
Table Boot Mode Selection
BOOTCFG1-0 Booting Mode Slave Boot Master Boot Parallel Port boot EPROM
CORE INSTRUCTION RATE CLKIN RATIO MODES
details processor timing, Timing Specifications Figure Page Table Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1-0 Core CLKIN Ratio 32:1 16:1
ADDRESS DATA MODES
following table shows functionality pins 8-bit 16-bit transfers parallel port. 8-bit data transfers, latches address bits A23-A8 when asserted, followed address bits A7-A0 data bits D7-D0 when deasserted. 16-bit data transfers, latches address bits A15-A0 when asserted, followed data bits D15-D0 when deasserted. Table Address/ Data Mode Selection
Data Mode 8-bit 8-bit 16-bit 16-bit Asserted Deasserted Asserted Deasserted AD7-0 Function A15-8 D7-0 A7-0 D7-0 AD15-8 Function A23-16 A7-0 A15-8 D15-8
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Preliminary Technical DatADSP-21364 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter1 Grade VDDINT AVDD VDDEXT
ADSP-21364
Grade 1.14 1.14 3.13 -0.5 1.74 -0.5 1.26 1.26 3.47 VDDEXT +0.8 VDDEXT +1.19
Grade 0.95 0.95 3.13 -0.5 1.74 -0.5 1.05 1.05 3.47 VDDEXT +0.8 VDDEXT +1.19 +105 Unit
1.26 1.26 3.47 VDDEXT +0.8 VDDEXT +1.19
Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage VDDEXT Level Input Voltage VDDEXT High Level Input Voltage VDDEXT Level Input Voltage VDDEXT Ambient Operating Temperature
1.14 1.14 3.13 -0.5 1.74 -0.5
VIL2 VIH_CLKIN3 VIL_CLKIN TAMB
Specifications subject change without notice. Applies input bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST. Applies input CLKIN. Thermal Characteristics Page information thermal specifications. Engineer-to-Engineer Note (No. TBD) further information.
ELECTRICAL CHARACTERISTICS
Parameter1 VOH2 VOL2 IIH4, IIL4 IILPU5 IOZH IOZL6 IOZLPU7 IDD-INTYP8, AIDD10 CIN11,
High Level Output Voltage Level Output Voltage High Level Input Current Level Input Current Level Input Current Pullup Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Pullup Supply Current (Internal) Supply Current (Analog) Input Capacitance
Test Conditions VDDEXT min, -1.0 VDDEXT min, VDDEXT max, VDDEXT VDDEXT max, VDDEXT max, VDDEXT= max, VDDEXT VDDEXT max, VDDEXT max, tCCLK min, VDDINT AVDD fIN=1 MHz, TCASE=25°C, VIN=1.2V
Unit
Specifications subject change without notice. Applies output bidirectional pins: AD15-0, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL. Output Drive Currents Page typical drive current capabilities. Applies input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN. Applies input pins with 22.5 internal pullups: TRST, TMS, TDI. Applies three-statable pins: FLAG3-0. Applies three-statable pins with 22.5 pullups: AD15-0, DAI_Px, SPICLK, EMU, MISO, MOSI. Typical internal current data reflects nominal operating conditions. Engineer-to-Engineer Note (No. TBD) further information. Characterized, tested. Applies signal pins. Guaranteed, tested.
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ADSP-21364
MAXIMUM POWER DISSIPATION
data this table based theta (JA) established JEDEC standards JESD51-2 JESD51-6. Engineer-toEngineer note (EE-TBD) further information. information package thermal specifications, Thermal Characteristics Page
Ambient Temp1 70°C 85°C 105°C
Preliminary Technical
INT-HS LQFP2 3.33W 2.42W 1.21W
INT-HS LQFP3 2.10W
MiniBGA4 2.44W 1.77W
MiniBGA5 2.18W
Power Dissipation greater than that listed above cause permanent damage device. more information, Thermal Characteristics Page Heat slug soldered Heat slug soldered Thermal vias thermal vias
ABSOLUTE MAXIMUM RATINGS
Parameter Internal (Core) Supply Voltage (VDDINT)1 Analog (PLL) Supply Voltage (AVDD)1 External (I/O) Supply Voltage (VDDEXT)1 Input Voltage-0.5 VDDEXT1 Output Voltage Swing-0.5 VDDEXT1 Load Capacitance1 Storage Temperature Range1 Junction Temperature under Bias
Rating -0.3 +1.5 -0.3 +1.5 -0.3 +4.6 -65°C +150°C 125°C
Stresses greater than those listed above cause permanent damage device. These stress ratings only; functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although ADSP-21364 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
TIMING SPECIFICATIONS
ADSP-21364's internal clock multiple CLKIN) provides clock signal timing internal memory, processor core, serial ports, parallel port required read/write strobes asynchronous access mode). During reset, program ratio between processor's internal clock frequency external (CLKIN) clock frequency with CLKCFG1-0 pins.
determine switching frequencies serial ports, divide down internal clock, using programmable divider control each port (DIVx serial ports). ADSP-21364's internal clock switches higher frequencies than system input clock (CLKIN). generate internal clock, processor uses internal phase-locked loop (PLL). This PLL-based clocking minimizes skew between system clock (CLKIN) signal processor's internal clock (the clock source parallel port logic pads).
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Preliminary Technical DatNote definitions various clock periods that function CLKIN appropriate ratio control (Table Table ADSP-21364 CLKOUT CCLK Clock Generation Operation
Timing Requirements CLKIN CCLK Description Input Clock Core Clock Calculation 1/tCK 1/tCCLK
ADSP-21364
exact timing information given. attempt derive parameters from addition subtraction others. While addition subtraction would yield meaningful results individual device, values given this data sheet reflect statistical variations worst cases. Consequently, meaningful parameters derive longer times. Figure page under Test Conditions voltage reference levels. Switching Characteristics specify processor changes signals. Circuitry external processor must designed compatibility with these signal characteristics. Switching characteristics describe what processor will given circumstance. switching characteristics ensure that timing requirement device connected processor (such memory) satisfied. Timing Requirements apply signals that controlled circuitry external processor, such data input read operation. Timing requirements guarantee that processor operates correctly with other devices.
Table Clock Periods
Timing Requirements tCCLK tPCLK tSCLK tSPICLK
Description1 CLKIN Clock Period (Processor) Core Clock Period (Peripheral) Clock Period tCCLK Serial Port Clock Period (tPCLK) Clock Period (tPCLK) SPIR
where: serial port-to-core clock ratio (wide range, determined SPORT CLKDIV) SPIR SPI-to-Core Clock Ratio (wide range, determined SPIBAUD register) DAI_Px Serial Port Clock SPICLK Clock
Figure shows Core CLKIN ratios 6:1, 16:1 32:1 with external oscillator crystal. Note that more ratios possible through software using power management control register (PMCTL). more information, ADSP-2136x SHARC Processor Programming Reference.
CLKOUT
CLKIN XTAL
XTAL
PLLILCLK
6:1, 16:1, 32:1
CCLK (CORE CLOCK)
CLK-CFG [1:0]
Figure Core Clock System Clock Relationship CLKIN
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ADSP-21364
Power-Up Sequencing
timing requirements processor startup given Table Table Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD1 tCLKRST tPLLRST RESET Before VDDINT/VDDEXT VDDINT Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid CLKIN Valid Before RESET Deasserted Control Setup Before RESET Deasserted
Preliminary Technical
Unit
Switching Characteristic Core Reset Deasserted After RESET Deasserted tCORERST
4096tCK tCCLK
Valid VDDINT/VDDEXT assumes that supplies fully ramped their volt rails. Voltage ramp rates vary from microseconds hundreds milliseconds depending design power supply subsystem. Assumes stable CLKIN signal, after meeting worst-case startup timing crystal oscillators. Refer your crystal oscillator manufacturer's datasheet startup time. Assume maximum oscillator startup time using XTAL internal oscillator circuit conjunction with external crystal. Based CLKIN cycles Applies after power-up sequence complete. Subsequent resets require minimum CLKIN cycles RESET held order properly initialize propagate default states pins. 4096 cycle count depends tSRST specification Table setup time met, additional CLKIN cycle added core reset time, resulting 4097 cycles maximum.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1-0
tPLLRST
RSTOUT
tCORERST
Figure Power Sequencing
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Preliminary Technical DatClock Input
Table Clock Input
Parameter Timing Requirements CLKIN Period tCKL CLKIN Width tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4V-2.0V) tCCLK3 CCLK Period
ADSP-21364
TBD2 TBD2 TBD2
Unit
7.51 7.51 3.01
Applies only CLKCFG1-0 default values control bits PMCTL. Applies only CLKCFG1-0 default values control bits PMCTL. changes control bits PMCTL register must meet core clock timing specification tCCLK.
CLKIN
tCKH tCKL
Figure Clock Input
Clock Signals
ADSP-21364 external clock crystal. CLKIN description. programmer configure ADSP-21364 internal clock generator connecting necessary components CLKIN XTAL. Figure shows component connections used crystal operating fundamental mode. Note that clock rate achieved using 16.67 crystal multiplier ratio 16:1 (CCLK:CLKIN achieves clock speed MHz). achieve full core clock rate, programs need configure multiplier bits PMCTL register.
CLKIN
XTAL
NOTE: SPECIFIC CRYSTAL SPECIFIED CONTACT CRYSTAL MANUFACTURER DETAILS. CRYSTAL SELECTION MUST COMPLY WITH CLKCFG1-0
Figure Operation (Fundamental Mode Crystal)
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ADSP-21364
Reset
Table Reset
Parameter Timing Requirements tWRST1 RESET Pulse Width tSRST RESET Setup Before CLKIN
Preliminary Technical
4tCK
Unit
Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than while RESET low, assuming stable CLKIN (not including start-up time external clock oscillator).
CLKIN
tWRST
RESET
tSRST
Figure Reset
Interrupts
following timing specification applies FLAG0, FLAG1, FLAG2 pins when they configured IRQ0, IRQ1, IRQ2 interrupts. Also applies DAI_P20-1 pins when configured interrupts
Table Interrupts
Parameter Timing Requirement tIPW IRQx Pulse Width tPCLK Unit
DAI_P20-1 FLAG2-0 (IRQ2-0)
tIPW
Figure Interrupts
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Preliminary Technical DatCore Timer
following timing specification applies FLAG3 when configured core timer (CTIMER). Table Core Timer
Parameter Switching Characteristic tWCTIM CTIMER Pulse Width tPCLK
ADSP-21364
Unit
FLAG3 (CTIMER)
tWCTIM
Figure Core Timer
Timer PWM_OUT Cycle Timing
following timing specification applies Timer0, Timer1, Timer2 PWM_OUT (pulse width modulation) mode. Timer signals routed DAI_P20-1 pins through SRU. Therefore, timing specifications provided below valid DAI_P20-1 pins.
Table Timer PWM_OUT Timing
Parameter Switching Characteristic tPWMO Timer Pulse Width Output tPCLK 2(231 tPCLK Unit
tPWMO DAI_P20-1 (TIMER2-0)
Figure Timer PWM_OUT Timing
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ADSP-21364
Timer WDTH_CAP Timing
following timing specification applies Timer0, Timer1, Timer2 WDTH_CAP (pulse width count capture) mode. Timer signals routed DAI_P20-1 pins through SRU. Therefore, timing specifications provided below valid DAI_P20-1 pins. Table Timer Width Capture Timing
Parameter Timing Requirement tPWI Timer Pulse Width tPCLK
Preliminary Technical
Unit
2(231- tPCLK
tPWI
DAI_P20-1 (TIMER2-0)
Figure Timer Width Capture Timing
Direct Routing
direct connections only (for example DAI_PB01_I DAI_PB02_O).
Table Routing
Parameter Timing Requirement tDPIO Delay Input Valid Output Valid Unit
DAI_PN
DAI_PM
tDPIO
Figure Direct Routing
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Preliminary Technical DatPrecision Clock Generator (Direct Routing)
This timing only valid when configured such that Precision Clock Generator (PCG) takes inputs directly from pins (via buffers) sends outputs directly pins. other cases, where PCG's Table Precision Clock Generator (Direct Routing)
Parameter Timing Requirements tPCGIW Input Clock Period tSTRIG Trigger Setup Before Falling Edge Input Clock Trigger Hold After Falling Edge Input Clock tHTRIG Switching Characteristics Output Clock Frame Sync Active Edge Delay After tDPCGIO Input Clock tDTRIG Output Clock Frame Sync Delay After Trigger Output Clock Period tPCGOW
ADSP-21364
inputs outputs directly routed to/from pins (via buffers) there timing data available. Timing Parameters Switching Characteristics apply external pins (DAI_P07 DAI_P20).
Unit
tPCGOW
tPCGOW
tSTRIG
DAI_PN PCG_TRIGX_I
tHTRIG
DAI_PM PCG_EXTX_I (CLKIN)
tPCGIW
DAI_PY PCG_CLKX_O
tDPCGIO
tPCGOW
DAI_PZ PCG_FSX_O
tDTRIG
Figure Precision Clock Generator (Direct Routing)
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ADSP-21364
Flags
timing specifications provided below apply FLAG3-0 DAI_P20-1 pins, parallel port serial peripheral interface (SPI). Table "Pin Descriptions," page more information flag use. Table Flags
Parameter Timing Requirement tFIPW FLAG3-0 Pulse Width Switching Characteristic tFOPW FLAG3-0 Pulse Width
Preliminary Technical
Unit
tPCLK
tPCLK
DAI_P20-1 (FLAG3-0IN) (AD15-0)
tFIPW
DAI_P20-1 (FLAG3-0OUT) (AD15-0)
tFOPW
Figure Flags
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Preliminary Technical DatMemory Read-Parallel Port
these specifications asynchronous interfacing memories (and memory-mapped peripherals) when ADSP-21364 accessing external memory space. Table 8-Bit Memory Read Cycle
Parameter Timing Requirements Address/Data Setup Before High tDRS tDRH Address/Data Hold After High tDAD Address 15-8 Data Valid
ADSP-21364
Unit
tPCLK
Switching Characteristics tALEW Pulse Width tPCLK tADAS1 Address/Data 15-0 Setup Before Deasserted tPCLK tRRH Delay Between Rising Edge Next Falling Edge. tPCLK tALERW Deasserted Read Asserted tPCLK Read Deasserted Asserted tRWALE tADAH1 Address/Data 15-0 Hold After Deasserted tPCLK tALEHZ Deasserted Address/Data7-0 High tPCLK Pulse Width tRDDRV Address Drive After Read High tPCLK tADRH Address/Data 15-8 Hold After High (Data Cycle Duration value PPDUR bits (5-1) PPCTL register) tPCLK tPCLK hold cycle specified, else tPCLK FLASH_MODE else tPCLK (Peripheral) Clock Period tCCLK
tPCLK
reset, active high cycle. However, configured software active low.
tRWALE tALERW tRRH
tALEW
tRDDRV
tADAS
AD15-8
tADAH
VALID ADDRESS
tADRH
VALID ADDRESS VALID ADDRESS
VALID ADDRESS
tDAD
VALID ADDRESS VALID DATA
tDRS
tDRH
VALID ADDRESS
AD7-0
VALID DATA
tALEHZ
Figure Read Cycle 8-Bit Memory Timing
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ADSP-21364
Table 16-bit Memory Read Cycle
Parameter Timing Requirements tDRS tDRH Address/Data 15-0 Setup Before High Address/Data 15-0 Hold After High
Preliminary Technical
Unit
Switching Characteristics tALEW Pulse Width tPCLK tADAS1 Address/Data 15-0 Setup Before Deasserted tPCLK tALERW Deasserted Read Asserted tPCLK Delay Between Rising Edge Next Falling Edge. tPCLK tRRH tRWALE Read Deasserted Asserted tRDDRV Address Drive After Read High tPCLK tADAH Address/Data 15-0 Hold After Deasserted tPCLK tALEHZ1 Deasserted Address/Data15-0 High tPCLK Pulse Width (Data Cycle Duration value PPDUR bits (5-1) PPCTL register) tPCLK tPCLK hold cycle specified, else tPCLK FLASH_MODE else
reset, active high cycle. However, configured software active low.
ALERW
ALEW
tRRH
RDDRV
tALEHZ
ADAS
AD15-0
ADAH
tDRH
VALID ADDRESS
VALID ADDRESS
VALID DATA
Figure Read Cycle 16-Bit Memory Timing
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Preliminary Technical DatMemory Write-Parallel Port
these specifications asynchronous interfacing memories (and memory-mapped peripherals) when ADSP-21364 accessing external memory space. Table 8-bit Memory Write Cycle
Parameter Switching Characteristics: Pulse Width tPCLK tALEW tADAS1 Address/Data 15-0 Setup Before Deasserted tPCLK tALERW Deasserted Read/Write Asserted tPCLK tRWALE Write Deasserted Asserted tWRH Delay Between Rising Edge next Falling Edge tPCLK tADAH1 Address/Data 15-0 Hold After Deasserted tPCLK Pulse Width D-F-2 tADWL Address/Data 15-8 tPCLK tADWH Address/Data 15-8 Hold After High tDWS Address/Data Setup Before High tPCLK tDWH Address/Data Hold After High tDAWH Address/Data High tPCLK (Data Cycle Duration value PPDUR bits (5-1) PPCTL register) tPCLK tPCLK hold cycle specified, else tPCLK FLASH_MODE else
ADSP-21364
Unit
reset, active high cycle. However, configured software active low.
tALEW
tALERW tRWALE
tADWL tDAWH
tWRH
tADAS
tADAH tADWH
AD15-8
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS tDWH
tDWS AD7-0 VALID ADDRESS VALID DATA VALID DATA
Figure Write Cycle 8-Bit Memory Timing
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ADSP-21364
Table 16-bit Memory Write Cycle
Preliminary Technical
Parameter Switching Characteristics tALEW Pulse Width tPCLK tADAS1 Address/Data 15-0 Setup Before Deasserted tPCLK tALERW Deasserted Write Asserted tPCLK tRWALE Write Deasserted Asserted Delay Between Rising Edge next Falling Edge tPCLK tWRH tADAH Address/Data 15-0 Hold After Deasserted tPCLK Pulse Width D-F-2 tALEHZ1 Deasserted Address/Data15-0 High tPCLK tDWS Address/Data 15-0 Setup Before High tPCLK tDWH Address/Data 15-0 Hold After High (Data Cycle Duration value PPDUR bits (5-1) PPCTL register) tPCLK tPCLK hold cycle specified, else tPCLK FLASH_MODE else
Unit
reset, active high cycle. However, configured software active low.
tALEW
tALERW tRWALE
tWRH
tADAS
tADAH
tDWH
AD15-0
VALID ADDRESS
VALID DATA tDWS
VALID DATA
Figure Write Cycle 16-Bit Memory Timing
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Preliminary Technical DatSerial Ports
determine whether communication possible between devices clock speed following specifications must confirmed: frame sync delay frame sync setup hold, data delay data setup hold, SCLK width. Table Serial Ports-External Clock
Parameter Timing Requirements tSFSE1 Setup Before SCLK (Externally Generated either Transmit Receive Mode) tHFSE1 Hold After SCLK (Externally Generated either Transmit Receive Mode) tSDRE Receive Data Setup Before Receive SCLK tHDRE1 Receive Data Hold After SCLK tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE2 Delay After SCLK (Internally Generated either Transmit Receive Mode) tHOFSE2 Hold After SCLK (Internally Generated either Transmit Receive Mode) tDDTE2 Transmit Data Delay After Transmit SCLK tHDTE2 Transmit Data Hold After Transmit SCLK
ADSP-21364
Serial port signals (SCLK, DxA,/DxB) routed DAI_P20-1 pins using SRU. Therefore, timing specifications provided below valid DAI_P20-1 pins.
Unit
Referenced sample edge. Referenced drive edge.
Table Serial Ports-Internal Clock
Parameter Timing Requirements tSFSI1 Setup Before SCLK (Externally Generated either Transmit Receive Mode) Hold After SCLK tHFSI1 (Externally Generated either Transmit Receive Mode) tSDRI Receive Data Setup Before SCLK tHDRI1 Receive Data Hold After SCLK Switching Characteristics tDFSI2 Delay After SCLK (Internally Generated Transmit Mode) Hold After SCLK (Internally Generated Transmit Mode) tHOFSI2 tDFSI Delay After SCLK (Internally Generated Receive Mode) tHOFSI2 Hold After SCLK (Internally Generated Receive Mode) tDDTI2 Transmit Data Delay After SCLK tHDTI Transmit Data Hold After SCLK tSCLKIW Transmit Receive SCLK Width
Unit
-1.0 -1.0 -1.0 0.5tSCLK 0.5tSCLK
Referenced sample edge. Referenced drive edge.
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ADSP-21364
Table Serial Ports-Enable Three-State
Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK Data Disable from External Transmit SCLK tDDTTE1 tDDTIN1 Data Enable from Internal Transmit SCLK
Preliminary Technical DatMin Unit
Referenced drive edge.
Table Serial Ports-External Late Frame Sync
Parameter Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit External Receive with tDDTENFS1 Data Enable
Unit
tDDTLFSE tDDTENFS parameters apply Left-justified Sample Pair well serial mode,
EXTERNAL RECEIVE WITH
DAI_P20-1 (SCLK)
DRIVE
SAMPLE
DRIVE
tSFSE/I
DAI_P20-1 (FS)
tHFSE/I
tDDTENFS
DAI_P20-1 (DATA CHANNEL A/B)
tDDTE/I tHDTE/I
tDDTLFSE
LATE EXTERNAL TRANSMIT DRIVE SAMPLE DRIVE
DAI_P20-1 (SCLK)
tSFSE/I
DAI_P20-1 (FS)
tHFSE/I
tDDTENFS
DAI_P20-1 (DATA CHANNEL A/B)
tDDTE/I tHDTE/I
tDDTLFSE
NOTE SERIAL PORT SIGNALS (SCLK, DATA CHANNEL A/B) ROUTED DAI_P20-1 PINS USING SRU. TIMING SPECIFICATIONS PROVIDED HERE VALID DAI_P20-1 PINS.
Figure External Late Frame Sync1
This figure reflects changes made support Left-justified Sample Pair mode.
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Preliminary Technical
ADSP-21364
DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA RECEIVE- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
DAI_P20-1 (SCLK) DAI_P20-1 (SCLK)
tSCLKW
tDFSI tHOFSI
DAI_P20-1 (FS)
tSFSI
tHFSI
DAI_P20-1 (FS)
tDFSE tHOFSE tSFSE
tHFSE
tSDRI
DAI_P20-1 (DATA CHANNEL A/B)
tHDRI
DAI_P20-1 (DATA CHANNEL A/B)
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE SCLK (EXTERNAL), SCLK (INTERNAL) USED ACTIVE SAMPLING EDGE.
DATA TRANSMIT INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
DAI_P20-1 (SCLK) DAI_P20-1 (SCLK)
tSCLKW
tDFSI tHOFSI
DAI_P20-1 (FS)
tSFSI
tHFSI
DAI_P20-1 (FS)
tDFSE tHOFSE tSFSE tHFSE
tHDTI
DAI_P20-1 (DATA CHANNEL A/B)
tDDTI
DAI_P20-1 (DATA CHANNEL A/B)
tHDTE
tDDTE
NOTE: EITHER RISING EDGE FALLING EDGE SCLK (EXTERNAL), SCLK (INTERNAL) USED ACTIVE SAMPLING EDGE.
DRIVE EDGE DAI_P20-1 SCLK (EXT)
DRIVE EDGE
SCLK tDDTEN tDDTTE
DAI_P20-1 (DATA CHANNEL A/B)
DRIVE EDGE
DAI_P20-1 SCLK (INT)
tDDTIN
DAI_P20-1 (DATA CHANNEL A/B)
Figure Serial Ports
Rev.
Page
September 2004
ADSP-21364
Input Data Port (IDP)
timing requirements given Table 28.IDP Signals (SCLK, SDATA) routed DAI_P20-1 pins using SRU. Therefore, timing specifications provided below valid DAI_P20-1 pins. Table
Parameter Timing Requirements tSIFS1 Setup Before SCLK Rising Edge tSIHFS Hold After SCLK Rising Edge SData Setup Before SCLK Rising Edge tSISD1 tSIHD1 SData Hold After SCLK Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period
Preliminary Technical
Unit
DATA, SCLK, come from pins. SCLK also come SPORTs. PCG's input either CLKIN pins.
SAMPLE EDGE tSISCLKW
DAI_P20-1 (SCLK)
tSISFS
DAI_P20-1 (FS)
tSIHFS
tSISD
DAI_P20-1 (SDATA)
tSIHD
Figure Master Timing
Rev.
Page
September 2004
Preliminary Technical DatParallel Data Acquisition Port (PDAP)
timing requirements PDAP provided Table PDAP parallel mode operation channel IDP. details operation IDP, chapter ADSP-2136x SHARC Processor Hardware ReferTable Parallel Data Acquisition Port (PDAP)
Parameter Timing Requirements tSPCLKEN1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge tPDSD1 tPDHD1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge tPDCLKW Clock Width tPDCLK Clock Period Switching Characteristics tPDHLDD Delay PDAP Strobe After Last PDAP_CLK Capture Edge Word tPDSTRB PDAP Strobe Pulse Width
ADSP-21364
ence. Note that most significant bits external PDAP data provided through either parallel port AD15-0 DAI_P20-5 pins. remaining bits only sourced through DAI_P4-1. timing below valid DAI_P20-1 pins AD15-0 pins.
Unit
tCCLK tCCLK
Source pins DATA ADDR7-0, DATA7-0, pins. Source pins SCLK are: pins, CLKIN through PCG, pins through PCG.
SAMPLE EDGE
PDCLK
PDCLKW
DAI_P20-1 (PDAP_CLK)
SPCLKEN
DAI_P20-1 (PDAP_CLKEN)
HPCLKEN
PDSD
DATA
PDHD
DAI_P20-1 (PDAP_STROBE)
tPDSTRB
PDHLDD
Figure PDAP Timing
Rev.
Page
September 2004
ADSP-21364
Sample Rate Converter-Serial Input Port
input signals (SCLK, SDATA) routed from DAI_P20-1 pins using SRU. Therefore, timing specifications provided Table valid DAI_P20-1 pins. Table SRC, Serial Input Port
Parameter Timing Requirements Setup Before SCLK Rising Edge tSIFS1 tSIHFS1 Hold After SCLK Rising Edge tSISD1 SData Setup Before SCLK Rising Edge tSIHD SData Hold After SCLK Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period
Preliminary Technical
Unit
DATA, SCLK, come from pins. SCLK also come SPORTs. PCG's input either CLKIN pins.
SAMPLE EDGE IDPCLKW
DAI_P20-1 (SCLK)
tSISFS
DAI_P20-1 (FS)
SIHFS
SISD
DAI_P20-1 (SDATA)
tSIHD
Figure Serial Input Port Timing
Rev.
Page
September 2004
Preliminary Technical DatSample Rate Converter-Serial Output Port
serial output port, frame-sync input should meet setup hold times with regard SCLK output port. serial data output, SDATA, hold time Table SRC, Serial Output Port
Parameter Timing Requirements Setup Before SCLK Rising Edge tSIFS1 tSIHFS1 Hold Before SCLK Rising Edge tSRCTDD1 Transmit Data Delay After SCLK Falling Edge tSRCTDH Transmit Data Hold After SCLK Falling Edge
ADSP-21364
delay specification with regard SCLK. Note that SCLK rising edge sampling edge falling edge drive edge.
Unit
DATA, SCLK, come from pins. SCLK also come SPORTs. PCG's input either CLKIN pins.
SAMPLE EDGE SISCLKW
DAI_P20-1 (SCLK)
tSIFS
DAI_P20-1 (FS)
SIHFS
CTDH tSRCTDD
DAI_P20-1 (SDATA)
Figure Serial Output Port Timing
Rev.
Page
September 2004
ADSP-21364
SPDIF Transmitter
Serial data input SPDIF transmitter formatted left justified, right justified with word widths bits. following sections provide timing transmitter. SPDIF Transmitter-Serial Input Waveforms Figure shows right-justified mode. LRCLK left channel right channel. Data valid rising edge SCLK. delayed 12-bit clock periods 20-bit output mode) 16-bit clock periods 16-bit output
Preliminary Technical
mode) from LRCLK transition, that when there SCLK periods LRCLK period, data will right-justified next LRCLK transition.
LRCLK SCLK SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB-1
MSB-2
LSB+2 LSB+1
MSB-1 MSB-2
LSB+2
LSB+1
Figure Right-Justified Mode
Figure shows default I2S-justified mode. LRCLK left channel right channel. Data valid rising edge SCLK. left-justified LRCLK transition with single SCLK period delay.
RIGHT CHANNEL LRCLK LEFT CHANNEL
SCLK
SDATA
MSB-1 MSB-2
LSB+2 LSB+1
MSB-1
MSB-2
LSB+2
LSB+1
Figure I2S-Justified Mode
Figure shows left-justified mode. LRCLK left channel right channel. Data valid rising edge SCLK. left-justified LRCLK transition with delay.
LRCLK SCLK SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB-1
MSB-2
LSB+2
LSB+1
MSB-1
MSB-2
LSB+2
LSB+1
MSB+1
Figure Left-Justified Mode
Rev.
Page
September 2004
Preliminary Technical DatSPDIF Transmitter Input Data Timing timing requirements Input port given Table Input Signals (SCLK, SDATA) routed DAI_P20-1 pins using SRU. Therefore, timing specifications provided below valid DAI_P20-1 pins. Table SPDIF Transmitter Input Data Timing
Parameter Timing Requirements tSIFS1 Setup Before SCLK Rising Edge tSIHFS1 Hold After SCLK Rising Edge tSISD1 SData Setup Before SCLK Rising Edge tSIHD1 SData Hold After SCLK Rising Edge Clock Width tSISCLKW tSISCLK Clock Period
ADSP-21364
Unit
DATA, SCLK, come from pins. SCLK also come SPORTs. PCG's input either CLKIN pins.
SAMPLE EDGE SISCLKW
DAI_P20-1 (SCLK)
tSISFS
DAI_P20-1 (FS)
tSIHFS
SISD
DAI_P20-1 (SDATA)
tSIH
Figure SPDIF Transmitter Input Timing
Over Sampling Clock (TXCLK) Switching Characteristics SPDIF Transmitter over sampling clock. This TXCLK input divided down generate Biphase Clock.
Table Over Sampling Clock (TXCLK) Switching Characteristics
Parameter TXCLK Frequency TXCLK TXCLK Frequency TXCLK TXCLK Frequency TXCLK TXCLK Frequency TXCLK Frame Rate 147.5 98.4 73.8 49.2 192.0 Unit
Rev.
Page
September 2004
ADSP-21364
SPDIF Receiver
following sections describe timing relates SPDIF receiver. Internal Digital Mode internal Digital Phase-locked Loop mode internal (Digital PLL) generates clock. Table SPDIF Receiver Internal Digital Mode Timing
Parameter Switching Characteristics LRCLK Delay After SCLK tDFSI tHOFSI LRCLK Hold After SCLK tDDTI Transmit Data Delay After SCLK tHDTI Transmit Data Hold After SCLK tSCLKIW1 Transmit SCLK Width tCCLK Core Clock Period
Preliminary Technical
Unit
SCLK frequency where frequency LRCLK.
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
DAI_P20-1 (SCLK)
tDFSI
tHOFSI
DAI_P20-1 (FS)
tSFSI
tHFSI
tHDTI
DAI_P20-1 (DATA CHANNEL A/B)
tDDTI
Figure SPDIF Receiver Internal Digital Mode Timing
Rev.
Page
September 2004
Preliminary Technical DatExternal Mode External Mode internal Digital disabled receiver runs that connected processor externally. This external generates clock (MCLK) from reference clock (LRCLK) gives SPDIF receiver. Table SPDIF Receiver External Mode Timing
Parameter Timing Requirements tMCP FMCLK tBDM tLDM tDDP tDDS tDDH MCLK Period MCLK Frequency (1/tMCP) SCLK Propagation Delay from MCLK Falling Edge LRCLK Propagation Delay From MCLK Data Propagation Delay From MCLK Data Output Setup SCLK Data Output Hold From SCLK SCLK Period SCLK Period
ADSP-21364
Unit
MCLK INPUT (NOT SCALE)
BCLK OUTPUT
tBDM
LRCLK OUTPUT
tLDM
tDDS
SDATA OUTPUT I2S-JUSTIFIED MODE
tDDH
tDDP
tDDS
tDDS
SDATA OUTPUT RIGHT-JUSTIFIED MODE
tDDH
tDDP
tDDH
Figure SPDIF Receiver External Mode Timing
Rev.
Page
September 2004
ADSP-21364
Interface-Master
Table Interface Protocol Master Switching Timing Specifications
Parameter Timing Requirements tSSPIDM Data Input Valid SPICLK Edge (Data Input Set-up Time) tHSPIDM SPICLK Last Sampling Edge Data Input Valid Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period tSPICLM Serial Clock Period tDDSPIDM SPICLK Edge Data Valid (Data Delay Time) tHDSPIDM SPICLK Edge Data Valid (Data Hold Time) FLAG3-0IN (SPI Device Select) First SPICLK Edge tSDSCIM tHDSM Last SPICLK edge FLAG3-0IN High tSPITDM Sequential Transfer Delay
Preliminary Technical
Unit
tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK
FLAG3-0 (OUTPUT)
tSDSCIM
SPICLK (OUTPUT)
tSPICHM
tSPICLM
tSPICLKM
tHDSM
tSPICLM
SPICLK (OUTPUT)
tSPICHM
tDDSPIDM
MOSI (OUTPUT)
HDSPIDM
tSSPIDM
CPHASE=1 MISO (INPUT) VALID
tHSSPIDM
VALID
tHSPIDM
tDDSPIDM
MOSI (OUTPUT) CPHASE=0 MISO (INPUT)
tHDSPIDM
VALID
tHSPIDM
VALID
Figure Master Timing
Rev.
Page
September 2004
Preliminary Technical DatSPI Interface-Slave
Table Interface Protocol -Slave Switching Timing Specifications
Parameter Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO Serial Clock Cycle Serial Clock High Period Serial Clock Period SPIDS Assertion First SPICLK Edge CPHASE CPHASE Last SPICLK Edge SPIDS Asserted, CPHASE Data Input Valid SPICLK edge (Data Input Set-up Time) SPICLK Last Sampling Edge Data Input Valid SPIDS Deassertion Pulse Width (CPHASE=0) tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK
ADSP-21364
Unit
tHDS tSSPIDS tHSPIDS tSDPPW
Switching Characteristics tDSOE SPIDS Assertion Data Active tDSDHI SPIDS Deassertion Data High Impedance tDDSPIDS SPICLK Edge Data Valid (Data Delay Time) tHDSPIDS SPICLK Edge Data Valid (Data Hold Time) tDSOV SPIDS Assertion Data Valid (CPHASE=0)
tPCLK
tPCLK
SPIDS (INPUT)
SPICLK (INPUT)
tSPICLS
tSPICL tHDS tSDPPW
tSDSCO
SPICLK (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPIDS tDDSPIDS
tDSDHI
MISO (OUTPUT) CPHASE=1 MOSI (INPUT)
tHSPIDS tSSPIDS
VALID
tSSPIDS
VALID
tDSOV
MISO (OUTPUT) CPHASE=0 MOSI (INPUT)
tDDSPIDS
tHDLSBS
tDSDHI
tSSPIDS
VALID VALID
tHSPIDS
Figure Slave Timing
Rev.
Page
September 2004
ADSP-21364
JTAG Test Access Port Emulation
Table JTAG Test Access Port Emulation
Parameter Timing Requirements tTCK Period tSTAP TDI, Setup Before High tHTAP TDI, Hold After High tSSYS1 System Inputs Setup Before tHSYS System Inputs Hold After tTRSTW TRST Pulse Width Switching Characteristics tDTDO Delay From System Outputs Delay After tDSYS
Preliminary Technical
4tCK
Unit
System Inputs AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0. System Outputs MISO, MOSI, SPICLK, DAI_Px, AD15-0, FLAG3-0, CLKOUT, EMU, ALE.
tTCK tSTAP tDTDO tSSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS tHSYS tHTAP
Figure IEEE 1149.1 JTAG Test Access Port
Rev.
Page
September 2004
Preliminary Technical DatOUTPUT DRIVE CURRENTS
Figure shows typical characteristics output drivers ADSP-21364. curves represent current drive capability output drivers function output voltage.
ADSP-21364
CAPACITIVE LOADING
Output delays holds based standard capacitive loads: pins (see Figure 37). Figure shows graphically output delays holds vary with load capacitance. graphs Figure Figure Figure linear outside ranges shown Typical Output Delay Load Capacitance Typical Output Rise Time (20%-80%, V=Min) Load Capacitance.
SOURCE (VDDEXT) CURRENT (mA)
3.3V, 3.47V, -45°
3.11V, 125°
RISE FALL TIMES (ns)
0.0467x 1.6323
RISE FALL
3.11V, 125°
3.3V,
3.47V, -45°
SWEEP (VDDEXT) VOLTAGE
0.045x 1.524
Figure ADSP-21364 Typical Drive
TEST CONDITIONS
signal specifications (timing parameters) appear Table Page through Table Page These include output disable time, output enable time, capacitive loading. timing specifications SHARC apply voltage reference levels Figure Timing measured signals when they cross level described Figure Page delays nanoseconds) measured between point that first signal reaches point that second signal reaches
LOAD CAPACITANCE (pF)
Figure Typical Output Rise/Fall Time (20%-80%, VDDEXT Max)
RISE
RISE FALL TIMES (ns)
0.049x 1.5105
FALL
OUTPUT
1.5V
0.0482x 1.4604
30pF
Figure Equivalent Device Loading Measurements (Includes Fixtures)
LOAD CAPACITANCE (pF)
Figure Typical Output Fall Time (20%-80%, VDDEXT Min)
INPUT 1.5V OUTPUT 1.5V
Figure Voltage Reference Levels Measurements
Rev.
Page
September 2004
ADSP-21364
OUTPUT DELAY HOLD (ns)
Preliminary Technical DatT
0.0488X 1.5923
where: Ambient Temperature Values provided package comparison design considerations when external heatsink required. Values provided package comparison design considerations. Table Thermal Characteristics Ball Mini-BGA thermal vias PCB)1
Parameter Condition Airflow Airflow Airflow Airflow Airflow Airflow Typical 25.20 21.70 20.80 5.00 0.140 0.330 0.410 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
LOAD CAPACITANCE (pF)
Figure Typical Output Delay Hold Load Capacitance Ambient Temperature)
THERMAL CHARACTERISTICS
ADSP-21364 processor rated performance maximum junction temperature 125°C. Table airflow measurements comply with JEDEC standards JESD51-2 JESD51-6 junction-to-board measurement complies with JESD51-8. Test board thermal design comply with JEDEC standards JESD51-9 (Mini-BGA) JESD51-5 (Integrated Heatsink LQFP). junction-tocase measurement complies with MIL- STD-883. measurements 2S2P JEDEC test board. Industrial applications using Mini-BGA package require thermal vias, embedded ground plane, PCB. Refer JEDEC Standard JESD51-9 printed circuit board thermal ball land thermal design information. Industrial applications using LQFP package require thermal trace squares thermal vias, embedded ground plane, PCB. bottom side heat slug must soldered thermal trace squares. Refer JEDEC Standard JESD51-5 more information. determine Junction Temperature device while application PCB, use: CASE where: Junction temperature TCASE Case temperature measured center package Junction-to-Top package) characterization parameter Typical value from Table Table Power dissipation (see Note #216) Values provided package comparison design considerations. used first order approximation equation:
Table Thermal Characteristics Ball Mini-BGA (Thermal vias PCB)1
Parameter Condition Airflow Airflow Airflow Airflow Airflow Airflow Typical 22.50 19.30 18.40 5.00 0.130 0.300 0.360 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Table Thermal Characteristics 144-Lead Integrated Heatsink (INT-HS) LQFP (With heat slug soldered PCB)1
Parameter Condition Airflow Airflow Airflow Airflow Airflow Airflow Typical 26.08 24.59 23.77 6.83 0.236 0.427 0.441 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Rev.
Page
September 2004
Preliminary Technical DatTable Thermal Characteristics 144-Lead Integrated Heatsink (INT-HS) LQFP (With heat slug soldered PCB)1
Parameter
ADSP-21364
Condition Airflow Airflow Airflow Airflow Airflow Airflow
Typical 16.50 15.14 14.35 6.83 0.129 0.255 0.261
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
thermal characteristics values provided these tables modeled values.
Rev.
Page
September 2004
ADSP-21364
136-BALL CONFIGURATIONS
following table shows ADSP-21364's names their default function after reset parentheses). Table 136-Ball Mini-BGA Assignments
Name CLKCFG0 XTAL CLKOUT MOSI MISO SPIDS VDDINT VDDINT FLAG3 Pin# Name CLKCFG1 VDDEXT CLKIN TRST AVSS AVDD VDDEXT SPICLK RESET VDDINT FLAG1 FLAG0 FLAG2 DAI_P20 (SFS45) Pin# Name BOOTCFG1 BOOTCFG0 VDDINT
Preliminary Technical
Pin#
Name VDDINT VDDINT
Pin#
VDDINT VDDEXT DAI_P19 (SCLK45)
VDDEXT DAI_P18 (SD5B) DAI_P17 (SD5A)
Rev.
Page
September 2004
Preliminary Technical DatTable 136-Ball Mini-BGA Assignments (Continued)
Name VDDINT DAI_P16 (SD4B) AD15 VDDINT VDDEXT VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT DAI_P10 (SD2B) Pin# Name VDDINT DAI_P15 (SD4A) AD14 AD13 AD12 AD11 AD10 DAI_P1 (SD0A) DAI_P3 (SCLK0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) DAI_P8 (SFS1) DAI_P9 (SD2A) DAI_P11 (SD3A) Pin# Name DAI_P14 (SFS23) Pin# Name
ADSP-21364
Pin#
DAI_P12 (SD3B) DAI_P13 (SCLK23)
Rev.
Page
September 2004
ADSP-21364
Preliminary Technical
VDDINT VDDEXT GND* AVSS AVDD SIGNALS
*USE CENTER BLOCK GROUND PINS PROVIDE THERMAL PATHWAYS YOUR PRINTED CIRCUIT BOARD'S GROUND PLANE.
Figure 136-Ball Mini-BGA Assignments (Bottom View, Summary)
Rev.
Page
September 2004
Preliminary Technical Dat144-LEAD LQFP CONFIGURATIONS
following table shows ADSP-21364's names their default function after reset parentheses). Table 144-Lead LQFP Assignments
Name VDDINT CLKCFG0 CLKCFG1 BOOTCFG0 BOOTCFG1 VDDEXT VDDINT VDDINT VDDINT FLAG0 FLAG1 VDDINT VDDEXT VDDINT VDDINT VDDEXT VDDINT LQFP Name VDDINT AD15 AD14 AD13 VDDEXT AD12 VDDINT AD11 AD10 DAI_P1 (SD0A) VDDINT DAI_P2 (SD0B) DAI_P3 (SCLK0) VDDEXT VDDINT DAI_P4 (SFS0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) VDDINT VDDINT DAI_P8 (SFS1) DAI_P9 (SD2A) VDDINT LQFP LQFP VDDEXT VDDINT DAI_P10 (SD2B) DAI_P11 (SD3A) DAI_P12 (SD3B) DAI_P13 (SCLK23) DAI_P14 (SFS23) DAI_P15 (SD4A) VDDINT DAI_P16 (SD4B) DAI_P17 (SD5A) DAI_P18 (SD5B) DAI_P19 (SCLK45) VDDINT VDDEXT DAI_P20 (SFS45) VDDINT FLAG2 FLAG3 VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT Name Name VDDINT VDDINT VDDINT VDDEXT VDDINT VDDINT RESET SPIDS VDDINT SPICLK MISO MOSI VDDINT VDDEXT AVDD AVSS CLKOUT TRST CLKIN XTAL VDDEXT
ADSP-21364
LQFP
Rev.
Page
September 2004
ADSP-21364
PACKAGE DIMENSIONS
ADSP-21364 available 136-ball Mini-BGA package 144-lead integrated heatsink LQFP package.
Preliminary Technical
12.00
10.40
0.80
INDICATOR
0.80
VIEW
BOTTOM VIEW
1.70
DETAIL
0.25 DIMENSIONS MILIMETERS (MM). ACTUAL POSITION BALL GRID WITHIN 0.15 IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.08 IDEAL POSITION RELATIVE BALL GRID. COMPLIANT JEDEC STANDARD MO-205-AE, EXCEPT BALL DIAMETER. CENTER DIMENSIONS NOMINAL.
0.50 0.45 0.40 (BALL DIAMETER)
SEATING PLANE
0.12 (BALL COPLANARITY)
DETAIL
Figure 136-Ball Mini-BGA (BC-136-2)
Rev.
Page
September 2004
Preliminary Technical Dat22.00 0.27 0.22 0.17
ADSP-21364
SEATING PLANE 0.08 (LEAD COPLANARITY) 0.15 0.05 1.60
0.50 (LEAD PITCH)
INDICA
13.71 13.21 12.71
0.75 0.60 0.45
TAIL
DETAIL
HEATSLUG BOTTOM (NOTE
NOTES: DIMENSIONS MILLIMETERS COMPLY WITH JEDEC STANDARD MS-026-BFB-HD. ACTUAL SITION EACH LEAD WITHIN 0.08 IDEAL POSITION, WHEN MEASURED LATERAL DIRECTI CENTER DIMENSIONS NOMINAL. HEATSLUG COINCIDENT TTOM SURFACE DOES PROTRUDE BEYOND
Figure 144-Lead Integrated Heatsink LQFP (SQ-144-3)
Rev.
Page
September 2004
ADSP-21364
ORDERING GUIDE
Preliminary Technical
Analog Devices offers wide variety audio algorithms combinations ADSP-21364 processor. These products sold part chip set, bundled with necessary application software under special part numbers. complete list, visit site www.analog.com/SHARC. These products also contain party that require users have authorization from respective holders receive them. Royalty party also payable users.
Part Number1, Ambient Temperature Range Instruction Rate 333MHz 333MHz 333MHz 333MHz 333MHz 333MHz 333MHz 333MHz 200MHz 200MHz On-Chip SRAM Operating Voltage Internal/External Volts 1.2/3.3 1.2/3.3 1.2/3.3 1.2/3.3 1.2/3.3 1.2/3.3 1.2/3.3 1.2/3.3 1.0/3.3 1.0/3.3 Package
ADSP-21364SKBCZENG ADSP-21364SKBC-ENG ADSP-21364SKSQZENG ADSP-21364SKSQ-ENG ADSP-21364SBBCZENG4 ADSP-21364SBBC-ENG4 ADSP-21364SBSQZENG5 ADSP-21364SBSQ-ENG5 ADSP-21364SCSQZENG5 ADSP-21364SCSQ-ENG5
Mini-BGA Pb-free Mini-BGA INT-HS LQFP Pb-free INT-HS LQFP Mini-BGA Pb-free Mini-BGA INT-HS LQFP Pb-free INT-HS LQFP INT-HS LQFP Pb-free INT-HS LQFP
indicates Lead Free package. more information about lead free package offerings, please visit www.analog.com. Thermal Characteristics Page information package thermal specifications. Engineer-to-Engineer Note TBD) further information. must have thermal vias. Thermal Characteristics Page more information JEDEC Standard JESD51-9. Heat slug must soldered PCB. Thermal Characteristics Page more information JEDEC Standard JESD51-5.
2004 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners.
PR04624-0-10/04(PrB)
Rev.
Page
September 2004
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