28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit nanoWatt T
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PIC16F7X7 Data Sheet
28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit nanoWatt Technology
2004 Microchip Technology Inc.
DS30498C
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel Total Endurance trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2004, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit nanoWatt Technology
Low-Power Features:
Power-Managed modes: Primary (XT, oscillator, MHz, RC_RUN 31.25 kHz, SEC_RUN kHz, Sleep (0.1 Timer1 Oscillator (1.8 kHz, Watchdog Timer (0.7 Two-Speed Oscillator Start-up
Peripheral Features:
High Sink/Source Current: 8-bit Timers with Prescaler Timer1/RTC module: 16-bit timer/counter with prescaler incremented during Sleep external watch crystal Master Synchronous Serial Port (MSSP) with 3-wire SPIand I2C(Master Slave) modes Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) Three Capture, Compare, modules: Capture 16-bit, max. resolution 12.5 Compare 16-bit, max. resolution max. resolution bits Parallel Slave Port (PSP) 40/44-pin devices only
Oscillators:
Three Crystal modes: MHz) External modes External Clock mode: ECIO MHz) Internal Oscillator Block: user-selectable frequencies kHz, kHz, kHz, kHz, MHz, MHz, MHz, MHz)
Special Microcontroller Features:
Fail-Safe Clock Monitor protecting critical applications against crystal failure Two-Speed Start-up mode immediate code execution Power-on Reset (POR), Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Programmable Code Protection Processor Read Access Program Memory Power-Saving Sleep mode In-Circuit Serial Programming (ICSP) pins MPLAB® In-Circuit Debug (ICD) pins MCLR function replaceable with input only
Analog Features:
10-bit, 14-channel Analog-to-Digital Converter: Programmable Acquisition Time Conversion available during Sleep mode Dual Analog Comparators Programmable Low-Current Brown-out Reset (BOR) Circuitry Programmable Low-Voltage Detect (LVD)
Comparators
Device
Program Data Memory SRAM Single-Word (Bytes) Instructions) 4096 4096 8192 8192
Interrupts
MSSP (PWM) SPI3 Timers I2CAUSART 8/16-bit (Master)
10-bit (ch)
PIC16F737 PIC16F747 PIC16F767 PIC16F777
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
Diagrams
PDIP, SOIC, SSOP (28-pin)
MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/SS/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RB7/PGD RB6/PGC RB5/AN13/CCP3 RB4/AN11 RB3/CCP2(1)/AN9 RB2/AN8 RB1/AN10 RB0/INT/AN12 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RA1/AN1 RA0/AN0 MCLR/VPP/RE3 RB7/PGD RB6/PGC RB5/AN13/CCP3 RB4/AN11 PIC16F737 PIC16F767
PIC16F737/767
(28-pin)
RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/SS/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6
RB3/CCP2(1)/AN9 RB2/AN8 RB1/AN10 RB0/INT/AN12 RC7/RX/DT
Note
location CCP2 determined CCPMX Configuration Word Register
RB3/CCP2(1)/AN9 RB4/AN11 RB5/AN13/CCP3 RB6/PGC RB7/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RB0/INT/AN12 RB1/AN10 RB2/AN8
PIC16F747 PIC16F777
OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/LVDIN/SS/C2OUT RA4/T0CKI/C1OUT
DS30498C-page
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK
(44-pin)
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2(1) RC0/T1OSO/T1CKI
2004 Microchip Technology Inc.
PIC16F7X7
Diagrams (Continued)
PDIP (40-pin)
MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/SS/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1
RB7/PGD RB6/PGC RB5/AN13/CCP3 RB4/AN11 RB3/CCP2(1)/AN9 RB2/AN8 RB1/AN10 RB0/INT/AN12 RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
TQFP (44-pin)
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2(1)
PIC16F747/777
Note
location CCP2 determined CCPMX Configuration Word Register
2004 Microchip Technology Inc.
RB4/AN11 RB5/AN13/CCP3 RB6/PGC RB7/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RB0/INT/AN12 RB1/AN10 RB2/AN8 RB3/CCP2(1)/AN9
PIC16F747 PIC16F777
RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/LVDIN/SS/C2OUT RA4/T0CKI/C1OUT
DS30498C-page
PIC16F7X7
Table Contents
Device Overview Memory Organization Reading Program Memory Oscillator Configurations Ports Timer0 Module Timer1 Module Timer2 Module Capture/Compare/PWM Modules 10.0 Master Synchronous Serial Port (MSSP) Module 11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) 12.0 Analog-to-Digital Converter (A/D) Module 13.0 Comparator Module. 14.0 Comparator Voltage Reference Module 15.0 Special Features 16.0 Instruction Summary 17.0 Development Support. 18.0 Electrical Characteristics 19.0 Characteristics Graphs Tables 20.0 Packaging Information. Appendix Revision History. Appendix Device Differences. Appendix Conversion Considerations Index On-Line Support. Systems Information Upgrade Line Reader Response PIC16F7X7 Product Identification System
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
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DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
DEVICE OVERVIEW
This document contains device specific information about following devices: PIC16F737 PIC16F747 PIC16F767 PIC16F777 Timer1 module current consumption been greatly reduced from (previous PIC16 devices) typical 2V), which ideal real-time clock applications. Refer Section "Timer1 Module" further details. Extended Watchdog Timer (WDT) that have programmable period from 268s. 16-bit prescaler. Refer Section 15.17 "Watchdog Timer (WDT)" further details. Two-Speed Start-up: When oscillator configured this feature will clock device from INTRC while oscillator warming This, turn, will enable almost immediate code execution. Refer Section 15.17.3 "Two-Speed Clock Start-up Mode" further details. Fail-Safe Clock Monitor: This feature will allow device continue operation primary secondary clock source fails switching over INTRC. available features summarized Table 1-1. Block diagrams PIC16F737/767 PIC16F747/777 devices provided Figure Figure 1-2, respectively. pinouts these device families listed Table Table 1-3. Additional information found "PICmicro® Mid-Range Family Reference Manual" (DS33023) which obtained from your local Microchip Sales Representative downloaded from Microchip site. Reference Manual should considered complementary document this data sheet highly recommended reading better understanding device architecture operation peripheral modules.
PIC16F737/767 devices available only 28-pin packages, while PIC16F747/777 devices available 40-pin 44-pin packages. devices PIC16F7X7 family share common architecture with following differences: PIC16F737 PIC16F767 have one-half total on-chip memory PIC16F747 PIC16F777. 28-pin devices have ports, while 40/44-pin devices have 28-pin devices have interrupts, while 40/44-pin devices have 28-pin devices have input channels, while 40/44-pin devices have Parallel Slave Port implemented only 40/44-pin devices. Low-Power modes: RC_RUN allows core peripherals clocked from INTRC, while SEC_RUN allows core peripherals clocked from low-power Timer1. Refer Section "Power-Managed Modes" further details. Internal oscillator with eight selectable frequencies, including 31.25 kHz, kHz, kHz, kHz, MHz, MHz, MHz. INTRC configured primary secondary clock source. Refer Section "Internal Oscillator Block" further details.
TABLE 1-1:
PIC16F7X7 DEVICE FEATURES
PIC16F737 POR, (PWRT, OST) Ports MSSP, AUSART Input Channels Instructions 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin PIC16F747 POR, (PWRT, OST) Ports MSSP, AUSART Input Channels Instructions 40-pin PDIP 44-pin 44-pin TQFP PIC16F767 POR, (PWRT, OST) Ports MSSP, AUSART Input Channels Instructions 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin PIC16F777 POR, (PWRT, OST) Ports MSSP, AUSART Input Channels Instructions 40-pin PDIP 44-pin 44-pin TQFP
Features Operating Frequency Resets (and Delays) Flash Program Memory (14-bit words) Data Memory (bytes) Interrupts Ports Timers Capture/Compare/PWM Modules Master Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Instruction Packaging
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
FIGURE 1-1: PIC16F737 PIC16F767 BLOCK DIAGRAM
PORTA Standard Flash Program Memory 4K/8K Program Program Counter Data RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/ SS/C2OUT OSC2/CLKO/RA6 OSC1/CLKI/RA7 PORTB RB0/INT/AN12 RB1/AN10 RB2/AN8 RB3/CCP2(1)/AN9 RB4/AN11 RB5/AN13/CCP3 RB7/PGD:RB6/PGC PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
8-Level Stack (13-bit)
File Registers Addr(1)
Instruction Register Direct Addr
Addr Indirect Addr
Status
Power-up Timer Instruction Decode Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
WREG
PORTE VDD, MCLR/VPP/RE3
Timer0
Timer1
Timer2
10-bit
Comparators
CCP1,
MSSP
Addressable USART
BOR/LVD
Note location CCP2 determined CCPMX Configuration Word Register
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
FIGURE 1-2: PIC16F747 PIC16F777 BLOCK DIAGRAM
PORTA Standard Flash Program Memory 4K/8K Program Counter Data RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/ SS/C2OUT OSC2/CLKO/RA6 OSC1/CLKI/RA7 PORTB RB0/INT/AN12 RB1/AN10 RB2/AN8 RB3/CCP2(1)/AN9 RB4/AN11 RB5/AN13/CCP3 RB7/PGD:RB6/PGC PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2(1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD WREG RD7/PSP7:RD0/PSP0 Parallel Slave Port
8-Level Stack (13-bit)
File Registers Addr(1)
Program
Instruction Register Direct Addr
Addr Indirect Addr
Status
Power-up Timer Instruction Decode Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
VDD,
PORTE RE0/RD/AN5 RE1/WR/AN6
Timer0
Timer1
Timer2
10-bit
RE2/CS/AN7 MCLR/VPP/RE3
Comparators
CCP1,
MSSP
Addressable USART
BOR/LVD
Note location CCP2 determined CCPMX Configuration Word Register
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
TABLE 1-2:
Name
PIC16F737 PIC16F767 PINOUT DESCRIPTION
PDIP SOIC SSOP I/O/P Type Buffer Type Description
OSC1/CLKI/RA7 OSC1 CLKI OSC2/CLKO/RA6 OSC2
ST/CMOS(3) Oscillator crystal external clock input. Oscillator crystal input external clock source input. buffer when configured mode; otherwise CMOS. External clock source input. Always associated with function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). Digital I/O. Oscillator crystal clock output. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. mode, OSC2 outputs CLKO which frequency OSC1 denotes instruction cycle rate. Digital I/O. Master Clear (input) programming voltage (output). Master Clear (Reset) input. This active-low Reset device. Programming voltage input. Digital input only pin. PORTA bidirectional port.
CLKO MCLR/VPP/RE3 MCLR RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF VREFCVREF RA3/AN3/VREF+ VREF+ RA4/T0CKI/C1OUT T0CKI C1OUT RA5/AN4/LVDIN/SS/C2OUT LVDIN C2OUT Legend: Note
Digital I/O. Analog input Digital I/O. Analog input Digital I/O. Analog input reference voltage input (low). Comparator voltage reference output. Digital I/O. Analog input reference voltage input (high). Digital Open-drain when configured output. Timer0 external clock input. Comparator output bit. Digital I/O. Analog input Low-Voltage Detect input. SPIslave select input. Comparator output bit.
input output input/output power used input Schmitt Trigger input This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used Serial Programming mode. This buffer Schmitt Trigger input when configured Oscillator mode CMOS input otherwise. location CCP2 determined CCPMX Configuration Word Register
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
TABLE 1-2:
Name
PIC16F737 PIC16F767 PINOUT DESCRIPTION (CONTINUED)
PDIP SOIC SSOP I/O/P Type Buffer Type Description
PORTB bidirectional port. PORTB software programmed internal weak pull-up inputs. RB0/INT/AN12 AN12 RB1/AN10 AN10 RB2/AN8 RB3/CCP2/AN9 CCP2(4) RB4/AN11 AN11 RB5/AN13/CCP3 AN13 CCP3 RB6/PGC RB7/PGD Legend: Note TTL/ST(2) Digital I/O. In-Circuit Debugger ICSP programming data. TTL/ST(2) Digital I/O. In-Circuit Debugger ICSPprogramming clock. Digital I/O. Analog input channel CCP3 capture input, compare output, output. Digital I/O. Analog input channel Digital I/O. CCP2 capture input, compare output, output. Analog input channel Digital I/O. Analog input channel Digital I/O. Analog input channel TTL/ST(1) Digital I/O. External interrupt. Analog input channel
input output input/output power used input Schmitt Trigger input This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used Serial Programming mode. This buffer Schmitt Trigger input when configured Oscillator mode CMOS input otherwise. location CCP2 determined CCPMX Configuration Word Register
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
TABLE 1-2:
Name
PIC16F737 PIC16F767 PINOUT DESCRIPTION (CONTINUED)
PDIP SOIC SSOP I/O/P Type Buffer Type Description
PORTC bidirectional port. RC0/T1OSO/T1CKI T1OSO T1CKI RC1/T1OSI/CCP2 T1OSI CCP2(4) RC2/CCP1 CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Legend: Note Digital I/O. AUSART asynchronous receive. AUSART synchronous data. Ground reference logic pins. Positive supply logic pins. Digital I/O. AUSART asynchronous transmit. AUSART synchronous clock. Digital I/O. data out. Digital I/O. data data I/O. Digital I/O. Synchronous serial clock input/output SPImode. Synchronous serial clock input/output I2Cmode. Digital I/O. Capture1 input, Compare1 output, PWM1 output. Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. Digital I/O. Timer1 oscillator output. Timer1 external clock input.
input output input/output power used input Schmitt Trigger input This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used Serial Programming mode. This buffer Schmitt Trigger input when configured Oscillator mode CMOS input otherwise. location CCP2 determined CCPMX Configuration Word Register
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
TABLE 1-3:
Name OSC1/CLKI/RA7 OSC1
PIC16F747 PIC16F777 PINOUT DESCRIPTION
PDIP TQFP I/O/P Type Buffer Type Description
CLKI
OSC2/CLKO/RA6 OSC2 CLKO
ST/CMOS(4) Oscillator crystal external clock input. Oscillator crystal input external clock source input. buffer when configured mode; otherwise CMOS. External clock source input. Always associated with function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). Bidirectional pin. Oscillator crystal clock output. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. mode, OSC2 outputs CLKO which frequency OSC1 denotes instruction cycle rate. Bidirectional pin. Master Clear (input) programming voltage (output). Master Clear (Reset) input. This active-low Reset device. Programming voltage input. Digital input only pin. PORTA bidirectional port.
MCLR/VPP/RE3 MCLR RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF VREFCVREF RA3/AN3/VREF+ VREF+ RA4/T0CKI/C1OUT T0CKI C1OUT RA5/AN4/LVDIN/SS/C2OUT LVDIN C2OUT Legend: Note
Digital I/O. Analog input Digital I/O. Analog input Digital I/O. Analog input reference voltage input (low). Comparator voltage reference output. Digital I/O. Analog input reference voltage input (high). Digital Open-drain when configured output. Timer0 external clock input. Comparator output. Digital I/O. Analog input Low-Voltage Detect input. SPIslave select input. Comparator output.
input output input/output power used input Schmitt Trigger input This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used Serial Programming mode. This buffer Schmitt Trigger input when configured general purpose input when used Parallel Slave Port mode (for interfacing microprocessor bus). This buffer Schmitt Trigger input when configured Oscillator mode CMOS input otherwise. location CCP2 determined CCPMX Configuration Word Register
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
TABLE 1-3:
Name
PIC16F747 PIC16F777 PINOUT DESCRIPTION (CONTINUED)
PDIP TQFP I/O/P Type Buffer Type Description PORTB bidirectional port. PORTB software programmed internal weak pull-up inputs.
RB0/INT/AN12 AN12 RB1/AN10 AN10 RB2/AN8 RB3/CCP2/AN9 CCP2(5) RB4/AN11 AN11 RB5/AN13/CCP3 AN13 CCP3 RB6/PGC RB7/PGD Legend: Note
TTL/ST(1) Digital I/O. External interrupt. Analog input channel Digital I/O. Analog input channel Digital I/O. Analog input channel Digital I/O. CCP2 capture input, compare output, output. Analog input channel Digital I/O. Analog input channel Digital I/O. Analog input channel CCP3 capture input, compare output, output. TTL/ST(2) Digital I/O. In-Circuit Debugger ICSPprogramming clock. TTL/ST(2) Digital I/O. In-Circuit Debugger ICSP programming data.
input output input/output power used input Schmitt Trigger input This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used Serial Programming mode. This buffer Schmitt Trigger input when configured general purpose input when used Parallel Slave Port mode (for interfacing microprocessor bus). This buffer Schmitt Trigger input when configured Oscillator mode CMOS input otherwise. location CCP2 determined CCPMX Configuration Word Register
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
TABLE 1-3:
Name
PIC16F747 PIC16F777 PINOUT DESCRIPTION (CONTINUED)
PDIP TQFP I/O/P Type Buffer Type Description PORTC bidirectional port.
RC0/T1OSO/T1CKI T1OSO T1CKI RC1/T1OSI/CCP2 T1OSI CCP2(5) RC2/CCP1 CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Legend: Note
Digital I/O. Timer1 oscillator output. Timer1 external clock input. Digital I/O. Timer1 oscillator input. Capture input, Compare output, output. Digital I/O. Capture input, Compare output, output. Digital I/O. Synchronous serial clock input/output SPImode. Synchronous serial clock input/output I2Cmode. Digital I/O. data data I/O. Digital I/O. data out. Digital I/O. AUSART asynchronous transmit. AUSART synchronous clock. Digital I/O. AUSART asynchronous receive. AUSART synchronous data.
input output input/output power used input Schmitt Trigger input This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used Serial Programming mode. This buffer Schmitt Trigger input when configured general purpose input when used Parallel Slave Port mode (for interfacing microprocessor bus). This buffer Schmitt Trigger input when configured Oscillator mode CMOS input otherwise. location CCP2 determined CCPMX Configuration Word Register
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
TABLE 1-3:
Name
PIC16F747 PIC16F777 PINOUT DESCRIPTION (CONTINUED)
PDIP TQFP I/O/P Type Buffer Type Description PORTD bidirectional port Parallel Slave Port when interfacing microprocessor bus.
RD0/PSP0 PSP0 RD1/PSP1 PSP1 RD2/PSP2 PSP2 RD3/PSP3 PSP3 RD4/PSP4 PSP4 RD5/PSP5 PSP5 RD6/PSP6 PSP6 RD7/PSP7 PSP7 RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 Legend: Note
ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. PORTE bidirectional port. ST/TTL(3) Digital I/O. Read control Parallel Slave Port. Analog input ST/TTL(3) Digital I/O. Write control Parallel Slave Port. Analog input ST/TTL(3) Digital I/O. Chip select control Parallel Slave Port. Analog input Analog ground reference. Ground reference logic pins. Analog positive supply. Positive supply logic pins. These pins internally connected. These pins should left unconnected.
input output input/output power used input Schmitt Trigger input This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used Serial Programming mode. This buffer Schmitt Trigger input when configured general purpose input when used Parallel Slave Port mode (for interfacing microprocessor bus). This buffer Schmitt Trigger input when configured Oscillator mode CMOS input otherwise. location CCP2 determined CCPMX Configuration Word Register
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
MEMORY ORGANIZATION
Data Memory Organization
There memory blocks each these PICmicro® MCUs. program memory data memory have separate buses that concurrent access occur detailed this section. program memory read internally user code (see Section "Reading Program Memory"). Additional information device memory found "PICmicro® Mid-Range Family Reference Manual" (DS33023). data memory partitioned into multiple banks which contain General Purpose Registers Special Function Registers. Bits (Status<6>) (Status<5>) bank select bits: RP1:RP0 Bank
Program Memory Organization
PIC16F7X7 devices have 13-bit program counter capable addressing word 14-bit program memory space. PIC16F767/777 devices have words Flash program memory PIC16F737/747 devices have words. program memory maps PIC16F7X7 devices shown Figure 2-1. Accessing location above physically implemented address will cause wraparound. Reset vector 0000h interrupt vector 0004h.
Each bank extends (128 bytes). lower locations each bank reserved Special Function Registers. Above Special Function Registers General Purpose Registers, implemented static RAM. implemented banks contain Special Function Registers. Some frequently used Special Function Registers from bank mirrored another bank code reduction quicker access.
2.2.1
GENERAL PURPOSE REGISTER FILE
register file (shown Figure Figure 2-3) accessed either directly, indirectly, through File Select Register (FSR).
FIGURE 2-1:
PROGRAM MEMORY MAPS STACKS PIC16F7X7 DEVICES
PC<12:0> CALL, RETURN RETFIE, RETLW
Stack Level Stack Level
Stack Level Reset Vector
0000h
Interrupt Vector Page Page On-Chip Program Memory
0004h 0005h 07FFh 0800h 0FFFh 1000h 17FFh 1800h Memory available PIC16F767 PIC16F777. memory wraps 000h through 0FFFh PIC16F737 PIC16F747. Memory available PIC16F7X7.
Page2
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FIGURE 2-2: DATA MEMORY PIC16F737 PIC16F767
File Address Indirect addr.(*) TMR0 STATUS PORTA PORTB PORTC PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 Indirect addr.(*) OPTION_REG STATUS TRISA TRISB TRISC TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 SSPADD SSPSTAT CCPR3L CCPR3H CCP3CON TXSTA SPBRG ADCON2 CMCON CVRCON ADRESL ADCON1 General Purpose Register Bytes File Address Indirect addr.(*) TMR0 STATUS WDTCON PORTB File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h File Address Indirect addr.(*) OPTION_REG STATUS TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
LVDCON PCLATH INTCON PMDATA PMADR PMDATH PMADRH
PCLATH INTCON PMCON1
General Purpose Register Bytes
General Purpose Register Bytes
11Fh 120h General Purpose Register Bytes 16Fh 170h Accesses 70h-7Fh Accesses 70h-7Fh 17Fh Bank Bank General Purpose Register Bytes
19Fh 1A0h
General Purpose Register Bytes
Accesses 70h-7Fh Bank
1EFh 1F0h
1FFh
Bank
Unimplemented data memory locations read `0'. physical register.
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FIGURE 2-3: DATA MEMORY PIC16F747 PIC16F777
File Address Indirect addr.(*) TMR0 STATUS PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 Indirect addr.(*) OPTION_REG STATUS TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 SSPADD SSPSTAT CCPR3L CCPR3H CCP3CON TXSTA SPBRG ADCON2 CMCON CVRCON ADRESL ADCON1 General Purpose Register Bytes File Address Indirect addr.(*) TMR0 STATUS WDTCON PORTB File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h File Address Indirect addr.(*) OPTION_REG STATUS TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
LVDCON PCLATH INTCON PMDATA PMADR PMDATH PMADRH
PCLATH INTCON PMCON1
General Purpose Register Bytes
General Purpose Register Bytes
11Fh 120h General Purpose Register Bytes 16Fh 170h Accesses 70h-7Fh Accesses 70h-7Fh 17Fh Bank Bank General Purpose Register Bytes
19Fh 1A0h
General Purpose Register Bytes
Accesses 70h-7Fh Bank
1EFh 1F0h
1FFh
Bank
Unimplemented data memory locations read `0'. physical register.
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2.2.2 SPECIAL FUNCTION REGISTERS
Special Function Registers registers used peripheral modules controlling desired operation device. These registers implemented static RAM. list these registers given Table 2-1. Special Function Registers classified into sets: core (CPU) peripheral. Those registers associated with core functions described detail this section. Those related operation peripheral features described detail peripheral feature section.
TABLE 2-1:
Address Bank 00h(4) 02h(4) 03h(4) 04h(4) 08h(5) 09h(5) 0Bh(4) INDF TMR0 STATUS PORTA PORTB PORTC PORTD PORTE INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 Name
SPECIAL FUNCTION REGISTER SUMMARY
Value POR, Details page
Addressing this location uses contents address data memory (not physical register) 0000 0000 Timer0 Module Register Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read PSPIF(3) OSFIF PEIE ADIF CMIF TMR0IE RCIF LVDIF INT0IE TXIF RBIE SSPIF BCLIF TMR0IF CCP1IF INT0IF TMR2IF CCP3IF RBIF TMR1IF CCP2IF Write Buffer upper bits Program Counter xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xx0x 0000 xx00 0000 xxxx xxxx xxxx xxxx x000 0000 0000 000x 0000 0000 000- 0-00 xxxx xxxx xxxx xxxx TMR1CS TMR1ON -000 0000 0000 0000 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 SSPM3 SSPM2 SSPM1 SSPM0
0Ah(1,4) PCLATH
Holding Register Least Significant Byte 16-bit TMR1 Register Holding Register Most Significant Byte 16-bit TMR1 Register WCOL T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Timer2 Module Register TOUTPS3 TOUTPS2 SSPOV SSPEN Synchronous Serial Port Receive Buffer/Transmit Register Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) SPEN CCP1X SREN CCP1Y CREN CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR RX9D
xxxx xxxx 101, 0000 0000 101, xxxx xxxx xxxx xxxx CCP1M0 0000
0000 000x 134, 0000 0000 139, 0000 0000 141, xxxx xxxx xxxx xxxx
AUSART Transmit Data Register AUSART Receive Data Register Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) ADCS1 ADCS0 CCP2X CHS2 CCP2Y CHS1 CCP2M3 CHS0 CCP2M2 GO/DONE CCP2M1 CHS3 Result Register High Byte ADON
CCP2M0 0000
xxxx xxxx 160, 0000 0000 152,
Legend: unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. Note upper byte program counter directly accessible. PCLATH holding register PC<12:8> bits, whose contents transferred upper byte program counter during branches (CALL GOTO). Other (non Power-up) Resets include external Reset through MCLR Watchdog Timer Reset. Bits PSPIE PSPIF reserved 28-pin devices; always maintain these bits clear. These registers addressed from bank. PORTD, PORTE, TRISD TRISE physically implemented 28-pin devices (except RE3), read `0'. This always reads `1'. OSCCON<OSTS> resets with dual-speed start-up HS-PLL selected oscillator. input only. state TRISE3 effect will always read `1'.
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TABLE 2-1:
Address Bank 80h(4) 82h(4) 83h(4) 84h(4) 88h(5) 89h(5) 8Bh(4) INDF OPTION_REG STATUS TRISA TRISB TRISC TRISD TRISE INTCON PIE1 PIE2 PCON OSCCON OSCTUNE SSPCON2 SSPADD SSPSTAT CCPR3L CCPR3H CCP3CON TXSTA SPBRG ADCON2 CMCON CVRCON ADRESL ADCON1 Addressing this location uses contents address data memory (not physical register) 0000 0000 RBPU INTEDG T0CS T0SE 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 1111 1111 1111 1111 1111 1111 PSPMODE(5) INT0IE TXIE IRCF0 TUN4 ACKEN -(8) RBIE SSPIE BCLIE OSTS(7) TUN3 RCEN PORTE Data Direction bits TMR0IF CCP1IE SBOREN IOFS TUN2 INT0IF TMR2IE CCP3IE SCS1 TUN1 RSEN RBIF TMR1IE CCP2IE SCS0 TUN0 0000 1111 0000 0000 000x 0000 0000 000- 0-00 -1qq -000 1000 0000 0000 0000 1111 1111 Write Buffer upper bits Program Counter Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF(5) PSPIE(3) OSFIE GCEN OBF(5) PEIE ADIE CMIE IRCF2 ACKSTAT IBOV(5) TMR0IE RCIE LVDIE IRCF1 TUN5 ACKDT Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Details page
8Ah(1,4) PCLATH
Timer2 Period Register Synchronous Serial Port (I2Cmode) Address Register Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) CSRC CCP3X TXEN CCP3Y SYNC CCP3M3 CCP3M2 BRGH CCP3M1 TRMT TX9D
0000 0000 101, 0000 0000 101, xxxx xxxx xxxx xxxx CCP3M0 0000
0000 -010 145, 0000 0000 145,
Baud Rate Generator Register Unimplemented C2OUT CVREN ADFM C1OUT CVROE ADCS2 ACQT2 C2INV CVRR VCFG1 ACQT1 C1INV VCFG0 ACQT0 CVR3 PCFG3 CVR2 PCFG2 CVR1 PCFG1 CVR0 PCFG0
0-0000 0111 000- 0000 xxxx xxxx
Result Register Byte
0000 0000 153,
Legend: unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. Note upper byte program counter directly accessible. PCLATH holding register PC<12:8> bits, whose contents transferred upper byte program counter during branches (CALL GOTO). Other (non Power-up) Resets include external Reset through MCLR Watchdog Timer Reset. Bits PSPIE PSPIF reserved 28-pin devices; always maintain these bits clear. These registers addressed from bank. PORTD, PORTE, TRISD TRISE physically implemented 28-pin devices (except RE3), read `0'. This always reads `1'. OSCCON<OSTS> resets with dual-speed start-up HS-PLL selected oscillator. input only. state TRISE3 effect will always read `1'.
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TABLE 2-1:
Address Bank 100h(4) 101h 102h(4) 103h(4) 104h(4) 105h 106h 107h 108h 109h 10Bh(4) 10Ch 10Dh 10Eh 10Fh Bank 180h(4) 181h 182h(4) 183h(4) 184h(4) 185h 186h 187h 188h 189h 18Bh(4) 18Ch 18Dh 18Eh 18Fh INDF OPTION_REG STATUS TRISB INTCON PMCON1 Addressing this location uses contents address data memory (not physical register) 0000 0000 RBPU INTEDG T0CS T0SE 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 TMR0IE Write Buffer upper bits Program Counter INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 000x Program Counter (PC) Least Significant Byte Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented r(6) PEIE INDF TMR0 STATUS WDTCON PORTB LVDCON INTCON PMDATA PMADR PMDATH PMADRH Addressing this location uses contents address data memory (not physical register) 0000 0000 Timer0 Module Register Program Counter (PC) Least Significant Byte WDTPS3 Indirect Data Memory Address Pointer PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented PEIE IRVST TMR0IE LVDEN INT0IE LVDL3 RBIE LVDL2 TMR0IF LVDL1 INT0IF LVDL0 RBIF Write Buffer upper bits Program Counter xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx WDTPS2 WDTPS1 WDTPS0 SWDTEN 1000 xxxx xxxx 0101 0000 0000 000x xxxx xxxx xxxx xxxx xxxx xxxx EEPROM Address Register High Byte Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Details page
10Ah(1,4) PCLATH
EEPROM Data Register Byte EEPROM Address Register Byte EEPROM Data Register High Byte
18Ah(1,4) PCLATH
Reserved, maintain clear Reserved, maintain clear Reserved, maintain clear
Legend: unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. Note upper byte program counter directly accessible. PCLATH holding register PC<12:8> bits, whose contents transferred upper byte program counter during branches (CALL GOTO). Other (non Power-up) Resets include external Reset through MCLR Watchdog Timer Reset. Bits PSPIE PSPIF reserved 28-pin devices; always maintain these bits clear. These registers addressed from bank. PORTD, PORTE, TRISD TRISE physically implemented 28-pin devices (except RE3), read `0'. This always reads `1'. OSCCON<OSTS> resets with dual-speed start-up HS-PLL selected oscillator. input only. state TRISE3 effect will always read `1'.
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2.2.2.1 Status Register
Status register contains arithmetic status ALU, Reset status bank select bits data memory. Status register destination instruction, with other register. Status register destination instruction that affects bits, then write these three bits disabled. These bits cleared according device logic. Furthermore, bits writable, therefore, result instruction with Status register destination different than intended. example, CLRF STATUS, will clear upper three bits bit. This leaves Status register 000u u1uu (where unchanged). recommended, therefore, that only BCF, BSF, SWAPF MOVWF instructions used alter Status register because these instructions affect bits from Status register. other instructions affecting Status bits, Section 16.0 "Instruction Summary". Note bits operate borrow digit borrow bit, respectively, subtraction. SUBLW SUBWF instructions examples.
REGISTER 2-1:
STATUS: ARITHMETIC STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R/W-x R/W-x R/W-x
IRP: Register Bank Select (used indirect addressing) Bank (100h-1FFh) Bank (00h-FFh) RP1:RP0: Register Bank Select bits (used direct addressing) Bank (180h-1FFh) Bank (100h-17Fh) Bank (80h-FFh) Bank (00h-7Fh) Each bank bytes. Time-out After power-up, CLRWDT instruction SLEEP instruction time-out occurred Power-Down After power-up CLRWDT instruction execution SLEEP instruction Zero result arithmetic logic operation zero result arithmetic logic operation zero Digit Carry/borrow (ADDWF, ADDLW, SUBLW, SUBWF instructions) carry-out from low-order result occurred carry-out from low-order result Carry/borrow (ADDWF, ADDLW, SUBLW, SUBWF instructions) carry-out from Most Significant result occurred carry-out from Most Significant result occurred Note: borrow, polarity reversed. subtraction executed adding two's complement second operand. rotate (RRF, RLF) instructions, this loaded with either high low-order source register.
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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2.2.2.2 OPTION_REG Register
Note: OPTION_REG register readable writable register which contains various control bits configure TMR0 prescaler/WDT postscaler (single assignable register also known prescaler), external interrupt, TMR0 weak pull-ups PORTB. achieve prescaler assignment TMR0 register, assign prescaler Watchdog Timer.
REGISTER 2-2:
OPTION_REG: OPTION CONTROL REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 R/W-1 R/W-1 R/W-1
RBPU: PORTB Pull-up Enable PORTB pull-ups disabled PORTB pull-ups enabled individual port latch values INTEDG: Interrupt Edge Select Interrupt rising edge RB0/INT Interrupt falling edge RB0/INT T0CS: TMR0 Clock Source Select Transition RA4/T0CKI Internal instruction cycle clock (CLKO) T0SE: TMR0 Source Edge Select Increment high-to-low transition RA4/T0CKI Increment low-to-high transition RA4/T0CKI PSA: Prescaler Assignment Prescaler assigned Prescaler assigned Timer0 module PS2:PS0: Prescaler Rate Select bits Value Legend: Readable Value Writable Unimplemented bit, read cleared unknown TMR0 Rate Rate
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2.2.2.3 INTCON Register
Note: INTCON register readable writable register which contains various enable flag bits TMR0 register overflow, port change external RB0/INT interrupts. Interrupt flag bits when interrupt condition occurs regardless state corresponding enable Global Interrupt Enable bit, (INTCON<7>). User software should ensure appropriate interrupt flag bits clear prior enabling interrupt.
REGISTER 2-3:
INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 PEIE R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF
GIE: Global Interrupt Enable Enables unmasked interrupts Disables interrupts PEIE: Peripheral Interrupt Enable Enables unmasked peripheral interrupts Disables peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable Enables TMR0 interrupt Disables TMR0 interrupt INT0IE: RB0/INT External Interrupt Enable Enables RB0/INT external interrupt Disables RB0/INT external interrupt RBIE: Port Change Interrupt Enable Enables port change interrupt Disables port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag TMR0 register overflowed (must cleared software) TMR0 register overflow INT0IF: RB0/INT External Interrupt Flag RB0/INT external interrupt occurred (must cleared software) RB0/INT external interrupt occur RBIF: Port Change Interrupt Flag mismatch condition will continue flag RBIF. Reading PORTB will mismatch condition allow flag RBIF cleared. least RB7:RB4 pins changed state (must cleared software) None RB7:RB4 pins have changed state Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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2.2.2.4 PIE1 Register
Note: PIE1 register contains individual enable bits peripheral interrupts. PEIE (INTCON<6>) must enable peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER (ADDRESS 8Ch)
R/W-0 PSPIE(1) R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) Enables read/write interrupt Disables read/write interrupt Note PSPIE reserved 28-pin devices; always maintain this clear.
ADIE: Converter Interrupt Enable Enables converter interrupt Disables converter interrupt RCIE: AUSART Receive Interrupt Enable Enables AUSART receive interrupt Disables AUSART receive interrupt TXIE: AUSART Transmit Interrupt Enable Enables AUSART transmit interrupt Disables AUSART transmit interrupt SSPIE: Synchronous Serial Port Interrupt Enable Enables interrupt Disables interrupt CCP1IE: CCP1 Interrupt Enable Enables CCP1 interrupt Disables CCP1 interrupt TMR2IE: TMR2 Match Interrupt Enable Enables TMR2 match interrupt Disables TMR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable Enables TMR1 overflow interrupt Disables TMR1 overflow interrupt Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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2.2.2.5 PIR1 Register
PIR1 register contains individual flag bits peripheral interrupts. Note: Interrupt flag bits when interrupt condition occurs regardless state corresponding enable Global Interrupt Enable bit, (INTCON<7>). User software should ensure appropriate interrupt bits clear prior enabling interrupt.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER (ADDRESS 0Ch)
R/W-0 PSPIF(1) R/W-0 ADIF RCIF TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) read write operation taken place (must cleared software) read write occurred Note: PSPIF reserved 28-pin devices; always maintain this clear. ADIF: Converter Interrupt Flag conversion completed (must cleared software) conversion complete RCIF: AUSART Receive Interrupt Flag AUSART receive buffer full AUSART receive buffer empty TXIF: AUSART Transmit Interrupt Flag AUSART transmit buffer empty AUSART transmit buffer full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag interrupt condition occurred must cleared software before returning from Interrupt Service Routine. conditions that will this are: SPI: transmission/reception taken place. Slave: transmission/reception taken place. Master: transmission/reception taken place. initiated Start condition completed module. initiated Stop condition completed module. initiated Restart condition completed module.The initiated Acknowledge condition completed module. Start condition occurred while module Idle (multi-master system). Stop condition occurred while module Idle (multi-master system). interrupt condition occurred CCP1IF: CCP1 Interrupt Flag Capture mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode: Unused this mode. TMR2IF: TMR2 Match Interrupt Flag TMR2 match occurred (must cleared software) TMR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag TMR1 register overflowed (must cleared software) TMR1 register overflow Legend: Readable Value
Writable
Unimplemented bit, read cleared unknown
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2.2.2.6 PIE2 Register
PIE2 register contains individual enable bits CCP2 CCP3 peripheral interrupts.
REGISTER 2-6:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER (ADDRESS 8Dh)
R/W-0 OSFIE R/W-0 CMIE R/W-0 LVDIE R/W-0 BCLIE R/W-0 CCP3IE R/W-0 CCP2IE
OSFIE: Oscillator Fail Interrupt Enable Enabled Disabled CMIE: Comparator Interrupt Enable Enabled Disabled LVDIE: Low-Voltage Detect Interrupt Enable interrupt enabled interrupt disabled Unimplemented: Read BCLIE: Collision Interrupt Enable Enable collision interrupt when configured Master mode Disable collision interrupt when configured Master mode Unimplemented: Read CCP3IE: CCP3 Interrupt Enable Enables CCP3 interrupt Disables CCP3 interrupt CCP2IE: CCP2 Interrupt Enable Enables CCP2 interrupt Disables CCP2 interrupt Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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2.2.2.7 PIR2 Register
Note: Interrupt flag bits when interrupt condition occurs regardless state corresponding enable Global Interrupt Enable bit, (INTCON<7>). User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. PIR2 register contains flag bits CCP2 interrupt.
REGISTER 2-7:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER (ADDRESS 0Dh)
R/W-0 OSFIF R/W-0 CMIF R/W-0 LVDIF R/W-0 BCLIF R/W-0 CCP3IF R/W-0 CCP2IF
OSFIF: Oscillator Fail Interrupt Flag System oscillator failed, clock input changed INTRC (must cleared software) System clock operating CMIF: Comparator Interrupt Flag Comparator input changed (must cleared software) Comparator input changed LVDIF: Low-Voltage Detect Interrupt Flag supply voltage fallen below specified voltage (must cleared software) supply voltage greater then specified voltage Unimplemented: Read BCLIF: Collision Interrupt Flag collision occurred when configured Master mode collision occurred Unimplemented: Read CCP3IF: CCP3 Interrupt Flag Capture mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode: Unused this mode. CCP2IF: CCP2 Interrupt Flag Capture mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode: Unused. Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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2.2.2.8 PCON Register
Note: Power Control (PCON) register contains flag bits allow differentiation between Power-on Reset (POR), Brown-out Reset (BOR), Watchdog Reset (WDT) external MCLR Reset. unknown POR. must user checked subsequent Resets clear, indicating brown-out occurred. status predictable brown-out circuit disabled clearing BOREN Configuration Word register).
REGISTER 2-8:
PCON: POWER CONTROL/STATUS REGISTER (ADDRESS 8Eh)
R/W-1 SBOREN R/W-0 R/W-1
Unimplemented: Read SBOREN: Software Brown-out Reset Enable BORSEN Configuration Word BOREN Configuration Word `0': enabled disabled POR: Power-on Reset Status Power-on Reset occurred Power-on Reset occurred (must software after Power-on Reset occurs) BOR: Brown-out Reset Status Brown-out Reset occurred Brown-out Reset occurred (must software after Brown-out Reset occurs) Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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PCLATH
Program Counter (PC) bits wide. byte comes from register which readable writable register. upper bits (PC<12:8>) readable indirectly writable through PCLATH register. Reset, upper bits will cleared. Figure shows situations loading upper example figure shows loaded write (PCLATH<4:0> PCH). lower example figure shows loaded during CALL GOTO instruction (PCLATH<4:3> PCH). stack operates circular buffer. This means that after stack been PUSHed eight times, ninth push overwrites value that stored from first push. tenth push overwrites second push (and on). Note There Status bits indicate stack overflow stack underflow conditions. There instructions/mnemonics called PUSH POP. These actions that occur from execution CALL, RETURN, RETLW RETFIE instructions vectoring interrupt address.
FIGURE 2-4:
LOADING DIFFERENT SITUATIONS
Instruction with Destination
Program Memory Paging
PCLATH<4:0>
PCLATH PCLATH<4:3> Opcode <10:0> PCLATH GOTO,CALL
PIC16F7X7 devices capable addressing continuous word block program memory. CALL GOTO instructions provide only bits address allow branching within program memory page. When doing CALL GOTO instruction, upper bits address provided PCLATH<4:3>. When doing CALL GOTO instruction, user must ensure that page select bits programmed that desired program memory page addressed. return from CALL instruction interrupt) executed, entire 13-bit POPed stack. Therefore, manipulation PCLATH<4:3> bits required RETURN instructions (which POPs address from stack). Note: contents PCLATH unchanged after RETURN RETFIE instruction executed. user must PCLATH subsequent CALLs GOTOs.
2.3.1
COMPUTED GOTO
computed GOTO accomplished adding offset program counter (ADDWF PCL). When doing table read using computed GOTO method, care should exercised table location crosses memory boundary (each 256-byte block). Refer Application Note, AN556 "Implementing Table Read" (DS00556).
Example shows calling subroutine page program memory. This example assumes that PCLATH saved restored Interrupt Service Routine interrupts used).
EXAMPLE 2-1:
CALL SUBROUTINE PAGE FROM PAGE
2.3.2
STACK
PIC16F7X7 family 8-level deep 13-bit wide hardware stack. stack space part either program data space stack pointer readable writable. PUSHed onto stack when CALL instruction executed interrupt causes branch. stack POPed event RETURN, RETLW RETFIE instruction execution. PCLATH affected PUSH operation.
0x500 PCLATH, PCLATH, ;Select page ;(800h-FFFh) CALL SUB1_P1 ;Call subroutine ;page (800h-FFFh) 0x900 ;page (800h-FFFh) SUB1_P1 RETURN ;called subroutine ;page (800h-FFFh) ;return Call ;subroutine page ;(000h-7FFh)
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Indirect Addressing, INDF Registers
EXAMPLE 2-2:
MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE
INDIRECT ADDRESSING
0x20 ;initialize pointer INDF ;clear INDF register FSR, ;inc pointer FSR, ;all done? NEXT clear next ;yes continue
INDF register physical register. Addressing INDF register will cause indirect addressing. Indirect addressing possible using INDF register. instruction using INDF register actually accesses register pointed File Select Register, FSR. Reading INDF register itself indirectly (FSR will read 00h. Writing INDF register indirectly results operation (although Status bits affected). effective 9-bit address obtained concatenating 8-bit register (Status<7>) shown Figure 2-5. simple program clear locations 20h-2Fh using indirect addressing shown Example 2-2.
FIGURE 2-5:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing Register
RP1:RP0
From Opcode
Bank Select
Location Select 100h 180h
Bank Select
Location Select
Data Memory(1)
Bank Note
Bank
17Fh Bank
1FFh Bank
register file detail, Figure 2-2.
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PIC16F7X7
READING PROGRAM MEMORY
Flash program memory readable during normal operation over entire range. indirectly addressed through Special Function Registers (SFR). 14-bit numbers stored memory calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing program memory location containing data that forms invalid instruction results NOP. There five SFRs used read program memory. These registers are: PMCON1 PMDATA PMDATH PMADR PMADRH When interfacing program memory block, PMDATH:PMDATA registers form two-byte word which holds 14-bit data reads. PMADRH:PMADR registers form two-byte word which holds 13-bit address Flash location being accessed. These devices have words program Flash, with address range from 3FFFh. unused upper bits both PMDATH PMADRH registers implemented read `0's.
PMADR
address registers address maximum words program Flash. When selecting program address value, address written PMADRH register written PMADR register. upper Most Significant bits PMADRH must always clear.
program memory allows word reads. Program memory access allows checksum calculation reading calibration tables.
PMCON1 Register
PMCON1 control register memory accesses. control bit, initiates read operations. This cannot cleared, only set, software. cleared hardware completion read operation.
REGISTER 3-1: PMCON1: PROGRAM MEMORY CONTROL REGISTER (ADDRESS 18Ch)
reserved Reserved: Read Unimplemented: Read Read Control Initiates Flash read, cleared hardware. only (not cleared) software. Flash read completed Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/S-0
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Reading Flash Program Memory Operation During Code-Protect
Flash program memory code-protect mechanism. External read write operations programmers disabled this mechanism enabled. microcontroller read execute instructions internal Flash program memory, regardless state code-protect configuration bits.
program memory location read writing bytes address PMADR PMADRH registers then setting control bit, (PMCON1<0>). Once read control set, microcontroller will next instruction cycles read data. data available PMDATA PMDATH registers after second instruction; therefore, read bytes following instructions. PMDATA PMDATH registers will hold this value until next read operation.
EXAMPLE 3-1:
MOVF MOVWF MOVF MOVWF Required Sequence MOVF MOVF
FLASH PROGRAM READ
STATUS, STATUS, ADDRH, PMADRH ADDRL, PMADR STATUS, PMCON1, Bank MSByte Program Address read LSByte Program Address read Bank Required
EEPROM Read Sequence memory read next cycles after PMCON1,RD Bank LSByte Program PMDATA MSByte Program PMDATH
STATUS, PMDATA, PMDATH,
TABLE 3-1:
Address 10Dh 10Fh 10Ch 10Eh 18Ch Legend: Note
REGISTERS ASSOCIATED WITH PROGRAM FLASH
Value POR, Value other Resets
Name PMADR PMADRH PMDATH
EEPROM Address Register Byte
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx uuuu
EEPROM Address Register High Byte xxxx uuuu
PMDATA EEPROM Data Register Byte EEPROM Data Register High Byte PMCON1 reserved(1)
unknown, unchanged, unimplemented, read `0'. Shaded cells used during Flash access. This always reads `1'.
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PIC16F7X7
OSCILLATOR CONFIGURATIONS
Oscillator Types
TABLE 4-1:
CAPACITOR SELECTION CRYSTAL OSCILLATOR (FOR DESIGN GUIDANCE ONLY)
Crystal Freq Typical Capacitor Values Tested:
PIC16F7X7 operated eight different oscillator modes. user program three configuration bits (FOSC2:FOSC0) select these eight modes (modes PIC16 oscillator configurations): Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator External Resistor/Capacitor with FOSC/4 output RCIO External Resistor/Capacitor with INTIO1 Internal Oscillator with FOSC/4 output INTIO2 Internal Oscillator with ECIO External Clock with
Type
Capacitor values design guidance only. These capacitors were tested with crystals listed below basic start-up operation. These values were optimized. Different capacitor values required produce acceptable oscillator operation. user should test performance oscillator over expected temperature range application. notes following this table additional information. Note Higher capacitance increases stability oscillator also increases start-up time. Since each crystal characteristics, user should consult crystal manufacturer appropriate values external components. required mode, well mode, avoid overdriving crystals with drive level specification. Always verify oscillator performance over temperature range that expected application.
Crystal Oscillator/Ceramic Resonators
modes, crystal ceramic resonator connected OSC1/CLKI OSC2/CLKO pins establish oscillation (see Figure Figure 4-2). PIC16F7X7 oscillator design requires parallel crystal. series crystal give frequency crystal manufacturer's specifications.
FIGURE 4-1:
CRYSTAL OPERATION (HS, CONFIGURATION)
OSC1
PIC16F7X7
C1(1) XTAL OSC2 C2(1) RS(2) Internal Logic RF(3) Sleep
Note Table typical values series resistor (RS) required strip crystals. varies with crystal chosen (typically between
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PIC16F7X7
FIGURE 4-2: CERAMIC RESONATOR OPERATION CONFIGURATION)
OSC1 C1(1) OSC2 C2(1) RS(2) Internal Logic RF(3) Sleep
External Clock Input
PIC16F7X7
ECIO Oscillator mode requires external clock source connected OSC1 pin. There oscillator start-up time required after Power-on Reset after exit from Sleep mode. ECIO Oscillator mode, OSC2 becomes additional general purpose pin. becomes PORTA (RA6). Figure shows connections ECIO Oscillator mode.
FIGURE 4-3:
Note Table typical values series resistor (RS) required. varies with resonator chosen (typically between Clock from Ext. System
EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)
OSC1/CLKI PIC16F7X7 (OSC2)
TABLE 4-2:
CERAMIC RESONATORS (FOR DESIGN GUIDANCE ONLY)
Typical Capacitor Values Used: Mode Freq 16.0 OSC1 OSC2
Capacitor values design guidance only. These capacitors were tested with resonators listed below basic start-up operation. These values were optimized. Different capacitor values required produce acceptable oscillator operation. user should test performance oscillator over expected temperature range application. notes following this table additional information.
Note:
When using resonators with frequencies above MHz, mode rather than mode recommended. mode used which controller rated. selected, possible that gain oscillator will overdrive resonator. Therefore, series resistor should placed between OSC2 resonator. good starting point, recommended value 330.
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PIC16F7X7
Oscillator Internal Oscillator Block
timing insensitive applications, "RC" "RCIO" device options offer additional cost savings. oscillator frequency function supply voltage, resistor (REXT) capacitor (CEXT) values operating temperature. addition this, oscillator frequency will vary from unit unit normal manufacturing variation. Furthermore, difference lead frame capacitance between package types will also affect oscillation frequency, especially CEXT values. user also needs take into account variation tolerance external components used. Figure shows combination connected. Oscillator mode, oscillator frequency divided available OSC2 pin. This signal used test purposes synchronize other logic. PIC16F7X7 devices include internal oscillator block which generates different clock signals; either used system's clock source. This eliminate need external oscillator circuits OSC1 and/or OSC2 pins. main output (INTOSC) clock source which used directly drive system clock. also drives INTOSC postscaler which provide range clock frequencies, from MHz. other clock source internal oscillator (INTRC) which provides 31.25 nominal period) output. INTRC oscillator enabled selecting INTRC system clock source when following enabled: Power-up Timer Watchdog Timer Two-Speed Start-up Fail-Safe Clock Monitor
FIGURE 4-4:
REXT
OSCILLATOR MODE
OSC1 CEXT FOSC/4 OSC2/CLKO
Internal Clock
These features discussed greater detail Section 15.0 "Special Features CPU". clock source frequency (INTOSC direct, INTRC direct INTOSC postscaler) selected configuring IRCF bits OSCCON register (page 38). Note: Throughout this data sheet, when referring specifically generic clock source, term "INTRC" also used refer clock modes using internal oscillator block. This regardless whether actual frequency used INTOSC MHz), INTOSC postscaler INTRC (31.25 kHz).
PIC16F7X7
Recommended values: REXT CEXT
RCIO Oscillator mode (Figure 4-5) functions like mode, except that OSC2 becomes additional general purpose pin. becomes PORTA (RA6).
FIGURE 4-5:
REXT
RCIO OSCILLATOR MODE
OSC1 CEXT (OSC2)
Internal Clock
PIC16F7X7
Recommended values: REXT CEXT
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4.5.1 INTRC MODES 4.5.2 OSCTUNE REGISTER
Using internal oscillator clock source eliminate need external oscillator pins, after which used digital I/O. distinct configurations available: INTIO1 mode, OSC2 outputs FOSC/4, while OSC1 functions digital input output. INTIO2 mode, OSC1 functions OSC2 functions RA6, both digital input output. internal oscillator's output been calibrated factory adjusted application. This done writing OSCTUNE register (Register 4-1). tuning sensitivity constant throughout tuning range. OSCTUNE register tuning range ±12.5%. When OSCTUNE register modified, INTOSC INTRC frequencies will begin shifting frequency. INTRC clock will reach frequency within clock cycles (approximately µs); INTOSC clock will stabilize within Code execution continues during this shift. There indication that shift occurred. Operation features that depend 31.25 INTRC clock source frequency, such WDT, Fail-Safe Clock Monitor peripherals, will also affected change frequency.
REGISTER 4-1:
OSCTUNE: OSCILLATOR TUNING REGISTER (ADDRESS 90h)
R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0
Unimplemented: Read TUN<5:0>: Frequency Tuning bits 011111 Maximum frequency 011110 000001 000000 Center frequency. Oscillator module running calibrated frequency. 111111 100000 Minimum frequency Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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PIC16F7X7
Clock Sources Oscillator Switching
main oscillator that selected FOSC2:FOSC0 configuration bits Configuration Register When bits other manner, system clock source provided Timer1 oscillator (SCS1:SCS0 from internal oscillator block (SCS1:SCS0 10). After Reset, SCS<1:0> always `00'. internal oscillator select bits, IRCF2:IRCF0, select frequency output internal oscillator block that used drive system clock. choices INTRC source (31.25 kHz), INTOSC source MHz) frequencies derived from INTOSC postscaler (125 MHz). Changing configuration these bits immediate change multiplexor's frequency output. OSTS IOFS bits indicate status primary oscillator INTOSC source; these bits when their respective oscillators stable. particular, OSTS indicates that Oscillator Start-up Timer timed out.
PIC16F7X7 devices include feature that allows system clock source switched from main oscillator alternate low-frequency clock source. PIC16F7X7 devices offer three alternate clock sources. When enabled, these give additional options switching various power-managed operating modes. Essentially, there three clock sources these devices: Primary oscillators Secondary oscillators Internal oscillator block (INTRC) primary oscillators include External Crystal Resonator modes, External modes, External Clock mode internal oscillator block. particular mode defined contents Configuration Word details these modes covered earlier this chapter. secondary oscillators those external sources connected OSC1 OSC2 pins. These sources continue operate even after controller placed power-managed mode. PIC16F7X7 devices offer Timer1 oscillator secondary oscillator. This oscillator continues when SLEEP instruction executed often time base functions, such real-time clock. Most often, 32.768 watch crystal connected between RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 pins. Like mode oscillator circuit, loading capacitors also connected from each ground. Timer1 oscillator discussed greater detail Section "Timer1 Oscillator". addition being primary clock source, internal oscillator block available power-managed mode clock source. 31.25 INTRC source also used clock source several special features, such WDT, Fail-Safe Clock Monitor, Power-up Timer Two-Speed Start-up. clock sources PIC16F7X7 devices shown Figure 4-6. Section "Timer1 Module" further details Timer1 oscillator. Section 15.1 "Configuration Bits" Configuration register details.
4.6.2
CLOCK SWITCHING
Clock switching will occur following reasons: FCMEN (CONFIG2<0>) set, device running from primary oscillator primary oscillator fails. clock source will internal oscillator. FCMEN set, device running from Timer1 oscillator (T1OSC) T1OSC fails. clock source will internal oscillator. Following wake-up Reset POR, when device configured Two-Speed Start-up mode, switching will occur between INTRC system clock defined FOSC<2:0> bits. wake-up from Sleep occurs interrupt wake-up Two-Speed Start-up enabled. primary clock clock will switch between INTRC primary system clock after 1024 clocks clocks primary oscillator. This conditional upon bits being equal `00'. bits modified from their original value. IRCF bits modified from their original value. Note: Because bits cleared Reset, clock switching will occur Reset unless Two-Speed Start-up enabled primary clock device will wait primary clock become stable before execution begins (Two-Speed Start-up disabled).
4.6.1
OSCCON REGISTER
OSCCON register (Register 4-2) controls several aspects system clock's operation, both full power operation power-managed modes. system clock select bits, SCS1:SCS0, select clock source that used when device operating power-managed modes. When bits cleared (SCS<1:0> 00), system clock source comes from
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PIC16F7X7
4.6.3 CLOCK TRANSITION
When clock switching performed, Watchdog Timer disabled because Watchdog Ripple Counter used Oscillator Start-up Timer (OST). Note: only used when switching Oscillator modes. Once clock transition complete (i.e., oscillator selection switch occurred), Watchdog Counter re-enabled with Counter Reset. This allows user synchronize Watchdog Timer start execution clock frequency.
REGISTER 4-2:
OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh)
R/W-0 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 OSTS
IOFS
R/W-0 SCS1
R/W-0 SCS0
Unimplemented: Read IRCF<2:0>: Internal Oscillator Frequency Select bits 31.25 OSTS: Oscillator Start-up Time-out Status bit(1) Device running from primary system clock Device running from Timer1 oscillator (T1OSC) INTRC secondary system clock Note resets with Two-Speed Start-up selected oscillator mode.
IOFS: INTOSC Frequency Stable Frequency stable Frequency stable SCS<1:0>: Oscillator Mode Select bits Oscillator mode defined FOSC<2:0> T1OSC used system clock Internal used system clock Reserved Legend: Readable Value Writable Unimplemented bit, read cleared unknown
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PIC16F7X7
FIGURE 4-6: PIC16F7X7 CLOCK DIAGRAM
Primary Oscillator OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator Timer1 OSCCON<6:4> Internal Oscillator Block (INTOSC) Postscaler 31.25 WDT, FSCM Internal Oscillator T1OSC Peripherals CONFIG1 (FOSC2:FOSC0) SCS<1:0> (T1OSC)
T1OSI
31.25 Source
31.25 (INTRC)
4.6.4
MODIFYING IRCF BITS
IRCF bits modified time regardless which clock source currently being used system clock. internal oscillator allows users change frequency during time. This achieved modifying IRCF bits OSCCON register. sequence events that occur after IRCF bits modified dependent upon initial value IRCF bits before they modified. INTRC (31.25 kHz, IRCF<2:0> 000) running IRCF bits modified other value than `000', (approx.) clock switch delay turned Code execution continues higher than expected frequency while frequency stabilizes. Time sensitive code should wait IOFS OSCCON register become before continuing. This monitored ensure that frequency stable before using system clock time critical applications.
IRCF bits modified while internal oscillator running other frequency than INTRC (31.25 kHz, IRCF<2:0> 000), there need (approx.) clock switch delay. INTOSC frequency will stable immediately after eight falling edges. IOFS will remain after clock switching occurs. Note: Caution must taken when modifying IRCF bits using instructions. possible modify IRCF bits frequency that specification range; example: 2.0V IRCF MHz).
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4.6.5 CLOCK TRANSITION SEQUENCE
following three different sequences switching internal oscillator frequency: Clock before switch: 31.25 (IRCF<2:0> 000) IRCF bits modified INTOSC/INTOSC postscaler frequency. clock switching circuitry waits falling edge current clock, which point CLKO held low. clock switching circuitry then waits eight falling edges requested clock, after which switches CLKO this clock source. IOFS clear indicate that clock unstable (approx.) delay started. Time dependent code should wait IOFS become set. Switchover complete. Clock before switch: INTOSC/INTOSC postscaler (IRCF<2:0> 000) IRCF bits modified INTRC (IRCF<2:0> 000). clock switching circuitry waits falling edge current clock, which point CLKO held low. clock switching circuitry then waits eight falling edges requested clock, after which switches CLKO this clock source. Oscillator switchover complete. Clock before switch: INTOSC/INTOSC postscaler (IRCF<2:0> 000) IRCF bits modified different INTOSC/ INTOSC postscaler frequency. clock switching circuitry waits falling edge current clock, which point CLKO held low. clock switching circuitry then waits eight falling edges requested clock, after which switches CLKO this clock source. IOFS set. Oscillator switchover complete.
4.6.6
OSCILLATOR DELAY UPON POWER-UP, WAKE-UP CLOCK SWITCHING
Table shows different delays invoked various clock switching sequences. also shows delays invoked wake-up.
TABLE 4-3:
OSCILLATOR DELAY EXAMPLES
Frequency Oscillator Delay Start-up(1) (approx.) Start-up(1) Following wake-up from Sleep mode POR, start-up invoked allow become ready code execution. Comments
Clock Switch From INTRC T1OSC INTOSC/INTOSC Postscaler 31.25 32.768 kHz-8 32.768 kHz-20 kHz-8 1024 Clock Cycles (approx.) Following change from INTRC, count 1024 cycles must occur. Refer Section 4.6.4 "Modifying IRCF Bits" further details.
Sleep/POR
INTRC/ Sleep INTRC (31.25 kHz) Sleep
INTRC INTOSC/INTOSC (31.25 kHz) Postscaler Note
µs-10 start-up delay based system clock.
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PIC16F7X7
4.7.1
Power-Managed Modes
RC_RUN MODE
When bits configured from INTRC, clock transition generated system clock already using INTRC. event will clear OSTS switch system clock from primary system clock SCS<1:0> determined value contained configuration bits, from T1OSC SCS<1:0> INTRC clock option shut-down primary system clock conserve power. Clock switching will occur primary system clock already configured INTRC.
system clock does come from INTRC (31.25 kHz) when bits changed IRCF bits OSCCON register configured frequency other than INTRC, frequency stable immediately. IOFS (OSCCON<2>) will when INTOSC postscaler frequency stable, after (approx.). After clock switch been executed, OSTS cleared, indicating low-power mode device does from primary system clock. internal clocks held state until eight falling edge clocks counted INTRC oscillator. After eight clock periods have transpired, clock input clocks released operation resumes (see Figure 4-7).
FIGURE 4-7:
TIMING DIAGRAM EXTRC RC_RUN MODE
TINP(1) TSCS(3)
INTOSC OSC1 System Clock TOSC(2)
TDLY(4) SCS<1:0> Program Counter Note TINP typical. TOSC minimum. TSCS TINP. TDLY TINP.
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4.7.2 SEC_RUN MODE
Note T1OSCEN must enabled user's responsibility ensure T1OSC stable before clock switching T1OSC input clock occur. When T1OSCEN following possible effects result. Original Modified SCS<1:0> SCS<1:0> Final SCS<1:0> change INTRC change Oscillator defined FOSC<2:0> core peripherals configured clocked T1OSC using 32.768 crystal. crystal must connected T1OSO T1OSI pins. This same configuration low-power timer circuit (see Section "Timer1 Oscillator"). When bits configured from T1OSC, clock transition generated. will clear OSTS bit, switch system clock from either primary system clock INTRC, depending value SCS<1:0> FOSC<2:0>, external low-power Timer1 oscillator input (T1OSC) shut-down primary system clock conserve power. After clock switch been executed, internal clocks held state until eight falling edge clocks counted T1OSC. After eight clock periods have transpired, clock input clocks released operation resumes (see Figure 4-8). addition, T1RUN T1CON) indicate that T1OSC being used system clock.
clock switching event will occur final state bits different from original.
FIGURE 4-8:
TIMING DIAGRAM SWITCHING SEC_RUN MODE
TT1P(1) TSCS(3)
T1OSI OSC1 System Clock TOSC(2)
TDLY(4) SCS<1:0> Program Counter Note TT1P 30.52 TOSC minimum. TSCS TT1P TDLY TT1P.
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PIC16F7X7
4.7.3 SEC_RUN/RC_RUN PRIMARY CLOCK SOURCE 4.7.3.1 Returning Primary Clock Source Sequence
When switching from SEC_RUN RC_RUN mode back primary system clock, following change SCS<1:0> `00', sequence events that take place will depend upon value FOSC bits Configuration register. primary clock source configured crystal (HS, LP), then transition will take place after 1024 clock cycles. This necessary because crystal oscillator been powered down until time transition. order provide system with reliable clock when changeover occurred, clock will released changeover circuit until 1024 counts have expired. During oscillator start-up time, system clock comes from current system clock. Instruction execution and/or peripheral operation continues using currently selected oscillator clock source, until necessary clock count expired, ensure that primary system clock stable. know when expired, OSTS should monitored. OSTS indicates that Oscillator Start-up Timer timed system clock comes from primary clock source. Following oscillator start-up time, internal clocks held state until eight falling edge clocks counted from primary system clock. clock input clocks then released operation resumes with primary system clock determined FOSC bits (see Figure 4-10). When SEC_RUN mode, clearing T1OSCEN T1CON register will cause SCS<0> cleared, which causes SCS<1:0> bits revert `00' `10' depending what SCS<1> Although T1OSCEN cleared, T1OSC will enabled instruction execution will continue until time-out main system clock complete. that time, system clock will switch from T1OSC primary clock INTRC. Following this, Timer1 oscillator will shut-down. Note: primary system clock either internal delay timer (5-10 will suspend operation after exiting Secondary Clock mode allow become ready code execution. Changing back primary oscillator from SEC_RUN RC_RUN accomplished either changing SCS<1:0> `00' clearing T1OSCEN T1CON register T1OSC secondary clock). sequence events that follows same both modes: primary system clock configured INTRC, then time-out skipped. Skip step primary system clock configured external oscillator (HS, LP), then will active, waiting 1024 clocks primary system clock. following device holds system clock device stays while eight falling edges primary system clock counted. Once eight counts transpire, device begins from primary oscillator. secondary clock INTRC primary clock INTRC, INTRC will shut-down save current, providing that INTRC being used other function, such Fail-Safe Clock Monitoring. secondary clock T1OSC, T1OSC will continue T1OSCEN still set; otherwise, Timer1 oscillator will shut-down.
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PIC16F7X7
FIGURE 4-9: TIMING TRANSITION BETWEEN SEC_RUN/RC_RUN PRIMARY CLOCK
Secondary Oscillator OSC1 TOST(6) OSC2 Primary Clock System Clock TOSC(3) TSCS(4) TT1P(1) TINP(2)
SCS<1:0> OSTS Program Counter Note
TDLY(5)
TT1P 30.52 TINP typical. TOSC minimum. TSCS TINP TT1P. TDLY TINP TT1P. Refer parameter D032 Section 18.0 "Electrical Characteristics".
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PIC16F7X7
4.7.3.2 Returning Primary Oscillator with Reset
Reset will clear SCS<1:0> back `00'. sequence starting primary oscillator following Reset same forms Reset, including POR. There transition sequence from alternate system clock primary system clock Reset condition. Instead, device will reset state OSCCON register default primary system clock. sequence events that take place after this will depend upon value FOSC bits Configuration register. external oscillator configured crystal (HS, LP), will held state until 1024 clock cycles have transpired primary clock. This necessary because crystal oscillator been powered down until time transition. During oscillator start-up time, instruction execution and/or peripheral operation suspended. Note: Two-Speed Clock Start-up mode enabled, INTRC will system clock until Oscillator Start-up Timer timed out. oscillator start-up time required because primary clock already stable; however, there delay between wake-up event following internal delay timer 5-10 will suspend operation after Reset allow become ready code execution. peripheral clock will held first sequence events follows: device Reset asserted from many sources (WDT, BOR, MCLR, etc.). device resets start-up timer enabled Sleep mode. device held Reset until start-up time-out complete. primary system clock configured external oscillator (HS, LP), then will active waiting 1024 clocks primary system clock. While waiting OST, device will held Reset. start-up timers parallel. After both start-up timer Oscillator Start-up Timer have timed out, device will wait additional clock cycle instruction execution will begin.
primary system clock either INTRC, will begin operating first cycle following wake-up event. This means that there
FIGURE 4-10:
T1OSI OSC1
TIMING CLOCK PRIMARY SYSTEM CLOCK AFTER RESET (HS,
TT1P(1)
TOST(4) OSC2 TEPU(3) Start-up System Clock Peripheral Clock Reset Sleep OSTS Program Counter Note TOSC(2)
0000h
0001h
0003h
0004h
0005h
TT1P 30.52 TOSC minimum. TEPU 5-10 Refer parameter D032 Section 18.0 "Electrical Characteristics".
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FIGURE 4-11: TIMING CLOCK PRIMARY SYSTEM CLOCK AFTER RESET (EC, INTRC)
TT1P(1) T1OSI OSC1 OSC2 Start-up System Clock TCPU(2)
MCLR
OSTS Program Counter Note 0000h 0001h 0002h 0003h 0004h
TT1P 30.52 TCPU 5-10
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PIC16F7X7
TABLE 4-4:
Current System Clock
CLOCK SWITCHING MODES
bits<1:0> Modified Delay Clocks INTRC OSTS IOFS T1RUN 1(1) System Clock Comments
T1OSC, (INTRC) FOSC<2:0>
INTRC internal oscillator frequency dependant upon INTOSC IRCF bits. INTOSC Postscaler T1OSC T1OSCEN must enabled.
INTRC, (T1OSC) FOSC<2:0> INTRC T1OSC FOSC<2:0> FOSC<2:0> FOSC<2:0>
Clocks T1OSC
Clocks 1024 Clocks Clocks 1024 Clocks
During 1024 clocks, program execution clocked from secondary oscillator until primary oscillator becomes stable. When Reset occurs, there clock transition sequence. Instruction execution and/or peripheral operation suspended unless Two-Speed Start-up mode enabled, after which INTRC will system clock until Oscillator Start-up Timer expired.
INTRC T1OSC
(Due Reset)
Note
clock source INTOSC INTOSC postscaler, then IOFS will (approx.) after clock change.
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4.7.4 EXITING SLEEP WITH INTERRUPT
SCS<1:0> device held Sleep until start-up time-out complete. After start-up timer timed out, device will exit Sleep begin instruction execution with selected oscillator mode. Note: user changes SCS<1:0> just before entering Sleep mode, system clock used when exiting Sleep mode could different than system clock used when entering Sleep mode. example, SCS<1:0> T1OSC system clock following instructions executed: SLEEP OSCCON,SCS0 interrupt, such INT0, will cause part leave Sleep mode. bits unaffected SLEEP command same before after entering leaving Sleep. clock source used after exit from Sleep determined bits.
4.7.4.1
Sequence Events
SCS<1:0> device held Sleep until start-up time-out complete. primary system clock configured external oscillator (HS, LP), then will active waiting 1024 clocks primary system clock. While waiting OST, device will held Sleep unless Two-Speed Start-up enabled. start-up timers parallel. Refer Section 15.17.3 "Two-Speed Clock Start-up Mode" details Two-Speed Start-up. After both start-up timer Oscillator Start-up Timer have timed out, device will exit Sleep begin instruction execution with primary clock defined FOSC bits.
then clock change event executed. primary oscillator core will continue T1OSC execute SLEEP command. When Sleep exited, part will resume operation with primary oscillator after expired.
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PIC16F7X7
PORTS
Some pins these ports multiplexed with alternate function peripheral features device. general, when peripheral enabled, that used general purpose pin. Additional information ports found "PICmicro® Mid-Range Family Reference Manual" (DS33023). other PORTA pins multiplexed with analog inputs, analog VREF+ VREF- inputs comparator voltage reference output. operation pins RA3:RA0 converter inputs selected clearing/setting control bits ADCON1 register (A/D Control Register Pins through also used comparator inputs outputs setting appropriate bits CMCON register. Note: Power-on Reset, RA3:RA0 configured analog inputs read `0'. configured digital input.
PORTA TRISA Register
PORTA 8-bit wide, bidirectional port. corresponding data direction register TRISA. Setting TRISA will make corresponding PORTA input (i.e., corresponding output driver high-impedance mode). Clearing TRISA will make corresponding PORTA output (i.e., contents output latch selected pin). Reading PORTA register reads status pins, whereas writing will write port latch. multiplexed with Timer0 module clock input comparator outputs become RA4/T0CKI/C1OUT pin. Pins multiplexed with main oscillator pins; they enabled oscillator pins selection main oscillator Configuration Register (see Section 15.1 "Configuration Bits" details). When they used port pins, their associated TRIS bits read `0'.
RA4/T0CKI/C1OUT Schmitt Trigger input open-drain output. other PORTA pins have input levels full CMOS output drivers. TRISA register controls direction pins even when they being used analog inputs. user must ensure bits TRISA register maintained when using them analog inputs.
EXAMPLE 5-1:
CLRF
INITIALIZING PORTA
Bank0 Initialize PORTA clearing output data latches Select Bank Configure pins digital inputs Value used initialize data direction RA<3:0> inputs RA<5:4> outputs TRISA<7:6>are always read '0'.
STATUS, STATUS, PORTA
MOVLW MOVWF MOVLW
STATUS, 0x0F ADCON1 0xCF
MOVWF
TRISA
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
FIGURE 5-1: BLOCK DIAGRAM RA0/AN0:RA1/AN1 PINS FIGURE 5-2: BLOCK DIAGRAM RA3/AN3/VREF+
Data PORTA
Data Analog Input Mode Input Buffer PORTA TRISA PORTA
Analog Input Mode Input Buffer
Data Latch
Data Latch TRISA
TRIS Latch
TRIS Latch
TRISA
TRISA
PORTA
Comparator Module Channel Input
Comparator Module Channel Input Module VREF+ Input
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
FIGURE 5-3:
Data PORTA TRISA
BLOCK DIAGRAM RA2/AN2/VREF-/CVREF
Analog Input Mode RA2/AN2/VREF-/ CVREF Data Latch
TRIS Latch
TRISA PORTA
Input Buffer
Comparator Module VREFTo Module Channel Input CVROE CVREF
FIGURE 5-4:
Data PORTA
BLOCK DIAGRAM RA4/T0CKI/C1OUT
Comparator Mode 011, 101, Comparator Output Data Latch Analog Input Mode Schmitt Trigger Input Buffer TRISA RA4/T0CKI/ C1OUT
TRISA
TRIS Latch
PORTA TMR0 Clock Input
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
FIGURE 5-5:
Data PORTA
BLOCK DIAGRAM RA5/AN4/LVDIN/SS/C2OUT
Comparator Mode 011, Comparator Output
Data Latch TRISA
Analog Input Mode Buffer TRISA TRIS Latch
RA5/AN4/LVDIN/ SS/C2OUT
PORTA
Input LVDIN Module Channel Input
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
FIGURE 5-6: BLOCK DIAGRAM OSC2/CLKO/RA6
(FOSC 1x1) CLKO (FOSC/4) From OSC1 Oscillator Circuit
Data PORTA
OSC2/CLKO
Data Latch (FOSC 1x1) EMUL EMUL FOSC 00x,010 TRISA PORTA (FOSC 1x0,011) EMUL (FOSC 1x0,011)
TRISA
TRIS Latch
Buffer
(FOSC 1x1) EMUL FOSC 00x,
Note CLKO signal FOSC frequency.
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
FIGURE 5-7: BLOCK DIAGRAM OSC1/CLKI/RA7
Oscillator Circuit (FOSC 011) Data PORTA OSC1/CLKI
Data Latch TRISA (FOSC 10x) EMUL (FOSC 10x) TRISA PORTA NEMUL (FOSC 10x)
TRIS Latch
Buffer
(FOSC 10x) EMUL
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
TABLE 5-1:
RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/LVDIN/SS/C2OUT OSC2/CLKO/RA6
PORTA FUNCTIONS
Bit# Buffer Function Input/output analog input. Input/output analog input. Input/output analog input VREF-. Input/output analog input VREF+. Input/output external clock input Timer0. Output open-drain type. Input/output slave select input synchronous serial port analog input. Input/output, connects crystal resonator, oscillator output frequency OSC1 denotes instruction cycle mode.
Name
OSC1/CLKI/RA7
ST/CMOS(1) Input/output, connects crystal resonator oscillator input.
Legend: input, Schmitt Trigger input Note This buffer Schmitt Trigger input when configured Oscillator mode CMOS input otherwise.
TABLE 5-2:
Address Legend: Name PORTA TRISA
SUMMARY REGISTERS ASSOCIATED WITH PORTA
ADFM C2OUT ADCS2 C1OUT PCFG1 CVR1 PCFG0 CVR0 Value POR, xx0x 0000 1111 1111 0000 0000 0000 0111 000- 0000 CVR3 CVR2 Value other Resets uu0u 0000 1111 1111 0000 0000 0000 0111 000- 0000
PORTA Data Direction Register VCFG1 VCFG0 PCFG3 PCFG2 C2INV CVRR C1INV
ADCON1 CMCON CVRCON
CVREN CVROE
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTA.
Note:
When using module Slave mode enabled, converter must following modes, where PCFG2:PCFG0 100, 101, 11x.
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
PORTB TRISB Register
PORTB 8-bit wide, bidirectional port. corresponding data direction register TRISB. Setting TRISB will make corresponding PORTB input (i.e., corresponding output driver high-impedance mode). Clearing TRISB will make corresponding PORTB output (i.e., contents output latch selected pin). Each PORTB pins weak internal pull-up. single control turn pull-ups. This performed clearing RBPU (OPTION_REG<7>). weak pull-up automatically turned when port configured output. pull-ups disabled Power-on Reset. PORTB pins multiplexed with analog inputs. operation each selected clearing/setting appropriate control bits ADCON1 register. Note: Power-on Reset, these pins configured analog inputs read `0'. interrupt-on-change feature recommended wake-up depression operation operations where PORTB only used interrupt-on-change feature. Polling PORTB recommended while using interrupt-on-change feature. This interrupt mismatch feature, together with software configureable pull-ups these four pins, allow easy interface keypad make possible wake-up depression. Refer Application Note AN552 "Implementing Wake-up Stroke" (DS00552). RB0/INT external interrupt input configured using INTEDG (OPTION_REG<6>). RB0/INT discussed detail Section 15.15.1 "INT Interrupt". PORTB multiplexed with several peripheral functions (see Table 5-3). PORTB pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should taken defining TRIS bits each PORTB pin. Some peripherals override TRIS make output, while other peripherals override TRIS make input. Since TRIS override effect while peripheral enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISB destination should avoided. user should refer corresponding peripheral section correct TRIS settings.
Four PORTB pins (RB7:RB4) have interrupton-change feature. Only pins configured inputs cause this interrupt occur (i.e., RB7:RB4 configured output excluded from interrupton-change comparison). input pins RB7:RB4) compared with value latched last read PORTB. "mismatch" outputs RB7:RB4 ORed together generate port change interrupt with flag bit, RBIF (INTCON<0>). This interrupt wake device from Sleep. user, Interrupt Service Routine, clear interrupt following manner: read write PORTB. This will mismatch condition. Clear flag RBIF.
mismatch condition will continue flag RBIF. Reading PORTB will mismatch condition allow flag RBIF cleared.
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
FIGURE 5-8: BLOCK DIAGRAM RB0/INT/AN12
Analog Input Mode RBPU Data PORTB Data Latch TRIS Latch TRISB Analog Input Mode TRISB Input Buffer Weak Pull-up
PORTB
Analog Input Mode Channel Input
PORTB
Note enable weak pull-ups, appropriate TRIS bit(s) clear RBPU bit.
FIGURE 5-9:
BLOCK DIAGRAM RB1/AN10
Analog Input Mode RBPU Data PORTB Data Latch TRIS Latch TRISB Analog Input Mode Input Buffer Weak Pull-up
TRISB
PORTB
PORTB Channel Input Note enable weak pull-ups, appropriate TRIS bit(s) clear RBPU bit.
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
FIGURE 5-10: BLOCK DIAGRAM RB2/AN8
RBPU(1) Data Latch TRIS Latch TRISB Analog Input Mode Input Buffer TRISB Weak Pull-up
Data PORTB
PORTB
PORTB Channel Input Note enable weak pull-ups, appropriate TRIS bit(s) clear RBPU bit.
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
FIGURE 5-11: BLOCK DIAGRAM RB3/CCP2(1)/AN9
Analog Input Mode CCP2 Output Select CCPMX CCP2 Output RBPU(2) Data Latch TRIS Latch TRISB Analog Input Mode Input Buffer Weak Pull-up
Data PORTB
TRISB
PORTB
Channel Input Schmitt Trigger Buffer(3) Module Input Analog Input Mode
PORTB
Note location CCP2 determined CCPMX Configuration Word Register enable weak pull-ups, appropriate TRIS bit(s) clear RBPU bit. Schmitt Trigger conforms I2Cspecification.
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
FIGURE 5-12: BLOCK DIAGRAM RB4/AN11
Analog Input Mode RBPU(1) Weak Pull-up
Data Latch Data PORTB TRIS Latch TRISB
TRISB
Analog Input Mode Input Buffer
Latch PORTB RBIF Analog Input Mode channel input Note enable weak pull-ups, appropriate TRIS bit(s) clear RBPU bit. PORTB
From other RB7:RB4 pins
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
FIGURE 5-13: BLOCK DIAGRAM RB5/AN13/CCP3
Analog Input Mode CCP3 Output Select CCP3 Output RBPU
Weak Pull-up
Data PORTB
Data Latch TRIS Latch
TRISB
Analog Input Mode TRISB Input Buffer
Latch PORTB RBIF Analog Input Mode Schmitt Trigger Buffer Analog Input Mode PORTB
From other RB7:RB4 pins Module Input Channel Input
Note enable weak pull-ups, appropriate TRIS bit(s) clear RBPU bit.
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
FIGURE 5-14: BLOCK DIAGRAM RB6/PGC
Program Mode/ICD RBPU(1) Data PORTB Data Latch
Weak Pull-up
TRIS Latch
TRISB
TRISB
Input Buffer
Latch RBIF PORTB Program Mode/ICD
From other RB7:RB4 pins Schmitt Trigger Buffer
PORTB
Note enable weak pull-ups, appropriate TRIS bit(s) clear RBPU bit.
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
FIGURE 5-15: BLOCK DIAGRAM RB7/PGD
Port/Program Mode/ICD RBPU(1) Data PORTB Data Latch TRIS Latch TRISB Weak Pull-up
TRISB
Input Buffer
DRVEN
Latch RBIF PORTB Program Mode/ICD
From other RB7:RB4 pins
PORTB
Note enable weak pull-ups, appropriate TRIS bit(s) clear RBPU bit.
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
TABLE 5-3:
Name RB0/INT/AN12 RB1/AN10 RB2/AN8 RB3/CCP2/AN9 RB4/AN11 RB5/AN13/CCP3
PORTB FUNCTIONS
Bit# Buffer TTL/ST
Function Input/output external interrupt input. Internal software programmable weak pull-up analog input. Input/output pin. Internal software programmable weak pull-up analog input. Input/output pin. Internal software programmable weak pull-up analog input. Input/output Capture input/Compare output/PWM output. Internal software programmable weak pull-up analog input. Input/output (with interrupt-on-change). Internal software programmable weak pull-up analog input. Input/output (with interrupt-on-change). Internal software programmable weak pull-up analog input Capture input/ Compare output/PWM output.
RB6/PGC RB7/PGD
TTL/ST(2) Input/output (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. TTL/ST(2) Input/output (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data.
Legend: input, Schmitt Trigger input Note This buffer Schmitt Trigger input when configured external interrupt. This buffer Schmitt Trigger input when used Serial Programming mode.
TABLE 5-4:
Address 06h, 106h 86h, 186h 81h, 181h Legend:
SUMMARY REGISTERS ASSOCIATED WITH PORTB
Name INTEDG ADCS2 T0CS VCFG1 T0SE VCFG0 Value POR, Value other Resets
PORTB TRISB ADCON1
xx00 0000 uu00 0000 1111 1111 1111 1111 1111 1111 1111 1111
PORTB Data Direction Register ADFM
OPTION_REG RBPU
PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
unknown, unchanged. Shaded cells used PORTB.
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
PORTC TRISC Register
FIGURE 5-17:
PORTC 8-bit wide, bidirectional port. corresponding data direction register TRISC. Setting TRISC will make corresponding PORTC input (i.e., corresponding output driver high-impedance mode). Clearing TRISC will make corresponding PORTC output (i.e., contents output latch selected pin). PORTC multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should taken defining TRIS bits each PORTC pin. Some peripherals override TRIS make output, while other peripherals override TRIS make input. Since TRIS override effect while peripheral enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC destination should avoided. user should refer corresponding peripheral section correct TRIS settings Section 16.1 "Read-ModifyWrite Operations" additional information read-modify-write operations.
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<4:3> PINS
Port/Peripheral Select(2) Peripheral Data Data Port
pin(1)
Data Latch TRIS Schmitt Trigger Schmitt Trigger with SMBus Levels
TRIS Latch TRIS Peripheral OE(3) Port SSPl Input
FIGURE 5-16:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<2:0>, RC<7:5> PINS
SSPSTAT<6> Note pins have diode protection VSS. Port/Peripheral Select signal selects between port data peripheral output. Peripheral (Output Enable) only activated Peripheral Select active.
Port/Peripheral Select(2) Peripheral Data Data Port pin(1)
Data Latch TRIS Schmitt Trigger
TRIS Latch TRIS Peripheral OE(3) Port Peripheral Input Note pins have diode protection VSS. Port/Peripheral Select signal selects between port data peripheral output. Peripheral (Output Enable) only activated Peripheral Select active.
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
TABLE 5-5:
Name RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
PORTC FUNCTIONS
Bit# Buffer Type Function Input/output port Timer1 oscillator output/Timer1 clock input. Input/output port Timer1 oscillator input Capture input/ Compare output/PWM output. Input/output port Capture input/Compare output/PWM output. also synchronous serial clock both SPIand I2Cmodes. also data (SPI mode) data (I2C mode). Input/output port Synchronous Serial Port data output. Input/output port AUSART asynchronous transmit synchronous clock. Input/output port AUSART asynchronous receive synchronous data.
Legend: Schmitt Trigger input
TABLE 5-6:
Address
SUMMARY REGISTERS ASSOCIATED WITH PORTC
Value POR, Value other Resets
Name PORTC TRISC
xxxx xxxx uuuu uuuu 1111 1111 1111 1111
PORTC Data Direction Register
Legend: unknown, unchanged
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
PORTD TRISD Registers
FIGURE 5-18:
This section applicable PIC16F737 PIC16F767. PORTD 8-bit port with Schmitt Trigger input buffers. Each individually configureable input output. PORTD configured 8-bit wide microprocessor port (Parallel Slave Port) setting control bit, PSPMODE (TRISE<4>). this mode, input buffers TTL.
PORTD BLOCK DIAGRAM PORT MODE)
pin(1) Data Latch Schmitt Trigger Input Buffer
Data Port
TRIS
TRIS Latch
TRIS Port
Note pins have protection diodes VSS.
TABLE 5-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
PORTD FUNCTIONS
Bit# Buffer Type ST/TTL(1) ST/TTL
Function Input/output port Parallel Slave Port Input/output port Parallel Slave Port Input/output port Parallel Slave Port Input/output port Parallel Slave Port Input/output port Parallel Slave Port Input/output port Parallel Slave Port Input/output port Parallel Slave Port Input/output port Parallel Slave Port
ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL ST/TTL
ST/TTL(1)
Legend: Schmitt Trigger input, input Note Input buffers Schmitt Triggers when mode buffers when Parallel Slave Port mode.
TABLE 5-8:
Address Legend: Note
SUMMARY REGISTERS ASSOCIATED WITH PORTD
IBOV PSPMODE -(1) Value POR, xxxx xxxx 1111 1111 PORTE Data Direction bits 0000 1111 Value other Resets uuuu uuuu 1111 1111 0000 1111
Name PORTD TRISD TRISE
PORTD Data Direction Register
unknown, unchanged, unimplemented, read `0'. Shaded cells used PORTD. input only. state TRISE3 effect will always read `1'.
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
PORTE TRISE Register
FIGURE 5-19:
This section applicable PIC16F737 PIC16F767. PORTE four pins, RE0/RD/AN5, RE1/WR/AN6, RE2/CS/AN7 MCLR/VPP/RE3, which individually configureable inputs outputs. These pins have Schmitt Trigger input buffers. only available input MCLRE Configuration Word PORTE becomes control inputs microprocessor port when bit, PSPMODE (TRISE<4>), set. this mode, user must make sure that TRISE<2:0> bits (pins configured digital inputs). Ensure ADCON1 configured digital I/O. this mode, input buffers TTL. Register shows TRISE register which also controls Parallel Slave Port operation. PORTE pins multiplexed with analog inputs. When selected analog input, these pins will read `0's. TRISE controls direction pins, even when they being used analog inputs. user must make sure keep pins configured inputs when using them analog inputs. Note: Power-on Reset, these pins configured analog inputs read `0'.
Port
PORTE BLOCK DIAGRAM PORT MODE)
pin(1) Data Latch Schmitt Trigger Input Buffer
Data Port
TRIS
TRIS Latch
TRIS
Note pins have protection diodes VSS.
TABLE 5-9:
Name RE0/RD/AN5
PORTE FUNCTIONS
Bit# Buffer Type ST/TTL
Function Input/output port read control input Parallel Slave Port mode analog input. (PSP mode): Idle Read operation. Contents PORTD register output PORTD pins chip selected). Input/output port write control input Parallel Slave Port mode analog input. (PSP mode): Idle Write operation. Value PORTD pins latched into PORTD register chip selected). Input/output port chip select control input Parallel Slave Port mode analog input. (PSP mode): Device selected Device selected Input, Master Clear (Reset) programming input voltage.
RE1/WR/AN6
ST/TTL(1)
RE2/CS/AN7
ST/TTL(1)
MCLR/VPP/RE3 Legend: Note
Schmitt Trigger input, input Input buffers Schmitt Triggers when mode buffers when Parallel Slave Port mode.
TABLE 5-10:
Addr Name PORTE TRISE ADCON1
SUMMARY REGISTERS ASSOCIATED WITH PORTE
ADFM IBOV PSPMODE VCFG0 -(1) PCFG1 PCFG0 Value POR, x000 0000 1111 0000 0000 Value other Resets x000 0000 1111 0000 0000
PORTE Data Direction bits
ADCS2 VCFG1
PCFG3 PCFG2
Legend: Note
unknown, unchanged, unimplemented, read `0'. Shaded cells used PORTE. input only. state TRISE3 effect will always read `1'.
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
REGISTER 5-1: TRISE REGISTER (ADDRESS 89h)
Parallel Slave Port Status/Control bits: IBF: Input Buffer Full Status word been received waiting read word been received OBF: Output Buffer Full Status output buffer still holds previously written word output buffer been read IBOV: Input Buffer Overflow Detect Microprocessor mode) write occurred when previously input word been read (must cleared software) overflow occurred PSPMODE: Parallel Slave Port Mode Select Parallel Slave Port mode General Purpose mode Unimplemented: Read `1'(1) Note input only. state TRISE3 effect will always read `1'. PORTE Data Direction bits: TRISE2: Direction Control RE2/CS/AN7 Input Output TRISE1: Direction Control RE1/WR/AN6 Input Output TRISE0: Direction Control RE0/RD/AN5 Input Output Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 IBOV R/W-0 PSPMODE -(1) R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0
2004 Microchip Technology Inc.
DS30498C-page
PIC16F7X7
Parallel Slave Port
Parallel Slave Port (PSP) implemented PIC16F737 PIC16F767. PORTD operates 8-bit wide Parallel Slave Port microprocessor port when control bit, PSPMODE (TRISE<4>), set. Slave mode, asynchronously readable writable external system using read control input RE0/RD/AN5, write control input RE1/WR/AN6 chip select control input RE2/CS/AN7. directly interface 8-bit microprocessor data bus. external microprocessor read write PORTD latch 8-bit latch. Setting PSPMODE enables port RE0/RD/AN5 input, RE1/WR/AN6 input RE2/CS/AN7 (Chip Select) input. this functionality, corresponding data direction bits TRISE register (TRISE<2:0>) must configured inputs (i.e., set). port configuration bits, PCFG3:PCFG0 (ADCON1<3:0>), must configure pins RE2:RE0 digital I/O. There actually 8-bit latches, data output (external reads) data input (external writes). firmware writes 8-bit data PORTD output data latch reads data from PORTD input data latch (note that they have same address). this mode, TRISD register ignored since external device controlling direction data flow. external write occurs when lines both detected low. Firmware read actual data PORTD pins during this time. When either lines become high (level triggered), data PORTD pins latched Input Buffer Full (IBF) status flag (TRISE<7>) interrupt flag bit, PSPIF (PIR1<7>), clock cycle following next cycle signal write complete (Figure 5-21). Firmware clears flag reading latched PORTD data clears PSPIF bit. Input Buffer Overflow (IBOV) status flag (TRISE<5>) external write occurs while flag from previous external write. previous PORTD data overwritten with data. IBOV cleared reading PORTD clearing IBOV. read from occurs when both lines detected low. data PORTD output latch output PORTD pins. Output Buffer Full (OBF) status flag (TRISE<6>) cleared immediately (Figure 5-22), indicating that PORTD latch being read been read external bus. firmware writes data output latch during this time, immediately output PORTD pins will remain cleared. When either pins detected high, PORTD outputs disabled interrupt flag PSPIF clock cycle following next cycle, indicating that read complete. remains until firmware writes data PORTD. When mode, bits held clear. Flag IBOV remains unchanged. PSPIF must cleared user firmware; interrupt disabled clearing interrupt enable bit, PSPIE (PIE1<7>).
FIGURE 5-20:
PORTD PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
Data Port Port PORTD Interrupt Flag PSPIF (PIR1<7>)
Read
Chip Select Write Note: protection diodes VSS.
DS30498C-page
2004 Microchip Technology Inc.
PIC16F7X7
FIGURE 5-21: PARALLEL SLAVE PORT WRITE WAVEFORMS
PORTD<7:0> PSPIF
FIGURE 5-22:
PARALLEL SLAVE PORT READ WAVEFORMS
PORTD<7:0> PSPIF
TABLE 5-11:
Address Legend: Note Name PORTD PORTE TRISE P
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