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Hot-Swappable Dual I2C Isolators ADuM1250 / ADuM1251

Isolated I2C, SMbus, or PMBus Interfaces Multi-Level I2C Interfaces Power Supplies Networking Power-over-Ethernet

Preliminary Technical Data
FEATURES
Hot-Swappable Dual I2C Isolators ADuM1250 / ADuM1251
GENERAL DESCRIPTION
APPLICATIONS
Isolated I2C, SMbus, or PMBus Interfaces Multi-Level I2C Interfaces Power Supplies Networking Power-over-Ethernet
Protected by U.S. Patents 5, 952, 849 and 6, 873, 065. Other patents pending.
FUNCTIONAL BLOCK DIAGRAMS
VDD1 SDA1 SCL1 GND1
DECODE ENCODE DECODE ENCODE
ENCODE DECODE ENCODE DECODE
VDD2 SDA2 SCL2 GND2
VDD1 SDA1 SCL1 GND1
DECODE ENCODE ENCODE
ENCODE DECODE DECODE
VDD2 SDA2 SCL2 GND2
Figure 1. ADuM1250 Functional Block Diagram.
Figure 2. ADuM1251 Functional Block Diagram.
Rev. PrM,
August 30, 2006 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
ADuM1250 / ADuM1251 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Preliminary Technical Data
Parameter DC SPECIFICATIONS ADuM1250 Input Supply Current, Side 1, 5V Input Input Supply Current, Side 2, 5V Input Input Supply Current, Side 1, 3.3V Input Input Supply Current, Side 2, 3.3V Input ADuM1251 Input Supply Current, Side 1, 5V Input Input Supply Current, Side 2, 5V Input Input Supply Current, Side 1, 3.3V Input Input Supply Current, Side 2, 3.3V Input Leakage Currents Side 1 Logic Levels Logic Low Input Threshold Logic High Input Threshold Logic Low Output Voltages Input / Output Logic Low Level Difference1 Side 2 Logic Levels Logic Low Input Threshold Logic High Input Threshold Logic Low Output Voltages Symbol Min Typ Max Unit Test Conditions
IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 IISDA1, IISDA2, IISCL1, IISCL2 VSDA1IL, VSCL1IL VSDA1IH, VSCL1IH VSDA1OL, VSCL1OL VSDA1, VSCL1 VSDA2IL, VSCL2IL VSDA2IH, VSCL2IH VSDA2OL, VSCL2OL
500 700 600 600 50 0.3VDD2 0.7VDD2 400 900 800
Preliminary Technical Data
ADuM1250 / ADuM1251
Test Conditions
ADuM1250 / ADuM1251
PACKAGE CHARACTERISTICS
Table 2.
Parameter Resistance (Input-Output)1 Capacitance (Input-Output)1 Input Capacitance IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2 Symbol RI-O CI-O CI JCI JCO Min Typ 1012 1.0 4.0 46 41 Max
Preliminary Technical Data
The device is considered a 2-terminal device Pins 1, 2, 3, and 4 are shorted together, and Pins 5, 6, 7, and 8 are shorted together.
REGULATORY INFORMATION (PENDING)
The ADuM1250 / ADuM1251 will be approved by the following organizations upon product release Table 3.
UL (pending) Recognized under 1577 Component Recognition Program1 Basic insulation, 2500 V rms isolation rating CSA (pending) Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (560 V peak) maximum working voltage VDE (pending) Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2):2003-012 Basic insulation, 400 V rms (560 V peak) maximum working voltage
File E214100
File 205078
File 2471900-4880-0001
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Preliminary Technical Data
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 5.
ADuM1250 / ADuM1251
Symbol
Characteristic I-IV I-III I-II 40 / 105 / 21 2 560 1050
VIORM VPR VPR
V peak V peak
896 672 VTR 4000
V peak
TS IS1 IS2 RS
Note that the "" marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage. This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
RECOMMENDED OPERATING CONDITIONS
Table 6.
Parameter Operating Temperature Supply Voltages1 Input / Output Signal Voltage Symbol TA VDD1, VDD2 VSDA1, VSCL1, VSDA2, VSCL2 CL1 CL2 ISDA1, ISCL1 ISDA2, ISCL2 Min -40 3.0 Max +105 5.5 5.5 Unit °C V V
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
Capacitive Load, Side 1 Capacitive Load, Side 2 Static Output Loading, Side 1 Static Output Loading, Side 2
All voltages are relative to their respective ground. See the Application Information section for data on immunity to external magnetic fields.
ADuM1250 / ADuM1251 ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Operating Temperature Supply Voltages1 Input / Output Voltage1, Side 1 Input / Output Voltage1, Side 2 Average Output Current, per Pin2 Common-Mode Transients3 Symbol TST TA VDD1, VDD2 VSDA1, VSCL1 VSDA2, VSCL2 IO Min -55 -40 -0.5 -0.5 -0.5 -100
Preliminary Technical Data
Max 150 105 7.0 VDD1 + 0.5 VDD2 + 0.5 +100
All voltages are relative to their respective ground. See Figure 3 for maximum rated current values for various temperatures. Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1 SDA1 2 SCL1 3 GND1
8 VDD2
ADuM1250 / ADuM1251
7 SDA2 TOP VIEW 6 SCL2 (Not to Scale) 4 5 GND2
ADuM1250
Figure 4. ADuM1250 / ADuM1251 Pin Configuration
Table 8. ADuM1250 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 SDA1 SCL1 GND1 GND2 SCL2 SDA2 VDD2 Function Supply voltage, 3.0 V to 5.5 V. Data Input / Output, Side 1. Clock Input / Output, Side 1. Ground 1. Ground reference for isolator Side 1. Ground 2. Isolated ground reference for isolator Side 2. Clock Input / Output, Side 2. Data Input / Output, Side 2. Supply voltage, 3.0 V to 5.5 V.
Table 9. ADuM1251 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 SDA1 SCL1 GND1 GND2 SCL2 SDA2 VDD2 Function Supply voltage, 3.0 V to 5.5 V. Data Input / Output, Side 1. Clock Input, Side 1. Ground 1. Ground reference for isolator Side 1. Ground 2. Isolated ground reference for isolator Side 2. Clock Output, Side 2. Data Input / Output, Side 2. Supply voltage, 3.0 V to 5.5 V.
ADuM1250 / ADuM1251 TEST CONDITIONS
VDD1 R1 R1 SDA1 SCL1 CL1 CL1
DECODE ENCODE DECODE ENCODE ENCODE DECODE ENCODE DECODE
Preliminary Technical Data
VDD2 SDA2 SCL2 GND2 CL2 CL2 R2 R2
GND1 4
Figure 5. Timing Test Diagram.
Preliminary Technical Data APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The ADuM1250 / ADuM1251 interfaces on each side to a bidirectional I2C signal. Internally, the I2C interface is split into two unidirectional channels communicating in opposing directions via a dedicated iCoupler isolation channel for each. One channel (the bottom one of each channel pair of Figure 6) senses the voltage state of the Side 1 I2C pin and transmits state to its respective Side 2 I2C pin. Both the Side 1 and the Side 2 I2C pins are designed to interface to a I2C bus operating in the 3.0V-to-5.5V range. A logic low on either will cause the opposite pin to be pulled low enough to comply with the logic LOW threshold requirements of other I2C devices on the bus. Avoidance of I2C bus contention is ensured by an input low threshold at SDA1 or SCL2 that is guaranteed to be at least 50 mV less than the output low signal at the same pin. This prevents an output logic LOW at Side 1 from being transmitted back to Side 2 and pulling down the I2C bus. Since the Side 2 logic levels / thresholds are standard I2C values, multiple ADuM1250 / ADuM1251 devices connected to a bus by their Side 2 pins can communicate with each other and with other devices having I2C compatibility1. However, since the Side 1 pin has a modified output level / input threshold, this side of the ADuM1250 / ADuM1251 can only communicate with devices conforming to the I2C standard. In other words, Side 2 of the ADuM1250 / ADuM1251 is I2C-compliant while Side 1 is only I2C-compatible. The output Logic LOW levels are independent of the VDD1 and VDD2 voltages. The input logic low threshold at Side 1 is also independent of VDD1. However, the input logic LOW threshold at Side 2 is design to be at 0.3VDD2 consistent with I2C requirements. The Side 1 and Side 2 pins have open-collector outputs whose HIGH levels are set via pull-up resistors to their respective supply voltages.
VDD1 SDA1 SCL1
DECODE ENCODE DECODE ENCODE ENCODE DECODE ENCODE DECODE
ADuM1250 / ADuM1251
STARTUP
Both the VDD1 and VDD2 supplies have an under voltage lockout feature that prevent the signal channels from operating unless certain criteria are met. This is to avoid the possibility of input logic low signals from pulling down the I2C bus inadvertently during power-up / power-down. The two criteria that must be met in order for the signal channels to be enabled are as follows: · · Both supplies must be at least 2.5V At least 40 s must have elapsed since both supplies exceeded the internal startup threshold of 2.0V
Until both of these criteria are met for both supplies, the ADuM1250 / 1251 outputs are pulled high thereby ensuring a startup that will avoid any disturbances on the bus. Figure 7 and Figure 8 illustrate the supply conditions for fast and slow input supply slew rates.
min. recommended operating supply, 3.0V min. valid supply, 2.5V internal startup threshold, 2.0V
supply valid
min. recommended operating supply, 3.0V min. valid supply, 2.5V supply valid
VDD2 SDA2 SCL2 GND2 CL CL R2 R2
internal startup threshold, 2.0V
GND1 4
Figure 6. ADuM1250 Block Diagram.
ADuM1250 / ADuM1251
Preliminary Technical Data
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
TYPICAL APPLICATION DIAGRAMS
VDD SDA1 SCL1 GND
ADuM1250
V2 SDA2 SCL2 GND2
I2C Bus
Figure 9. Typical Isolated I2C Interface using ADuM1250.
0.001 1k
MAGNETIC FIELD IMMUNITY
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
Figure 10. Maximum Allowable External Magnetic Flux Density
MAXIMUM ALLOWABLE CURRENT (kA)
MAGNETIC FIELD FREQUENCY (Hz)
Figure 11. Maximum Allowable Current for Various Current-to-ADuM1250 Spacings
Note that at combinations of strong magnetic fields and high frequencies, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
Preliminary Technical Data OUTLINE DIMENSIONS
ADuM1250 / ADuM1251
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 12. 8-Lead Standard Small Outline Package SOIC-Narrow Body (R-8) Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model ADuM1250ARZ ADuM1250ARZ-RL7 ADuM1251ARZ ADuM1251ARZ-RL7 Number of Inputs, VDD1 Side 2 2 2 2 Number of Inputs, VDD2 Side 2 2 1 1 Maximum Data Rate (Mbps) 1 1 1 1 Maximum Propagation Delay (ns) 150 150 150 150 Temperature Range (°C) -40 to +105 -40 to +105 -40 to +105 -40 to +105 Package Option1 R-8 R-8 R-8 R-8
PR06113-0-8 / 06(PrM)