Analog Multi-Channel, 12-bit, 1MSPS channels Fully differential single
|
|
|
Top Searches for this datasheet
Precision Analog Microcontroller ARM7TDMI® with 12-bit Preliminary Technical Data
Analog Multi-Channel, 12-bit, 1MSPS channels Fully differential single-ended modes VREF Analog Input Range 10-bit 32-bit 21MHz Current-to-Voltage (I/V) Conversion Integrated order Input 100ohm Line Driver On-Chip Voltage Reference On-Chip Temperature Sensor (±3°C) Uncommitted Voltage Comparator Microcontroller ARM7TDMI Core, 16/32-bit RISC architecture JTAG Port supports code download debug External Watch crystal/ Clock Source 41.78 with Programmable Divider Optional Trimmed On-Chip Oscillator
ADuC7128
Memory 126k Bytes Flash/EE Memory, Bytes SRAM In-Circuit Download, JTAG based Debug Software triggered in-circuit re-programmability On-Chip Peripherals UART, I2C® Serial 28-Pin GPIO Port General Purpose Timers Wake-up Watchdog Timers Power Supply Monitor 16-bit generator Quadrature Encoder Programmable Logic (Array) Power Specified operation Active Mode: 11mA (@5MHz) 45mA (@41.78 MHz) Packages Temperature Range lead LFCSP (9mm 9mm) package -40°C 85°C Tools Low-Cost QuickStart Development System Full Third-Party Support
FUNCTIONAL BLOCK DIAGRAM
DACGND DACVDD IOGND IOGND AGND IOVDD DGND LVDD
ADC0
CMP0 CMP1
XCLKI XCLKO XCLK
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
Figure Basic Block Diagram Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 2006 Analog Devices, Inc. rights reserved.
JTAG
P3.0
P3.3
TEMP SENSOR
12-BIT 1MSPS
10-BIT IOUT
VDAC LD1TX LD2TX
BAND REFERENCE
ADuC7128
PWM1 PWM2 PWM3 KBYTES FLASH/EE (32k bits) 8192 BYTES SRAM bits) Quad Encoder PWM4 PWM5 PWM6 KBYTES KBYTES FLASH/EE (31k bits)
ARM7TDMI BASED WITH ADDITIONAL PERIPHERALS
PURPOSE TIMERS WAKE-UP/ TIMER OSC/PLL INTERRUPT CONTROLLER JTAG
GPIO UART0 UART1 CONTROL
ADuC7128
GENERAL DESCRIPTION
ADuC7128 fully integrated, 1MSPS, 12-bit data acquisition system incorporating high performance multichannel ADC, with line driver, 16/32-bit Flash/EE Memory single chip. consists single-ended inputs. operate single-ended differential input modes. input voltage VREF. drift bandgap reference, temperature sensor voltage comparator complete peripheral set. ADuC7128 also integrates differential line driver output. This line driver transmits sine wave whose values calculated chip voltage output determined DACDAT MMR.
Preliminary Technical Data
device operates from on-chip oscillator generating internal high-frequency clock 41.78 MHz. This clock routed through programmable clock divider from which core clock operating frequency generated. microcontroller core ARM7TDMI, 16/32-bit RISC machine, offering MIPS peak performance. 126k Bytes non-volatile Flash/EE provided on-chip well Bytes SRAM. ARM7TDMI core views memory registers single linear array. On-chip factory firmware supports in-circuit serial download UART JTAG serial interface ports while nonintrusive emulation also supported JTAG interface. These features incorporated into low-cost QuickStart Development System supporting this MicroConverter family. parts operate from 3.0V 3.6V specified over industrial temperature range -40°C 85°C. When operating 41.78 power dissipation 150mW. line driver output enabled consumes additional 30mW.
Rev. Page
Preliminary Technical Data
ADUC7128-SPECIFICATIONS
ADuC7128
Table (AVDD IOVDD VREF Internal Reference, fCORE 41.78MHz, specifications TMAX TMIN, unless otherwise noted.)
Parameter CHANNEL SPECIFICATIONS Powerup Time Accuracy1,2 Resolution Integral Nonlinearity
ADuC7128 ±1.5 ±0.6 ±2.0 +1/-0.9 ±0.5 +0.7/-0.6
Unit
Test Conditions/Comments
Eight acquisition clocks Fadc/2 Bits 10kHz Sine Wave, fSAMPLE 1MSPS
Integral Nonlinearity3 Differential Nonlinearity Differential Nonlinearity3 Code Distribution ENDPOINT ERRORS4 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential mode5 Single-ended mode Leakage Current
2.5V internal reference 2.5V internal reference 1.0V external reference 2.5V internal reference 2.5V internal reference 1.0V external reference input voltage
Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT6 Input Voltage Range
VCM±VREF/2 VREF
Volts Volts ppm/°C
During Acquisition 0.47µF from VREF AGND
0.625 AVDD
Measured 25°C
Input Impedance CHANNEL SPECIFICATIONS VDAC Output Voltage Swing output resistance Pass Filter point
0.33*VREF 0.2*VREF
Resolution
Bits
100pF VREF internal 2.5V reference mode selected
2-pole.
Rev. Page
ADuC7128
Parameter Relative Accuracy Differential Nonlinearity, +'ve Differential Nonlinearity, -'ve Offset Error Gain Error Voltage Output Settling Time 0.1% Line Driver Output Total Harmonic Distortion Output Voltage Swing ADuC7128 0.25 Unit
Preliminary Technical Data
Test Conditions/Comments
Mode Mode measured into range specified loads (see Figure PL1/LD2TX unless otherwise noted operating 691.2kHz.
Common Mode
0.30 ±1.753 ±1.768 ±1.782
Differential Input Impedance Leakage current LD1TX, LD2TX Leakage current LDIN Short Circuit Current Digital Analog Glitch Energy Line Driver Powerup time COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis3,5 Response Time TEMPERATURE SENSOR Voltage Output 25°C Voltage Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy Glitch Immunity RESET Pin3 Watchdog Timer (WDT) Timeout Period
12.5 AGND AVDD-1.2
nVsec Vmin/Vmax
Mode Each output common mode 0.5*AVDD swings 0.5*VREF above below this. VREF internal 2.5V reference Mode Each output common mode 0.5*VREF swings 0.5*VREF above below this. VREF internal 2.5V reference Line Driver Buffer disabled
Line Driver Buffer disabled
change major carry
Hysteresis turned CMPHYST CMPCON register Response time modified CMPRES bits CMPCON register
-1.3
mV/°C
2.79 3.07 ±2.5
Rev. Page
selectable Trip Points selected nominal Trip Point Voltage
Preliminary Technical Data
Parameter Flash/EE MEMORY7,8 Endurance Data Retention Digital Inputs Logic Input Current (leakage Current Logic Input Current (leakage Current ADuC7128 10,000 Unit Cycles Years Test Conditions/Comments
ADuC7128
85°C
±0.2 -120
digital inputs including XCLKI XCLKO VINH VINH VINL except VINL Only
Logic inputs including XCLKI XCLKO
Input Capacitance Logic Inputs3 VINL, Input Voltage VINH, Input High Voltage Quadrature Encoder Inputs S1/S2/CLR (Schmitt-Triggered Inputs)
-VTB
IOVDD 400mV
ISOURCE 1.6mA
Logic Outputs9 VOH, Output High Voltage VOL, Output Voltage CRYSTAL INPUTS XCLKI XCLKO Logic Inputs, XCLKI Only VINL, Input Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance CLOCK RATE (PLL)
ISINK 1.6mA
programmable core clock selections within this range. (32.768kHz 1275)/128 (32.768kHz 1275)/1
INTERNAL OSCILLATOR Tolerance STARTUP TIME Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode Programmable Logic Array (PLA) Propagation Delay
326.4 41.779200 32.768
Core Clock 41.78
From input output
Rev. Page
ADuC7128
Parameter Element Propagation Delay ADuC7128 Unit
Preliminary Technical Data
Test Conditions/Comments
POWER REQUIREMENTS Power Supply Voltage Range IOVDD, AVDD DACVDD (Supply Voltage Chip) LVDD (Regulator Output from Chip)
5.52MHz clock 5.52MHz clock 41.78MHz clock 41.78MHz clock 691kHz, load (Fig. 44.2MHz clock External Crystal Internal
Power Supply Current10,11 Normal Mode
Additional Line Driver Supply Current Pause Mode Sleep Mode
channel specifications guaranteed during normal MicroConverter core operation. Apply input channels. production tested supported design and/or characterization data production release. Measured using external AD845 input buffer stage shown Figure Based external system components. input signal centered common-mode voltage (VCM) long this value within voltage input range specified. When using external reference input pin, internal reference must disabled setting REFCON memory mapped register Endurance qualified JEDEC Std. method A117 measured -40°C, +25°C, +85°C. Retention lifetime equivalent junction temperature (Tj) 85°C JEDEC Std. method A117. Retention lifetime derates with junction temperature. Test carried with maximum output level. Power supply current consumption measured normal, pause sleep modes under following conditions: Normal Mode: supply, Pause Mode: supply, Sleep Mode: supply IOVDD power supply current decreases typically during Flash/EE erase cycle.
Rev. Page
Preliminary Technical Data
100nF LD1TX 100nF LD2TX 27.5uH
ADuC7128
100nF LD1TX 100nF LD2TX
Figure Line Driver Load (top) (bottom)
8.9uH
Rev. Page
ADuC7128
Table Timing Fast Mode (400 kHz)
Preliminary Technical Data
Parameter tLOW tHIGH tHD;STA tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF tSUP
Description SCLOCK pulsewidth1 SCLOCK high pulsewidth1 Start condition hold time Data setup time Data hold time Setup time repeated start STOP condition setup time Bus-free time between STOP condition START condition Rise time both CLOCK SDATA Fall time both CLOCK SDATA Pulsewidth spike suppressed
Slave
Master 1360 1140 251350 12.51350
Unit
tHCLK depends clock divider bits PLLCON MMR. THCLK tUCLK/2CD.
tBUF
SDATA (I/O)
tSUP
tDSU tPSU tSHD
SCLK STOP START CONDITION CONDITION
tDHD
tDSU tRSU
tDHD
S(R) REPEATED START
Figure Compatible Interface Timing
Rev. Page
04955-054
tSUP
Preliminary Technical Data
Table Master Mode Timing (PHASE Mode
Parameter
ADuC7128
Description SCLOCK pulsewidth1
SCLOCK high pulsewidth1
(SPIDIV tHCLK (SPIDIV tHCLK
Unit
tDAV tDSU tDHD
Data output valid after SCLOCK edge Data input setup time before SCLOCK edge2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
tHCLK tUCLK
tUCLK tUCLK
12.5 12.5 12.5 12.5
tHCLK depends clock divider bits PLLCON MMR. THCLK tUCLK/2CD. tUCLK 23.9 corresponds 41.78 internal clock from before clock divider.
SCLOCK (POLARITY SCLOCK (POLARITY
tDAV
MOSI
BITS
MISO
BITS
04955-055
tDSU tDHD
Figure Master Mode Timing (PHASE Mode
Rev. Page
ADuC7128
Preliminary Technical Data
Table Master Mode Timing (PHASE Mode
Parameter tDAV
Description SCLOCK pulsewidth1 SCLOCK high pulsewidth1 Data output valid after SCLOCK edge
(SPIDIV tHCLK (SPIDIV tHCLK
tDOSU tDSU tDHD
Data output setup before SCLOCK edge Data input setup time before SCLOCK edge2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
tHCLK tUCLK
Unit
tUCLK tUCLK
12.5 12.5 12.5 12.5
tHCLK depends clock divider bits PLLCON MMR. THCLK tUCLK/2CD. tUCLK 23.9 corresponds 41.78 internal clock from before clock divider.
SCLOCK (POLARITY
SCLOCK (POLARITY
tDOSU
MOSI
tDAV
BITS
MISO
BITS
tDHD
Figure Master Mode Timing (PHASE Mode
Rev. Page
04955-056
tDSU
Preliminary Technical Data
ADuC7128
Table Slave Mode Timing (PHASE Mode
Parameter tDAV
Description SCLOCK edge1 SCLOCK pulsewidth2 SCLOCK high pulsewidth2 Data output valid after SCLOCK edge
tUCLK
(SPIDIV tHCLK (SPIDIV tHCLK
tHCLK tUCLK
Unit
tDSU tDHD tSFS
Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time high after SCLOCK edge
tUCLK tUCLK
12.5 12.5 12.5 12.5
tUCLK 23.9 corresponds 41.78 internal clock from before clock divider. tHCLK depends clock divider bits PLLCON MMR. THCLK tUCLK/2CD.
SCLOCK (POLARITY
tSFS
SCLOCK (POLARITY
tDAV
MISO
BITS
MOSI
BITS
04955-057
tDSU tDHD
Figure Slave Mode Timing (PHASE Mode
Rev. Page
ADuC7128
Preliminary Technical Data
Table Slave Mode Timing (PHASE Mode
Parameter tDAV
Description SCLOCK edge1 SCLOCK pulsewidth2 SCLOCK high pulsewidth2 Data output valid after SCLOCK edge
tUCLK
(SPIDIV tHCLK (SPIDIV tHCLK
tHCLK tUCLK
Unit
tDSU tDHD tDOCS tSFS
Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after edge high after SCLOCK edge
tUCLK tUCLK
12.5 12.5 12.5 12.5
tUCLK 23.9 corresponds 41.78 internal clock from before clock divider. tHCLK depends clock divider bits PLLCON MMR. THCLK tUCLK/2CD.
Rev. Page
Preliminary Technical Data
ADuC7128
SCLOCK (POLARITY
tSFS
SCLOCK (POLARITY
tDAV tDOCS
MISO
BITS
MOSI
BITS
04955-058
tDSU tDHD
Figure Slave Mode Timing (PHASE Mode
Rev. Page
ADuC7128
ABSOLUTE MAXIMUM RATINGS
25°C unless otherwise noted. DVDD IOVDD, AGND REFGND DACGND GNDREF.
Preliminary Technical Data
Table
Parameter AVDD DVDD AGND DGND IOVDD IOGND, AVDD AGND Digital Input Voltage IOGND Digital Output Voltage IOGND VREF AGND Analog Inputs AGND Analog Output AGND Operating Temperature Range Industrial ADuC7128 Storage Temperature Range Junction Temperature Thermal Impedance (64-pin CSP) Peak Solder Reflow Temperature SnPb Assemblies sec) PbFree Assemblies sec)
Rating -0.3 +0.3 -0.3 +0.3 -0.3 -0.3 IOVDD -0.3 IOVDD -0.3 AVDD -0.3 AVDD -0.3 AVDD -40°C +85°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Only absolute maximum rating applied time.
-65°C +150°C 125°C 24°C/W 240°C 260°C
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
Preliminary Technical Data
FUNCTION DESCRIPTIONS ADUC7128
Pin# Mnemonic ADC5 VDACout ADC9 ADC10 GNDREF
ADuC7128
Type
Function Single-ended differential Analog input Line Driver input Output from buffer Single-ended differential Analog input Single-ended differential Analog input Ground voltage reference ADC. optimal performance analog power supply should separated from IOGND DGND Bias point Negative Analog Input pseudo differential mode. Must connected ground signal convert. This bias point must between Analog Power Single-ended differential Analog input differential negative output Single-ended differential Analog input differential Positive output Analog Ground. Ground reference point analog circuitry JTAG Test Port Input Test Mode Select. Debug download access JTAG Test Port Input Test Data Debug download access General Purpose Input-Output Port Serial Port General Purpose Input-Output Port Serial Port General Purpose Input-Output Port /Boot Mode. ADuC7128 will enter download mode reset will execute code pulled high reset through 1kOhm resistor/ Voltage Comparator Output General Purpose Output Port Timer Input Power reset output JTAG Test Port Input Test Clock. Debug download access JTAG Test Port Output Test Data Out. Debug download access Ground GPIO. Typically connected DGND 3.3V Supply GPIO input on-chip voltage regulator. 2.5V. Output on-chip voltage regulator. Must connected 0.47µF capacitor DGND Ground core logic. General Purpose Input-Output Port 3.0/ output General Purpose Input-Output Port 3.1/ output General Purpose Input-Output Port 3.2/ output General Purpose Input-Output Port 3.3/ output General Purpose Input-Output Port 3.3/ ADCBUSY signal JTAG Test Port Input Test Reset. Debug download access Reset Input. (active low) General Purpose Input-Output Port 3.4/ output General Purpose Input-Output Port 3.5/ output General Purpose Input-Output Port External Interrupt Request active high Start conversion input signal General Purpose Input-Output Port External Interrupt Request active high ADCBUSY signal General Purpose Input-Output Port Serial Port General Purpose Input-Output Port Serial Port Output External Clock signal/ Input internal clock generator circuits Output from crystal oscillator inverter Input crystal oscillator inverter input internal clock generator circuits
ADCNEG AVDD
ADC12/LD1TX ADC13/ LD2TX AGND P4.6/SPM10 P4.7/SPM11 P0.0/BM/CMPOUT
P0.6/T1/MRST IOGND IOVDD
LVDD
DGND P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4 P0.3/ADCBUSY/TRST
P3.4/PWM5 P3.5/PWM6 P0.4/IRQ0/CONVST P0.5/IRQ1/ADCBUSY
P2.0/SPM9 P0.7/SPM8/ECLK/XCLK XCLKO XCLKI PVDD
2.5V.PLL supply. Must connected 0.1µF capacitor DGND Should connected 2.5V output.
Rev. Page
ADuC7128
Pin# Mnemonic DGND P1.7/SPM7 P1.6/SPM6 IOGND IOVDD P4.0/S1 P4.1/S2 P1.5/SPM5 P1.4/SPM4 P1.3/SPM3 P1.2/SPM2 P1.1/SPM1 P1.0/SPM0 P4.2 P4.3/ PWMTRIP P4.4 P4.5
Preliminary Technical Data
Type Function Ground PLL. General Purpose Input-Output Port 1.7/Serial Port General Purpose Input-Output Port 1.6/Serial Port Ground GPIO. Typically connected DGND 3.3V Supply GPIO input on-chip voltage regulator. General Purpose Input-Output Port 4.0/ Quadrature Input General Purpose Input-Output Port Quadrature Input General Purpose Input-Output Port 1.5/Serial Port General Purpose Input-Output Port 1.4/Serial Port General Purpose Input-Output Port 1.3/Serial Port General Purpose Input-Output Port 1.2/Serial Port General Purpose Input-Output Port 1.1/Serial Port General Purpose Input-Output Port 1.0/Serial Port General Purpose Input-Output Port General Purpose Input-Output Port 4.3/ safety General Purpose Input-Output Port General Purpose Input-Output Port 2.5V internal Voltage Reference. Must connected 0.47uF capacitor when using internal reference. Ground DAC. Typically connected AGND Analog Ground. Ground reference point analog circuitry Analog Power Power Supply DAC, This must supplied with 2.5V. This connected output. Single-ended differential Analog input Single-ended differential Analog input Single-ended differential Analog input Comparator positive input Single-ended differential Analog input Comparator negative input Single-ended differential Analog input
VREF
DACGND AGND AVDD
DACVDD
ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4
Rev. Page
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
(LSB)
ADuC7128
774kSPS
774kSPS
(LSB)
04955-075
-0.2 -0.4 -0.6 -0.8 -1.0 1000 2000 CODES
-0.2 -0.4 -0.6 -0.8 -1.0 1000 2000 CODES 3000 4000
04955-074
3000
4000
Figure Typical Error, kSPS
Figure Typical Error, kSPS
1MSPS
(LSB)
1MSPS
(LSB)
-0.2 -0.4 -0.6
04955-077
-0.2 -0.4 -0.6 -0.8 -1.0 1000 2000 CODES
-0.8 -1.0 1000 2000 CODES
3000
4000
3000
4000
Figure Typical Error, MSPS
(LSB) (LSB)
Figure Typical Error, MSPS
-0.1 -0.2 -0.3
(LSB)
-0.1 -0.2 -0.3 -0.4
EXTERNAL REFERENCE
-0.6 EXTERNAL REFERENCE
-0.5 -0.6
-0.7 -0.8
04955-072
-0.7 -0.8 -0.9 -1.0
-0.9 -1.0
Figure Typical Worse Case Error VREF, kSPS
Figure Typical Worse Case Error VREF, kSPS
Rev. Page
04955-071
(LSB)
-0.5
04955-076
ADuC7128
9000 8000 7000
Preliminary Technical Data
6000
FREQUENCY
(dB)
5000 4000 3000
2000 1000
04955-070
04955-073
1161
1162
1163
EXTERNAL REFERENCE
Figure Code Histogram Plot
1350 1500
Figure Typical Dynamic Performance VREF
774kSPS, 69.3dB, -80.8dB, PHSN -83.4dB
1450 1400
CODE
(dB)
1300 1250 1200 1150
-100 -120
1100
04955-078
1050 1000 TEMPERATURE (°C)
-160
FREQUENCY (kHz)
Figure Dynamic Performance, kSPS
Figure On-Chip Temperature Sensor Voltage Output Temperature
39.8 39.7 39.6 39.5
1MSPS, 70.4dB, -77.2dB, PHSN -78.9dB
(dB)
-100
39.2
(mA)
39.4 39.3
-120 -140 -160
04955-079
39.1 39.0 38.9
04955-080
FREQUENCY (kHz)
Figure Dynamic Performance, MSPS
TEMPERATURE (°C)
Figure Current Consumption Temperature
Rev. Page
04955-060
-140
(dB)
Preliminary Technical Data
12.05 12.00 11.95 11.90 11.85
ADuC7128
Current consumption sleep mode
(mA)
11.80
04955-081
11.75 11.70 11.65 11.60 11.55 TEMPERATURE (°C)
TEMPERATURE (DEGREE
Figure Current Consumption Temperature
7.85 7.80 7.75 7.70 37.0 37.2
Figure Current Consumption Temperature Sleep Mode
37.4
(mA)
7.65 7.60 7.55 36.6 7.50 7.45 7.40
04955-082
(mA)
36.8
36.4
04955-084
TEMPERATURE (°C)
36.2
62.25
Figure Current Consumption Temperature@t
125.00 250.00 500.00 SAMPLING FREQUENCY (kSPS)
1000.00
Figure Current Consumption Speed
Rev. Page
ADuC7128
TERMINOLOGY
SPECIFICATIONS
Integral Nonlinearity maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero scale, point below first code transition full scale, point above last code transition. Differential Nonlinearity difference between measured ideal change between adjacent codes ADC. Offset Error deviation first code transition (0000 000) (0000 001) from ideal, that LSB. Gain Error deviation last code transition from ideal voltage (full scale LSB) after offset error been adjusted out. Signal (Noise Distortion) Ratio measured ratio signal (noise distortion) output ADC. signal amplitude fundamental. Noise nonfundamental signals half sampling frequency (fS2), excluding ratio dependent upon number quantization levels digitization process; more levels, smaller quantization noise.
Preliminary Technical Data
theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02 1.76) Thus, 12-bit converter, this Total Harmonic Distortion ratio harmonics fundamental.
SPECIFICATIONS
Relative Accuracy Otherwise known endpoint linearity, relative accuracy measure maximum deviation from straight line passing through endpoints transfer function. measured after adjusting zero error full-scale error. Voltage Output Settling Time amount time takes output settle within level full-scale input change.
Rev. Page
Preliminary Technical Data
OVERVIEW ARM7TDMI CORE
ARM7 core 32-bit Reduced Instruction Computer (RISC). uses single 32-bit instruction data. length data bits. length instruction word bits. ARM7TDMI ARM7 core with additional features: support Thumb bit) instruction set. support debug support long multiplies include embeddedICE module support embedded system debugging.
ADuC7128
state, processor registers inspected well Flash/EE, SRAM memory mapped registers.
EXCEPTIONS
supports five types exceptions, privileged processing mode each type. five types exceptions are: Normal interrupt IRQ. This provided service general-purpose interrupt handling internal external events. Fast interrupt FIQ. This provided service data transfer communication channel with latency. priority over IRQ. Memory abort. Attempted execution undefined instruction. Software interrupt instruction (SWI). This used make call operating system.
Thumb mode
instruction 32-bits long. ARM7TDMI processor supports second instruction that been compressed into 16-bits, called thumb instruction set. Faster execution from 16-bit memory greater code density usually achieved using thumb instruction instead instruction set, which makes ARM7TDMI core particularly suitable embedded applications. However, thumb mode limitations: Thumb code usually uses more instructions same job. result, code usually best maximising performance time-critical code. thumb instruction does include some instructions needed exception handling, which automatically switches core code exception handling.
Typically, programmer defines interrupt IRQ, higher priority interrupt, that faster response time, programmer define interrupt FIQ.
REGISTERS
ARM7TDMI total registers: general purpose registers status registers. Each operating mode dedicated banked registers. When writing user-level programs, general-purpose 32-bit registers R14), program counter (R15) current program status register (CPSR) usable. remaining registers only used system-level programming exception handling. When exception occurs, some standard registers replaced with registers specific exception mode. exception modes have replacement banked registers stack pointer (R13) link register (R14) represented Figure fast interrupt mode more registers R12) fast interrupt processing. This means interrupt processing begin without need save restore these registers, thus save critical time interrupt handling process.
ARM7TDMI user guide details core architecture, programming model, both thumb instruction sets.
Long Multiply
ARM7TDMI instruction includes four extra instructions that perform 32-bit 32-bit multiplication with 64-bit result, 32-bit 32-bit multiplication-accumulation (MAC) with 64-bit result. This result achieved fewer cycles than required standard ARM7 core.
EmbeddedICE
EmbeddedICE provides integrated on-chip support core. EmbeddedICE module contains breakpoint watchpoint registers that allow code halted de-bugging purposes. These registers controlled through JTAG test port. When breakpoint watchpoint encountered, processor halts enters debug state. Once debug
Rev. Page
ADuC7128
(PC) usable user mode
Preliminary Technical Data
Memory organisation
part incorporates three separate blocks memory, 8kByte SRAM 64kByte On-Chip Flash/EE memory. 126kByte On-Chip Flash/EE memory available user, remaining 2kBytes reserved factory configured boot page. These blocks mapped shown Figure Note that default, after reset, Flash/EE memory mirrored address 0x00000000. possible remap SRAM address 0x00000000 clearing REMAP MMR. This remap function described more details Flash/EE memory chapter.
FFFFFFFFh FFFF0000h
system modes only r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_abt r13_fiq r13_svc r14_abt r14_svc r14_fiq
r13_und r13_irq r14_und r14_irq
CPSR user mode
SPSR_fiq
SPSR_svc
SPSR_abt
SPSR_irq
SPSR_und
MMRs Reserved
mode
mode
abort mode
undefined mode mode
0009F800h
Flash/EE
Figure register organisation
00080000h
More information relative programmer's model ARM7TDMI core architecture found following documents from ARM: DDI0029G, ARM7TDMI Technical Reference Manual. DDI0100E, Architecture Reference Manual.
Reserved
00041FFFh 00040000h 0001FFFFh
SRAM Reserved Re-mappable Memory Space (Flash/EE SRAM)
Interrupt latency
worst case latency consists longest time request take pass through synchronizer, plus time longest instruction complete (the longest instruction LDM) which loads registers including plus time data abort entry, plus time entry. this time, ARM7TDMI will executing instruction 0x1C (FIQ interrupt vector address). maximum total time processor cycles, which just over 1.1µS system using continuous 41.78 processor clock. maximum latency calculation similar, must allow fact that higher priority could delay entry into handling routine arbitrary length time. This time reduced cycles command used, some compilers have option compile without using this command. Another option part THUMB mode where this reduced cycles. minimum latency interrupts five cycles total which consists shortest time request take through synchronizer plus time enter exception mode. Note that ARM7TDMI will always (32-bit) mode when privileged modes, i.e. when executing interrupt service routines.
00000000h
Figure Physical memory
Memory Access
ARM7 core sees memory linear array byte location where different blocks memory mapped outlined Figure ADuC7128 memory organisation configured little endian format: least significant byte located lowest byte address most significant byte highest byte address.
bit31 Byte3 Byte2 Byte1 bits bit0 Byte0 0xFFFFFFFFh
0x00000004h 0x00000000h
Figure little endian format
Rev. Page
Preliminary Technical Data
Flash/EE Memory
0xFFFF06BC 0xFFFFFFFF 0xFFFF0FBC
ADuC7128
128kBytes Flash/EE organised banks bits. first block bits user space bits reserved factory configured boot page. page size this Flash/EE memory 512Bytes. second 64kByte block organized similar manner. arranged bits. this available user space. kBytes Flash/EE available user code non-volatile data memory. There distinction between data program code shares same space. real width Flash/EE memory bits, which means that mode (32-bit instruction), accesses Flash/EE necessary each instruction fetch. therefore recommended Thumb mode when executing from Flash/EE memory optimum access speed. maximum access speed Flash/EE memory 41.78MHz Thumb mode 20.89MHz full mode. More details Flash/EE access time outlined later `Execution from SRAM Flash/EE' section this datasheet.
0xFFFF0690 0xFFFF0688 0xFFFF0F00 0xFFFF0F18
0xFFFF0670 0xFFFF0544 0xFFFF0F00 0xFFFF0EA8
0xFFFF0500 0xFFFF04A8 0xFFFF0480 0xFFFF0448 0xFFFF0440 0xFFFF0434 0xFFFF0400 0xFFFF0394 0xFFFF0E80 0xFFFF0E28 0xFFFF0E00 0xFFFF0D70
Flash Control Interface Flash Control Interface
Bandgap Reference Power Supply Monitor Oscillator Control General Purpose Timer Watchdog Timer Wake Timer General Purpose Timer
GPIO
0xFFFF0D00 0xFFFF0C30
External Memory
0xFFFF0C00 0xFFFF0B54
0xFFFF0B00 0xFFFF0A14
0xFFFF0380 0xFFFF0370 0xFFFF0360
0xFFFF0A00 0xFFFF0948
SRAM
8kBytes SRAM available user, organized bits, i.e. 2kWords. code directly from SRAM 41.78MHz given that SRAM array configured 32-bit wide memory array. More details SRAM access time outlined later `Execution from SRAM Flash/EE' section this datasheet.
0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0318
0xFFFF0900 0xFFFF0848
0xFFFF0800 0xFFFF076C
Timer
0xFFFF0300 0xFFFF0240 0xFFFF0740 0xFFFF072C
UART
Memory Mapped Registers
Memory Mapped Register (MMR) space mapped into upper pages memory array accessed indirect addressing through ARM7 banked registers. space provides interface between on-chip peripherals. registers except core registers reside area. shaded locations shown Figure unoccupied reserved locations should accessed user software. Table shows full memory map. access time reading writing depends advanced microcontroller architecture (AMBA) used access peripheral. processor AMBA busses: advanced high performance (AHB) used system modules, advanced peripheral (APB) used lower performance peripheral. Access cycle, access cycles. peripherals ADuC7128 except Flash/EE memory GPIOs.
0xFFFF0200 0xFFFF0110 0xFFFF0000
Remap System Control Interrupt Controller
UART
0xFFFF0700 0xFFFF06E8
Figure Memory Mapped
Rev. Page
ADuC7128
Table Complete MMRs list
Address Name Byte Access Type address base 0xFFFF0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C 0x0220 0x0230 0x0234 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 IRQSTA IRQSIG IRQEN IRQCLR SWICFG FIQSTA FIQSIG FIQEN FIQCLR REMAP RSTSTA RSTCLR T0LD T0VAL0 T0VAL1 T0CON T0ICLR T0CAP T1LD T1VAL T1CON T1ICLR T1CAP T2LD T2VAL T2CON T2ICLR T3LD T3VAL T3CON T3ICLR T4LD T4VAL T4CON 0x0708
Rev. Page
Preliminary Technical Data
Address Page Cycle 0x038C 0x0390 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 Name T4ICLR T4CAP POWKEY1 POWCON POWKEY2 PLLKEY1 PLLCON PLLKEY2 Byte Access Type Cycle Page
base address 0xFFFF0400
address base 0xFFFF0440 0x0440 0x0444 PSMCON CMPCON
System Control address base 0xFFFF0200
Reference address base 0xFFFF0480 0x048C 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0530 0x0534 0x0670 0x0690 0x0694 0x0698 0x06A4 0x06B4 0x06B8 0x06BC 0x0700 REFCON ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST ADCGN ADCOF DACCON DDSCON DDSFRQ DDSPHS DACKEY0 DACDAT DACEN DACKEY1 COM0TX COM0RX COM0DIV0 0x0704 COM0IEN0 COM0DIV1 COM0IID0 address base 0xFFFF0500
Timer address base 0xFFFF0300
address base 0xFFFF0670
UART base address 0xFFFF0700
Preliminary Technical Data
Address Name Byte Access Type 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0X072C
COM0CON0 COM0CON1 COM0STA0 COM0STA1
ADuC7128
Page Address Name Byte Access Type 0x0838 0x083C 0x0840 0x0844 0x0848 0x084C I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0SSC I2C0FIF Cycle Page
Cycle
COM0SCR COM0IEN1 COM0IID1 COM0ADR COM0DIV2
I2C1 base address 0xFFFF0900 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0924 0x0928 0x092C 0x0930 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C 0x0A00 I2C1MSTA I2C1SSTA I2C1SRX I2C1STX I2C1MRX I2C1MTX I2C1CNT I2C1ADR I2C1BYT I2C1ALT I2C1CFG I2C1DIV I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1SSC I2C1FIF SPISTA SPIRX SPITX SPIDIV SPICON PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5
UART base address 0xFFFF0740 0x0740 COM1TX COM1RX COM1DIV0 0x0744 0x0748 0x074C 0x0750 0x0754 0x0758 0x075C 0x0760 0x0764 0x0768 0X076C 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0824 0x0828 0x082C 0x0830 COM1IEN0 COM1DIV1 COM1IID0
COM1CON0 COM1CON1 COM1STA0 COM1STA1
COM1SCR COM1IEN1 COM1IID1 COM1ADR COM1DIV2 I2C0MSTA I2C0SSTA I2C0SRX I2C0STX I2C0MRX I2C0MTX I2C0CNT I2C0ADR I2C0BYT I2C0ALT I2C0CFG I2C0DIV
base address 0xFFFF0A00 0x0A04 0x0A08 0x0A0C 0x0A10 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14
I2C0 base address 0xFFFF0800
base address 0xFFFF0B00
Rev. Page
ADuC7128
Address Name Byte Access Type 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLAOUT Cycle 0x0D68 0x0D6C 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E98 0x0E9C 0x0EA0 0x0F00 0x0F04 0x0F08 0x0F0C 0x0F14 0x0F18 Page Address
Preliminary Technical Data
Name Byte Access Type GP4CLR GP4PAR FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID QENCON QENSTA QENDAT QENVAL QENCLR QENSET
PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1
Page Cycle
Flash/EE Block base address 0xFFFF0E00
Flash/EE Block base address 0xFFFF0E80
GPIO base address 0xFFFF0D00 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D10 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D50 0x0D54 0x0D58 0x0D5C 0x0D60 0x0D64 GP0CON GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP3DAT GP3SET GP3CLR GP3PAR GP4DAT GP4SET
base address= 0xFFFF0F00
base address= 0xFFFF0F80 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4
Rev. Page
Preliminary Technical Data
Address Name Byte Access Type 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8
PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR
ADuC7128
Page
Cycle
`Access' column corresponds access time reading writing MMR. depends AMBA (Advanced Microcontroller Architecture) used access peripheral. processor AMBA busses, (Advanced High-performance Bus) used system modules (Advanced Peripheral Bus) used lower performance peripheral.
Rev. Page
ADuC7128
CIRCUIT INFORMATION
GENERAL OVERVIEW
Analog Digital Converter (ADC) incorporates fast, multichannel, 12-bit ADC. operate from 3.0V 3.6V supplies capable providing throughput 1MSPS when clock source 41.78MHz. This block provides user with multi-channel multiplexer, differential track-and-hold, on-chip reference ADC. consists 12-bit successive-approximation converter based around capacitor DACs. Depending input signal configuration, operate three different modes Fully differential mode, small balanced signals. Single-ended mode, single-ended signals. Pseudo differential mode, single-ended signals, taking advantage common mode rejection offered pseudo differential input.
Preliminary Technical Data
temperature sensor channel, measuring temperature accuracy ±3°C.
TRANSFER FUNCTION
Pseudo-differential single-ended modes
pseudo-differential single-ended mode, input range VREF. output coding straight binary pseudo differential single-ended modes with: FS/4096 V/4096 0.61 when VREF
ideal code transitions occur midway between successive integer values (i.e. LSB, LSBs, LSBs, -3/2 LSBs). ideal input/output transfer characteristic shown Figure
OUTPUT CODE 1111 1111 1111 1111 1111 1110 1111 1111 1101
converter accepts analog input range VREF when operating single-ended mode pseudo-differential mode. fully differential mode, input signal must balanced around common mode voltage VCM, range AVDD with maximum amplitude VREF (see Figure 28).
AVDD 2VREF 2VREF
1111 1111 1100
1LSB
4096
0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 1LSB VOLTAGE INPUT 1LSB
Figure transfer function pseudo differential mode single-ended mode
2VREF
Fully differential mode
amplitude differential signal difference between signals applied VIN+ VIN- pins (i.e., VIN+ VIN-). maximum amplitude differential signal therefore -VREF +VREF (i.e. VREF). This regardless common mode (CM). common mode average signals, i.e. (VIN+ VIN-)/2 therefore voltage that inputs centred This results span each input being VREF/2. This voltage externally range varies with VREF, (see driving ADC). output coding two's complement fully differential mode with 2VREF/4096 2x2.5 V/4096 1.22 when VREF output result bits this shifted right. This allows result ADCDAT declared signed integer when writing code. designed code transitions occur midway between successive integer values (i.e., LSB, LSBs, LSBs, -3/2 LSBs). ideal input/output transfer characteristic shown Figure
Figure examples balanced signals fully differential mode
high precision, drift, factory calibrated reference provided on-chip. external reference also connected described later Bandgap Reference section. Single continuous conversion modes initiated software. external CONVSTART pin, output generated from on-chip Timer0 Timer1 overflow also used generate repetitive trigger conversions.
signal been asserted time conversion complete then second conversion will begin automatically. voltage output from proportional absolute through front additional channel on-chip bandgap reference temperature also routed multiplexer, effectively input. This facilitates internal
Rev. Page
Preliminary Technical Data
TRIAL
ADuC7128
WRITE
SIGN
OUTPUT CODE 1111 1111 1110
CLOCK
1111 1111 1100 1111 1111 1010
1LSB
4096
CONVTSTART
0000 0000 0001 0000 0000 0000 1111 1111 1110
ADCDAT DATA ADCBUSY
0000 0000 0100 0000 0000 0010 0000 0000 0000 1LSB 0LSB 1LSB
INTERRUPT ADCSTA ADCSTA
04955-015
VOLTAGE INPUT (Vin+ Vin-)
Figure Timing
Figure transfer function differential mode
MMRS interface
controlled configured number MMRs that listed below described detail following pages: ADCCON: Control Register allows programmer enable peripheral, select mode operation ADC, either Single-ended, pseudo-differential fully differential mode conversion type. This described Table ADCCP: positive Channel selection Register ADCCN: negative Channel selection Register ADCSTA: Status Register, indicates when conversion result ready. ADCSTA register contains only bit, ADCReady, (bit representing status ADC. This conversion generating interrupt, cleared automatically reading ADCDAT MMR. When performing conversion, status read externally ADCBusy pin. This high during conversion. When conversion finished, ADCBusy goes back low. This information available P0.5 (see chapter GPIO) enabled GP0CON register. ADCDAT: Data Result Register, hold 12-bit result shown Figure ADCRST: Reset Register. Resets registers their default value.
TYPICAL OPERATION
Once configured control channel selection registers, will convert analog input provide 11-bit result data register. bits sign bits 11-bit result placed from shown Figure Again, should noted that fully differential mode, result represented two's complement format shifted right pseudo differential single-ended mode, result represented straight binary format.
SIGN BITS
12-bit RESULT
Figure Result Format
Timing
Figure gives details timing. Users have control clock speed number acquisition clock ADCCON MMR. default, acquisition time eight clocks clock divider two. number extra clocks (such trial write) which gives sampling rate kSPS. conversion temperature sensor, acquisition time automatically clocks clock divider
Rev. Page
ADuC7128
Table ADCCON Designations 1210 Description Speed (Fadc Fcore, conversion clocks Acquisition time) Fadc Fadc Fadc Fadc Fadc Fadc Acquisition Time (number clocks) Enable Conversion user enable conversion mode Cleared user disable conversion mode Reserved This should user. power control:
Preliminary Technical Data
user place normal mode, must powered least 500uS before will convert correctly. Cleared user place power-down mode Conversion Mode: Single Ended Mode Differential Mode Pseudo-Differential Mode Reserved
Conversion Type: Enable CONVSTART conversion input
Enable timer conversion input Enable timer conversion input Single software conversion, will after conversion. (Bit ADCCON should cleared after starting single software conversion avoid further conversions triggered CONVSTART pin).
Rev. Page
Preliminary Technical Data
Other Continuous software conversion conversion conversion Reserved
ADuC7128
Table ADCCP* designation Description Reserved Positive Channel Selection Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12/LD2TX ADC13/LD1TX Reserved Reserved Temperature sensor AGND Reference AVDD/2 Reserved
Table ADCCN* designation Description Reserved Negative Channel Selection Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12/LD2TX ADC13/LD1TX Reserved Reserved Temperature sensor Reserved
channel availability depends part model.
Since ADC12 ADC13 shared with Line Driver pins high level crosstalk will seen these pins when used mode.
Rev. Page
ADuC7128
CONVERTER OPERATION
incorporates successive approximation (SAR) architecture involving charge-sampled input stage. This architecture described below three different modes operation.
Preliminary Technical Data
Pseudo-differential mode
pseudo-differential mode, Channel- linked VIN- ADuC7128 switches between (Channel-) (VREF). VIN- must connected Ground voltage. input signal VIN+ then vary from VIN- VREF VIN-. Note VIN- must chosen that VREF VIN- does exceed AVDD.
Differential mode
ADuC7128 contains successive approximation based capacitive DACs. Figure Figure show simplified schematics acquisition conversion phase, respectively. comprised control logic, SAR, capacitive DACs. Figure (the acquisition phase), closed Position comparator held balanced condition, sampling capacitor arrays acquire differential signal input.
CAPACITIVE AIN0 Channel+ ChannelAIN11 VREF COMPARATOR CONTROL LOGIC
AIN0
CAPACITIVE COMPARATOR CONTROL LOGIC
Channel+
VREF
AIN11
VINChannel-
CAPACITIVE
Figure pseudo-differential mode
Single-ended mode
Single-ended mode, always connected internally ground. VIN- floating. input signal range VIN+ VREF.
AIN0 CAPACITIVE COMPARATOR CONTROL LOGIC
CAPACITIVE
Figure acquisition phase
When starts conversion (Figure 34), will open will move Position causing comparator become unbalanced. Both inputs disconnected once conversion begins. control logic charge redistribution DACs used subtract fixed amounts charge from sampling capacitor arrays bring comparator back into balanced condition. When comparator rebalanced, conversion complete. control logic generates ADC's output code. output impedances sources driving VIN+ VIN- pins must matched; otherwise, inputs will have different settling times, resulting errors.
CAPACITIVE AIN0 Channel+ VREF COMPARATOR CONTROL LOGIC
Channel+
Channel-
AIN11
VIN-
CAPACITIVE
Figure single-ended mode
Analog Input Structure
Figure shows equivalent circuit analog input structure ADC. four diodes provides protection analog inputs. Care must taken ensure that analog input signals never exceed supply rails more than This would cause these diodes become forward biased start conducting into substrate. These diodes conduct without causing irreversible damage part. capacitors Figure typically primarily attributed capacitance. resistors lumped components made resistance switches. value these resistors typically about capacitors, ADC's sampling capacitors have capacitance typically.
Channel-
AIN11 CAPACITIVE
Figure conversion phase
Rev. Page
Preliminary Technical Data
AVDD
ADuC7128
will increase source impedance increases performance will degrade.
DRIVING ANALOG INPUTS
Internal external reference used ADC. differential mode operation, there restrictions common mode input signal (VCM) that dependant reference value supply voltage used ensure that signal remains within supply rails. Table gives some calculated some conditions.
AVDD
Table ranges
Figure Equivalent Analog Input Circuit Conversion Phase: Switches Open Track Phase: Switches Closed
AVDD 3.3V
VREF 2.5V 2.048V
Signal Peak-Peak 2.5V 2.048V 1.25 2.5V 2.048V 1.25
1.25V 1.024V 0.75V 1.25V 1.024V 0.75V
2.05V 2.276V 2.55V 1.75V 1.976V 2.25V
applications, removing high-frequency components from analog input signal recommended low-pass filter relevant analog input pins. applications where harmonic distortion signal-to-noise ratio critical, analog input should driven from impedance source. Large source impedances will significantly affect performance ADC. This necessitate input buffer amplifier. choice will function particular application. Figure Figure give example front end.
ADuC7229
1.25 3.0V 2.5V 2.048V 1.25
TEMPERATURE SENSOR
ADuC7128 provides voltage output from on-chip bandgap reference proportional absolute temperature. also routed through front multiplexer (effectively additional channel input) facilitating internal temperature sensor channel, measuring temperature accuracy ±3°C.
0.01µ
ADC0
BANDGAP REFERENCE
ADuC7128 provides on-chip bandgap reference 2.5V, which used DAC. This internal reference also appears VREF pin. When using internal reference, capacitor 0.47µF must connected from external VREF AGND, ensure stability fast response during conversions. This reference also connected external (VREF) used reference other circuits system. external buffer would required because drive capability VREF output. programmable option also allows external reference input VREF pin.
Figure Buffering Single-Ended/Pseudo Differential Input
ADuC7229 ADC0 Vref ADC1
Figure Buffering Differential Inputs
bandgap reference interface consists 8-bit MMR, REFCON described following table.
When amplifier used drive analog input, source impedance should limited values lower than maximum source impedance will depend amount total harmonic distortion (THD) that tolerated.
Rev. Page
ADuC7128
Table REFCON designations Description Reserved Internal reference powerdown enable user place internal reference powerdown mode external reference Cleared user place internal reference normal mode conversions Internal reference output enable user connect internal 2.5V reference VREF pin. reference used external component will need buffered. Cleared user disconnect reference from VREF pin. Note: chip only functional with internal reference output enable set. will work with external reference.
Preliminary Technical Data
Rev. Page
Preliminary Technical Data
NONVOLATILE FLASH/EE MEMORY
ADuC7128
code download debug. application note available www.analog.com/microconverter describing protocol JTAG. possible write single Flash/EE location address twice. single address written more than twice, then data within Flash/EE memory could corrupted. That possible walk zeros only byte wise.
FLASH/EE MEMORY OVERVIEW
ADuC7128 incorporates Flash/EE memory technology onchip provide user with non-volatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory programmed in-system byte level, although must first erased. erase performed page blocks. result, flash memory often more correctly referred Flash/EE memory. Overall, Flash/EE memory represents step closer ideal memory device that includes non-volatility, in-circuit programmability, high density, cost. Incorporated ADuC7128, Flash/EE memory technology allows user update program code space in-circuit, without need replace time programmable (OTP) devices remote operating nodes.
FLASH/EE MEMORY SECURITY
Flash/EE memory available user read write protected. FEE0PRO/FEE0HID protects from being read through JTAG also parallel programming mode. other bits this register protect writing flash memory; each protects pages, that Write protection activated type access. FEE1PRO FEE1HID similarly protect second 64kB block. bits this used protect pages time.
FLASH/EE MEMORY ADUC7128
ADuC7128 contains kByte arrays Flash/EE Memory. first block lower Kbytes available user upper kBytes this Flash/EE program memory array contain permanently embedded firmware, allowing circuit serial download. These Kbytes embedded firmware also contain power-on configuration routine that downloads factory calibrated coefficients various calibrated peripherals (bandgap references on). This kByte embedded firmware hidden from user code. possible user read, write erase this page. second block 64kB Flash/EE memory available user. 126kBytes Flash/EE memory programmed incircuit, using serial download mode JTAG mode provided.
Three Levels Protection
Protection removed writing directly into FEExHID MMR. This protection does remain after reset. Protection writing into FEExPRO MMR. only takes effect after save protection command reset. FEExPRO protected avoid direct access. saved once must entered again modify FEExPRO. mass erase sets back also erases user code. Flash permanently protected using FEEPRO particular value key: Entering again modify FEExPRO register allowed
Serial Downloading (In-Circuit Programming)
ADuC7128 facilitates code download standard UART serial port port. ADuC7128 enters serial download mode after reset power cycle pulled through external 1kOhm resistor. Once serial download mode, user download code full 126kBytes Flash/EE memory while device circuit target application hardware. serial download executable provided part development system serial downloading UART. application note available www.analog.com/microconverter describing protocol serial downloading UART I2C.
Sequence Write
Write FEExPRO corresponding page protected. Enable protection setting FEExMOD (Bit must Write 32-bit FEExADR, FEExDAT. write command FEExCON; wait read successful monitoring FEExSTA. Reset part.
JTAG access
JTAG protocol uses on-chip JTAG interface facilitate
remove modify protection, same sequence used with modified value FEExPRO. chosen value then memory protection cannot removed. Only mass erase unprotects part, also
Rev. Page
ADuC7128
erases user code. sequence write illustrated following example; this protects writing pages Flash:
Name FEE1DAT
Preliminary Technical Data
FEE1DAT Register
Address 0xFFFF0E8C Default Value 0xXXXX Access
FEE0PRO=0xFFFFFFFD; FEE0MOD=0x48; FEE0ADR=0x1234; FEE0DAT=0x5678; FEE0CON= 0x0C; command
//Protect pages //Write enable //16 value //16 value Write
FEE1DAT 16-bit data register.
FEE1ADR Register
Name FEE1ADR Address 0xFFFF0E90 Default Value 0x0000 Access
FEE1ADR another 16-bit address register.
same sequence should followed protect part permanently with FEEADR FEEDAT
FEE1SGN Register
Name FEE1SGN Address 0xFFFF0E98 Default Value 0xFFFFFF Access
FLASH/EE CONTROL INTERFACE
FEE0DAT Register
Name FEE0DAT Address 0xFFFF0E0C Default Value 0xXXXX Access
FEE1SGN 24-bit code signature.
FEE1PRO Register
Name FEE1PRO Address 0xFFFF0E9C Default Value 0x00000000 Access
FEE0DAT 16-bit data register.
FEE1PRO provides immediate protection MMR. does require software keys. description Table
Access
FEE0ADR Register
Name FEE0ADR Address 0xFFFF0E10 Default Value 0x0000
FEE1HID Register
Name FEE1HID Address 0xFFFF0EA0 Default Value 0xFFFFFFFF Access
FEE0ADR another 16-bit address register.
FEE0SGN Register
Name FEE0SGN Address 0xFFFF0E18 Default Value 0xFFFFFF Access
FEE1HID provides protection following subsequent reset MMR. requires software key. description Table
FEE0SGN 24-bit code signature.
FEE0PRO Register
Name FEE0PRO Address 0xFFFF0E1C Default Value 0x00000000 Access
FEE0PRO provides immediate protection MMR. does require software keys. description Table
FEE0HID Register
Name FEE0HID Address 0xFFFF0E20 Default Value 0xFFFFFFFF Access
FEE0HID provides protection following subsequent reset MMR. requires software key. description Table
Command Sequence Executing Mass Erase
FEE0DAT=0x3CFF; FEE0ADR 0xFFC3; FEE0MOD= FEE0MOD|0x8; //Erase enable FEE0CON=0x06; //Mass erase command
Rev. Page
Preliminary Technical Data
Table FEExSTA designations 15-6 Description Reserved Burst command enable when command burst command: 0x07, 0x08 0x09 Cleared when other command Reserved
ADuC7128
Flash interrupt status automatically when interrupt occurs, i.e. when command complete Flash/EE interrupt enable FEExMOD register Cleared when reading FEExSTA register Flash/EE controller busy automatically when controller busy Cleared automatically when controller busy Command fail automatically when command completes unsuccessfully Cleared automatically when reading FEExSTA register Command complete MicroConverter when command complete Cleared automatically when reading FEExSTA register
Table FEExMOD designations Description Reserved Flash/EE interrupt enable: user enable Flash/EE interrupt. interrupt will occur when command complete. Cleared user disable Flash/EE interrupt
Erase/write command protection. user enable erase write commands. Clear protect Flash against erase/write command.
Reserved Flash waitstates, when kernel exits this with user should first switch external 32kHz crystal before setting waitstates Both flash blocks must have same wait state value change take effect.
Table command codes FEExCON Code 0x00* 0x01* 0x02* 0x03*
command Null Single Read Single Write Erase-Write Single Verify Single Erase Mass erase Burst read Burst readwrite Erase Burst read-write
0x04* 0x05* 0x06* 0x07 0x08 0x09
Description Idle state Load FEExDAT with 16-bit data indexed FEExADR Write FEExDAT address pointed FEExADR. This operation takes 20µs. Erase page indexed FEExADR write FEExDAT location pointed FEExADR. This operation takes 20ms Compare contents location pointed FEExADR data FEExDAT. result comparison returned FEExSTA Erase page indexed FEExADR Erase user space. 2kByte kernel protected block This operation takes 2.48s prevent accidental execution command sequence required execute this instruction, this described below. Default command. write allowed. This operation takes cycles Write handle maximum data bits takes maximum Will automatically erase page indexed write, allow write pages without running erase command. This command takes erase page data write
Rev. Page
ADuC7128
0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
Preliminary Technical Data
Stops running burst allow execution from Flash/EE immediately Give signature 64kBytes Flash/EE 24-bit FEExSIGN MMR. This operation takes 32778 clock cycles. This command only once. value FEExPRO saved removed only with mass erase (0x06) with Reserved Reserved operation, interrupt generated
Burst termination Signature Protect Reserved Reserved Ping
FEExCON will always read 0x07 immediately after execution these commands.
Table FEE0PRO FEE0HID designations 30-0 Description Read protection Cleared user protect block user allow reading block Write protection pages 120, pages 116. pages Cleared user protect pages writing user allow writing pages Table FEE1PRO FEE1HID designations 31-0 Description Read protection Cleared user protect block user allow reading block Write Protection pages Cleared user protect pages writing user allow writing pages Write protection pages pages 116. pages Cleared user protect pages writing user allow writing pages
Rev. Page
Preliminary Technical Data
Execution time from SRAM FLASH/EE
This chapter describes SRAM Flash/EE access times during execution applications where execution time critical.
ADuC7128
that involve using Flash/EE data memory. instruction executed control flow instruction, extra cycle needed decode address program counter then four cycles needed fill pipe-line. data processing instruction involving only core register doesn't require extra clock cycle involves data Flash/EE, extra clock cycle needed decode address data cycles 32-bit data from Flash/EE. extra cycle must also added before fetching another instruction. Data transfer instruction more complex summarised Table Table execution cycles ARM/Thumb mode Instructions LDM/PUSH STRH STRM/POP Fetch cycles Dead time Data access 20µs 20µs 20µs Dead time
Execution from SRAM
Fetching instructions from SRAM takes clock cycle access time SRAM clock cycle 23ns minimum. However, instruction involve reading writing data memory, extra cycle must added data SRAM, three cycle data Flash/EE, cycle execute instruction cycles 32-bit data from Flash/EE. control flow instruction, example branch instruction will take cycle fetch also cycle fill pipeline with instructions.
Execution from Flash/EE
Because Flash/EE width 16-bit access time 16-bit words 23ns, execution from Flash/EE cannot done cycle from SRAM when Also some dead times needed before accessing data value bits. mode, where instructions bits, cycles needed fetch instruction when Thumb mode, where instructions bits, cycle needed fetch instruction. Timing identical both mode when executing instructions
With 1<N16, number data load store multiple load/store instruction. SWAP instruction combine instruction with only fetch giving total cycles plus 40µs.
Rev. Page
ADuC7128
RESET REMAP
exception vectors situated bottom memory array, from address 0x00000000 address 0x00000020 shown Figure
Preliminary Technical Data
Remap operation
When reset occurs ADuC7128, execution starts automatically factory programmed internal configuration code. This called kernel hidden cannot accessed user code. ADuC7128 normal mode high), will execute power-on configuration routine kernel then jump reset vector address, 0x00000000, execute users reset exception routine. Because Flash/EE mirrored bottom memory array reset, reset interrupt routine must always written Flash/EE. remap done from Flash/EE setting bit0 REMAP register. Precaution must taken execute this command from Flash/EE, above address 0x00080020, from bottom array this will replaced SRAM. This operation reversible: Flash/EE remapped address 0x00000000 clearing Bit0 REMAP MMR. Precaution must again taken execute remap function from outside mirrored area. kind reset will remap Flash memory bottom array.
FFFFFFFFh
kernel interrupt service routines
0008FFFFh
Flash/EE
00080000h
00041FFFh interrupt service routines 00040000h
SRAM
Mirror Space
exception 0x00000020 00000000h vector addresses 0x00000000
Figure remap exception execution
default after reset, Flash/EE mirrored bottom memory array. remap function allows programmer mirror SRAM bottom memory array, facilitating execution exception routines from SRAM instead from Flash/EE. This means exceptions executed twice fast, exception being executed mode bit) SRAM being 32-bit wide instead 16-bit wide Flash/EE memory.
Reset
There four kinds reset: external reset, Power-on-reset, watchdog expiation software force. RSTSTA register indicates source last reset RSTCLR allows clear RSTSTA register. These registers used during reset exception service routine identify source reset. RSTSTA null, reset external. Note: When clearing RSTSTA bits that currently must cleared, otherwise reset event will occur.
Table REMAP designations Name Remap Description Remap Bit. user remap SRAM address 0x00000000. Cleared automatically after reset remap Flash/EE memory address 0x00000000. Table RSTSTA designations Description Reserved Software reset user force software reset. Cleared setting corresponding RSTCLR Watchdog timeout automatically when watchdog timeout occurs Cleared setting corresponding RSTCLR Power-on-reset automatically when power-on-reset occurs Cleared setting corresponding RSTCLR
Rev. Page
Preliminary Technical Data
OTHER ANALOG PERIPHERALS
ADuC7128
ADuC7128 features 10-bit current which used generate user defined waveforms sine waves generated DDS. consists IDAC followed current voltage conversion. current output IDAC passed through resistor capacitor network where both filtered converted voltage. This voltage then buffered op-amp passed line driver. user optionally disable internal filter place external filter between VDAC AIN5. function internal 2.5v voltage reference must enabled driven onto external capacitor, i.e. REFCON 0x01. Once enabled users will drop internal reference value. This bias currents drawn from reference used circuitry. recommended that using then left powered avoid seeing variations results. Table DACCON designations 10-9 Description Shuffle increment time. Shuffle based internal counter. Shuffle based input data. Reserved.
Shuffle Enable Control user enable Shuffling Cleared user disable Shuffling Shuffle Enable Control user enable Shuffling Cleared user disable Shuffling Power Reduction Control user reduce power consumption line driver, this will also reduce performance circuit. Cleared user operate normal power mode. Output Enable. This operates modes user enable Line Drive output. Cleared user disable Line Driver output. this mode line driver output high impedance. Single ended Differential output Control. user operated differential mode, output differential voltage between LD1TX LD2TX voltage output range will Vref/2 Vref/2 Cleared user reference LD1TX output AGND voltage output rage will AVdd/2 Vref/2 Reserved, This should user. Operation Mode Control. This selects mode operation DAC. Powerdown Reserved Reserved mode, selected DACEN update rate control This effect when mode. user update negative edge Timer This allows user core clk, clk, baud clks user divide these down 32768. user waveform generation writing Data Register from update regular intervals timer1. Cleared user update negative edge HCLK.
Rev. Page
ADuC7128
DACEN Register
Name DACEN Address 0xFFFF06B8 Default Value 0x00
Preliminary Technical Data
Access
DACEN Designations
Description Reserved. user enable mode user enable mode
DACDAT Register
Name DACDAT Address 0xFFFF06B4 Description Reserved. 10-bit data Default Value 0x0000 Access
Table DACDAT Designations
DACDAT controls output DAC. data written this register bits signed value. This means that 0x0000 represents midscale, 0x0200 represents zero scale 0x01FF full scale. DACEN DACDAT require access, write these MMRs follow sequence below,
DACEN DACKEY0 0x07 DACEN User Value DACKEY1 0xB9 DACDAT DACKEY0 0x07 DACDAT User Value DACKEY1 0xB9
Rev. Page
Preliminary Technical Data
ADuC7128
used generate digital sine wave signal ADuC7128. enabled into free running mode user. Both phase frequency controlled. Table DDSCON designations Description Reserved Output Enable user enable output, this only effect selected DACCON Cleared user disable output. Reserved Binary Divide Control. Scale Ratio 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 0.000 0.125 0.250 0.375 0.500 0.625 0.750 0.875 1.000
DDSFRQ Register
Name DDSFRQ Address 0xFFFF0694 Description Default Value 0x00000000 Access
Table DACDAT Designations
Frequency controlled DDSFRQ MMR. This contains word (FSW, frequency select word) which controls frequency according following formula:
Frequency
20.8896MHz
Address 0xFFFF0698 Description Reserved. Phase Default Value 0x00000000 Access
DDSPHS Register
Name DDSPHS
Table DDSPHS Designations
Rev. Page
ADuC7128
Preliminary Technical Data
Phase offset controlled DDSPHS MMR. This contains value which controls phase output according following formula:
Phaseoffset
Phase
Rev. Page
Preliminary Technical Data
ADuC7128
POWER SUPPLY MONITOR
Power Supply Monitor monitors IOVDD supply ADuC7128. indicate when IOVDD supply drops below supply trip points. monitor function controlled PSMCON register. enabled IRQEN FIQEN register, monitor will interrupt core using PSMI PSMCON MMR. This will cleared immediately once goes high. Note that interrupt generated exited before goes high (i.e. IOVdd above trip point) then further interrupts will generated until returns high. user should ensure that code execution remains within until returns high.
This monitor function allows user save working registers avoid possible data loss supply brown-out conditions, also ensures that normal code execution will resume until safe supply level been established. will operate correctly when using JTAG debug. should disabled this mode.
Table PSMCON descriptions Name Description Comparator This read-only directly reflects state comparator Read indicates IOVDD supply above selected trip point. Read indicates IOVDD supply below selected trip point. Trip Point Selection Bits
PSMEN
PSMI
2.79V 3.07V Power Supply Monitor Enable user enable Power Supply Monitor circuit Clear user disable Power Supply Monitor circuit Power Supply Monitor Interrupt Bit. This will high MicroConverter low, indicating supply. PSMI used interrupt processor. Once returns high, PSMI cleared writing this location. write effect. There timeout delay, PSMI cleared immediately once goes high.
Rev. Page
ADuC7128
COMPARATOR
ADuC7128 also integrates uncommitted voltage comparator. positive input multiplexed with ADC2 negative input options: ADC3 internal reference. output comparator configured generate system interrupt, routed directly Programmable Logic Array, start conversion external pin, CMPOUT.
Preliminary Technical Data
COMPOUT
COMP0
Figure Comparator Hysteresis Transfer Function
Hysteresis
Figure shows input offset voltage hysteresis terms defined. Input offset voltage (VOS) difference between center hysteresis range ground level. This either positive negative. hysteresis voltage (VH) one-half width hysteresis range.
ADC2/CMP0 ADC3/CMP1 P0.0/CMP
START CONVERSION
Figure Comparator
comparator interface consists 16-bit MMR, CMPCON described below. Table CMPCON descriptions 15-11 CMPEN Name Description Reserved Comparator enable bit: user enable comparator, Note: comparator interrupt will generated enable comparator, this should cleared user software. Cleared user disable comparator Comparator negative input select bits: AVDD/2 ADC3 input Vref Reserved Comparator output configuration bits: connections disabled connections disabled Connections enabled Connections enabled Comparator output logic state When comparator output high when positive input (CMP0) above negative input (CMP1). When high, comparator output high when positive input below negative input Response time response time typical large signals (2.5 differential).
response time typical small signals (0.65 differential).
CMPIN
CMPOC
CMPOL
CMPRES
Reserved Reserved
response time typical signal type.
Rev. Page
04955-063
Preliminary Technical Data
CMPHYST Comparator hysteresis bit: user have hysteresis about 7.5mV Cleared user have hysteresis Comparator output rising edge interrupt automatically when rising edge occurs monitored voltage (CMP0) Cleared user writing this bit. Comparator output falling edge interrupt automatically when falling edge occurs monitored voltage (CMP0) Cleared user
ADuC7128
CMPORI
CMPOFI
Rev. Page
ADuC7128
Preliminary Technical Data
OSCILLATOR POWER CONTROL
ADuC7128 integrates 32.768kHz oscillator, clock divider PLL. locks onto multiple (1275) internal oscillator provide stable 41.78 clock system. core operate this frequency, binary submultiples allow power saving. default core clock clock divided MHz. core clock frequency outputted ECLK described GPIO section. power down mode available ADuC7128. operating mode, clocking mode programmable clock divider controlled MMRs, PLLCON POWCON. PLLCON controls operating mode clock system while POWCON controls core clock frequency powerdown mode.
WATCHDOG TIMER WAKEUP TIMER POWER OCLK 32.768kHz 41.78MHz MDCLK CORE 32.768kHz +/-3% UCLK HCLK ANALOG PERIPHERALS P0.7/XCLK INT. 32kHz OSCILLATOR CRYSTAL OSCILLATOR XCLKO XCLKI
Figure clocking system
External Crystal Selection
switch external crystal, clear OSEL PLLCON (see Table 31). noisy environments, noise might couple external crystal pins could loose lock momentary. interrupt provided interrupt controller. core clock halted immediately this interrupt only serviced once lock been restored. case crystal loss, watchdog timer should used. During initialisation test RSTSTA determine reset came from watchdog timer.
External Clock Selection
switch external clock P0.7, configure P0.7 Mode MDCLK bits External clock providing tolerance
P0.7/ECLK
Rev. Page
Preliminary Technical Data
Power Control System
ADuC7128
choice operating modes available ADuC7128. Table describes what part ADuC7128 powered different modes indicates power-up time. Table gives some typical values total current consumption (analog digital supply currents) different modes depending clock divider bits. turned off. Note that these values also include current consumption regulator other parts test board which these values were measured. Table Operating Modes
Mode Active Pause Sleep Stop Core Peripherals XTAL/T2/T3 XIRQ Start /power Time 3.06 3.06
Table Typical Current Consumption 25°C
PC[2-0] Mode Active Pause Sleep Stop
MMRs Keys
operating mode, clocking mode programmable clock divider controlled MMRs, PLLCON (see Table POWCON (see Table 32). PLLCON controls operating mode clock system, while POWCON controls core clock frequency power-down mode. prevent accidental programming, certain sequence, shown Table followed write PLLCON POWCON registers.
POWCON Register
Name POWCON Address 0xFFFF0408 Default Value 0x0003 Access
Table PLLCON Designations
Value Name OSEL Description Reserved. input selection. user internal oscillator. default. Cleared user external crystal. Reserved. Clocking modes. Reserved. PLL. Default configuration. Reserved. External clock P0.7 pin.
PLLKEYx Register
Name PLLKEY1 PLLKEY2 Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access
MDCLK
PLLCON Register
Name PLLCON Address 0xFFFF0414 Default Value 0x21 Access
POWKEYx Register
Name POWKEY1 POWKEY2 Address 0xFFFF0404 0xFFFF040C Default Value 0x0000 0x0000 Access
Rev. Page
ADuC7128
Table POWCON Designations
Value Name Description Reserved. Operating modes. Active mode. Pause mode. Nap. Sleep mode. XIRQ0, XIRQ1, Timer2, Timer3 wake-up ADuC7128 Stop mode. Reserved. Reserved clock divider bits. 41.779200 20.889600 10.444800 5.222400 2.611200 1.305600 654.800 326.400
Preliminary Technical Data
Others RSVD
Table PLLCON POWCON Write Sequence
PLLCON PLLKEY1 0xAA PLLCON 0x01 PLLKEY2 0x55 POWCON POWKEY1 0x01 POWCON User Value POWKEY2 0xF4
Rev. Page
Preliminary Technical Data
DIGITAL PERIPHERALS
General overview
ADuC7128 integrates channel interface. outputs configured drive H-Bridge used standard outputs. power outputs default H-Bridge mode. This ensures that motor turned default. standard mode outputs arranged pairs pins. Users have control over period each pair outputs duty cycle each individual output.
ADuC7128
following MMRs Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Function Control Compare register o/ps Compare register o/ps Compare register o/ps Frequency Control o/ps Compare register o/ps Compare register o/ps Compare register o/ps Frequency Control o/ps Compare register o/ps Compare register o/ps Compare register o/ps Frequency Control o/ps Convert Start Control Interrupt Clear
clock selectable PWMCON1 with following values, UCLK 256. length period defined PWMxLEN. waveforms count value 16-bit timer compare registers contents shown with PWM1 PWM2 waveforms above. low-side waveform, PWM2, goes high when timer count reaches PWM1LEN, goes when timer count reaches value held PWM1COM3 when high-side waveform PWM1 goes low. high-side waveform, PWM1, goes high when timer count reaches value held PWM1COM1, goes when timer count reaches value held PWM1COM2. Table PWMCON1 Designations
Value Name SYNC Description Enables synchronization user that counters reset next clock edge after detection high transition SYNC pin. Cleared user ignore transitions SYNC pin. user invert PWM6 Cleared user PWM6 normal mode. user invert PWM4 Cleared user PWM4 normal mode. user invert PWM2 Cleared user PWM2 normal mode. user enable trip interrupt. When PWMTRIP input PWMEN cleared interrupt generated.
modes PWMxCOMx MMRs controls point which outputs change state. example first pair outputs PWM1 PWM2) shown below. Figure Timing.
PWM6INV
PWM4NV
PWM2INV
PWMTRIP
Rev. Page
ADuC7128
Cleared user diable PWMTRIP interrupt. HOFF HMODE user enable outputs Cleared user disable outputs. HOFF=1 HMODE=1, table H-Bridge mode this effect. Clock prescaler bits. Sets UCLCK divider. user invert outputs Cleared user outputs normal. High side off. user force PWM1 PWM3 outputs high, this also forces PWM2 PWM4 low. Cleared user outputs normal Load compare regiseters. user load internal compare registers with values PWMxCOMx next transition timer from 0x00 0x01. Cleared user values previously stored internal compare registers. Direction Control user enalble PWM1 PWM2 output signals while PWM3 PWM4 held low. Cleared user enable PWM3 PWM4 output signals while PWM2 held low. Enables H-Bridge mode user enable HBridge mode bits PWMCON1. Cleared user operate PWMs standard mode. user enable outputs.
Preliminary Technical Data
H-Bridge mdoe i.e. HMODE then table below determines outputs. High side, side Table PWMCOM1 HOFF POINV Outputs
PWM1 PWM2 PWMR3 PWM4
PWMCP2 PWMCP1 PWMCP0
POINV
HOFF
Note POWERUP PWMCON1 defaults 0x12 i.e. HOFF HMODE GPIO pins associated with configured mode default. compare registers detailed below.
LCOMP
Name PWM1COM1 PWM1COM2 PWM1COM3 PWM2COM1 PWM2COM2 PWM2COM3 PWM3COM1 PWM3COM2 PWM3COM3
Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC
Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Access
Trip interrupt cleared writing PWMICLR MMR. Note: When using trip interrupt users should make sure that interrupt been cleared before exiting ISR. This avoids multiple interrupts being generated. Convert Start Control configured generated convert start signal after active side signal goes high. There programmable delay between when side signal goes high Convert Start signal generated. This controlled PWMCON2 MMR. delay
HMODE
PWMEN
Rev. Page
Preliminary Technical Data
selected higher than width pulse, interrupt will remain low. Table PWMCON2 Designations
Value Name CSEN Description user enable generate convert start signal. Cleared user diable convert start signal. Convert Start Delays. Delay convert start signal number clock pulses.
ADuC7128
CSD3 CSD2 CSD1 CSD0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
When calculating time from convert start delay start conversion user needs take account internal delays. example below shows case delay clocks. additional clock required pass convert start signal logic. Once logic receives convert start signal conversion will begin next clock edge. figure section.
Uclock
Side
Count
Signal Convst
Signal Passed Logic
Rev. Page
ADuC7128
Quadrature Encoder quadrature encoder used determine both speed direction rotating shaft. it's most common form there digital outputs shaft rotates both will toggle, however they will phase. leading output determines direction rotation. time between each transition indicates speed rotation. Input Filtering
Preliminary Technical Data
Filtering applied input setting FILTEN QENCON. normally acts clock counter, however filter used ignore positive edges unless there been high pulse between positive edges (See figure
Figure Input Filtering Table QENCON Designations
1511 Value Name Description Reserved. user enable filtering Cleared user disable filtering pin. Reserved, This should user. user invert intput. Cleared user input normal. DIRCON set, then S2INV controls direction counter. this case: user operate counter increment mode. Cleared user operate counter decrement mode. user invert intput. Cleared user input normal. Direction Control. user enable input counter clock. driection counter controlled S2INV bit. Cleared user operated normal mode. user geneate when high transition
Figure Quadrate Encoder Input Values quadrature encoder takes incremental input shown above increments decrements counter depending direction speed rotating shaft. ADuC7128, internal counter clocked rising edge input, input indicates direction rotation/count. counter increments when high decrements when low. addition, software prior knowledge direction rotation. Then input ignored (S2) other clock (S1). added flexibility, inputs internally inverted prior use. Quadrature Encoder operates asynchronously from system clock.
FILTEN
RSVD S2INV
S1INV
DIRCON
S1IRQEN
Rev. Page
Preliminary Technical Data
detected Cleared user disable interrupt. This should user. Underflow enable. user generate interrupt QENVAL underflows. Cleared user disable interrupt. Overflow enable. user generate interrupt QENVAL overflows. Cleared user disable interrupt. This should user. Enable Quadrature Encoder user enable quadrature encoder. Cleared user diable quadrature encoder.
ADuC7128
QENDAT. Table QENVAL
Name QENVAL Address 0xFFFF0F0C Default Value 0x0000 Access
RSVD UIRQEN
This register contains current value Quadrature Encoder counter. Table QENCLR
Name QENCLR Address 0xFFFF0F14 Default Value 0x00000000 Access
OIREQEN
Writing value this register clears QENVAL register 0x0000. bits this register undefined. Table QENSET
Name QENSET Address 0xFFFF0F18 Default Value 0x00000000 Access
RSVD ENQEN
Writing value this register loads QENVAL register with value QENDAT. bits this register undefined. Note:
Table QENSTA Designations
Value Name S1EDGE Description Reserved. rising edge. This automatically rising edge Cleared reading QENSTA Reserved. Underflow flag This automatically underflow occurs. Cleared read QENSTA This automatically overflow occurred. Cleared reading QENSTA Direction counter hardare idicate that counter incrementing. hardware indicate that counter decrementing.
interrupt conditions ORed together form interrupt interrupt controller. Interrupt Service Routine should check QENSTA register find cause interrupt. inputs shall appear QENS1 QENS2 inputs GPIO list. motor speed measured using capture facility Timer Timer overflow either timer checked using checking IRQSIG. counter with quadrature encoder gray encoded ensure reliable data transfer across clock boundaries. When underflow overflow occurs count value does jump other scale, instead direction count changes. When this happens value QENDAT subtracted from value derived from gray count. When value QENDAT changes value read back from QENVAL changes, however gray encoded value will change. This will only occur after underflow overflow. value QENDAT changes then there must write QENSET QENCLR ensure that valid number read back from QENVAL.
RSVD UNDER
OVER
Table QENDAT
Name QENDAT Address 0xFFFF0F08 Default Value 0Xffff Access
This register holds maximum value allowed QENVAL register. QENVAL register increments past value this register then overflow condition occurs. When overflow occurs QENVAL register reset 0x0000. When QENVAL register decrements past zero during underflow will loaded with value
Rev. Page
ADuC7128
GENERAL PURPOSE
ADuC7128 provides general purpose, bi-directional (GPIO) pind. pins tolerant, which means that GPIOs support input voltage general, many GPIO pins have multiple functions (see function definitions page 14). default, GPIO pins configured GPIO mode. GPIO pins have internal pull-up resistor about their drive capability Note that maximum GPIO drive same time. following GPIO have programmable pull P0.0, P0.4, P0.5, P0.6, P0.7, GPIOs GPIO grouped ports, Port Port Each port controlled four five MMRs, representing port number.
P1.7 P2.0 P2.12 P2.22 P2.32 P2.42 P2.52 P2.62 P2.72 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.62 P3.72 P4.0 P4.1 P4.2 P4.3
Preliminary Technical Data
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO DTR0 SYNC RTS1 CTS1 DCD1 DSR1 DTR1 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM1 PWM3 QENS1 QENS2 RSVD Trip (Shutdown) P4.4 P4.5 P4.6 P4.7
GPxCON Register
Name GP0CON GP1CON GP2CON GP3CON GP4CON Address 0xFFFF0D00 0xFFFF0D04 0xFFFF0D08 0xFFFF0D0C 0xFFFF0D10 Default Value 0x00000000 0x00000000 0x00000000 Access
SOUT AD10 AD11
PLAO[0] PLAO[5] PLAO[6] PLAO[7]
PLAI[8] PLAI[9] PLAI[10] PLAI[11] PLAI[12] PLAI[13] PLAI[14] PLAI[15] PLAO[8] PLAO[9] PLAO[10] PLAO[11]
GPIO GPIO GPIO GPIO
0x11111111
0x00000000
PLMIN PLMOUT SIN1 SOUT1
AD12 AD13 AD14 AD15
PLAO[12] PLAO[13] PLAO[14] PLAO[15]
Note that kernel changes P0.6 from default configuration reset (MRST) GPIO mode. MRST used external circuitry, external pull-up resistor should used insure that level P0.6 does drop when kernel switches mode. example, MRST required power down, reconfigured GP0CON MMR. GPxCON port control register, selects function each port described Table Table GPIO Function Descriptions
Port P0.0 P0.12 P0.22 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 GPIO GPIO GPIO GPIO GPIO/IRQ0 GPIO/IRQ1 GPIO/T1 GPIO GPIO/T1 GPIO GPIO GPIO GPIO/IRQ2 GPIO/IRQ3 GPIO Configuration TRST CONVSTART ADCBUSY PLM_COMP MRST ECLK/XCLK1 SIN0 SIN0 SCL0 SOUT0 SDA0 RTS0 SCL1 CTS0 SDA1 DCD0 MISO DSR0 MOSI
When configured Mode PO.7 ECLK default, core clock output. configure clock output, MDCLK bits PLLCON must Only available ADuC7129 part.
Table GPxCON Descriptions
Description Reserved Select function Px.7 Reserved Select function Px.6 Reserved Select function Px.5 Reserved Select function Px.4 Reserved Select function Px.3 Reserved Select function Px.2 Reserved Select function Px.1 Reserved Select function Px.0
PLAI[7] ADCBUSY PLAO[1] PLAO[2] PLAO[3] PLAO[4] PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6]
Rev. Page
Preliminary Technical Data
GPxPAR Register
Name GP0PAR GP1PAR GP3PAR GP4PAR Address 0xFFFF0D2C 0xFFFF0D3C 0xFFFF0D5C 0xFFFF0D6C Default Value 0x20000000 0x00000000 0x00222222 0x00000000 Access
ADuC7128
Reflect state port pins reset (read only). Port data input (read only).
GPxSET Register
Name GP0SET GP1SET GP2SET GP3SET GP4SET Address 0xFFFF0D24 0xFFFF0D34 0xFFFF0D44 0xFFFF0D54 0xFFFF0D64 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access
GPxPAR programs parameters Port Port 1,,Port Port Note that GPxDAT must always written after changing GPxPAR MMR. Table GPxPAR Descriptions
Description Reserved Pull disable Px.7 Reserved Pull disable Px.6 Reserved Pull disable Px.5 Reserved Pull disable Px.4 Reserved Pull disable Px.3 Reserved Pull disable Px.2 Reserved Pull disable Px.1 Reserved Pull disable Px.0
GPxSET data port register. Table GPxSET Descriptions
Description Reserved. Data port bit. user port also sets corresponding GPxDAT MMR. Clear user; does affect data out. Reserved.
GPxCLR Register
Name GP0CLR GP1CLR GP2CLR GP3CLR GP4CLR Address 0xFFFF0D28 0xFFFF0D38 0xFFFF0D48 0xFFFF0D58 0xFFFF0D68 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access
GPxCLR data clear port register.
GPxDAT Register
Name GP0DAT GP1DAT GP2DAT GP3DAT GP4DAT Address 0xFFFF0D20 0xFFFF0D30 0xFFFF0D40 0xFFFF0D50 0xFFFF0D60 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access
Table GPxCLR Descriptions
Description Reserved. Data port clear bit. user clear port also clears corresponding GPxDAT MMR. Clear user does affect data out. Reserved.
GPxDAT port configuration data register. configures direction GPIO pins port sets output value pins configured output, receives stores input value pins configured input. Table GPxDAT Descriptions
Description Direction data. user configure GPIO output. Clear user configure GPIO input. Port data output.
Rev. Page
ADuC7128
SERIAL PORT
Serial Port multiplexes serial port peripherals (two I2C, SPI, UARTs) Programmable Logic Array (PLA) GPIO pins. Each must configured specific function described Table GPIO P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.7 P2.01 P2.21 P2.31 P2.41 P2.51 P2.61 P2.71 P4.6 P4.7 UART SIN0 SOUT0 RTS0 CTS0 DCD0 DSR0 DTR0 ECLK PWMSYNC RTS1 CTS1 DCD1 DSR1 DTR1 SIN1 SOUT1 UART/I2C/SPI I2C0SCL I2C0SDA I2C1SCL I2C1SDA SPICLK SPIMISO SPIMOSI SPICSL SIN0 SOUT0
Preliminary Technical Data
SPM0 SPM1 SPM2 SPM3 SPM4 SPM5 SPM6 SPM7 SPM8 SPM9
SPM10 SPM11 SPM12 SPM13 SPM14 SPM15 SPM16 SPM17
PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6] PLAO[0] PLAO[4] PLAO[5] PLAO[7]
SPM0 (mode SPM1 (mode SPM2 (mode SPM3 (mode SPM4 (mode SPM5 (mode SPM6 (mode SPM7 (mode SPM8 (mode SPM9 (mode
Signal SIN0 SOUT0 RTS0 CTS0 DCD0 DSR0 DTR0 SIN0 SOUT0
Description Serial Receive Data Serial Transmit Data Request Send Clear Send Ring Indicator Data Carrier Detect Data Ready Data Terminal Ready Serial Receive Data Serial Transmit Data
Table UART signal description
serial communication adopts asynchronous protocol that supports various word length, stop bits parity generation options selectable configuration register.
Baud rate generation
There generating UART baudrate. Normal UART baudrate generation: baudrate divided version core clock using value COM0DIV0 COM0DIV1 MMRs (16-bit value, DL).
Baud rate 41.78
AD14 AD15
PLAO[14] PLAO[15]
Table configuration
Only available part.
following table gives some common baudrate values:
Baud Rate 9600 19200 115200 9600 19200 115200 Actual Baud Rate 9600 19200 118691 9600 20400 163200 Error 6.25% 41.67%
Table details mode each SPMUX GPIO pins. This configuration done GP0CON, GP1CON GP2CON MMRs. default these pins configured GPIOs.
UART SERIAL INTERFACE
ADuC7128 contains identical UART blocks. Only UART0 described here, UART1 functions exact same manner. UART peripheral full-duplex Universal Asynchronous Receiver/Transmitter, fully compatible with 16450 serial port standard. UART performs serial-to-parallel conversion data characters received from peripheral device MODEM, parallel-to-serial conversion data characters received from CPU. UART includes fractional divider baudrate generation network addressable mode. UART function made available following pins ADuC7128:
Table baudrate using normal baudrate generator
Using fractional divider: fractional divider combined with normal baudrate generator allows generating wider range more accurate baudrates.
Rev. Page
Preliminary Technical Data
Core Clock FBEN
ADuC7128
UART registers definition
UART interface consists registers namely:
/16DL /(M+N/2048)
UART
Figure baudrate generation options
Calculation baudrate using fractional divider follow:
Baud rate
41.78 2048
41.78 2048 Baud rate
example: Generation 19200 baud with bits (Table gives
41.78 2048 19200
COMxTX: 8-bit transmit register COMxRX: 8-bit receive register COMxDIV0: divisor latch (low byte) COMTX, COMRX COMDIV0 share same address location. COMTX COMTX accessed when COMCON0 register cleared. COMDIV0 accessed when COMCON0 set. COMxDIV1: divisor latch (high byte) COMxCON0: line control register COMxSTA0: line status register COMxIEN0: interrupt enable register COMxIID0: interrupt identification register COMxCON1: modem control register COMxSTA1: modem status register COMxDIV2: 16-bit fractional baud divide register COMxSCR: 8-bit scratch register used temporary storage. Also used network addressable UART mode.
1.06 2048
where: 0.06 2048
Baud rate 41.78 2048
where: Baud rate 19200 Error compared 6.25% with normal baud rate generator.
Table COMxCON0 Descriptions Name DLAB Description Divisor latch access user enable access COMDIV0 COMDIV1 registers Cleared user disable access COMDIV0 COMDIV1 enable access COMRX COMTX break. user force SOUT Cleared operate normal mode Stick parity user force parity defined values: Even parity select even parity Cleared parity
Rev. Page
ADuC7128
STOP
Preliminary Technical Data
Parity enable bit: user transmit check parity Cleared user parity transmission checking Stop user transmit Stop Word Length bits Stop bits word length bits. receiver checks first Stop only, regardless number Stop bits selected Cleared user generate Stop transmitted data Word length select: bits bits bits bits
Rev. Page
Preliminary Technical Data
Table COMxSTA0 Descriptions TEMT THRE Name Description Reserved COMTX empty status automatically COMTX empty Cleared automatically when writing COMTX COMTX COMRX empty automatically COMTX COMRX empty Cleared automatically when register receives data Break error when held more than maximum word length Cleared automatically Framing error when invalid stop Cleared automatically Parity error when parity error occurs Cleared automatically Overrun error automatically data overwrite before been read Cleared automatically Data ready automatically when COMRX full Cleared reading COMRX
ADuC7128
Table COMxIEN0 Descriptions EDSSI ELSI ETBEI ERBFI Name Description Reserved Modem status interrupt enable user enable generation interrupt COMSTA1[3:0] Cleared user status interrupt enable user enable generation interrupt COMSTA0[3:0] Cleared user Enable transmit buffer empty interrupt user enable interrupt when buffer empty during transmission Cleared user Enable receive buffer full interrupt user enable interrupt when buffer full during reception Cleared user
Table COMxIID0 Descriptions Status bits NINT interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt Read COMSTA0 Read COMRX Write data COMTX read COMIID0 Read COMSTA1 register Priority Definition Clearing operation
Rev. Page
ADuC7128
LOOPBACK Name Description Reserved
Preliminary Technical Data
Table COMxCON1 Descriptions
Loop back user enable loop back mode. loop back mode SOUT forced high. Also modem signals directly connected status inputs (RTS CTS, DSR, OUT1 OUT2 DCD) Request send user force output Cleared user force output Data terminal ready user force output Cleared user force output
Table COMxSTA1 Descriptions Name DDCD TERI DDSR DCTS Description Data carrier detect Ring indicator Data ready Clear send Delta automatically changed state since COMSTA1 last read Cleared automatically reading COMSTA1 Trailing edge changed from since COMSTA1 last read Cleared automatically reading COMSTA1 Delta automatically changed state since COMSTA1 last read Cleared automatically reading COMSTA1 Delta automatically changed state since COMSTA1 last read Cleared automatically reading COMSTA1
Table COMxDIV2 Descriptions 14-13 12-11 10-0 FBM[1-0] FBN[10-0] Name FBEN Description Fractional baudrate generator enable user enable fractional baudrate generator Cleared user generate baudrate using standard UART baudrate generator Reserved
Rev. Page
Preliminary Technical Data
Network addressable UART mode
This mode allows connecting MicroConverter 256node serial network, either hardware single-master software multi-master network. COMxIEN1 (ENAM bit) must enable UART network addressable mode. Note that there parity check this mode, parity used address.
ADuC7128
network address mode, least significant scratch register transmitted network address control bit. device transmitting address. cleared device transmitting data. COMxIEN1: 8-bit network enable register. COMxIID1: 8-bit network interrupt register. reserved. Table COMxADR: 8-bit read write network address register. Holds address network addressable UART checks for. receiving this address device interrupts processor and/or sets appropriate status COMIID1. COMIEN1, COMIID1 COMADR used only network addressable UART mode.
Network addressable UART register definitions
Three additional register: COMxSCR: 8-bit scratch register used temporary storage.
Table COMxIEN1 Descriptions Name ENAM E9BT E9BR E9BD NABP Description Network address mode Enable user enable network address mode cleared user disable network address mode 9-bit transmit enable user enable 9-bit transmit. ENAM must Cleared user disable 9-bit transmit 9-bit receive enable user enable 9-bit receive. ENAM must Cleared user disable 9-bit receive network interrupt Enable Word length 9-bit data. E9BT cleared. Cleared 8-bit data Transmitter driver Enable user enable SOUT output slave mode multi-master mode Cleared user, SOUT three-state Network address bit, interrupt polarity Network address user transmit slave's address Cleared user transmit data
Table COMxIID1 Descriptions Status bits NINT interrupt Matching network address Address transmitted, buffer empty Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt Read COMxRX Write data COMTX read COMxIID0 Read COMxSTA0 Read COMxRX Write data COMxTX read COMxIID0 Read COMxSTA1 register priority Definition Clearing operation
Rev. Page
ADuC7128
SERIAL PERIPHERAL INTERFACE
ADuC7128 integrates complete hardware serial peripheral interface (SPI) on-chip. industry standard synchronous serial interface that allows eight bits data synchronously transmitted simultaneously received, that full duplex maximum rate interface only operational with core clock divider bits POWCON[2:0] port configured master slave operation typically consists four pins, namely: MISO, MOSI, SCL,
Preliminary Technical Data
Chip Select (CS) Input
slave mode, transfer initiated assertion which active input signal. port then transmits receives 8-bit data until transfer concluded desassertion slave mode, always input.
Registers
following registers used control interface: SPISTA, SPIRX, SPITX, SPIDIV, SPICON.
SPISTA Register
Name SPISTA Address 0xFFFF0A00 Default Value 0x00 Access
MISO (Master Slave Out) Data
MISO configured input line master mode output line slave mode. MISO line master (data should connected MISO line slave device (data out). data transferred byte wide (8-bit) serial data, first.
SPISTA 8-bit read only status register. Table SPISTA Descriptions
Description Reserved. SPIRX data register overflow status bit. SPIRX overflowing. Cleared reading SPISRX register. SPIRX data register IRQ. automatically set. Cleared reading SPIRX register. SPIRX data register full status bit. automatically valid data present SPIRX register. Cleared reading SPIRX register. SPITX data register underflow status bit. automatically SPITX under flowing. Cleared writing SPITX register. SPITX data register IRQ. automatically clear set. Cleared writing SPITX register finished transmission disabling SPI. SPITX data register empty status bit. writing SPITX send data. This during transmission data. Cleared when SPITX empty.
MOSI (Master Out, Slave
MOSI configured output line master mode input line slave mode. MOSI line master (data out) should connected MOSI line slave device (data in). data transferred byte wide (8-bit) serial data, first.
(Serial Clock)
master serial clock (SCL) used synchronize data being transmitted received through MOSI period. Therefore, byte transmitted/received after eight periods. configured output master mode input slave mode. master mode, polarity phase clock controlled SPICON register, rate defined SPIDIV register follows:
SPIRX Register
Name SPIRX Address 0xFFFF0A04 Default Value 0x00 Access
SPIRX 8-bit read only receive register.
serialclock
HCLK SPIDIV
SPITX Register
Name SPITX Address 0xFFFF0A08 Default Value 0x00 Access
slave mode, SPICON register must configured with phase polarity expected input clock. slave accepts data from external master both master slave modes, data transmitted edge signal sampled other. Therefore, important that polarity phase configured same master slave devices.
SPITX 8-bit write only transmit register.
SPIDIV Register
Name SPIDIV Address 0xFFFF0A0C Default Value 0x1B Access
SPIDIV 8-bit serial clock divider register.
Rev. Page
Preliminary Technical Data
SPICON Register
Name SPICON Address 0xFFFF0A10 Default Value 0x0000 Access
ADuC7128
SPICON 16-bit control register.
Table SPICON Descriptions
Description Reserved. Continuous Transfer Enable. user enable continuous transfer. master mode, transfer continues until valid data available register. asserted remains asserted duration each 8-bit serial transfer until empty. Cleared user disable continuous transfer. Each transfer consists single 8-bit serial transfer. valid data exists SPITX register, then transfer initiated after stall period. Loop Back Enable. user connect MISO MOSI test software. Cleared user normal mode. Slave Output Enable. user enable slave output. Cleared user disable slave output. Slave Select Input Enable. user master mode enable output. SPIRX Overflow Overwrite Enable. user, valid data register overwritten serial byte received. Cleared user, serial byte received discarded. SPITX Underflow Mode. user transmit Cleared user transmit previous data. Transfer Interrupt Mode (Master Mode). user initiate transfer with write SPITX register. Interrupt occurs when empty. Cleared user initiate transfer with read SPIRX register. Interrupt occurs when full. First Transfer Enable Bit. user, transmitted first. Cleared user, transmitted first. Reserved. Should Serial Clock Polarity Mode Bit. user, serial clock idles high. Cleared user, serial clock idles low. Serial Clock Phase Mode Bit. user, serial clock pulses beginning each serial transfer. Cleared user, serial clock pulses each serial transfer. Master Mode Enable Bit. user enable master mode. Cleared user enable slave mode. Enable Bit. user enable SPI. Cleared disable SPI.
Rev. Page
ADuC7128
COMPATIBLE INTERFACES
ADuC7128 supports fully licensed interfaces. interfaces both implemented full hardware master slave interface. Because interfaces identical, this document describes only I2C0 detail. Note that masters slaves have individual interrupts.
Preliminary Technical Data
register corresponds DIVH:DIVL.
Slave Addresses
registers I2C0ID0, I2C0ID1, I2C0ID2 I2C0ID3 contain device IDs. device compares four I2C0IDx registers address byte. seven most significant bits either register must identical that seven most significant bits first address byte received correctly addressed. registers, transfer direction bit, ignored process address recognition.
pins used data transfer, SCL, configured Wired-AND format that allows arbitration multi-master system. peripheral's addresses system programmed user. This modified time transfer progress. user configure interface respond four slave addresses. transfer sequence system consists master device initiating transfer generating start condition while idle. master transmits address slave device direction data transfer initial address transfer. master does loose arbitration slave acknowledges, then data transfer initiated. This continues until master issues stop condition becomes idle. peripheral master slave functionality independent simultaneously active. slave activated when transfer been initiated bus. addressed, remains inactive until another transfer initiated. This also allows master device, which looses arbitration, respond slave same cycle.
Registers
peripheral interface consists MMRs, which discussed this section.
I2CxMSTA Register
Name I2C0MSTA I2C1MSTA Address 0xFFFF0800 0xFFFF0900 Default Value 0x00 0x00 Access
I2CxMSTA status register master channel. Table I2C0MSTA Descriptions
Description Master busy. automatically master busy. Cleared automatically. Arbitration loss. multi-master mode another master bus. Cleared when becomes available. ACK. automatically. master receive FIFO full, master does acknowledge data received. Cleared automatically. Master receive FIFO overflow. automatically master receive FIFO overflowing. Cleared automatically reading I2C0MRX. Master receive IRQ. after receiving data. Cleared automatically reading I2C0MRX register. Master transmit IRQ. transmission. Cleared automatically writing I2C0MTX register. Master transmit FIFO underflow. automatically master transmit FIFO underflowing. Cleared automatically writing I2C0MTX register. Master FIFO empty. automatically master transmit FIFO empty. Cleared automatically writing I2C0MTX register.
Serial Clock Generation
master system generates serial clock transfer. master channel configured operate fast mode (400 kHz) standard mode (100 kHz). rate defined I2C0DIV follows:
serialclock
UCLK DIVH DIVL)
where: fUCLK clock before clock divider DIVH high period clock DIVL period clock.
Thus, operation, DIVH DIVL kHz, DIVH DIVL
Rev. Page
Preliminary Technical Data
I2CxSSTA Register
Name I2C0SSTA I2C1SSTA Address 0xFFFF0804 0xFFFF0904 Default Value 0x01 0x01 Access
ADuC7128
I2CxSSTA status register slave channel.
Table I2CxSSTA Descriptions
Value Description Reserved. These bits should written START decode bit. hardware device receives valid START matching address. Cleared stop condition general call reset. Repeated START decode bit. hardware device receives valid repeated start matching address. Cleared stop condition, read I2CSSTA register, general call reset. decode bits. Received address matched register Received address matched register Received address matched register Received address matched register Stop after start matching address interrupt. hardware slave device receives STOP condition after previous START condition matching address. Cleared read I2CxSSTA register. General call general call. General call reset program address. General call program address. General call matching alternative General call interrupt. Slave Busy. automatically slave busy. Cleared automatically. ACK. master asking data data available. Cleared automatically. Slave receive FIFO overflow. automatically slave receive FIFO overflowing. Cleared automatically reading I2C0SRX. Slave receive IRQ. after receiving data. Cleared automatically reading I2C0SRX register. Slave Transmit IRQ. transmission. Cleared automatically writing I2C0STX register. Slave transmit FIFO underflow. automatically slave transmit FIFO underflowing. Cleared automatically writing I2C0STX register. Slave transmit FIFO empty. automatically slave transmit FIFO empty. Cleared automatically writing I2C0STX register.
I2CxSRX Register
Name I2C0SRX I2C1SRX Address 0xFFFF0808 0xFFFF0908 Default Value 0x00 0x00 Access
I2CxSRX receive register slave channel.
I2CxSTX Register
Name I2C0STX I2C1STX Address 0xFFFF080C 0xFFFF090C Default Value 0x00 0x00 Access
I2CxSTX transmit register slave channel.
I2CxMRX Register
Name I2C0MRX I2C1MRX Address 0xFFFF0810 0xFFFF0910 Default Value 0x00 0x00 Access
I2CxMRX receive register master channel.
I2CxMTX Register
Name I2C0MTX I2C1MTX Address 0xFFFF0814 0xFFFF0914 Default Value 0x00 0x00 Access
I2CxSTX transmit register master channel.
I2CxCNT Register
Name I2C0CNT I2C1CNT Address 0xFFFF0818 0xFFFF0918 Default Value 0x00 0x00 Access
I2CxCNT master receive data count register. master read transfer sequence initiated, I2CxCNT register denotes number bytes (-1) read from slave device. default this counter which corresponds expected byte
I2CxADR Register
Name I2C0ADR I2C1ADR Address 0xFFFF081C 0xFFFF091C Default Value 0x00 0x00 Access
I2CxADR master address byte register. I2CxADR value device address that master wants communicate with. automatically transmitted start master transfer sequence there valid data I2CxMTX register when master enable set.
Rev. Page
ADuC7128
I2CxBYTE Register
Name I2C0BYT I2C1BYT Address 0xFFFF0824 0xFFFF0924 Default Value 0x00 0x00 Access
Preliminary Technical Data
I2CxALT hardware general call register used slave mode
I2CxCFG Register
Name I2C0CFG I2C1CFG Address 0xFFFF082C 0xFFFF092C Default Value 0x00 0x00 Access
I2CxBYTE broadcast byte register.
I2CxALT Register
Name I2C0ALT I2C1ALT Address 0xFFFF0828 0xFFFF0928 Default Value 0x00 0x00 Access
I2CxCFG configuration register.
Table I2C0CFG Descriptions
Description Reserved. These bits should written user Enable stop interrupt. user generate interrupt upon receiving stop condition after receiving valid start condition matching address. Cleared user disable generation interrupt upon receiving stop condition. Reserved. This should written user Reserved. This should written user Enable stretch (holds low). user stretch line. Cleared user disable stretching line. Reserved. This should written user Slave FIFO request interrupt enable. Cleared user gene
Other recent searches
SG16AA - SG16AA SG16AA Datasheet
RS507 - RS507 RS507 Datasheet
PM4318 - PM4318 PM4318 Datasheet
TM01108 - TM01108 TM01108 Datasheet
MMBT591A - MMBT591A MMBT591A Datasheet
HY5DU281622DT-6 - HY5DU281622DT-6 HY5DU281622DT-6 Datasheet
CSTCE20M0V53-R0 - CSTCE20M0V53-R0 CSTCE20M0V53-R0 Datasheet
2SD2414 - 2SD2414 2SD2414 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
