80x16 Icon line Segment Common Driver with Controller Character Displa

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80x16 Icon line Segment Common Driver with Controller Character Displa

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SSD1800
80x16 Icon line Segment Common Driver with Controller Character Display System
This document contains information product. Specifications information herein subject change without notice.
http://www.solomon-systech.com SSD1800 Series 1/42 2004 Copyright 2004 Solomon Systech Limited
TABLE CONTENTS
GENERAL DESCRIPTION FEATURES ORDERING INFORMATION. BLOCK DIAGRAM ARRANGEMENT SSD1800Z GOLD BUMP ARRANGEMENT SSD1800AV BARE DESCRIPTIONS FUNCTIONAL BLOCK DESCRIPTIONS VOLTAGE GENERATOR CIRCUIT FRAME FREQUENCY COMMAND TABLE COMMAND DESCRIPTIONS MAXIMUM RATINGS. CHARACTERISTICS. CHARACTERISTICS. APPLICATION EXAMPLES
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TABLE TABLES
Table Ordering Information Table SSD1800Z Gold Bump Coordinates Table SSD1800AV Bare Coordinates. Table Relationship between ICONRAM Address Display Pattern. Table CGROM Character Code Table Relationship between Character Code (DDRAM) Character Pattern (CGRAM). Table Contrast Control Register Table Command Table. Table CGRAM Address Mapping Table ICONRAM Address Mapping Table Maximum Ratings (Voltage Reference VSS) Table Characteristics (Unless otherwise specified, Voltage Referenced VSS, 3.6V, 85°C.). Table Characteristics (Unless otherwise specified, Voltage Referenced VSS, 3.6V, 85°C.). Table 6800-Series Parallel Interface Timing Characteristics (VDD 3.6V, 85°C). Table 8080-Series Parallel Interface Timing Characteristics (VDD 3.6V, 85°C). Table Serial Interface Timing Characteristics (VDD 3.6V, 85°C)
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TABLE FIGURES
Figure Block Diagram SSD1800. Figure SSD1800Z Arrangement Figure SSD1800AV Arrangement Figure Timing Diagram 8-bit Parallel Mode Data Transfer (6800 Mode) Figure Timing Diagram 8-bit Parallel Mode Data Transfer (8080 Mode) Figure Timing Diagram 4-bit Parallel Mode Data Transfer (6800 Mode) Figure Timing Diagram 4-bit Parallel Mode Data Transfer (8080 Mode) Figure Timing Diagram Serial Data Transfer Figure DDRAM Address Figure Configurations DC-DC Converter. Figure Configurations Voltage Regulator Figure When Built-in Power Supply used Figure When External Power Supply used Figure Function command (X1X0 Figure COM0 COM15 Double Height Line function command (X1X0 01). Figure Display Attributes Figure 6800-series Parallel Interface Waveform. Figure 8080-series Parallel Interface Waveform. Figure Serial Interface Characteristics Figure Application Circuit: External Regulator with internal divider mode (8-bit 6800 mode). Figure Application Circuit: internal power mode with regulated DC-DC converter (serial mode). Figure Application Circuit: internal power mode with regulated DC-DC converter (8-bit 8080 mode) Figure Recommended INITIALIZING SSD1800.
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GENERAL DESCRIPTION
SSD1800 single-chip CMOS driver with controller liquid crystal dot-matrix character display system. consists high voltage driving output pins driving Segments, Commons icon driving-Common. display lines characters with dots format. double height character mode line vertical scroll functions supported. SSD1800 displays character directly from internal 10,240 bits (256 characters dots) Character Generator (CGROM). character codes stored bits characters lines) Data Display (DDRAM). User defined character loaded bits characters dots) Character Generator (CGRAM). addition, there bits Icon Icon display. Data/ Commands sent from general through software selectable 6800-/8080-series compatible 8-bit Parallel Interface Serial Peripheral Interface. SSD1800 embeds DC-DC Converter, Voltage Regulator, Voltage divider oscillator that reduce number external components. With special design minimizing power consumption size, SSD1800 suitable portable battery-driven applications requiring long operation period compact size.
FEATURES
Single Supply Operation, 2.4V 3.6V Maximum 5.8V Driving Output Voltage Current Sleep Mode On-Chip 2x/3x DC-DC Converter/ External Power Supply On-Chip Oscillator/ External Clock On-Chip Voltage Regulator On-Chip Voltage Divider with programmable bias ratio (1/4, 1/5) Level Internal Contrast Control lines characters with dots format display icons Double Height Character Mode, Blink Mode, Cursor Display Line Vertical Scroll Functions remapping column remapping (4-type application available) 8/4-bit 6800-series Parallel Interface, 8/4-bit 8080-series Parallel Interface Serial Peripheral Interface Build characters user defined characters On-Chip Memories Character Generator (CGROM): 10240 bits (256 characters dots) Character Generator (CGRAM): bits characters dots) Display Data (DDRAM): bits characters lines) Segment Icon (ICONRAM): bits icons) Available Bare Die/Gold bumped
ORDERING INFORMATION
Table Ordering Information
Ordering Part Number SSD1800Z SSD1800AV Display Size Package Form Reference Remark
16x2 Characters 16x2 Characters
Gold-bump
Bare
Figure page Figure page
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BLOCK DIAGRAM
COM0~ COM15
COMI0, COMI
SEG0~SEG79
Buffer Cell (Level Shifter)
Level Selector
DIRS
Display Data Latch
Display Timing Generator
Cursor Control
Oscillator
AVSS DVSS AVDD DVDD
Internal Character Generator Character Generator (CGROM) Display Data (CGRAM) Icon (DDRAM) (ICONRAM)
Regulated DC/DC Converter, Voltage Divider, Contrast Control
Reset circuit
Command Decoder
Command Interface
Parallel/ Serial Interface
C68/
(WR)
(SDA) (SCK)
Figure Block Diagram SSD1800
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ARRANGEMENT SSD1800Z GOLD BUMP
Alignment Keys
26.3 26.3 26.3 26.3 26.3 26.3 Center (-2101.9, 169.6)
13.1
26.3 26.3 26.3
26.3
61.3
13.1
Center (-2940.9, 480.0)
Center (2940.9, 480.0)
52.5 61.3µm
8.75µm
8.75µm 37.6µm
37.6µm
(-2835, -598.5)
(2835, -598.5)
Figure SSD1800Z Arrangement
Size: Thickness: PAD: 1-63 PAD: 65-79, PAD: 81-162 PAD: 64,80,163,179 6170um 1480um (include scribe line) 6070um 1380um (exclude scribe line) +/-25um Bump Size 52.15 60.2 164-178 74.9 74.9 52.15 52.15 Minimum Pitch 76.3um 63.7um 63.7um
Bump Height: Nominal 18um Note: PADS: 35-36, 64-65, 75-81, 162-164, 166-169, 178-179 pads. faces diagram. Coordinates reference center chip. Unit coordinates size alignment keys alignment keys contain gold bump.
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Table SSD1800Z Gold Bump Coordinates
PAD# NAME DVSS -600.78 -600.78 -600.78 -600.78 -600.78 PAD# NAME 684.78 761.08 837.38 913.68 989.98 -600.78 -600.78 -600.78 -600.78 -600.78 -2401.53 -2325.23 -2248.93 DVDD -2172.63 -2096.33 -2020.03 -1943.73 -1867.43 -1791.13 -1714.83 -1638.53 -1562.23 -1485.93 -1409.63 DVDD -1333.33 AVDD -1257.03 DVDD -1180.73 DVSS -1104.43 AVSS -1028.13 DVSS -951.83 -861.18 -784.88 -708.58 -632.28 -555.98 -479.68 -403.38 -327.08 -246.05 -169.75 -93.45 -17.15 64.75 141.05 222.25 298.55 379.58 455.88 532.18 608.48
-600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.6 -600.6 -600.6 -600.78 -600.6 -600.6 -600.6 -600.6 -600.6 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78
DVSS AVSS DVSS DIRS DVDD AVDD DVDD DVDD DVSS C68/( DVDD TEST COMI0
1080.63 1156.93 1233.23 1309.53 1385.83 1462.13 1538.43 1614.73 1691.03 1767.33 1843.63 1919.93 1996.23 2072.53 2148.83 2225.13 2301.43 2377.73 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3 2939.3
-600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -600.78 -520.1 -456.4 -392.7 -329 -265.3 -201.6 -137.9 -74.2 -10.5 53.2 116.90 180.6 244.3 308.0 371.7 593.43
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PAD#
NAME SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48
2579.85 2516.15 2452.45 2388.75 2325.05 2261.35 2197.65 2133.95 2070.25 2006.55 1942.85 1879.15 1815.45 1751.75 1688.05 1624.35 1560.65 1496.95 1433.25 1369.55 1305.85 1242.15 1178.45 1114.75 1051.05 987.35 923.65 859.95 796.25 732.55 668.85 605.15 541.45 477.75 414.05 350.35 286.65 222.95 159.25 95.55 31.85 -31.85 -95.55 -159.25 -222.95 -286.65 -350.35 -414.05 -477.75 -541.45
593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43
PAD#
NAME SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 COMI1 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8
-605.15 -668.85 -732.55 -796.25 -859.95 -923.65 -987.35 -1051.05 -1114.75 -1178.45 -1242.15 -1305.85 -1369.55 -1433.25 -1496.95 -1560.65 -1624.35 -1688.05 -1751.75 -1815.45 -1879.15 -1942.85 -2006.55 -2070.25 -2133.95 -2197.65 -2261.35 -2325.05 -2388.75 -2452.45 -2516.15 -2579.85 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3 -2939.3
593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 593.43 371.7 244.3 180.6 116.9 53.2 -10.5 -74.2 -137.9 -201.6 -265.3 -329 -392.7 -456.4 -520.1 -600.78
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ARRANGEMENT SSD1800AV BARE
Figure SSD1800AV Arrangement
Size: Thickness: Metal Size: Opening Size:
6260um 1810um (include scribe line) +/-25um 88um 80um
metal size 103um x111um 111um x103um 90um x111um 111um x90um
number PADS: 1-9, 48-56, 72-80, 119-127 PADS: 128, 129, 141, PADS: 10-47, 81-118 PADS: 59-69, 130-140 Note: PADS: 1,2, 56-59, 141, pads. faces diagram. Coordinates reference center chip.
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Table SSD1800AV Bare Coordinates
NAME COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 -2748.20 -2638.13 -2528.05 -2417.98 -2307.90 -2197.83 -2087.75 -1977.68 -1867.60 -1757.53 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 NAME COM3 COM4 COM5 COM6 COM7 SEG0 2198.53 2308.60 2418.68 2528.75 2638.83 2748.90 2998.10 2998.10 2998.10 2998.10 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -687.75 -577.68 -467.60 -372.75 NAME SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 -145.08 -239.93 -334.78 -429.63 -524.48 -619.33 -714.18 -809.03 -903.88 -998.73 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98
AVSS DVSS DIRS AVDD DVDD C68/( TEST ICONS1 COM0 COM1 COM2
-1662.68 -1472.98 -1378.13 -1283.28 -1187.73 -1092.18 -996.63 -901.08 -805.53 -709.98 -614.43 -519.58 -424.73 -329.88 -235.03 -140.18 -45.33 49.53 144.38 239.23 334.08 428.93 523.78 618.63 713.48 808.33 903.18 998.03 1092.88 1187.73 1282.58 1377.43 1472.28 1567.13 1661.98 1758.23 1868.30 1978.38 2088.45
-772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71 -772.71
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40
2998.10 2998.10 2998.10 2998.10 2998.10 2998.10 2998.10 2998.10 2998.10 2998.10 2998.10 2742.43 2632.35 2522.28 2412.20 2302.13 2192.05 2081.98 1971.90 1861.83 1751.75 1657.08 1562.23 1467.38 1372.53 1277.68 1182.83 1087.98 993.13 898.28 803.43 708.58 613.73 518.88 424.03 329.18 234.33 139.48 44.63 -50.23
-277.90 -183.05 -88.20 6.65 101.50 196.35 291.20 386.05 480.90 590.98 701.05 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98
SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 ICONS2
-1093.58 -1188.43 -1283.28 -1378.13 -1472.98 -1567.83 -1662.68 -1757.53 -1867.60 -1977.68 -2087.75 -2197.83 -2307.90 -2417.98 -2528.05 -2638.13 -2748.20 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10 -2998.10
772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 772.98 -687.75 -577.68 -467.60 -372.75 -277.90 -183.05 -88.20 6.65 101.50 196.35 291.20 386.05 480.90 590.98 701.05
-1567.83
-772.71 -772.71 -772.71 -772.71 -772.71 -772.71
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DESCRIPTIONS
This Data/ Command control pin. When pulled high, data D7-D0 treated display data. When pulled low, data D7-D0 will transferred command register.
This microprocessor interface input. When interfacing 6800-series microprocessor, this will used signal input. Read mode will carried when this pulled high write mode when low. When interfacing 8080-microprocessor, this will input. Data write operation initiated when this pulled chip selected. This must fixed high serial mode.
DVDD AVDD
Digital Analog Power supply pin.
DVSS AVSS
Ground.
This microprocessor interface input. When interfacing 6800-series microprocessor, this will used enable signal, Read/ Write operation initiated when this pulled high chip selected. When interfacing 8080-microprocessor, this receives signal. Data read operation initiated when this pulled chip selected. This must fixed high serial mode.
This chip select input.
D7-D0
These pins 8-bit bi-directional data connected microprocessor parallel interface mode. 8-bit mode, while LSB. 4-bit mode, needed transfer 4-bit data (through D7-D4) times. high order bits (for 8-bit mode D7-D4) written before order bits (for 8-bit mode D3-D0) write transaction order bits (8-bit mode D3-D0) read before high order bits (8-bit mode D7D4) read transaction. D3-D0 pins must fixed high 4-bit mode. After resets, SSD1800 considers first 4-bit data from high order bits. When serial mode selected, serial data input (SDA) serial clock input (SCK). D5-D0 must fixed high serial mode
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VL6, VL5, VL4, VL3,
driving voltages. They supplied externally generated internal bias divider. They have following relationship:
bias bias (default)
most positive driving voltage. supplied externally generated internal regulator. recommended capacitor between external regulator.
This input built-in voltage regulator. When external resistor network selected generate driving level, VL6, external resistors, connected between AVSS VL6, respectively (see application circuit)
This select input voltage internal voltage regulator. This need pulled normal internal voltage regulator operation.
7.10 DIRS
This controls direction Segment. When DIRS SEG0 SEG2 SEG78 SEG79 When DIRS High SEG79 SEG78 SEG1 SEG0
7.11
External clock input. must fixed high when internal oscillation circuit used. case external clock mode, used clock should OFF.
7.12
This serial/ parallel interface selection input. When this pulled high, parallel mode selected. When pulled low, serial interface will selected. Read back operation only available parallel mode.
7.13
This select data length parallel data input. When High: serial interface mode When High Low: 4-bit mode High: 8-bit mode This must fixed high serial mode.
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7.14 C68/
This microprocessor interface selection input. When pulled high, 6800 series interface selected when pulled low, 8080 series interface selected. This must fixed high serial mode.
7.15
This reset signal input. Initialization chip started once this pulled low. Minimum pulse width completing reset 10ms.
7.16 TEST
Test pin. This used normal operation. Leave this open (NC).
7.17 C1P, C1N,
When internal DC-DC voltage converter used, external capacitors connected between these pins. Different connection will result different DC-DC converter multiple factor, 2x/3x. Details connections please refer Figure
7.18 COMI0, COMI1
There icons pins (pin47 140). Both pins output exactly same signal. reason duplicating enhance flexibility layout.
7.19 COM0 COM15
These pins provide common driving signal COM0 COM15 panel. Their output voltage levels AVss during sleep mode standby mode.
7.20 SEG0 SEG79
These pins provide segment driving signals. Their output voltage levels AVSS during sleep mode standby mode.
7.21
These Connection pins. Nothing should connected these pins, they connected together. These pins should left open individually.
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FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder Command Interface
This module determines whether input data interpreted data command. Data directed this module based upon input pin. high, data written internal memories (DDRAM, CGRAM, ICONRAM). low, input D7-D0 interpreted Command will decoded written corresponding command register.
Parallel 6800-series Interface bits mode
parallel interface consists bi-directional data pins (D7-D0), input high indicates read operation from internal (DDRAM, CGRAM ICONRAM). input indicates write operation internal (DDRAM, CGRAM ICONRAM) Internal Command Registers depending status input. input serves data latch signal (clock) when high provided that low. Refer Figure Parallel Interface Timing Diagram 6800-series microprocessors. order match operating frequency display with that microprocessor, some pipeline processings internally performed which require insertion dummy read before first actual display data read. This shown Figure below. dummy read make address counter (AC) increased recommended address again before writing. consecutive read after dummy read also valid data. instruction read cycle supported regarded operation cycle.
Parallel 8080-series Interface bits mode
parallel interface consists bi-directional data pins (D7-D0), input serves data read latch signal (clock) when provided that whether Command write internal read/ write controlled input serves data write latch signal (clock) when provided that low. Refer Figure Parallel Interface Timing Diagram 8080-series microprocessor. Similar 6800-series interface, dummy read also required before first actual display data read.
4-bit Parallel 6800/8080-Series Interface
control 4-bit mode exactly same 8-bit mode except consecutive access (read/ write) needed read/ write bits data. write operation, upper order bits written before order bits, order bits always read before upper order read transaction.
Serial Interface
serial interface consists serial clock (D6), serial data (D7), shifted into 8-bit shift register every rising edge order sampled every eighth clock determine whether data byte shift register written internal (DDRAM, CGRAM, ICONRAM) command register same clock.
Oscillator Circuit
This module On-Chip power oscillator circuitry. oscillator generates clock DC-DC voltage converter. This clock also used Display Timing Generator.
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ADDRESS COUNTER (AC)
Address Counter (AC) SSD1800 stores DDRAM/ CGRAM/ ICONRAM address. After writing into reading from DDRAM/ CGRAM/ ICONRAM. automatically increased There only address counter stores address among DDRAM CGRAM ICONRAM.
C68/80 (WR) E(RD)
Valid Data
Instruction Write Dummy Read Read Data Write
Figure Timing Diagram 8-bit Parallel Mode Data Transfer (6800 Mode)
C68/80 (WR) E(RD)
Instruction Write
Valid Data
Dummy Read
Read
Data Write
Figure Timing Diagram 8-bit Parallel Mode Data Transfer (8080 Mode)
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C68/80 (WR) E(RD)
Upper 4-bits Lower 4-bits Lower 4-bits Upper 4-bits Upper 4-bits Lower 4-bits
Instruction Write Dummy Read Read Data Write
Figure Timing Diagram 4-bit Parallel Mode Data Transfer (6800 Mode)
C68/80 (WR) E(RD)
Upper 4-bits Lower 4-bits Lower 4-bits Upper 4-bits Upper 4-bits Lower 4-bits
Instruction Write Dummy Read Read Data Write
Figure Timing Diagram 4-bit Parallel Mode Data Transfer (8080 Mode)
SDA(D7) SCK(D6)
Figure Timing Diagram Serial Data Transfer
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Display Data (DDRAM)
DDRAM stores display data maximum bits (Max characters). DDRAM address address counter hexadecimal number.
Figure DDRAM Address
COM0 COM7 COM8 COM15 Hidden Line Hidden Line
DDRAM Address
SEGMENT ICON (ICONRAM)
ICONRAM segment control data segment pattern data. There ICONS pins (COMI0 COMI1), which have same signal. icons same displayed same time. number icons
Table Relationship between ICONRAM Address Display Pattern
ICONRAM address Note: "-": Don't care. ICONRAM bits
8.10 Character Generator (CGROM)
CGROM characters. Function instruction selects characters (00h 07h) CGROM CGRAM.
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Table CGROM Character Code
Note: CGROM 0000xxxx empty.
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8.11 Character Generator (CGRAM)
CGRAM dots characters. writing font data CGRAM, user defined character used. CGRAM written regardless Function instruction.
Table Relationship between Character Code (DDRAM) Character Pattern (CGRAM)
Character Code (DDRAM data) (Pattern CGRAM address
(Pattern
(Pattern
(Pattern
(Pattern
(Pattern
ICONRAM bits
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Character Code (DDRAM data) (Pattern
CGRAM address
ICONRAM bits
(Pattern
NOTE: Don't Pattern
8.12 Driving Voltage Generator Regulator
This module generates voltage required display driving output. takes single supply input generates necessary voltage levels. This block consists 2x/3x DC-DC voltage converter built-in Regulated DC-DC voltage converter used generate positive driving voltage with internal voltage reference, VREF, relative AVSS
AVDD
SSD1800AVDD AVDD
SSD1800 AVDD
DC-DC
Converter
DC-DC Converter Remarks: 2.2µF 4.7µF 0.1µF
DC-DC Converter
VREF AVss
Remarks: 500K-2.5M ohms
Figure Configurations DC-DC Converter Figure Configurations Voltage Regulator
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Voltage Regulator
feedback gain control driving contrast adjusted using reference voltage external resistor network. reference voltage supplied internal Vref should connected normal operation internal voltage reference Vref. external resistors required connected between AVSS (R1), between (R2). following equations used calculate regulator output voltages.
VREF
VREF 0.06
Contrast Control Software control contrast voltage levels each voltage regulator feedback gain. equation calculating driving voltage given
VREF
where contrast control register.
Table Contrast Control Register
(default) Maximum Minimum Contrast High
Don't care)
Bias Divider Divide regulator output give driving voltages (VL5-VL2). power consumption circuit design this bias divider saves most display current comparing traditional design. Bias Ratio Selection circuitry Software control bias ratio match characteristic panel.
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8.13 Reset Circuit
This block includes Power Reset circuitry Reset Both these having same reset function. Once receives negative reset pulse, internal circuitry will start initialize. Minimum pulse width completing reset sequence 10ms. status chip after reset given
Display/ cursor/ blink turned 2-line display mode Power control register 000b Oscillator Power save CGRAM used Shift register data clear serial interface Bias ratio Address counter Normal scan direction outputs Contrast control register Test mode turned case 4-bit interface mode selection, SSD1800 considers 4-bit data from high order bits. line display address 00h-0Fh.
8.14 Display Data Latch
series registers carrying display signal information. SSD1800, there latches holding data, which will Buffer Cell Level Selector output required voltage levels.
8.15 Level Selector
Level Selector control display synchronization. Display voltage separated into sets used with different cycles. Synchronization important since selects required voltage level Buffer Cell, which turn outputs waveform.
8.16 Buffer Cell (Level Shifter)
Buffer Cell work level shifter, which translates voltage output signal required, driving voltage. output shifted with internal clock that comes from Display Timing Generator. voltage levels given level selector that synchronized with internal signal.
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VOLTAGE GENERATOR CIRCUIT
AVDD
AVDD
AVSS
AVSS
DC-DC Converter
DC-DC Converter
Remarks: (VC,VF 1,1) Note: command Power Control Register; 2.2µF 4.7µF turns on/off internal voltage converter regulator 0.1µF turns on/off voltage divider 500K-2.5M ohms
Figure When Built-in Power Supply used
AVDD
AVDD
AVSS
AVSS
Capacitor
Note: Power Control Register
Figure When External Power Supply used
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FRAME FREQUENCY
1/17 Duty
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COMMAND TABLE
Table Command Table
Command
Return Home
Description
DDRAM address from address counter cursor returns position contents DDRAM changed. X1X0 normal display (POR) X1X0 COM0 COM15 double height X1X0 10/11: normal display power save (POR) power save oscillator (POR) oscillator CGROM selected (POR) CGRAM selected COM0 COM15 (POR) COM15 COM0 X1X0 DDRAM line shows first line (POR). X1X0 DDRAM line shows first line LCD. X1X0 DDRAM line shows first line LCD. X1X0 DDRAM line shows first line LCD. bias (POR) bias turns voltage divider (POR) turns voltage divider Don't care turns internal voltage converter regulator (POR) turns internal voltage converter regulator turns display (POR) turns display blink (POR) blink cursor (POR) cursor DDRAM/ CGRAM address range: DDRAM: CGRAM: ICONRAM address range Contrast Control Register: ICONRAM: Contrast Control Register: (test byte) Command Operation Reserved testing.
Double Height Mode Power Save Mode Oscillator Control Function
Display Start Line
Bias Control Power Control Register
Display Control
DD/CGRAM address ICONRAM address Contrast Control Test Mode
Note: Patterns other than that given Command Table prohibited enter chip command. Otherwise, unexpected result will occur. Don't care.
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Data Read/ Write
read data from internal memories (DDRAM/ CGRAM/ ICONRAM), input high 6800-series parallel mode, high 8080-series parallel mode. data read provided serial mode. normal mode, address counter will increased automatically after each data read. dummy read required before first data read. Figure Functional Description. write data internal memories (DDRAM/ CGRAM/ ICONRAM), input high 6800-series 8080-series parallel mode. serial interface, will always write mode. Address counter will increased automatically after each data write.
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COMMAND DESCRIPTIONS
12.1 Return Home
Return Home instruction field makes cursor return home. DDRAM address from address counter cursor returns position. contents DDRAM changed.
12.2 Double Height Mode
This command increases height character line from dots. number signal needed exceeds existing signal, last character line will displayed. will happen following case:
X1X0 where COM0-COM15 double height.
line will displayed.
Figure Function command (X1X0
Figure COM0 COM15 Double Height Line function command (X1X0
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12.3 Power Save Mode Oscillator Control
enter Standby Sleep Mode, should done turning internal oscillator turning power save control bit. corresponding control bits X1X0 order system into power consumption mode, internal voltage converter, voltage regulator voltage divider should also turned using Power Control Register. After putting system into power save mode, following status will entered: Internal oscillator power supply circuits stopped. Segment Common drivers output AVSS level. display data operation mode before sleep held. internal circuit stopped.
12.4 Function
This command sets functions system. They shift direction (left right) CGROM/ CGRAM character area select.
12.5 Display Start Line
This command Display Start Line register determine starting address display data displayed selecting value from With value equals display will start from address (00h-0Fh). With value equals display will start from address (10h-1Fh). With value equals display will start from address (20h-2Fh). With value equals display will start from address (30-3Fh).
12.6 Bias Control
Bias ratio could using this command. When changing number line display, bias ratio also needs adjusted make display contrast consistent.
12.7 Power Control Register
This command turns various power circuits associated with chip which including regulated DC-DC converter voltage divider.
12.8 Display Control
This command provides display functions. turns on/off cursor, blink display. When both cursor blink control high, driver make alternate between inverting display character normal display character cursor position with about half second. contrary, cursor control low, only normal character displayed regardless blink control bit.
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(Cursor Mode)
Display State
(Blinking Mode)
Figure Display Attributes
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12.9 CGRAM Address
Before writing/ reading data into/ from RAM, address address instruction. Next, when data written/ read succession, address automatically increased by1. After accessing 7Fh, address 00h.
Table CGRAM Address Mapping ADDRESS
DDRAM LINE (00H 0FH) DDRAM LINE (10H 1FH) DDRAM LINE (20H 2FH) DDRAM LINE (30H 3FH) CGRAM (PATTERN CGRAM (PATTERN CGRAM (PATTERN CGRAM (PATTERN CGRAM (PATTERN CGRAM (PATTERN CGRAM (PATTERN CGRAM (PATTERN
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12.10 ICONRAM Address
Before writing/ reading data into/ from ICONRAM, address ICONRAM Address instruction. Next, when data written/ read succession, address automatically increased icons time blink blinking enabled. blink attributes ICON same cursor blink. accessing CGRAM, CGRAM Address instruction should before. After accessing 0Fh, address ICONRAM address 00h. ICONRAM address ranges 00h-0Fh.
Table ICONRAM Address Mapping ADDRESS
ICONRAM (00h 0Fh)
Reserved
12.11 Contrast Control Register
Contrast Control Register (CCR) ICONRAM Address Instruction. Next, data written CCR. default value (00000). Test Mode Register Use) (11H) When registers written, address counter increased.
12.12
command causing Operation.
12.13 Test Mode
This command forces driver chip into test mode internal testing chip. Under normal operation, user should this command.
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MAXIMUM RATINGS
Table Maximum Ratings (Voltage Reference VSS)
Symbol AVDD, DVDD Parameter Supply Voltage Value -0.3 +4.0V Unit
Tstg
VLCD Voltage Input Voltage Operating Temperature Storage Temperature Range
-0.3 +6.5V VSS-0.3 VDD+0.3 +150
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted limits Electrical Characteristics tables Description section This device contains circuitry protect inputs against damage high static voltages electric fields; however, advised that normal precautions taken avoid application voltage higher than maximum rated voltages this high impedance circuit. proper operation recommended that constrained range (Vin) VDD. Reliability operation enhanced unused inputs connected appropriate logic voltage level (e.g., either VDD). Unused outputs must left open. This device light sensitive. Caution should taken avoid exposure this device light source during normal operation. This device radiation protected.
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CHARACTERISTICS
Table Characteristics (Unless otherwise specified, Voltage Referenced VSS, 3.6V, 85°C.)
Symbol
DVDD AVDD IDD1
Parameter
Logic Analog Circuit Supply Voltage Range Display Operation Supply Current Drain Access operation from Supply Current Drain Standby Mode Supply Current Driving Voltage Input Voltage Regulator Output Logic High Input Voltage Logic Input Voltage Logic High Output Voltage Logic Output Voltage Driving Voltage Source (VL6) Driving Voltage Source (VL6)
Display Voltage Output VL4, VL3, VL2)
Test Condition
(Absolute value referenced DVss AVss) 25°C VLCD 5.8V without load access from 25°C fcyc 200kHz Current load Oscillator Power Save VLCD 25°C,
Unit
IDD2
VLCD
0.8*DVDD
DVDD 0.2*DVDD
-1mA, 2.4V 1mA, 2.4V Regulator Enable (VL6 voltage depends contrast control/ external resistors network) Regulator Disable
Voltage reference AVSS, Bias Divider Enabled, bias ratio
DVDD AVSS
Floating
(a-1)/a (a-2)/a
Display Voltage Output VL4, VL3, VL2)
Voltage reference AVSS, External Voltage Generator, Bias Divider Disable
Logic High Output Current Source Logic Output Current Drain
VOUT 0.4V
VOUT 0.4V
Logic Output Tri-state Current Drain Source
IIL/ Vref
Logic Input Current Logic Pins Input Capacitance Voltage regulator reference voltage
1.94
2.06
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CHARACTERISTICS
Table Characteristics (Unless otherwise specified, Voltage Referenced VSS, 3.6V, 85°C.)
Symbol
FFRM
Parameter
Frame Frequency
Test Condition
Internal Oscillator 25°C
67.5
Unit
Table 6800-Series Parallel Interface Timing Characteristics (VDD 3.6V, 85°C)
Symbol tcycle tDSW tDHW tDHR tACC Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Unit
Pulse Width (read) Pulse Width (write) High Pulse Width (read) High Pulse Width (write)
Rise Time Fall Time
Figure 6800-series Parallel Interface Waveform
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Table 8080-Series Parallel Interface Timing Characteristics (VDD 3.6V, 85°C)
Symbol tcycle tDSW tDHW tDHR tACC Parameter Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Unit
Pulse Width (read) Pulse Width (write) High Pulse Width (read) High Pulse Width (write)
Rise Time Fall Time
Figure 8080-series Parallel Interface Waveform
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Table Serial Interface Timing Characteristics (VDD 3.6V, 85°C)
Symbol tcycle tCSS tCSH tDSW tDHW tCLKL tCLKH Parameter Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Time Clock High Time Rise Time Fall Time 1000 Unit
Figure Serial Interface Characteristics
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APPLICATION EXAMPLES
COM8 COM9 COM14
DISPLAY PANEL SIZE ICON LINE
COM15 COMI1
COMI0 COM0 COM1 COM6 COM7
SEG0.SEG79
COMI1 COM15 COM14 COM9 COM8
SEG79.SEG0
SSD1800
(DIE FACE
COM7 COM6 COM5 COM0 COMI0
DVDD AVDD
D0-D7
0.1uF
DVSS AVSS[GND]
(#WR)
D/#C
E(/RD) /RES
VDD=3.0V
AVSS
External Power Supply
Logic connections specified above: Pins connected DVdd: C68/ DIRS Pins connected DVss: REF,
Figure Application Circuit: External Regulator with internal divider mode (8-bit 6800 mode)
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COM8 COM9 COM14 COM15 COMI1
DISPLAY PANEL SIZE ICON LINE
COMI0 COM0 COM1 COM6 COM7
SEG0.SEG79
COMI1 COM15 COM14 COM9 COM8
SEG79.SEG0
SSD1800
(DIE FACE
COM7 COM6 COM5 COM0 COMI0
DVDD AVDD
D/#C
(D6)
/RES
DVSS AVSS[GND]
(D7)
AVDD
-4.7 0.1-1uF
3.0V
AVSS Remarks: 500K-2.5M ohms
Note: recommended regulated DC-DC Logic connections specified above: converter reduce current consumption Pins connected DVdd: DIRS under certain condition. Pins connected DVss: REF, CLK, e.g. AVDD /DVDD 3.0V VLCD (LCD driving E(/RD), C68/ D5-D0 voltage) 5.0V. Figure Application Circuit: internal power mode with regulated DC-DC converter (serial mode)
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COM8 COM9 COM14 COM15 COMI1
DISPLAY PANEL SIZE ICON LINE
COMI0 COM0 COM1 COM6 COM7
SEG0.SEG79
COMI1 COM15 COM14 COM9 COM8
SEG79.SEG0
SSD1800
(DIE FACE
COM7 COM6 COM5 COM0 COMI0
DVDD AVDD -4.7 0.1-1uF
(#WR)
D0-D7
D/#C
E(/RD) /RES
DVSS AVSS[GND]
AVDD
3.0V Remarks: 500K-2.5M ohms
AVSS
Logic connections specified above: Pins connected DVdd: DIRS Pins connected DVss: REF, CLK, C68/(
Figure Application Circuit: internal power mode with regulated DC-DC converter (8-bit 8080 mode)
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Recommended INITIALIZING SSD1800
DVDD/AVCC-DVSS/AVSS Power
NOTE: instructions 1-6, minimum clock cycle time 650ns PPI. details, refer SSD1800 datasheet Characteristics". internal should cleared. clear DDRAM, address (first DDRAM) then write (space character code) 64times. clear CGRAM, address (first CGRAM) then write (null data) times clear ICONRAM, CONRAM address (first ICONRAM) then write (null data) times delay between each Command/Data input under ideal timing situation time shift signals, refer page details)
Send reset pulse pin. (Recommended minimum reset pulse width 10ms) Waiting 10usec
Command Input Function (000100X1X0) Contrast control register setup Power save (power save off; Power control (turns internal regulator turns internal divider)
Command Input address
Data Input Data writing (RAM clear) (DDRAM=20h, CG/ICONRAM=00h)
Command Input Display control (turns display) (There auto mask period 260ms)
initialization
Figure Recommended INITIALIZING SSD1800
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Solomon Systech reserves right make changes without further notice products herein. Solomon Systech makes warranty, representation guarantee regarding suitability products particular purpose, does Solomon Systech assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typical" must validated each customer application customer's technical experts. Solomon Systech does convey license under patent rights rights others. Solomon Systech products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Solomon Systech product could create situation where personal injury death occur. Should Buyer purchase Solomon Systech products such unintended unauthorized application, Buyer shall indemnify hold Solomon Systech offices, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Solomon Systech negligent regarding design manufacture part.
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80x16 Icon line Segment Common Driver with Controller Character Displa

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