INTRODUCTION SAMSUNG's S3C2400 16/32-bit RISC microprocessor desi
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S3C2400 RISC MICROPROCESSOR
INTRODUCTION
SAMSUNG's S3C2400 16/32-bit RISC microprocessor designed provide cost-effective, power, small size high performance micro-controller solution hand-held devices general applications. reduce total system cost, S3C2400 also provides following: separate 16KB Instruction 16KB Data Cache, handle virtual memory management, controller (STN TFT), 2-channel UART with handshake, 4-channel DMA, System Manager (chip select logic, EDO/SDRAM controller), 4-channel Timers with PWM, Ports, RTC, 8channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, Host, Device, Multi-Media Card Interface, clock generation. S3C2400 developed using ARM920T core, 0.18um CMOS standard cells memory complier. low-power, simple, elegant fully static design particularly suitable cost-sensitive power sensitive applications. Also S3C2400 adopts architecture, AMBA (Advanced Microcontroller Architecture) outstanding feature S3C2400 core, 16/32-bit ARM920T RISC processor designed Advanced RISC Machines, Ltd. ARM920T implements MMU, AMBA BUS, Harvard cache architecture with separate 16KB instruction 16KB data caches, each with 8-word line length. providing complete common system peripherals, S3C2400 minimizes overall system costs eliminates need configure additional components. integrated on-chip functions that described this document include: 1.8V internal, 3.3V external (I/O boundary) microprocessor with 16KB I-Cache, 16KB D-Cache, MMU. External memory controller. (EDO/SDRAM Control, Chip Select logic) controller color color TFT) with 1-ch LCD-dedicated DMA. 4-ch DMAs with external request pins 2-ch UART with handshake (IrDA1.0, 16-byte FIFO)/1-ch 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller interface (ver 2.11) 2-port Host port Device (ver 1.1) 4-ch timers 1-ch internal timer Watch Timer 90-bit general purpose ports/8-ch external interrupt source Power control: Normal, Slow, Idle, Stop SL_IDLE mode 8-ch 10-bit ADC. with calendar function. On-chip clock generator with
S3C2400 RISC MICROPROCESSOR
FEATURES
Architecture Integrated system hand-held devices general embedded applications. 16/32-Bit RISC architecture powerful instruction with ARM920T core. Enhanced architecture support WinCE, EPOC Linux. Instruction cache, data cache, write buffer Physical address reduce effect main memory bandwidth latency performance. ARM920T core supports debug architecture Tracking mode. Internal AMBA(Advanced Microcontroller Architecture) (AMBA2.0, AHB/APB) Cache Memory set-associative cache with I-Cache(16KB) D-Cache(16KB). 8-words line with valid dirty bits line Pseudo random round robin replacement algorithm. Write through write back cache operation update main memory. write buffer hold words data four address.
Clock Power Manager power on-chip MPLL UPLL UPLL makes clock operating Host/Device. MPLL makes clock operating maximum 150Mhz 1.8V. Clock selectively each function block software. Power mode: Normal, Slow, Idle, Stop mode SL_IDLE mode. Normal mode: Normal operating mode. Slow mode: frequency clock without PLL. Idle mode: Stop clock only CPU. Stop mode: clocks stopped. SL_IDLE mode: clocks except stopped. Wake EINT[7:0] alarm interrupt from Stop mode.
System Manager Little/Big Endian support. Address space: bytes each bank (Total 256Mbyte) Supports programmable 8/16/32-bit data width each bank. Fixed bank start address programmable bank size banks. Programmable bank start address bank size bank. memory banks. memory banks ROM, SRAM etc. memory banks ROM/SRAM/DRAM(EDO Synchronous DRAM) Fully Programmable access cycles memory banks. Supports external wait signal expend cycle. Supports self-refresh mode DRAM/SDRAM power-down. Supports asymmetric/symmetric address DRAM.
Interrupt Controller Interrupt sources (Watch timer, 5Timer, 6UART, 8External interrupts, DMA, RTC, ADC, IIC, SPI, MMC, USB) Level/Edge mode external interrupt source. Programmable polarity edge level. Supports (Fast Interrupt request) very urgent interrupt request.
S3C2400 RISC MICROPROCESSOR
Timer with (Pulse Width Modulation) 4-ch 16-bit Timer with 1-ch 16-bit internal timer with DMA-based interrupt-based operation Programmable duty cycle, frequency, polarity Dead-zone generation. Supports external clock source.
Converter 8-ch multiplexed ADC. Max. 500KSPS 10-bit Resolution.
Controller displays Feature Supports types panels 4-bit dual scan, 4-bit single scan, 8-bit single scan display type. Supports monochrome, gray levels, 16gray levels, color 4096 colors LCD. Supports multiple screen size Typical actual screen size: 640x480, 320x240, 160x160 (pixels) Maximum virtual screen size (color mode): 4096x1024, 2048x2048, 1024x4096 etc. Supports power saving mode(Enhanced SL_IDLE mode.)
(Real Time Clock) Full clock feature: msec, sec, min, hour, day, week, month, year. 32.768 operation. Alarm interrupt. Time tick interrupt
General Purpose Input/Output Ports external interrupt ports multiplexed input/output ports
(Thin Film Transistor) color displays Feature Supports (bit-per-pixel) palette color displays color TFT. Supports non-palette true-color displays color TFT. Supports maximum (64K using intensity) color mode. Supports multiple screen size Typical actual screen size: 720x240, 320x240, 160x160 (pixels) Recommended maximum screen size: 640x480 bpp, 32bit SDRAM @80MHz) Maximum virtual screen size (16bpp mode): 2048x1024
UART 2-channel UART with DMA-based interruptbased operation Supports 5-bit, 6-bit, 7-bit, 8-bit serial data transmit/receive Supports handshaking during transmit/receive Programmable baud rate Supports IrDA Loop back mode testing Each channel internal 16-byte FIFO 16-byte FIFO.
Watchdog Timer Controller 4-ch controller. Support memory memory, memory, memory Burst transfer mode enhance transfer rate. 16-bit Watchdog Timer. Interrupt request system reset time-out.
S3C2400 RISC MICROPROCESSOR
IIC-BUS Interface 1-ch Multi-Master IIC-Bus. Serial, 8-bit oriented bi-directional data transfers made Kbit/s standard mode Kbit/s fast mode.
Interface Multi-Media Card Protocol version 2.11 compatible 2x16 Bytes FIFO receive/transmit. DMA-based interrupt-based operation.
IIS-BUS Interface 1-ch IIS-bus audio interface with DMA-based operation. Serial, 8/16bit channel data transfers. Supports format MSB-justified data format.
Interface Serial Peripheral Interface Protocol version 2.11 compatible bits Shift register receive/transmit. DMA-based interrupt-based operation.
Operating Voltage Range Core: 1.8V I/O: 3.3V
Host 2-port Host Complies with OHCI Rev. Compatible with Specification version
Operating Frequency
Device 1-port Device. Endpoints Device. Compatible with Specification version
Package LQFP/208 FBGA
S3C2400 RISC MICROPROCESSOR
BLOCK DIAGRAM
ARM920T Instruction 2A[31:0] ARM9TDMI Processor core (Internal Embedded ICE) DD[31:0] 2A[31:0] Data DPA[31:0] Data CACHE (16KB) WriteBack WBPA[31:0] DVA[31:0] ID[31:0] AMBA Write Buffer IPA[31:0] InstructionCA (16KB) External Coproc Interface
JTAG
CP15
CONT.
CONT. Arbitor/Decode
Host CONT.
Interrupt CONT.
ExtMaster
Power Management Memory CONT. SRAM/ROM/DRAM/SDRAM
Clock Generator (MPLL) Bridge DMA(4Ch)
UART
Device
Watchdog Timer CONT. Arbitor/Decode
GPIO
Timer/PWM 4(Internal)
Figure 1-1. S3C2400 Block Diagram
S3C2400 RISC MICROPROCESSOR
ASSIGNMENTS
AIN4 AIN5 AIN6 AIN7 VDDA_ADC XTOrtc XTIrtc RTCVDD VDDi_MPLL VSSi_MPLL MPLLCAP VDDi_UPLL VSSi_UPLL UPLLCAP EINT0/GPE0 EINT1/GPE1/nSS EINT2/GPE2/I2SSDI EINT3/GPE3/nCTS1 EINT4/GPE4/nRTS1 EINT5/GPE5/TCLK1 EINT6/GPE6 EINT7/GPE7 nRESET VDDi EXTCLK VSSIO XTOpll XTIpll VDDIO VDDi SCLK VSSi SCKE/GPA10 nWAIT/GPD10 nGCS7:nSCS1:nRAS1 nGCS6:nSCS0:nRAS0 nGCS5/GPA17 nGCS4/GPA16 nGCS3/GPA15 nGCS2/GPA14 VSSIO nGCS1/GPA13 nGCS0 nBE0:nWBE0:DQM0 nBE1:nWBE1:DQM1 nBE2:nWBE2:DQM2 nBE3:nWBE3:DQM3 nCAS3:nSRAS VDDIO
AIN3 AIN2 AIN1 AIN0 Avref VSSA_ADC VSSIO RXD1/GPF1/IICSDA TXD1/GPF3/IICSCL RXD0/GPF0 TXD0/GPF2 nRTS0/GPF4/nXBACK nCTS0/GPF5/nXBREQ VDDi VSSi DN1/PDN0 DP1/PDP0 VD15/GPC15 VD14/GPC14 VSSIO VDDIO VD13/GPC13 VD12/GPC12 VD11/GPC11 VDDi VSSi VD10/GPC10 VD9/GPC9 VD8/GPC8 VD7/GPC7 VD6/GPC6 VD5/GPC5 VD4/GPC4 VSSIO VD3/GPC3 VD2/GPC2 VD1/GPC1 VD0/GPC0 VFRAME/GPD0 VDDi VSSi VM/GPD1 VLINE/GPD2 VCLK/GPD3 LEND/GPD4 VSSIO
VDDIO SPIMOSI/GPG8/IICSCL SPIMISO/GPG7/IICSDA SPICLK/GPG9/MMCCLK MMCCLK/GPG4/I2SSDI MMCCMD/GPG5/IICSDA MMCDAT/GPG6/IICSCL I2SSDO/GPG3/I2SSDI CDCLK/GPG2 I2SSCLK/GPG1 VSSi VDDi I2SLRCK/GPG0 nXDREQ0/GPE10 nXDACK0/GPE8 nXDREQ1/GPE11/nXBREQ nXDACK1/GPE9/nXBACK TCLK0/GPD9 TOUT3/GPD8 TOUT2/GPD7 TOUT1/GPD6 TOUT0/GPD5 nTRST CLKOUT/GPF6 VDDi VSSi VSSIO VDDIO DATA31/GPB15 DATA30/GPB14 DATA29/GPB13 DATA28/GPB12 DATA27/GPB11 DATA26/GPB10/nSS DATA25/GPB9/I2SSDI DATA24/GPB8 DATA23/GPB7 VSSIO DATA22/GPB6/nRTS1 DATA21/GPB5/nCTS1 DATA20/GPB4/RXD1 DATA19/GPB3/TXD1 DATA18/GPB2/TCLK1 DATA17/GPB1/nXBREQ DATA16/GPB0/nXBACK DATA15 DATA14 VSSIO
VSSIO nCAS2:nSCAS nCAS1/GPA12 nCAS0/GPA11 ADDR0/GPA0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 VDDIO VSSIO VDDi VSSi ADDR12 ADDR13 ADDR14 ADDR15 ADDR16/GPA1 ADDR17/GPA2 ADDR18/GPA3 ADDR19/GPA4 ADDR20/GPA5 ADDR21/GPA6 ADDR22/GPA7 ADDR23/GPA8 VDDIO VSSIO ADDR24/GPA9 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDi VSSi DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 VDDIO
Figure 1-2. S3C2400 Assignments (208-LQFP)
S3C2400X0
208-LQFP
S3C2400 RISC MICROPROCESSOR
BALL CORNER INDICATOR SOLDEER BALL)
BOTTOM VIEW
Figure 1-3. S3C2400 Assignments (208-FBGA)
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Assignment Number VSSIO DATA14 DATA15 DATA16/GPB0/nXBACK DATA17/GPB1/nXBREQ DATA18/GPB2/TCLK1 DATA19/GPB3/TXD1 DATA20/GPB4/RXD1 DATA21/GPB5/nCTS1 DATA22/GPB6/nRTS1 VSSIO DATA23/GPB7 DATA24/GPB8 DATA25/GPB9/I2SSDI DATA26/GPB10/nSS DATA27/GPB11 DATA28/GPB12 DATA29/GPB13 DATA30/GPB14 DATA31/GPB15 VDDIO VSSIO VSSi VDDi CLKOUT/GPF6 nTRST TOUT0/GPD5 TOUT1/GPD6 TOUT2/GPD7 Name Default Function VSSIO DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 VSSIO DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 VDDIO VSSIO VSSi VDDi GPF6 nTRST GPD5 GPD6 GPD7 State @BUS REQ. Hi-z Hi-z Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- -/-/- State @STOP Hi-z Hi-z Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/-/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- Hi-z/- -/-/- State @nRESET Type vss3op phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm vss3op phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm vdd3op vss3op Vss3i vdd1ih_core phbsu50ct8sm phic phic phic phic phot8 phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Assignment (Continued) Number Name TOUT3/GPD8 TCLK0/GPD9 nXDACK1/GPE9/ nXBACK nXDREQ1/GPE11/ nXBREQ nXDACK0/GPE8 nXDREQ0/GPE10 I2SLRCK/GPG0 VDDi VSSi I2SSCLK/GPG1 CDCLK/GPG2 I2SSDO/GPG3/I2SSDI MMCDAT/GPG6/IICSCL MMCCMD/GPG5/ IICSDA MMCCLK/GPG4/I2SSDI SPICLK/GPG9/ MMCCLK SPIMISO/GPG7/IICSDA SPIMOSI/GPG8/IICSCL VDDIO VSSIO LEND/GPD4 VCLK/GPD3 VLINE:HSYNC/GPD2 VM:VDEN/GPD1 VSSi VDDi VFRAME:VSYNC/GPD0 VD0/GPC0 VD1/GPC1 VD2/GPC2 VD3/GPC3 Default Function GPD8 GPD9 GPE9 GPE11 GPE8 GPE10 GPG0 VDDi VSSi GPG1 GPG2 GPG3 GPG6 GPG5 GPG4 GPG9 GPG7 GPG8 VDDIO VSSIO GPD4 GPD3 GPD2 GPD1 VSSi VDDi GPD0 GPC0 GPC1 GPC2 GPC3 State @BUS REQ. -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -:-/- -:-/- -:-/- State @STOP -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -:-/- -:-/- -:-/- State @nRESET Type phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm vdd1ih_core vss3i phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50cdct8sm phbsu50cdct8sm phbsu50ct8sm phbsu50ct8sm phbsu50cdct8sm phbsu50cdct8sm vdd3op vss3op phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm vss3i vdd1ih_core phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm
S3C2400 RISC MICROPROCESSOR
VSSIO
VSSIO
vss3op
1-10
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Assignment (Continued) Number Name VD4/GPC4 VD5/GPC5 VD6/GPC6 VD7/GPC7 VD8/GPC8 VD9/GPC9 VD10/GPC10 VSSi VDDi VD11/GPC11 VD12/GPC12 VD13/GPC13 VDDIO VSSIO VD14/GPC14 VD15/GPC15 DP1/PDP0 DN1/PDN0 VSSi VDDi nCTS0/GPF5/nXBREQ nRTS0/GPF4/nXBACK TXD0/GPF2 RXD0/GPF0 TXD1/GPF3/IICSCL RXD1/GPF1/IICSDA VSSIO VSSA_ADC Default Function GPC4 GPC5 GPC6 GPC7 GPC8 GPC9 GPC10 VSSi VDDi GPC11 GPC12 GPC13 VDDIO VSSIO GPC14 GPC15 PDP0 PDN0 VSSi VDDi GPF5 GPF4 GPF2 GPF0 GPF3 GPF1 VSSIO VSSA_ADC State @BUS REQ. -/-/- -/-/- -/-/- -/-/- State @STOP -/-/- -/-/- -/-/- -/-/- State @nRESET Type phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm vss3i vdd1ih_core phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm vdd3op vss3op phbsu50ct8sm phbsu50ct8sm pbusb pbusb pbusb pbusb vss3i vdd1ih_core phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50cdct8sm phbsu50cdct8sm phic phic phic phic vss3op vss3t_abb
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Assignment (Continued) Number Avref AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDDA_ADC XTOrtc XTIrtc RTCVDD VDDi_MPLL VSSi_MPLL MPLLCAP VDDi_UPLL VSSi_UPLL UPLLCAP EINT0/GPE0 EINT1/GPE1/nSS EINT2/GPE2/I2SSDI EINT3/GPE3/nCTS1 EINT4/GPE4/nRTS1 EINT5/GPE5/TCLK1 EINT6/GPE6 EINT7/GPE7 nRESET VDDi EXTCLK VSSIO XTOpll nRESET VDDi EXTCLK VSSIO XTOpll Name Default Function Avref AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDDA_ADC XTOrtc XTIrtc RTCVDD VDDi_MPLL VSSi_MPLL MPLLCAP VDDi_UPLL VSSi_UPLL UPLLCAP GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 State @BUS REQ. -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- State @STOP -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- -/-/- State @nRESET Type phia_abb phia_abb phia_abb phia_abb phia_abb phia_abb phia_abb phia_abb phia_abb vdd3t_abb phgpad_option phgpad_option vdd1ih vdd1ih_core vss3i phgpad_option vdd1ih_core vss3i phgpad_option phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phbsu50ct8sm phis vdd1ih phic vss3op phsoscm26
1-12
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Assignment (Continued) Number XTIpll VDDIO VDDi SCLK VSSi SCKE/GPA10 nWAIT/GPD10 nGCS7:nSCS1:nRAS1 nGCS6:nSCS0:nRAS0 nGCS5/GPA17 nGCS4/GPA16 nGCS3/GPA15 nGCS2/GPA14 VSSIO nGCS1/GPA13 nGCS0 nBE0:nWBE0:DQM0 Name Default Function XTIpll VDDIO VDDi SCLK VSSi SCKE GPD10 nGCS7 nGCS6 nGCS5 nGCS4 nGCS3 nGCS2 VSSIO nGCS1 nGCS0 DQM0 State @BUS REQ. Hi-z Hi-z/O Hi-z:Hi-z:Hi-z Hi-z:Hi-z:Hi-z Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z Hi-z Hi-z Hi-z:Hi-z:Hi-z State @STOP Low/O High:High:Low High:High:Low Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O Hi-z Hi-z Hi-z Hi-z Pre: Hi-z Pre: Hi-z Hi-z Pre: Hi-z Pre: Hi-z Hi-z Pre: Hi-z Pre: Hi-z Hi-z Pre: Hi-z Pre: Hi-z Low:High State @nRESET O(SCLK) O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) O(H) Type phsoscm26 vdd3op vdd1ih_core phot12sm vss3i phot8 phbsu50ct8sm phot8 phot8 phot8 phot8 phot8 phot8 vss3op phot8 phot8 phot8 phot8 phot8
nBE1:nWBE1:DQM
Hi-z:Hi-z:Hi-z
O(H)
phot8
nBE2:nWBE2:DQM2
DQM2
Hi-z:Hi-z:Hi-z
O(H)
phot8
nBE3:nWBE3:DQM3
DQM3
Hi-z:Hi-z:Hi-z
O(H)
phot8
nCAS3:nSRAS VDDIO VSSIO
nSRAS VDDIO VSSIO
Hi-z:Hi-z
O(H)
phot8 vdd3op vss3op
1-13
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Assignment (Continued) Number Name nCAS2:nSCAS nCAS1/GPA12 nCAS0/GPA11 ADDR0/GPA0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 VDDIO VSSIO VDDi VSSi ADDR12 ADDR13 ADDR14 ADDR15 ADDR16/GPA1 ADDR17/GPA2 ADDR18/GPA3 ADDR19/GPA4 ADDR20/GPA5 ADDR21/GPA6 ADDR22/GPA7 ADDR23/GPA8 VDDIO VSSIO Default Function nSCAS nCAS1 nCAS0 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 VDDIO VSSIO VDDi VSSi ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 VDDIO VSSIO State @BUS REQ. Hi-z:Hi-z Hi-z/O Hi-z/O Hi-z/O Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O Hi-z/O State @STOP Low:High Low/O Low/O Hi-z Pre/O Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O Hi-z Pre/O State @nRESET O(H) O(H) O(H) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) O(L) Type phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 vdd3op vss3op vdd1ih_core vss3i phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 phot8 vdd3op vss3op
1-14
S3C2400 RISC MICROPROCESSOR
Table 1-1. 208-Pin LQFP Assignment (Continued) Number Name ADDR24/GPA9 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDi VSSi DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 VDDIO Default Function ADDR24 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 VDDi VSSi DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 VDDIO State @BUS REQ. Hi-z/O Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z State @STOP Hi-z Pre/O Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z State @nRESET O(L) Type phot8 phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm vdd1ih_core vss3i phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm phbsu50ct12sm vdd3op
NOTES: @BUS REQ. shows states external bus, which used other master. @STOP shows states when S3C2400 STOP mode. mark indicates unchanged state STOP mode Request mode. Hi-z means Hi-z Previous state which determined setting MISCCR register. AI/AO means analog input/output. mean power, input output respectively. state @nRESET shows status below @nRESET duration.
4FCLK nRESET
@nRESET
FCLK
1-15
S3C2400 RISC MICROPROCESSOR
below table shows types descriptions.
Type vdd1ih, vss3I vdd1ih_core, vss3I vdd3op, vss3op vdd3t_abb, vss3t_abb phic phis pbusb phot8 phob8sm phot12sm phia_abb phgpad_option phsoscm26 phbsu50ct8sm phbsu50ct12sm phbsu50cdct8sm 1.8V Vdd/Vss internal logic
Descriptions
1.8V Vdd/Vss internal logic without input driver 3.3V Vdd/Vss external logic 3.3V Vdd/Vss analog circuitry input pad, LVCMOS level input pad, LVCMOS schmitt-trigger level output pad, tri-state, Io=8mA output pad, medium slew rate, Io=8mA output pad, tri-state, medium slew rate, Io=12mA bi-directional analog analog Oscillator cell with enable feedback resistor bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control, tri-state, Io=8mA bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control, tri-state, Io=12mA bi-directional pad, LVCMOS schmit-trigger, 50Kohm pull-up resistor with control, tri-state, selectable output pad(open-drain tri-state), Io=8mA
1-16
S3C2400 RISC MICROPROCESSOR
Table 1-2. 208-Pin FBGA Assignment Number VSSIO DATA12 DATA9 DATA8 DATA6 DATA2 VSSIO ADDR21/GPA6 ADDR17/GPA2 ADDR13 VDDi ADDR10 ADDR6 ADDR3 ADDR1 ADDR0/GPA0 DATA17/GPB1/nXBREQ DATA14 VDDIO DATA10 VDDi DATA3 DATA0 ADDR22/GPA7 ADDR18/GPA3 ADDR14 VSSi ADDR11 ADDR7 ADDR2 nCAS0/GPA11 nCAS2:nSCAS Name Number Name DATA20/GPB4/RXD1 DATA19/GPB3/TXD1 DATA15 DATA13 DATA11 DATA7 DATA1 ADDR23/GPA8 ADDR19/GPA4 ADDR15 VSSIO ADDR9 ADDR4 nCAS1/GPA12 VDDIO nCAS3:nSRAS DATA23/GPB7 VSSIO DATA21/GPB5/nCTS1 DATA18/GPB2/TCLK1 DATA16/GPB0/nXBACK VSSi DATA4 VDDIO ADDR20/GPA5 ADDR12 VDDIO ADDR5 VSSIO nBE3:nWBE3:DQM3 nBE2:nWBE2:DQM2 nBE1:nWBE1:DQM
1-17
S3C2400 RISC MICROPROCESSOR
Table 1-2. 208-Pin FBGA Assignment (Continued) Number Name DATA25/GPB9/I2SSDI DATA26/GPB10/nSS DATA24/GPB8 DATA22/GPB6/nRTS1 DATA5 ADDR24/GPA9 ADDR16/GPA1 ADDR8 nBE0:nWBE0:DQM0 nGCS0 DATA29/GPB13 DATA30/GPB14 DATA31/GPB15 DATA27/GPB11 nGCS1/GPA13 nGCS4/GPA16 nGCS3/GPA15 nGCS2/GPA14 VSSIO VSSi VDDi VDDIO DATA28/GPB12 VSSIO nGCS5/GPA17 nWAIT/GPD10 nGCS7:nSCS1:nRAS1 nGCS6:nSCS0:nRAS0 Number nTRST CLKOUT/GPF6 SCKE/GPA10 VDDIO VDDi SCLK VSSi TOUT0/GPD5 TOUT1/GPD6 TOUT2/GPD7 I2SLRCK/GPG0 EINT7/GPE7 EXTCLK VSSIO XTOpll XTIpll TOUT3/GPD8 TCLK0/GPD9 nXDACK1/GPE9/nXBACK nXDREQ1/GPE11/nXBREQ I2SSCLK/GPG1 EINT0/GPE0 EINT3/GPE3/nCTS1 nRESET VDDi Name
1-18
S3C2400 RISC MICROPROCESSOR
Table 1-2. 208-Pin FBGA Assignment(Continued) Number nXDACK0/GPE8 nXDREQ0/GPE10 VDDi I2SSDO/GPG3/I2SSDI UPLLCAP EINT4/GPE4/nRTS1 EINT5/GPE5/TCLK1 EINT6/GPE6 VSSi CDCLK/GPG2 MMCCMD/GPG5/IICSDA SPIMISO/GPG7/IICSDA VD4/GPC4 VD13/ GPC13 nRTS0/GPF4/nXBACK RTCVDD VDDi_UPLL EINT1/GPE1/nSS EINT2/GPE2/I2SSDI Name Number Name MMCDAT/GPG6/IICSCL MMCCLK/GPG4/I2SSDI SPIMOSI/GPG8/IICSCL VM:VDEN/GPD1 VD0/GPC0 VD7/ GPC7 VSSi VDDIO RXD0/GPF0 VSSA_ADC AIN2 VDDA_ADC VSSi_MPLL MPLLCAP VSSi_UPLL SPICLK/GPG9/MMCCLK VDDIO LEND/GPD4 VSSi VD3/GPC3 VD8/ GPC8 VDDi VD15/ GPC15 nCTS0/GPF5/nXBREQ RXD1/GPF1/IICSDA AIN1 AIN7 XTIrtc VDDi_MPLL
1-19
S3C2400 RISC MICROPROCESSOR
Table 1-2. 208-Pin FBGA Assignment (Continued) Number VSSIO VCLK/GPD3 VFRAME:VSYNC/GPD0 VD2/GPC2 VD5/ GPC5 VD9/ GPC9 VD12/ GPC12 VD14/ GPC14 DN1/PDN0 VDDi TXD1/GPF3/IICSCL Avref AIN4 AIN6 XTOrtc Name Number Name VLINE:HSYNC/GPD2 VDDi VD1/GPC1 VSSIO VD6/ GPC6 VD10/ GPC10 VD11/ GPC11 VSSIO DP1/PDP0 VSSi TXD0/GPF2 VSSIO AIN0 AIN3 AIN5
1-20
S3C2400 RISC MICROPROCESSOR
SIGNAL DESCRIPTIONS Table 1-3. S3C2400 Signal Descriptions Signal CONTROLLER OM[1:0] OM[1:0] sets S3C2400 TEST mode, which used only fabrication. Also, determines width nGCS0. logic level determined pull-up/down resistor during RESET cycle. 00:8-bit ADDR[24:0] DATA[31:0] nGCS[7:0] 01:16-bit 10:32-bit 11:Test mode Description
ADDR[24:0] (Address Bus) outputs memory address corresponding bank DATA[31:0] (Data Bus) inputs data during memory read outputs data during memory write. width programmable among 8/16/32-bit. nGCS[7:0] (General Chip Select) activated when address memory within address region each bank. number access cycles bank size programmed. (Write Enable) indicates that current cycle write cycle. Write Byte Enable Upper Byte/Lower Byte Enable(In case SRAM) (Output Enable) indicates that current cycle read cycle. nXBREQ (Bus Hold Request) allows another master request control local bus. BACK active indicates that control been granted. nXBACK (Bus Hold Acknowledge) indicates that S3C2400 surrendered control local another master. nWAIT requests prolong current cycle. long nWAIT current cycle cannot completed.
nWBE[3:0] nBE[3:0] nXBREQ nXBACK nWAIT
DRAM/SDRAM/SRAM nRAS[1:0] nCAS[3:0] nSRAS nSCAS nSCS[1:0] DQM[3:0] SCLK SCKE nBE[3:0] Address Strobe Column Address strobe SDRAM Address Strobe SDRAM Column Address Strobe SDRAM Chip Select SDRAM Data Mask SDRAM Clock SDRAM Clock Enable 16-bit SRAM Byte Enable
S3C2400 RISC MICROPROCESSOR
Table 1-3. S3C2400 Signal Descriptions (Continued) Signal Description
CONTROL UNIT VD[15:0] VCLK VFRAME VLINE VSYNC HSYNC VDEN LEND STN/TFT: Data STN/TFT: clock signal STN: Frame signal STN: line signal STN: alternates polarity column voltage TFT: Vertical synchronous signal TFT: Horizontal synchronous signal TFT: Data enable signal TFT: Line signal
INTERRUPT CONTROL UNIT EINT[7:0] nXDREQ[1:0] nXDACK[1:0] UART RxD[1:0] TxD[1:0] nCTS[1:0] nRTS[1:0] IIC-BUS IICSDA IICSCL IIS-BUS I2SLRCK I2SSDO I2SSDI I2SSCLK CDCLK IIS-bus channel select clock IIS-bus serial data output IIS-bus serial data input IIS-bus serial clock CODEC system clock IIC-bus data IIC-bus clock UART receives data input UART transmits data output UART clear send input signal UART request send output signal External request External acknowledge External Interrupt request
1-22
S3C2400 RISC MICROPROCESSOR
Table 1-3. S3C2400 Signal Descriptions (Continued) Signal AIN[7:0] Avref HOST DN[1:0] DP[1:0] DEVICE PDN0 PDP0 SPIMISO SPIMOSI SPICLK SPIMISO master data input line, when configured master. When configured slave, this reverse role. SPIMOSI master data output line, when configured master. When configured slave, this reverse role. clock chip select When configured master ENMUL set, slave select. When configured slave, also slave select. DATA peripheral DATA peripheral DATA from host DATA from host input[7:0] Vref Description
MMCDAT MMCCMD MMCCLK GENERAL PORT GPn[89:0] TIMMER/PWM TOUT[3:0] TCLK[1:0] Timer output[3:0] External clock input General input/output ports (some ports output mode only) receive/transmit data receive/transmit command clock
1-23
S3C2400 RISC MICROPROCESSOR
Table 1-3. S3C2400 Signal Descriptions (Continued) Signal JTAG TEST LOGIC nTRST nTRST(TAP Controller Reset) resets controller start. debugger used, pull-up resistor connected. debugger(black ICE) used, nTRST must active pulse. (TAP Controller Mode Select) controls sequence controller's states. pull-up resistor connected pin. (TAP Controller Clock) provides clock input JTAG logic. pull-up resistor must connected pin. (TAP Controller Data Input) serial input test instructions data. pull-up resistor must connected pin. (TAP Controller Data Output) serial output test instructions data. Description
RESET CLOCK POWER nRESET nRESET suspends operation progress places S3C2400 into known reset state. reset, nRESET must held level least FCLK after processor power been stabilized. OM[3:2] determines clock made. OM[3:2] 00b, Crystal used MPLL source UPLL source. OM[3:2] 01b, Crystal used MPLL source EXTCLK used UPLL source. OM[3:2] 10b, EXTCLK used MPLL source Crystal used UPLL source. OM[3:2] 11b, EXTCLK used MPLL source UPLL source. EXTCLK External clock source. When OM[3:2] 11b, EXTCLK used MPLL source UPLL source. When OM[3:2] 10b, EXTCLK used MPLL source only. When OM[3:2] 01b, EXTCLK used UPLL source only. isn't used, (3.3V). Crystal Input internal circuit. When OM[3:2] 00b, XTIpll used MPLL source UPLL source. When OM[3:2] 01b, XTIpll used MPLL source only. When OM[3:2] 10b, XTIpll used UPLL source only. isn't used, XTIpll (3.3V). Crystal Output internal circuit. When OM[3:2] 00b, XTIpll used MPLL source UPLL source. When OM[3:2] 01b, XTIpll used MPLL source only. When OM[3:2] 10b, XTIpll used UPLL source only. isn't used, floating pin.
OM[3:2]
XTIpll
XTOpll
NOTES: means input/output. AI/AO means analog input/output. means schmitt-trigger. means power.
1-24
S3C2400 RISC MICROPROCESSOR
Table 1-3. S3C2400 Signal Descriptions (Continued) Signal Description
RESET CLOCK POWER (continued) MPLLCAP UPLLCAP XTIrtc XTOrtc CLKOUT POWER VDDi VSSi VDDi_MPLL VSSi_MPLL VDDIO VSSIO RTCVDD VDDi_UPLL VSSi_UPLL VDDA_ADC VSSA_ADC S3C2400 core logic VDD(1.8V) CPU. S3C2400 core logic S3C2400 MPLL analog digital (1.8 S3C2400 MPLL analog digital VSS. S3C2400 port VDD(3.3V) S3C2400 port (1.8 support 3.3V) (This must connected power properly isn't used) S3C2400 UPLL analog digital (1.8V) S3C2400 UPLL analog digital S3C2400 VDD(3.3V) S3C2400 Loop filter capacitor main clock. Loop filter capacitor clock. crystal input RTC. crystal output RTC. Clock output signal. CLKSEL MISCCR register configures clock output mode among MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK.
1-25
S3C2400 RISC MICROPROCESSOR
S3C2400 SPECIAL REGISTERS Table 1-4. S3C2400 Special Registers Register Name Address Endian) Address Endian) Acc. Unit Read/ Write Function
MEMORY CONTROLLER BWSCON BANKCON0 BANKCON1 BANKCON2 BANKCON3 BANKCON4 BANKCON5 BANKCON6 BANKCON7 REFRESH BANKSIZE MRSRB6 MRSRB7 0x14000000 0x14000004 0x14000008 0x1400000c 0x14000010 0x14000014 0x14000018 0x1400001c 0x14000020 0x14000024 0x14000028 0x1400002c 0x14000030 Width Wait Status Control Boot Control BANK1 Control BANK2 Control BANK3 Control BANK4 Control BANK5 Control BANK6 Control BANK7 Control DRAM/SDRAM Refresh Control Flexible Bank Size Mode register SDRAM Mode register SDRAM
1-26
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name HOST CONTROLLER HcRevision HcControl HcCommonStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCuttentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 INTERRUPT CONTROLLER SRCPND INTMOD INTMSK PRIORITY INTPND INTOFFSET 0x14400000 0x14400004 0x14400008 0x1440000c 0x14400010 0x14400014 Interrupt Request Status Interrupt Mode Control Interrupt Mask Control Priority Control Interrupt Request Status Interrupt request source 0x14200000 0x14200004 0x14200008 0x1420000c 0x14200010 0x14200014 0x14200018 0x1420001c 0x14200020 0x14200024 0x14200028 0x1420002c 0x14200030 0x14200034 0x14200038 0x1420003c 0x14200040 0x14200044 0x14200048 0x1420004c 0x14200050 0x14200054 0x14200058 Root Group Frame Counter Group Memory Pointer Group
Address Endian)
Address Endian)
Acc. Unit
Read/ Write
Function
Control Status Group
1-27
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name DISRC0 DIDST0 DCON0 DSTAT0 DCSRC0 DCDST0 DMASKTRIG0 DISRC1 DIDST1 DCON1 DSTAT1 DCSRC1 DCDST1 DMASKTRIG1 DISRC2 DIDST2 DCON2 DSTAT2 DCSRC2 DCDST2 DMASKTRIG2 DISRC3 DIDST3 DCON3 DSTAT3 DCSRC3 DCDST3 DMASKTRIG3 0x14600000 0x14600004 0x14600008 0x1460000c 0x14600010 0x14600014 0x14600018 0x14600020 0x14600024 0x14600028 0x1460002c 0x14600030 0x14600034 0x14600038 0x14600040 0x14600044 0x14600048 0x1460004c 0x14600050 0x14600054 0x14600058 0x14600060 0x14600064 0x14600068 0x1460006c 0x14600060 0x14600064 0x14600068
Address Endian)
Address Endian)
Acc. Unit
Read/ Write
Function
Initial Source Initial Destination Control
Count Current Source Address Current Destination Address
Mask Trigger Initial Source Initial Destination Control
Count Current Source Address Current Destination Address
Mask Trigger Initial Source Initial Destination Control
Count Current Source Address Current Destination Address
Mask Trigger Initial Source Initial Destination Control Count Current Source Address Current Destination Address Mask Trigger
1-28
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name Address Endian) Address Endian) Acc. Unit Read/ Write Function
CLOCK POWER MANAGEMENT LOCKTIME MPLLCON UPLLCON CLKCON CLKSLOW CLKDIVN CONTROLLER LCDCON1 LCDCON2 LCDCON3 LCDCON4 LCDCON5 LCDSADDR1 LCDSADDR2 LCDSADDR3 REDLUT GREENLUT BLUELUT DP1_2 DP4_7 DP3_5 DP2_3 DP5_7 DP3_4 DP4_5 DP6_7 DITHMODE TPAL 0x14a00000 0x14a00004 0x14a00008 0x14a0000c 0x14a00010 0x14a00014 0x14a00018 0x14a0001c 0x14a00020 0x14a00024 0x14a00028 0x14a0002c 0x14a00030 0x14a00034 0x14a00038 0x14a0003c 0x14a00040 0x14a00044 0x14a00048 0x14a0004c 0x14a00050 Control Control Control Control Control STN/TFT: Frame Buffer Start Address1 STN/TFT: Frame Buffer Start Address2 STN/TFT: Virtual Screen Address STN: Lookup Table STN: Green Lookup Table STN: Blue Lookup Table STN: Dithering Pattern Duty STN: Dithering Pattern Duty STN: Dithering Pattern Duty STN: Dithering Pattern Duty STN: Dithering Pattern Duty STN: Dithering Pattern Duty STN: Dithering Pattern Duty STN: Dithering Pattern Duty STN: Dithering Mode TFT: Temporary Palette 0x14800000 0x14800004 0x14800008 0x1480000c 0x14800010 0x14800014 Lock Time Counter MPLL Control UPLL Control Clock Generator Control Slow Clock Control Clock divider Control
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S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name UART ULCON0 UCON0 UFCON0 UMCON0 UTRSTAT0 UERSTAT0 UFSTAT0 UMSTAT0 UTXH0 URXH0 UBRDIV0 ULCON1 UCON1 UFCON1 UMCON1 UTRSTAT1 UERSTAT1 UFSTAT1 UMSTAT1 UTXH1 URXH1 UBRDIV1 0x15000000 0x15000004 0x15000008 0x1500000c 0x15000010 0x15000014 0x15000018 0x1500001c 0x15000023 0x15000027 0x15000028 0x15004000 0x15004004 0x15004008 0x1500400c 0x15004010 0x15004014 0x15004018 0x1500401c 0x15004023 0x15004027 0x15004028 0x15004020 0x15004024
Address Endian)
Address Endian)
Acc. Unit
Read/ Write
Function
UART Line Control UART Control UART FIFO Control UART Modem Control
UART Tx/Rx Status UART Error Status UART FIFO Status UART Modem Status
0x15000020 0x15000024
UART Transmission Hold UART Receive Buffer UART Baud Rate Divisor UART Line Control UART Control UART FIFO Control UART Modem Control
UART Tx/Rx Status UART Error Status UART FIFO Status UART Modem Status
UART Transmission Hold UART Receive Buffer UART Baud Rate Divisor
1-30
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name TIMER TCFG0 TCFG1 TCON TCNTB0 TCMPB0 TCNTO0 TCNTB1 TCMPB1 TCNTO1 TCNTB2 TCMPB2 TCNTO2 TCNTB3 TCMPB3 TCNTO3 TCNTB4 TCNTO4 0x15100000 0x15100004 0x15100008 0x1510000c 0x15100010 0x15100014 0x15100018 0x1510001c 0x15100020 0x15100024 0x15100028 0x1510002c 0x15100030 0x15100034 0x15100038 0x1510003c 0x15100040
Address Endian)
Address Endian)
Acc. Unit
Read/ Write
Function
Timer Configuration Timer Configuration Timer Control Timer Count Buffer Timer Compare Buffer Timer Count Observation Timer Count Buffer Timer Compare Buffer Timer Count Observation Timer Count Buffer Timer Compare Buffer Timer Count Observation Timer Count Buffer Timer Compare Buffer Timer Count Observation Timer Count Buffer Timer Count Observation
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name DEVICE FUNC_ADDR_REG PWR_REG INT_REG INT_MASK_REG FRAME_NUM_REG RESUME_CON_REG EP0_CSR EP0_MAXP EP0_OUT_CNT EP0_FIFO EP1_IN_CSR EP1_IN_MAXP EP1_FIFO EP2_IN_CSR EP2_IN_MAXP EP2_FIFO EP3_OUT_CSR EP3_OUT_MAXP EP3_OUT_CNT EP3_FIFO EP4_OUT_CSR EP4_OUT_MAXP EP4_OUT_CNT EP4_FIFO DMA_CON DMA_UNIT DMA_FIFO DMA_TX TEST_MODE IN_CON_REG 0x15200140 0x15200144 0x15200148 0x1520014c 0x15200150 0x15200154 0x15200160 0x15200164 0x15200168 0x1520016c 0x15200180 0x15200184 0x15200188 0x15200190 0x15200194 0x15200198 0x152001a0 0x152001a4 0x152001a8 0x152001ac 0x152001b0 0x152001b4 0x152001b8 0x152001bc 0x152001c0 0x152001c4 0x152001c8 0x152001cc 0x152001f4 0x152001f8
Address Endian)
Address Endian)
Acc. Unit
Read/W rite
Function
Function Address Power Management Interrupt Pending Clear Interrupt Mask Frame Number Resume Signal Control Clock Generator Control Point0 Packet Point0 Write Count Point0 FIFO Read/Write Point1 Control Status Point1 Packet Point2 FIFO Write Point2 Control Status Point2 Packet Point2 FIFO Write Point3 Control Status Point3 Packet Point3 Write Count Point3 FIFO Read Point4 Control Status Point4 Packet Point4 Write Count Point4 FIFO Read Interface Control Transfer Unit Counter Transfer FIFO Counter Total Transfer Counter Test Mode Control Packet Number Control
1-32
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name WATCHDOG TIMER WTCON WTDAT WTCNT IICCON IICSTAT IICADD IICDS IISCON IISMOD IISPSR IISFIFCON IISFIF 0x15508000,02 0x15508004,06 0x15508008,0a 0x1550800c,0e 0x15508012 0x15508000 0x15508004 0x15508008 0x1550800c 0x15508010 HW,W HW,W HW,W HW,W Control Mode Prescaler FIFO Control FIFO Entry 0x15400000 0x15400004 0x15400008 0x1540000c
Address Endian)
Address Endian)
Acc. Unit
Read/ Write
Function
0x15300000 0x15300004 0x15300008
Watch-Dog Timer Mode Watch-Dog Timer Data Watch-Dog Timer Count
Control Status Address Data Shift
1-33
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name PORT PACON PADAT PBCON PBDAT PBUP PCCON PCDAT PCUP PDCON PDDAT PDUP PECON PEDAT PEUP PFCON PFDAT PFUP PGCON PGDAT PGUP OPENCR MISCCR EXTINT 0x15600000 0x15600004 0x15600008 0x1560000c 0x15600010 0x15600014 0x15600018 0x1560001c 0x15600020 0x15600024 0x15600028 0x1560002c 0x15600030 0x15600034 0x15600038 0x1560003c 0x15600040 0x15600044 0x15600048 0x1560004c 0x15600050 0x15600054 0x15600058
Address Endian)
Address Endian)
Acc. Unit
Read/ Write
Function
Port Control Port Data Port Control Port Data Pull-up Control Port Control Port Data Pull-up Control Port Control Port Data Pull-up Control Port Control Port Data Pull-up Control Port Control Port Data Pull-up Control Port Control Port Data Pull-up Control Open Drain Enable Miscellaneous Control External Interrupt Control
1-34
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name RTCCON TICINT RTCALM ALMSEC ALMMIN ALMHOUR ALMDAY ALMMON ALMYEAR RTCRST BCDSEC BCDMIN BCDHOUR BCDDAY BCDDATE BCDMON BCDYEAR CONVERTER ADCCON ADCDAT SPCON SPSTA SPPIN SPPRE SPTDAT SPRDAT 0x15900000 0x15900004 0x15900008 0x1590000c 0x15900010 0x15900014
Address Endian)
Address Endian)
Acc. Unit
Read/ Write
Function
0x15700043 0x15700047 0x15700053 0x15700057 0x1570005b 0x1570005f 0x15700063 0x15700067 0x1570006b 0x1570006f 0x15700073 0x15700077 0x1570007b 0x1570007f 0x15700083 0x15700087 0x1570008b
0x15700040 0x15700044 0x15700050 0x15700054 0x15700058 0x1570005c 0x15700060 0x15700064 0x15700068 0x1570006c 0x15700070 0x15700074 0x15700078 0x1570007c 0x15700080 0x15700084 0x15700088
Control Tick time count Alarm Control Alarm Second Alarm Minute Alarm Hour Alarm Alarm Month Alarm Year Round Reset Second Minute Hour Date Month Year
0x15800000 0x15800004
Control Data
Control Status Control Baud Rate Prescaler Data Data
1-35
S3C2400 RISC MICROPROCESSOR
Table 1-4. S3C2400 Special Registers (Continued) Register Name INTERFACE MMCON MMCRR MMFCON MMSTA MMFSTA MMPRE MMLEN MMCR7 MMRSP0 MMRSP1 MMRSP2 MMRSP3 MMCMD0 MMCMD1 MMCR16 MMDAT 0x15a00000,02,03 0x15a00004,06,07 0x15a00008,0a,0b 0x15a0000c,0e,0f 0x15a00010,12 0x15a00014,16,17 0x15a00018,1a 0x15a0001c,0e,0f 0x15a00020 0x15a00024 0x15a00028 0x15a0002c 0x15a00030,32,33 0x15a00034 0x15a00038,3a 0x15a0003c,3e,3f 0x15a00030
Address Endian)
Address Endian)
Acc. Unit
Read/ Write
Function
0x15a00000 0x15a00004 0x15a00008 0x15a0000c 0x15a00010 0x15a00014 0x15a00018 0x15a0001c
Control Command FIFO Control
Status FIFO Status Baud Rate Prescaler Block Length Response CRC7 Response Status Response Status Response Status Response Status
Command Command
0x15a00038 0x15a0003c
Data Read CRC16 Buffer Data
1-36
S3C2400 RISC MICROPROCESSOR
IMPORTANT NOTES ABOUT S3C2400 SPECIAL REGISTERS little endian mode, endian address must used. endian mode, endian address must used. special registers have accessed recommended access unit. registers except registers, registers UART registers must read/written word unit (32bit) little/big endian. very important that registers, registers UART registers read/written specified access unit specified address. Moreover, must carefully consider which endian mode used. 32-bit register, which must accessed LDR/STR type pointer(int 16-bit register, which must accessed LDRH/STRH short type pointer(short 8-bit register, which must accessed LDRB/STRB char type pointer(char
1-37
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
OVERVIEW
PROGRAMMER'S MODEL
S3C2400X01 been developed using advanced ARM920T core, which been designed Advanced RISC Machines, Ltd. PROCESSOR OPERATING STATES From programmer's point view, ARM920T states: state which executes 32-bit, word-aligned instructions. THUMB state which execute 16-bit, halfword-aligned THUMB instructions. this state, uses select between alternate halfwords. NOTE Transition between these states does affect processor mode contents registers. SWITCHING STATE Entering THUMB State Entry into THUMB state achieved executing instruction with state (bit operand register. Transition THUMB state will also occur automatically return from exception (IRQ, FIQ, UNDEF, ABORT, etc.), exception entered with processor THUMB state. Entering State Entry into state happens: execution instruction with state clear operand register. processor taking exception (IRQ, FIQ, RESET, UNDEF, ABORT, etc.). this case, placed exception mode's link register, execution commences exception's vector address.
MEMORY FORMATS ARM920T views memory linear collection bytes numbered upwards from zero. Bytes hold first stored word, bytes second ARM920T treat words memory being stored either BigEndian Little-Endian format.
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
BIG-ENDIAN FORMAT Big-Endian format, most significant byte word stored lowest numbered byte least significant byte highest numbered byte. Byte memory system therefore connected data lines through
Higher Address Lower Address
Word Address
Most significant byte lowest address. Word addressed byte address most significant byte.
Figure 2-1. Big-Endian Addresses Bytes within Words LITTLE-ENDIAN FORMAT Little-Endian format, lowest numbered byte word considered word's least significant byte, highest numbered byte most significant. Byte memory system therefore connected data lines through
Higher Address Lower Address
Word Address
Least significant byte lowest address. Word addressed byte address least significant byte.
Figure 2-2. Little-Endian Addresses Bytes whthin Words INSTRUCTION LENGTH Instructions either bits long state) bits long THUMB state). Data Types ARM920T supports byte (8-bit), halfword (16-bit) word (32-bit) data types. Words must aligned four-byte boundaries half words two-byte boundaries.
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
OPERATING MODES ARM920T supports seven modes operation:
User (usr): normal program execution state (fiq): Designed support data transfer channel process (irq): Used general-purpose interrupt handling Supervisor (svc): Protected mode operating system Abort mode (abt): Entered after data instruction prefetch abort System (sys): privileged user mode operating system Undefined (und): Entered when undefined instruction executed
Mode changes made under software control, brought about external interrupts exception processing. Most application programs will execute User mode. non-user modes' known privileged modesare entered order service interrupts exceptions, access protected resources. REGISTERS ARM920T total registers general-purpose 32-bit registers status registers these cannot seen once. processor state operating mode dictate which registers available programmer. State Register state, general registers status registers visible time. privileged (nonUser) modes, mode-specific banked registers switched Figure shows which registers available each mode: banked registers marked with shaded triangle. state register contains directly accessible registers: R15. these except generalpurpose, used hold either data address values. addition these, there seventeenth register used store status information. Register used subroutine link register. This receives copy when Branch Link (BL) instruction executed. other times treated generalpurpose register. corresponding banked registers R14_svc, R14_irq, R14_fiq, R14_abt R14_und similarly used hold return values when interrupts exceptions arise, when Branch Link instructions executed within interrupt exception routines. holds Program Counter (PC). state, bits [1:0] zero bits [31:2] contain THUMB state, zero bits [31:1] contain CPSR (Current Program Status Register). This contains condition code flags current mode bits.
Register Register
mode seven banked registers mapped R8-14 (R8_fiq-R14_fiq). state, many handlers need save registers. User, IRQ, Supervisor, Abort Undefined each have banked registers mapped R14, allowing each these modes have private stack pointer link registers.
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
State General Registers Program Counter
System User (PC) R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq (PC) Supervisor R13_svc R14_svc (PC) Abort R13_abt R14_abt (PC) R13_irq R14_irq (PC) Undefined R13_und R14_und (PC)
State Program Status Registers
CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und
banked register
Figure 2-3. Register Organization State
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
THUMB State Register THUMB state register subset state set. programmer direct access eight general registers, R0-R7, well Program Counter (PC), stack pointer register (SP), link register (LR), CPSR. There banked Stack Pointers, Link Registers Saved Process Status Registers (SPSRs) each privileged mode. This shown Figure 2-4.
THUMB State General Registers Program Counter
System User SP_fiq LR_fiq Supervisor SP_svc LR_svc Abort SP_abt LR_abt SP_und LR_und Undefined SP_fiq LR_fiq
THUMB State Program Status Registers
CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und
banked register
Figure 2-4. Register Organization THUMB state
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
relationship between THUMB state registers THUMB state registers relate state registers following way:
THUMB state R0-R7 state R0-R7 identical THUMB state CPSR SPSRs state CPSR SPSRs identical THUMB state maps onto state THUMB state maps onto state THUMB state Program Counter maps onto state Program Counter (R15)
This relationship shown Figure 2-5.
THUMB state
state Stack Pointer (R13) Link register (R14) Program Counter (R15) CPSR SPSR
Stack Pointer (SP) Link register (LR) Program Counter (PC) CPSR SPSR
Figure 2-5. Mapping THUMB State Registers onto State Registers
Hi-registers
Lo-registers
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
Accessing Hi-Registers THUMB State THUMB state, registers R8-R15 (the registers) part standard register set. However, assembly language programmer limited access them, them fast temporary storage. value transferred from register range R0-R7 register) register, from register register, using special variants instruction. register values also compared against added register values with instructions. more information, refer Figure 3-34. PROGRAM STATUS REGISTERS ARM920T contains Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) exception handlers. These register's functions are:
Hold information about most recently performed operation Control enabling disabling interrupts processor operating mode
arrangement bits shown Figure 2-6.
Condition Code Flags
(Reserved) Overflow Carry/Borrow/Extend Zero Negative/Less Than
Control Bits
Mode bits State disable disable
Figure 2-6. Program Status Register Format
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
Condition Code Flags bits condition code flags. These changed result arithmetic logical operations, tested determine whether instruction should executed. state, instructions executed conditionally: Table details. THUMB state, only Branch instruction capable conditional execution: Figure 3-46 details. Control Bits bottom bits (incorporating M[4:0]) known collectively control bits. These will changed when exception arises. processor operating privileged mode, they also manipulated software. This reflects operating state. When this set, processor executing THUMB state, otherwise executing state. This reflected TBIT external signal. Note that software must never change state TBIT CPSR. this happens, processor will enter unpredictable state. Interrupt disable bits mode bits bits interrupt disable bits. When set, these disable interrupts respectively. bits (M[4:0]) mode bits. These determine processor's operating mode, shown Table 2-1. combinations mode bits define valid processor mode. Only those explicitly described shall used. user should aware that illegal value programmed into mode bits, M[4:0], then processor will enter unrecoverable state. this occurs, reset should applied. remaining bits PSRs reserved. When changing PSR's flag control bits, must ensure that these unused bits altered. Also, your program should rely them containing specific values, since future processors they read zero.
Reserved bits
S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
Table 2-1. Mode Values M[4:0] 10000 User Mode Visible THUMB state registers R7.R0, CPSR R7.R0, LR_fiq, SP_fiq CPSR, SPSR_fiq R7.R0, LR_irq, SP_irq CPSR, SPSR_irq R7.R0, LR_svc, SP_svc, CPSR, SPSR_svc R7.R0, LR_abt, SP_abt, CPSR, SPSR_abt R7.R0 LR_und, SP_und, CPSR, SPSR_und R7.R0, CPSR Visible state registers R14.R0, CPSR R7.R0, R14_fiq.R8_fiq, CPSR, SPSR_fiq R12.R0, R14_irq, R13_irq, CPSR, SPSR_irq R12.R0, R14_svc, R13_svc, CPSR, SPSR_svc R12.R0, R14_abt, R13_abt, CPSR, SPSR_abt R12.R0, R14_und, R13_und, CPSR R14.R0, CPSR
1000
10010
1001
Supervisor
1011
Abort
1101
Undefined
1111
System
Reserved bits
remaining bits PSR's reserved. When changing PSR's flag control bits, must ensure that these unused bits altered. Also, your program should rely them containing specific values, since future processors they read zero.
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
EXCEPTIONS Exceptions arise whenever normal flow program halted temporarily, example service interrupt from peripheral. Before exception handled, current processor state must preserved that original program resume when handler routine finished. possible several exceptions arise same time. this happens, they dealt with fixed order. Exception Priorities page 2-14. Action Entering Exception When handling exception, ARM920T: Preserves address next instruction appropriate Link Register. exception been entered from state, then address next instruction copied into Link Register (that current depending exception. Table details). exception been entered from THUMB state, then value written into Link Register current offset value such that program resumes from correct place return from exception. This means that exception handler need determine which state exception entered from. example, case SWI, MOVS R14_svc will always return next instruction regardless whether executed THUMB state. Copies CPSR into appropriate SPSR Forces CPSR mode bits value which depends exception Forces fetch next instruction from relevant exception vector
also interrupt disable flags prevent otherwise unmanageable nestings exceptions. processor THUMB state when exception occurs, will automatically switch into state when loaded with exception vector address. Action Leaving Exception completion, exception handler: Moves Link Register, minus offset where appropriate, (The offset will vary depending type exception.) Copies SPSR back CPSR Clears interrupt disable flags, they were entry NOTE explicit switch back THUMB state never needed, since restoring CPSR from SPSR automatically sets value held immediately prior exception.
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PROGRAMMER'S MODEL
Exception Entry/Exit Summary Table summarises value preserved relevant exception entry, recommended instruction exiting exception handler. Table2-2. Exception Entry/Exit Return Instruction Previous State R14_x UDEF PABT DABT RESET MOVS R14_svc MOVS R14_und SUBS R14_fiq, SUBS R14_irq, SUBS R14_abt, SUBS R14_abt, THUMB R14_x Notes
NOTES: Where address BL/SWI/Undefined Instruction fetch which prefetch abort. Where address instruction which executed since took priority. Where address Load Store instruction which generated data abort. value saved R14_svc upon reset unpredictable.
(Fast Interrupt Request) exception designed support data transfer channel process, state sufficient private registers remove need register saving (thus minimising overhead context switching). externally generated taking nFIQ input LOW. This input except either synchronous asynchronous transitions, depending state ISYNC input signal. When ISYNC LOW, nFIQ nIRQ considered asynchronous, cycle delay synchronization incurred before interrupt affect processor flow. Irrespective whether exception entered from Thumb state, handler should leave interrupt executing SUBS PC,R14_fiq,#4
disabled setting CPSR's flag (but note that this possible from User mode). flag clear, ARM920T checks level output synchroniser each instruction.
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
(Interrupt Request) exception normal interrupt caused level nIRQ input. lower priority than masked when sequence entered. disabled time setting CPSR, though this only done from privileged (non-User) mode. Irrespective whether exception entered from Thumb state, handler should return from interrupt executing SUBS Abort abort indicates that current memory access cannot completed. signalled external ABORT input. ARM920T checks abort exception during memory access cycles. There types abort:
PC,R14_irq,#4
Prefetch abort: occurs during instruction prefetch. Data abort: occurs during data access.
prefetch abort occurs, prefetched instruction marked invalid, exception will taken until instruction reaches head pipeline. instruction executed example because branch occurs while pipeline abort does take place. data abort occurs, action taken depends instruction type:
Single data transfer instructions (LDR, STR) write back modified base registers: Abort handler must aware this. swap instruction (SWP) aborted though been executed. Block data transfer instructions (LDM, STM) complete. write-back set, base updated. instruction would have overwritten base with data base transfer list), overwriting prevented. register overwriting prevented after abort indicated, which means particular that (always last register transferred) preserved aborted instruction.
abort mechanism allows implementation demand paged virtual memory system. such system processor allowed generate arbitrary addresses. When data address unavailable, Memory Management Unit (MMU) signals abort. abort handler must then work cause abort, make requested data available, retry aborted instruction. application program needs knowledge amount memory available state affected abort. After fixing reason abort, handler should execute following irrespective state (ARM Thumb): SUBS SUBS PC,R14_abt,#4 PC,R14_abt,#8 prefetch abort, data abort
This restores both CPSR, retries aborted instruction.
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S3C2400X01 RISC MICROPROCESSOR
PROGRAMMER'S MODEL
Software Interrupt software interrupt instruction (SWI) used entering Supervisor mode, usually request particular supervisor function. handler should return executing following irrespective state (ARM Thumb): PC,R14_svc
This restores CPSR, returns instruction following SWI. NOTE nFIQ, nIRQ, ISYNC, LOCK, BIGEND, ABORT pins exist only ARM920T core. Undefined Instruction When ARM920T comes across instruction which cannot handle, takes undefined instruction trap. This mechanism used extend either THUMB instruction software emulation. After emulating failed instruction, trap handler should execute following irrespective state (ARM Thumb): MOVS PC,R14_und
This restores CPSR returns instruction following undefined instruction. Exception Vectors following table shows exception vector addresses. Table 2-3. Exception Vectors Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C Reset Undefined instruction Software Interrupt Abort (prefetch) Abort (data) Reserved Exception Supervisor Undefined Supervisor Abort Abort Reserved Mode Entry
2-13
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
Exception Priorites When multiple exceptions arise same time, fixed priority system determines order which they handled: Highest priority: Reset Data abort Prefetch abort
Lowest priority: Undefined Instruction, Software interrupt.
Exceptions Occur Once: Undefined Instruction Software Interrupt mutually exclusive, since they each correspond particular (nonoverlapping) decodings current instruction. data abort occurs same time FIQ, FIQs enabled CPSR's flag clear), ARM920T enters data abort handler then immediately proceeds vector. normal return from will cause data abort handler resume execution. Placing data abort higher priority than necessary ensure that transfer error does escape detection. time this exception entry should added worst-case latency calculations.
2-14
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PROGRAMMER'S MODEL
INTERRUPT LATENCIES worst case latency FIQ, assuming that enabled, consists longest time request take pass through synchroniser (Tsyncmax asynchronous), plus time longest instruction complete (Tldm, longest instruction which loads registers including PC), plus time data abort entry (Texc), plus time entry (Tfiq). this time ARM920T will executing instruction 0x1C. Tsyncmax processor cycles, Tldm cycles, Texc cycles, Tfiq cycles. total time therefore processor cycles. This just over microseconds system which uses continuous processor clock. maximum latency calculation similar, must allow fact that higher priority could delay entry into handling routine arbitrary length time. minimum latency consists shortest time request take through synchroniser (Tsyncmin) plus Tfiq. This processor cycles. RESET When nRESET signal goes LOW, ARM920T abandons executing instruction then continues fetch instructions from incrementing word addresses. When nRESET goes HIGH again, ARM920T: Overwrites R14_svc SPSR_svc copying current values CPSR into them. value saved SPSR defined. Forces M[4:0] 10011 (Supervisor mode), sets bits CPSR, clears CPSR's bit. Forces fetch next instruction from address 0x00. Execution resumes state.
2-15
PROGRAMMER'S MODEL
S3C2400X01 RISC MICROPROCESSOR
NOTES
2-16
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
INSTRUCTION
INSTRUCTION SUMMAY
This chapter describes instruction ARM920T core.
FORMAT SUMMARY instruction formats shown below.
Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Cond Opcode RdHi RdLo Operand2 Offset Data/Processing/ Transfer Multiply Multiply Long Single Data Swap Branch Exchange Halfword Data Transfer: register offset Halfword Data Transfer: immendiate offset Single Data Transfer Offset Offset Register List Undefined Block Data Transfer Branch Coprocessor Data Transfer Coprocessor Data Operation Coprocessor Register Transfer Software Interrupt
Offset Offset
Ignored processor
Figure 3-1. Instruction Format
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
NOTES Some instruction codes defined cause Undefined instruction trap taken, instance Multiply instruction with changed These instructions should used, their action change future implementations.
INSTRUCTION SUMMARY Table 3-1. Instruction Mnemonic with carry Branch Clear Branch with Link Branch Exchange Coprocessor Data Processing Compare Negative Compare Exclusive Load coprocessor from memory Load multiple registers Load register from memory Move register coprocessor register Multiply Accumulate Move register constant Instruction Action Carry R15: address R14: R15, R15: address R15: bit: Rn[0] (Coprocessor-specific) CPSR flags: CPSR flags: Op2) (Op2 Coprocessor load Stack manipulation (Pop) (address) cRn: {<op>cRm}
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
Table 3-1. Instruction (Continued) Mnemonic SSTR Instruction Move from coprocessor register register Move status/flags register Move register status/flags Multiply Move negative register Reverse Subtract Reverse Subtract with Carry Subtract with Carry Store coprocessor register memory Store Multiple Store register memory Subtract Software Interrupt Swap register with memory Test bitwise equality Test bits Action {<op>cRm} PSR: FFFFFFFF Carry Carry address: Stack manipulation (Push) <address>: call [Rn], [Rn] CPSR flags: CPSR flags:
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
CONDITION FIELD
state, instructions conditionally executed according state CPSR condition codes instruction's condition field. This field (bits 31:28) determines circumstances under which instruction executed. state flags fulfils conditions encoded field, instruction executed, otherwise ignored. There sixteen possible conditions, each represented two-character suffix that appended instruction's mnemonic. example, Branch assembly language) becomes "Branch Equal", which means Branch will only taken flag set. practice, fifteen different conditions used: these listed Table 3-2. sixteenth (1111) reserved, must used. absence suffix, condition field most instructions "Always" (suffix AL). This means instruction will always executed regardless CPSR condition codes. Table 3-2. Condition Code Summary Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Suffix clear clear clear clear clear clear equals equal clear equals equal (ignored) Flags equal equal unsigned higher same unsigned lower negative positive zero overflow overflow unsigned higher unsigned lower same greater equal less than greater than less than equal always Meaning
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
BRANCH EXCHANGE (BX)
This instruction only executed condition true. various conditions defined Table 3-2. This instruction performs branch copying contents general register, into program counter, branch causes pipeline flush refill from address specified This instruction also permits instruction exchanged. When instruction executed, value Rn[0] determines whether instruction stream will decoded THUMB instructions.
Cond
[3:0] Operand Register
bit0 subsequent instructions decoded THUMB instructions bit0 subsequent instructions decoded instructions
[31:28] Condition Field
Figure 3-2. Branch Exchange Instructions INSTRUCTION CYCLE TIMES instruction takes cycles execute, where defined sequential (S-cycle) nonsequential (N-cycle), respectively.
ASSEMBLER SYNTAX branch exchange. {cond} {cond}
character condition mnemonic. Table 3-2. expression evaluating valid register number.
USING OPERAND used operand, behavior undefined.
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
Examples Into_THUMB Generate branch target address high hence arrive THUMB state. Branch change THUMB state. Assemble subsequent code THUMB instructions
CODE16 Into_THUMB
Back_to_ARM
Generate branch target word aligned address hence change back state. Branch change back state.
ALIGN CODE32 Back_to_ARM
Word align Assemble subsequent code instructions
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
BRANCH BRANCH WITH LINK
instruction only executed condition true. various conditions defined Table 3-2. instruction encoding shown Figure 3-3, below.
Cond
Offset
[24] Link
Branch Branch with link
[31:28] Condition Field
Figure 3-3. Branch Instructions Branch instructions contain signed complement offset. This shifted left bits, sign extended bits, added instruction therefore specify branch 32Mbytes. branch offset must take account prefetch operation, which causes words bytes) ahead current instruction. Branches beyond 32Mbytes must offset absolute destination which been previously loaded into register. this case should manually saved Branch with Link type operation required.
LINK Branch with Link (BL) writes into link register (R14) current bank. value written into adjusted allow prefetch, contains address instruction following branch link instruction. Note that CPSR saved with R14[1:0] always cleared. return from routine called Branch with Link PC,R14 link register still valid Rn!,{.PC} link register been saved onto stack pointed
INSTRUCTION CYCLE TIMES Branch Branch with Link instructions take incremental cycles, where defined sequential (S-cycle) internal (I-cycle).
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
ASSEMBLER SYNTAX Items optional. Items must present. B{L}{cond} <expression> {cond} <expression> Examples here ADDS BLCC here there R1,#0 fred sub+ROM R1,#1 Assembles 0xEAFFFFFE (note effect offset). Always condition used default. Compare with zero branch fred zero, otherwise continue. Continue next instruction. Call subroutine computed address. register setting CPSR flags result then call subroutine flag clear, which will case unless held 0xFFFFFFFF. Used request Branch with Link form instruction. absent, will affected instruction. two-character mnemonic shown Table 3-2. absent then (ALways) will used. destination. assembler calculates offset.
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
DATA PROCESSING
data processing instruction only executed condition true. conditions defined Table 3-2. instruction encoding shown Figure 3-4.
Cond
Operand2
OpCode
[15:12] Destination register
Branch Branch with link
[19:16] operand register
Branch Branch with link
[20] condition codes
after condition codes condition codes
[24:21] Operation codes
0000 AND-Rd: 0001 EOR-Rd: 0010 SUB-Rd: Op1-Op2 0011 RSB-Rd: Op2-Op1 0100 ADD-Rd: Op1+Op2 0101 ADC-Rd: Op1+Op2+C 0110 SBC-Rd: OP1-Op2+C-1 0111 RSC-Rd: Op2-Op1+C-1 1000 TST-set condition codes 1001 TEO-set condition codes 1010 CMP-set condition codes Op1-Op2 1011 SMN-set condition codes Op1+Op2 1100 ORR-Rd: 1101 MOV-Rd: =Op2 1110 BIC-Rd: 1111 MVN-Rd:
[25] Immediate operand
Operand register Operand immediate value
[11:0] Operand type selection
Shift [3:0] operand register Rotate [11:8] Shift applied [11:4] Shift applied
[7:0] Unsigned immediate value
[31:28] Condition field Figure 3-4. Data Processing Instructions
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
instruction produces result performing specified arithmetic logical operation operands. first operand always register (Rn). second operand shifted register (Rm) rotated immediate value (Imm) according value instruction. condition codes CPSR preserved updated result this instruction, according value instruction. Certain operations (TST, TEQ, CMP, CMN) write result They used only perform tests condition codes result always have set. instructions their effects listed Table 3-3.
3-10
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
CPSR FLAGS data processing operations classified logical arithmetic. logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform logical action corresponding bits operand operands produce result. (and R15, below) flag CPSR will unaffected, flag will carry from barrel shifter preserved when shift operation #0), flag will only result zeros, flag will logical value result. Table 3-3. Data Processing Instructions Assembler Mnemonic Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Operand1 operand2 Operand1 operand2 Operand1 operand2 Operand2 operand1 Operand1 operand2 Operand1 operand2 carry Operand1 operand2 carry Operand2 operand1 carry AND, result written EOR, result written SUB, result written ADD, result written Operand1 operand2 Operand2 (operand1 ignored) Operand1 operand2 (Bit clear) operand2 (operand1 ignored) Action
arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand integer (either unsigned complement signed, equivalent). (and R15) flag CPSR will overflow occurs into result; this ignored operands were considered unsigned, warns possible error operands were complement signed. flag will carry ALU, flag will only result zero, flag will value result (indicating negative result operands considered complement signed).
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
SHIFTS When second operand specified shifted register, operation barrel shifter controlled Shift field instruction. This field indicates type shift performed (logical left right, arithmetic right rotate right). amount which register should shifted contained immediate field instruction, bottom byte another register (other than R15). encoding different shift types shown Figure 3-5.
[6:5] Shift type
logical left arithmetic right logical right rotate right
[6:5] Shift type
logical left arithmetic right logical right rotate right
[11:7] Shift amount
unsigned integer
[11:8] Shift register
Shift amount specified bottom-byte
Figure 3-5. Shift Operations Instruction specified shift amount When shift amount specified instruction, contained field which take value from logical shift left (LSL) takes contents moves each specified amount more significant position. least significant bits result filled with zeros, high bits which into result discarded, except that least significant discarded becomes shifter carry output which latched into CPSR when operation logical class (see above). example, effect shown Figure 3-6.
Contents
carry
Value Operand
Figure 3-6. Logical Shift Left NOTES special case, where shifter carry value CPSR flag. contents used directly second operand. logical shift right (LSR) similar, contents moved less significant positions result. effect shown Figure 3-7.
3-12
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
Contents
carry
Value Operand
Figure 3-7. Logical Shift Right form shift field which might expected correspond used encode #32, which zero result with carry output. Logical shift right zero redundant same logical shift left zero, assembler will convert (and into allow specified. arithmetic shift right (ASR) similar logical shift right, except that high bits filled with instead zeros. This preserves sign complement notation. example, shown Figure 3-8.
Contents
carry
Value Operand
Figure 3-8. Arithmetic Shift Right form shift field which might expected give used encode #32. again used carry output, each operand also equal result therefore ones zeros, according value
3-13
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
Rotate right (ROR) operations reuse bits which "overshoot" logical shift right operation reintroducing them high result, place zeros used fill high logical right operations. example, shown Figure 3-9.
Contents
carry
Value Operand
Figure 3-9. Rotate Right form shift field which might expected give used encode special function barrel shifter, rotate right extended (RRX). This rotate right position quantity formed appending CPSR flag most significant contents shown Figure 3-10.
Contents
Value Operand
carry
Figure 3-10. Rotate Right Extended
3-14
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
Register Specified Shift Amount Only least significant byte contents used determine shift amount. general register other than R15. this byte zero, unchanged contents will used second operand, value CPSR flag will passed shifter carry output. byte value between shifted result will exactly match that instruction specified shift with same value shift operation. value byte more, result will logical extension shift described above: result zero, carry equal more than result zero, carry zero. result zero, carry equal more than result zero, carry zero. more result filled with carry equal result equal carry equal where greater than will give same result carry n-32; therefore repeatedly subtract from until amount range above. NOTES zero instruction with register controlled shift compulsory; this will cause instruction multiply undefined instruction.
3-15
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
IMMEDIATE OPERAND ROTATES immediate operand rotate field unsigned integer which specifies shift operation immediate value. This value zero extended bits, then subject rotate right twice value rotate field. This enables many common constants generated, example powers WRITING When register other than R15, condition code flags CPSR updated from flags described above. When flag instruction result operation placed CPSR unaffected. When flag result operation placed SPSR corresponding current mode moved CPSR. This allows state changes which atomically restore both CPSR. This form instruction should used User mode. USING OPERANDY (the used operand data processing instruction register used directly. value will address instruction, plus bytes instruction prefetching. shift amount specified instruction, will bytes ahead. register used specify shift amount will bytes ahead. TEQ, TST, OPCODES NOTES TEQ, TST, write result their operation flags CPSR. assembler should always flag these instructions even this specified mnemonic. TEQP form instruction used earlier processors must used: transfer operations should used instead. action TEQP ARM920T move SPSR_<mode> CPSR processor privileged mode nothing User mode. INSTRUCTION CYCLE TIMES Data Processing instructions vary number incremental cycles taken follows: Table 3-4. Incremental Cycle Times Processing Type Normal data processing Data processing with register specified shift Data processing with written Data processing with register specified shift written
NOTE:
Cycles
defined sequential (S-cycle), non-sequential (N-cycle), internal (I-cycle) respectively.
3-16
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
ASSEMBLER SYNTAX
MOV,MVN (single operand instructions). <opcode>{cond}{S} Rd,<Op2> CMP,CMN,TEQ,TST (instructions which produce result). <opcode>{cond} Rn,<Op2> <opcode>{cond}{S} Rd,Rn,<Op2>
where: <Op2> {cond} Rm{,<shift>} or,<#expression> two-character condition mnemonic. Table 3-2. condition codes present (implied CMP, CMN, TEQ, TST).
Expressions evaluating register number. <#expression> <shift> <shiftname>s this used, assembler will attempt generate shifted immediate 8-bit field match expression. this impossible, will give error. <Shiftname> <register> <shiftname> #expression, (rotate right with extend). ASL, LSL, LSR, ASR, ROR. (ASL synonym LSL, they assemble same code.)
EXAMPLES ADDEQ TEQS R2,R4,R5 R4,#3 flag make R2:=R4+R5 Test equality with (The fact redundant assembler inserts automatically.) Logical right shift number bottom byte subtract result from answer into Return from subroutine. Return from exception restore CPSR from SPSR_mode.
R4,R5,R7,LSR
MOVS
PC,R14 PC,R14
3-17
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
TRANSFER (MRS, MSR)
instruction only executed condition true. various conditions defined Table 3-2. instructions formed from subset Data Processing operations implemented using TEQ, TST, instructions without flag set. encoding shown Figure 3-11. These instructions allow access CPSR SPSR registers. instruction allows contents CPSR SPSR_<mode> moved general register. instruction allows contents general register moved CPSR SPSR_<mode> register. instruction also allows immediate value register contents transferred condition code flags (N,Z,C CPSR SPSR_<mode> without affecting control bits. this case, four bits specified register contents immediate value written four bits relevant PSR.
OPERAND RESTRICTIONS
user mode, control bits CPSR protected from change, only condition code flags CPSR changed. other (privileged) modes entire CPSR changed. Note that software must never change state CPSR. this happens, processor will enter unpredictable state. SPSR register which accessed depends mode time execution. example, only SPSR_fiq accessible when processor mode. must specify source destination register. Also, attempt access SPSR User mode, since such register exists.
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
(transfer contents register)
Cond 00010 001111 000000000000
[15:12] Destination Register [22] Source
CPSR SPSR_<current mode>
[31:28] Condition Field (transfer register contents PSR)
Cond 00010 101001111 00000000
[3:0] Source Register [22] Destination
CPSR SPSR_<current mode>
[31:28] Condition Field (transfer register contents immediate value flag bits only)
Cond 101001111 Source operand
[22] Destination
CPSR SPSR_<current mode>
[25] Immediate Operand
Source operand register SPSR_<current mode>
[11:0] Source Operand
00000000
[3:0] Source Register [11:4] Source operand immediate value Rotate
[7:0] Unsigned immediate value [11:8] Shift applied
[31:28] Condition Field Figure 3-11. Transfer
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
RESERVED BITS Only twelve bits defined ARM920T (N,Z,C,V,I,F, M[4:0]); remaining bits reserved future versions processor. Refer Figure full description bits. ensure maximum compatibility between ARM920T programs future processors, following rules should observed: reserved bits should preserved when changing value PSR. Programs should rely specific values from reserved bits when checking status, since they read zero future processors.
read-modify-write strategy should therefore used when altering control bits register; this involves transferring appropriate register general register using instruction, changing only relevant bits then transferring modified value back register using instruction.
EXAMPLES following sequence performs mode change: R0,CPSR R0,R0,#0x1F R0,R0,#new_mode CPSR,R0 Take copy CPSR. Clear mode bits. Select mode Write back modified CPSR.
When simply change condition code flags PSR, value written directly flag bits without disturbing control bits. following instruction sets N,Z,C flags: CPSR_flg,#0xF0000000 flags regardless their previous state (does affect control bits).
attempt should made write immediate value into whole since such operation cannot preserve reserved bits.
INSTRUCTION CYCLE TIMES transfers take incremental cycles, where defined Sequential (S-cycle).
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
ASSEMBLY SYNTAX
transfer contents register MRS{cond} Rd,<psr> transfer register contents MSR{cond} <psr>,Rm transfer register contents flag bits only MSR{cond} <psrf>,Rm
most significant four bits register contents written N,Z,C flags respectively.
transfer immediate value flag bits only MSR{cond} <psrf>,<#expression>
expression should symbolise value which most significant four bits written N,Z,C flags respectively. Key: {cond} <psr> <psrf> <#expression> Two-character condition mnemonic. Table 3-2. Expressions evaluating register number other than CPSR, CPSR_all, SPSR SPSR_all. (CPSR CPSR_all synonyms SPSR SPSR_all) CPSR_flg SPSR_flg Where this used, assembler will attempt generate shifted immediate 8-bit field match expression. this impossible, will give error.
EXAMPLES User mode instructions behave follows: CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0xA0000000 Rd,CPSR CPSR[31:28] Rm[31:28] CPSR[31:28] Rm[31:28] CPSR[31:28] (set N,C; clear Z,V) Rd[31:0] CPSR[31:0]
privileged modes instructions behave follows: CPSR_all,Rm CPSR_flg,Rm CPSR_flg,#0x50000000 SPSR_all,Rm SPSR_flg,Rm SPSR_flg,#0xC0000000 Rd,SPSR CPSR[31:0] Rm[31:0] CPSR[31:28] Rm[31:28] CPSR[31:28] (set Z,V; clear N,C) SPSR_<mode>[31:0]<- Rm[31:0] SPSR_<mode>[31:28] Rm[31:28] SPSR_<mode>[31:28] (set N,Z; clear C,V) Rd[31:0] SPSR_<mode>[31:0]
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
MULTIPLY MULTIPLY-ACCUMULATE (MUL, MLA)
instruction only executed condition true. various conditions defined Table 3-2. instruction encoding shown Figure 3-12. multiply multiply-accumulate instructions Booth's algorithm perform integer multiplication.
Cond
[15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Condition Code
after condition codes condition codes
[21] Accumulate
Multiply only Multiply accumulate
[31:28] Condition Field
Figure 3-12. Multiply Instructions multiply form instruction gives Rd:=Rm*Rs. ignored, should zero compatibility with possible future upgrades instruction set. multiply-accumulate form gives Rd:=Rm*Rs+Rn, which save explicit instruction some circumstances. Both forms instruction work operands which considered signed (2's complement) unsigned integers. results signed multiply unsigned multiply operands differ only upper bits bits signed unsigned results identical. these instructions only produce bits multiply, they used both signed unsigned multiplies. example consider multiplication operands: Operand Operand Result 0xFFFFFFF6 0x0000001 0xFFFFFF38
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
Operands Interpreted Signed Operand value -10, operand value result -200 which correctly represented 0xFFFFFF38. Operands Interpreted Unsigned Operand value 4294967286, operand value result 85899345720, which represented 0x13FFFFFF38, least significant bits 0xFFFFFF38. Operand Restrictions destination register must same operand register must used operand destination register. other register combinations will give correct results, same register when required.
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
CPSR FLAGS Setting CPSR flags optional, controlled instruction. (Negative) (Zero) flags correctly result made equal result, only result zero). (Carry) flag meaningless value (oVerflow) flag unaffected.
INSTRUCTION CYCLE TIMES takes (m+1)I cycles execute, where defined sequential (S-cycle) internal (I-cycle), respectively. number multiplier array cycles required complete multiply, which controlled value multiplier operand specified possible values follows bits [32:8] multiplier operand zero one. bits [32:16] multiplier operand zero one. bits [32:24] multiplier operand zero one. other cases.
ASSEMBLER SYNTAX MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn {cond} Two-character condition mnemonic. Table 3-2. condition codes present Expressions evaluating register number other than R15.
EXAMPLES MLAEQS R1,R2,R3 R1,R2,R3,R4 R1:=R2*R3 Conditionally R1:=R2*R3+R4, Setting condition codes.
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
MULTIPLY LONG MULTIPLY-ACCUMULATE LONG (MULL, MLAL)
instruction only executed condition true. various conditions defined Table 3-2. instruction encoding shown Figure 3-13. multiply long instructions perform integer multiplication operands produce results. Signed unsigned multiplication each with optional accumulate give rise four variations.
Cond
RdHi
RdLo
[11:8][3:0] Operand Registers [19:16][15:12] Source Destination Registers [20] Condition Code
alter condition codes condition codes
[21] Accumulate
Multiply only Multiply accumulate
[22] Unsigned
Unsigned Signed
[31:28] Condition Field
Figure 3-13. Multiply Long Instructions multiply forms (UMULL SMULL) take numbers multiply them produce result form RdHi,RdLo lower bits result written RdLo, upper bits result written RdHi. multiply-accumulate forms (UMLAL SMLAL) take numbers, multiply them number produce result form RdHi,RdLo RdHi,RdLo. lower bits number read from RdLo. upper bits number read from RdHi. lower bits result written RdLo. upper bits result written RdHi. UMULL UMLAL instructions treat their operands unsigned binary numbers write unsigned result. SMULL SMLAL instructions treat their operands two's-complement signed numbers write two's-complement signed result.
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
OPERAND RESTRICTIONS must used operand destination register. RdHi, RdLo, must specify different registers.
CPSR FLAGS Setting CPSR flags optional, controlled instruction. flags correctly result equal result, only bits result zero). Both flags meaningless values.
INSTRUCTION CYCLE TIMES MULL takes (m+1)I MLAL (m+2)I cycles execute, where number multiplier array cycles required complete multiply, which controlled value multiplier operand specified possible values follows: Signed INSTRUCTIONS SMULL, SMLAL:
bits [31:8] multiplier operand zero one. bits [31:16] multiplier operand zero one. bits [31:24] multiplier operand zero one. other cases.
Unsigned Instructions UMULL, UMLAL:
bits [31:8] multiplier operand zero. bits [31:16] multiplier operand zero. bits [31:24] multiplier operand zero. other cases.
defined sequential (S-cycle) internal (I-cycle), respectively.
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic UMULL{cond}{S} RdLo,RdHi,Rm,Rs UMLAL{cond}{S} RdLo,RdHi,Rm,Rs SMULL{cond}{S} RdLo,RdHi,Rm,Rs SMLAL{cond}{S} RdLo,RdHi,Rm,Rs where: {cond} RdLo, RdHi, EXAMPLES UMULL UMLALS R1,R4,R2,R3 R1,R5,R2,R3 R4,R1:=R2*R3 R5,R1:=R2*R3+R5,R1 also setting condition codes Two-character condition mnemonic. Table 3-2. condition codes present Expressions evaluating register number other than R15. Description Unsigned Multiply Long Unsigned Multiply Accumulate Long Signed Multiply Long Signed Multiply Accumulate Long Purpose
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
SINGLE DATA TRANSFER (LDR, STR)
instruction only executed condition true. various conditions defined Table 3-2. instruction encoding shown Figure 3-14. single data transfer instructions used load store single bytes words data. memory address used transfer calculated adding offset subtracting offset from base register. result this calculation written back into base register auto-indexing required.
Cond Offset
[15:12] Source/Destination Registers [19:16] Base Register [20] Load/Store
Store memory Load from memory
[21] Write-back
write-back Write address into base
[22] Byte/Word
Transfer word quantity Transfer byte quantity
[23] Up/Down
Down: subtract offset from base offset base
[24] Pre/Post Indexing
Post: offset after transfer Pre: offset before transfer
[25] Immediate Offset
Offset immediate value
[11:0] Offset
Immediate [11:0] Unsigned 12-bit immediate offset Shift
[3:0] Offset register [11:4] Shift applied
[31:28] Condition Field Figure 3-14. Single Data Transfer Instructions
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
OFFSETS AUTO-INDEXING offset from base either unsigned binary immediate value instruction, second register (possibly shifted some way). offset added (U=1) subtracted from (U=0) base register offset modification performed either before (pre-indexed, P=1) after (post-indexed, P=0) base used transfer address. gives optional auto increment decrement addressing modes. modified base value written back into base (W=1), base value kept (W=0). case post-indexed addressing, write back redundant always zero, since base value retained setting offset zero. Therefore post-indexed data transfers always write back modified base. only postindexed data transfer privileged mode code, where setting forces non-privileged mode transfer, allowing operating system generate user address system where memory management hardware makes suitable this hardware. SHIFTED REGISTER OFFSET shift control bits described data processing instructions section. However, register specified shift amounts available this instruction class. Figure 3-5. BYTES WORDS This instruction class used transfer byte (B=1) word (B=0) between ARM920T register memory. action LDR(B) STR(B) instructions influenced BIGEND control signal ARM920T core. possible configurations described below. Little-Endian Configuration byte load (LDRB) expects data data inputs through supplied address word boundary, data inputs through word address plus byte, selected byte placed bottom bits destination register, remaining bits register filled with zeros. Please Figure 2-2. byte store (STRB) repeats bottom bits source register four times across data outputs through external memory system should activate appropriate byte subsystem store data. word load (LDR) will normally word aligned address. However, address offset from word boundary will cause data rotated into register that addressed byte occupies bits This means that halfwords accessed offsets from word boundary will correctly loaded into bits through register. shift operations then required clear sign extend upper bits. word store (STR) should generate word aligned address. word presented data affected address word aligned. That register being stored always appears data output
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
memory
register
from word aligned address memory from address offset register
Figure 3-15. Little-Endian Offset Addressing Big-Endian Configuration byte load (LDRB) expects data data inputs through supplied address word boundary, data inputs through word address plus byte, selected byte placed bottom bits destination register remaining bits register filled with zeros. Please Figure 2-1. byte store (STRB) repeats bottom bits source register four times across data outputs through external memory system should activate appropriate byte subsystem store data. word load (LDR) should generate word aligned address. address offset from word boundary will cause data rotated into register that addressed byte occupies bits through This means that half-words accessed these offsets will correctly loaded into bits through register. shift operation then required move (and optionally sign extend) data into bottom bits. address offset from word boundary will cause data rotated into register that addressed byte occupies bits through word store (STR) should generate word aligned address. word presented data affected address word aligned. That register being stored always appears data output
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
Write-back must specified specified base register (Rn). When using base register must remember contains address bytes from address current instruction. must specified register offset (Rm). When source register (Rd) register store (STR) instruction, stored value will address instruction plus Restriction base register When configured late aborts, following example code difficult unwind base register, gets updated before abort handler starts. Sometimes impossible calculate initial value. After abort, following example code difficult unwind base register, gets updated before abort handler starts. Sometimes impossible calculate initial value.
EXAMPLE: R0,[R1],R
Therefore post-indexed where same register should used.
DATA ABORTS transfer from legal address cause problems memory management system. instance, system which uses virtual memory required data absent from main memory. memory manager signal problem taking processor ABORT input HIGH whereupon Data Abort trap will taken. system software resolve cause problem, then instruction restarted original program continued.
INSTRUCTION CYCLE TIMES Normal instructions take take incremental cycles, where defined sequential (S-cycle), non-sequential (N-cycle), internal (I-cycle), respectively. instructions take incremental cycles execute.
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
ASSEMBLER SYNTAX <LDR|STR>{cond}{B}{T} Rd,<Address> where: {cond} Load from memory into register Store from register into memory Two-character condition mnemonic. Table 3-2. present then byte transfer, otherwise word transfer present will post-indexed instruction, forcing non-privileged mode transfer cycle. allowed when pre-indexed addressing mode specified implied. expression evaluating valid register number. Expressions evaluating register number. then assembler will subtract from offset value allow ARM920T pipelining. this case base write-back should specified.
<Address>can expression which generates address: assembler will attempt generate instruction using base corrected immediate offset address location given evaluating expression. This will relative, pre-indexed address. address range, error will generated. pre-indexed addressing specification: [Rn] offset zero [Rn,<#expression>]{!} [Rn,{+/-}Rm{,<shift>}]{!}
offset <expression> bytes offset contents index register, shifted <shift>
post-indexed addressing specification: [Rn],<#expression> offset <expression> bytes [Rn],{+/-}Rm{,<shift>} offset contents index register, shifted <shift>. General shift operation (see data processing instructions) cannot specify shift amount register. Writes back base register (set bit) present.
<shift>
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
EXAMPLES LDREQB PLACE R1,[R2,R4]! R1,[R2],R4 R1,[R2,#16] R1,[R2,R3,LSL#2] R1,[R6,#5] R1,PLACE Store R2+R4 (both which registers) write back address Store write back R2+R4 Load from contents R2+16, don't write back. Load from contents R2+R3*4. Conditionally load byte R6+5 into bits filling bits with zeros. Generate relative offset address PLACE.
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
HALFWORD SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH)
instruction only executed condition true. various conditions defined Table 3-2. instruction encoding shown Figure 3-16. These instructions used load store half-words data also load sign-extended bytes half-words data. memory address used transfer calculated adding offset subtracting offset from base register. result this calculation written back into base register auto-indexing required.
Cond
0000
[3:0] Offset Register [6][5]
instruction Unsigned halfword Signed byte Signed halfword
[15:12] Source/Destination Register [19:16] Base Register [20] Load/Store
Store memory Load from memory
[21] Write-back
write-back Write address into base
[23] Up/Down
Down: subtract offset from base offset base
[24] Pre/Post Indexing
Post: add/subtract offset after transfer Pre: add/subtract offset bofore transfer
[31:28] Condition Field
Figure 3-16. Halfword Signed Data Transfer with Register Offset
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
Cond
Offset
Offset
[3:0] Immediate Offset (Low Nibble) [6][5]
instruction Unsigned halfword Signed byte Signed halfword
[11:8] Immediate Offset (High Nibble) [15:12] Source/Destination Register [19:16] Base Register [20] Load/Store
Store memory Load from memory
[21] Write-back
write-back Write address into base
[23] Up/Down
Down: subtract offset from base offset base
[24] Pre/Post Indexing
Post: add/subtract offset after transfer Pre: add/subtract offset bofore transfer
[31:28] Condition Field Figure 3-17. Halfword Signed Data Transfer with Immediate Offset Auto-Indexing OFFSETS AUTO-INDEXING offset from base either 8-bit unsigned binary immediate value instruction, second register. 8-bit offset formed concatenating bits bits instruction word, such that becomes becomes LSB. offset added (U=1) subtracted from (U=0) base register offset modification performed either before (pre-indexed, P=1) after (post-indexed, P=0) base register used transfer address. gives optional auto-increment decrement addressing modes. modified base value written back into base (W=1), base kept (W=0). case post-indexed addressing, write back redundant always zero, since base value retained necessary setting offset zero. Therefore post-indexed data transfers always write back modified base. Write-back should high (W=1) when post-indexed addressing selected.
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
HALFWORD LOAD STORES Setting used transfer unsigned Half-words between ARM920T register memory. action LDRH STRH instructions influenced BIGEND control signal. possible configurations described section below. Signed byte halfword loads controls loading sign-extended data. When selects between Bytes (H=0) Halfwords (H=1). should (Store) when Signed (S=1) operations have been selected. LDRSB instruction loads selected Byte into bits destination register bits destination register value sign bit. LDRSH instruction loads selected Half-word into bits destination register bits destination register value sign bit. action LDRSB LDRSH instructions influenced BIGEND control signal. possible configurations described following section. Endianness byte/halfword selection Little-Endian Configuration signed byte load (LDRSB) expects data data inputs through supplied address word boundary, data inputs through word address plus byte, selected byte placed bottom destination register, remaining bits register filled with sign bit, byte. Please Figure 2-2. halfword load (LDRSH LDRH) expects data data inputs through supplied address word boundary data inputs through halfword boundary, (A[1]=1).The supplied address should always halfword boundary. supplied address HIGH then ARM920T will load unpredictable value. selected halfword placed bottom bits destination register. unsigned half-words (LDRH), bits register filled with zeros signed half-words (LDRSH) bits filled with sign bit, halfword. halfword store (STRH) repeats bottom bits source register twice across data outputs through external memory system should activate appropriate halfword subsystem store data. Note that address must halfword aligned, address HIGH this will cause unpredictable behaviour.
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
Big-Endian Configuration signed byte load (LDRSB) expects data data inputs through supplied address word boundary, data inputs through word address plus byte, selected byte placed bottom destination register, remaining bits register filled with sign bit, byte. Please Figure 2-1. halfword load (LDRSH LDRH) expects data data inputs through supplied address word boundary data inputs through halfword boundary, (A[1]=1). supplied address should always halfword boundary. supplied address HIGH then ARM920T will load unpredictable value. selected halfword placed bottom bits destination register. unsigned half-words (LDRH), bits register filled with zeros signed half-words (LDRSH) bits filled with sign bit, halfword. halfword store (STRH) repeats bottom bits source register twice across data outputs through external memory system should activate appropriate halfword subsystem store data. Note that address must halfword aligned, address HIGH this will cause unpredictable behaviour.
Write-back should specified specified base register (Rn). When using base register must remember contains address bytes from address current instruction. should specified register offset (Rm). When source register (Rd) Half-word store (STRH) instruction, stored address will address instruction plus
DATA ABORTS transfer from legal address cause problems memory management system. instance, system which uses virtual memory required data absent from main memory. memory manager signal problem taking processor ABORT input HIGH whereupon Data Abort trap will taken. system software resolve cause problem, then instruction restarted original program continued.
INSTRUCTION CYCLE TIMES Normal LDR(H,SH,SB) instructions take LDR(H,SH,SB) take incremental cycles. defined sequential (S-cycle), non-sequential (N-cycle), internal (I-cycle), respectively. STRH instructions take incremental cycles execute.
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
ASSEMBLER SYNTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> {cond} <address> expression which generates address: assembler will attempt generate instruction using base corrected immediate offset address location given evaluating expression. This will relative, pre-indexed address. address range, error will generated. pre-indexed addressing specification: [Rn] [Rn,<#expression>]{!} [Rn,{+/-}Rm]{!} Load from memory into register Store from register into memory Two-character condition mnemonic. Table 3-2. Transfer halfword quantity Load sign extended byte (Only valid LDR) Load sign extended halfword (Only valid LDR) expression evaluating valid register number.
offset zero offset <expression> bytes offset contents index register
post-indexed addressing specification: [Rn],<#expression> offset <expression> bytes [Rn],{+/-}Rm offset contents index register. expressions evaluating register number. then assembler will subtract from offset value allow ARM920T pipelining. this case base write-back should specified. Writes back base register (set bit) present.
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
EXAMPLES LDRH R1,[R2,-R3]! Load from contents halfword address contained R2-R3 (both which registers) write back address Store halfword R14+14 don't write back. Load with sign extended contents byte address contained write back R2-223 Conditionally load with sign extended contents halfword address contained Generate relative offset address FRED. Store halfword address FRED
STRH LDRSB LDRNESH HERE STRH FRED
R3,[R4,#14] R8,[R2],#-223 R11,[R0]
[PC,#(FRED-HERE-8)];
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
BLOCK DATA TRANSFER (LDM, STM)
instruction only executed condition true. various conditions defined Table 3-2. instruction encoding shown Figure 3-18. Block data transfer instructions used load (LDM) store (STM) subset currently visible registers. They support possible stacking modes, maintaining full empty stacks which grow down memory, very efficient instructions saving restoring context, moving large blocks data around main memory.
REGISTER LIST instruction cause transfer registers current bank (and non-user mode programs also transfer from user bank, below). register list field instruction, with each corresponding register. register field will cause transferred, will cause transferred; similarly controls transfer subset registers, registers, specified. only restriction that register list should empty. Whenever stored memory stored value address Sinstruction plus
Cond
Register list
[19:16] Base Register [20] Load/Store
Store memory Load from memory
[21] Write-back
write-back Write address into base
[22] Force User
load user mode Load force user mode
[23] Up/Down
Down: subtract offset from base offset base
[24] Pre/Post Indexing
Post: offset after transfer Pre: offset bofore transfer
[31:28] Condition Field Figure 3-18. Block Data Transfer Instructions
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
ADDRESSING MODES transfer addresses determined contents base register (Rn), pre/post down (U). registers transferred order lowest highest, list) will always transferred last. lowest register also gets transferred to/from lowest memory address. illustration, consider transfer case where Rn=0x1000 write back modified base required (W=1). Figure 3.19-22 show sequence register transfers, addresses used, value after instruction completed. cases, write back modified base been required (W=0), would have retained initial value 0x1000 unless also transfer list load multiple register instruction, when would have been overwritten with loaded value.
ADDRESS ALIGNMENT address should normally word aligned quantity non-word aligned addresses affect instruction. However, bottom bits address will appear A[1:0] might interpreted memory system.
0x100C
0x100C
0x1000
0x1000
0x0FF4 0x100C
0x0FF4
0x100C
0x1000
0x1000
0x0FF4
0x0FF4
Figure 3-19. Post-Increment Addressing
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
0x100C 0x1000
0x100C
0x1000
0x0FF4 0x100C 0x1000
0x0FF4
0x100C
0x1000
0x0FF4
0x0FF4
Figure 3-20. Pre-Increment Addressing
0x100C
0x100C
0x1000 0x0FF4 0x100C
0x1000
0x0FF4
0x100C
0x1000 0x0FF4
0x1000
0x0FF4
Figure 3-21. Post-Decrement Addressing
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INSTRUCTION
0x100C
0x100C
0x1000
0x1000
0x0FF4 0x100C
0x0FF4
0x100C
0x1000
0x1000
0x0FF4
0x0FF4
Figure 3-22. Pre-Decrement Addressing When LDM/Sinstruction meaning depends whether transfer list type instruction. should only instruction execute privileged mode. with Transfer List (Mode Changes) instruction then SPSR_<mode> transferred CPSR same time loaded. Swith Transfer List (User Bank Transfer) registers transferred taken from User bank rather than bank corresponding current mode. This useful saving user state process switches. Base write-back should used when this mechanism employed. List (User Bank Transfer) both Sinstructions, User bank registers transferred rather than register bank corresponding current mode. This useful saving user state process switches. Base write-back should used when this mechanism employed. When instruction LDM, care must taken read from banked register during following cycle (inserting dummy instruction such after will ensure safety). BASE should used base register Sinstruction.
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INSTRUCTION
S3C2400 RISC MICROPROCESSOR
INCLUSION BASE REGISTER LIST When write-back specified, base written back second cycle instruction. During STM, first register written start second cycle. Swhich includes storing base, with base first register stored, will therefore store unchanged value, whereas with base second later transfer order, will store modified value. will always overwrite updated base base list. DATA ABORTS Some legal addresses unacceptable memory management system, memory manager indicate problem with address taking ABORT signal HIGH. This happen transfer during multiple register load store, must recoverable ARM920T used virtual memory system. Abort during SInstructions abort occurs during store multiple instruction, ARM920T takes little action until instruction completes, whereupon enters data abort trap. memory manager responsible preventing erroneous writes memory. only change internal state processor will modification base register writeback specified, this must reversed software (and cause abort resolved) before instruction retried. Aborts during Instructions When ARM920T detects data abort during load multiple instruction, modifies operation instruction ensure that recovery possible. Overwriting registers stops when abort happens. aborting load will take place earlier ones have overwritten registers. always last register written will always preserved. base register restored, modified value write-back requested. This ensures recoverability case where base register also transfer list, have been overwritten before abort occurred.
data abort trap taken when load multiple completed, system software must undo base modification (and resolve cause abort) before restarting instruction.
INSTRUCTION CYCLE TIMES Normal instructions take takes (n+1)S incremental cycles, where defined sequential (S-cycle), non-sequential (N-cycle), internal (I-cycle), respectively. Sinstructions take (n-1)S incremental cycles execute, where number words transferred.
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S3C2400 RISC MICROPROCESSOR
INSTRUCTION
ASSEMBLER SYNTAX Rn{!},<Rlist>{^} where: {cond} <Rlist> character condition mnemonic. Table 3-2. expression evaluating valid register number list registers register ranges enclosed (e.g. {R0,R2-R7,R10}). present requests write-back (W=1), otherwise W=0. present load CPSR along with force transfer user bank when privileged mode.
Addressing Mode Names There different assembler mnemonics each addressing modes, depending whether instruction being used support stacks other purposes. equivalence between names values bits instruction shown following table 3-6. Table 3-6. Addressing Mode Names Name Pre-Increment Load Post-Increment Load Pre-Decrement Load Post-Decrement Load Pre-Increment Store Post-Increment Store Pre-Decrement Store Post-Decrement Store Stack LDMED LDMFD LDMEA LDMFA STMFA STMEA STMFD STMED Other LDMIB LDMIA LDMDB LDMDA STMIB STMIA STMDB STMDA
define pre/post indexing up/down reference form stack required. refer "full" "empty" stack, i.e. whether pre-index done (full) before storing stack. refer whether stack ascending descending. ascending, Swill down, descending, vice-versa. allow control when LDM/Sare being used stacks simply mean Increment After, Increment Before, Decrement After, Decrement Before.
3-45
INSTRUCTION
S3C2400 RISC MICROPROCESSOR
EXAMPLES LDMFD STMIA LDMFD LDMFD STMFD SP!,{R0,R1,R2} R0,{R0-R15} SP!,{R15} SP!,{R15}^ R13,{R0-R14}^ Unstack registers. Save registers. (SP), CPSR unchanged. (SP), CPSR SPSR_mode (allowed only privileged modes). Save user mode regs stack (allowed only privileged modes).
These instructions used save state subroutine entry, restore efficiently return calling routine: STMED LDMED SP!,{R0-R3,R14} somewhere SP!,{R0-R3,R15} Save workspace returning. This nested call will overwrite Restore workspace return.
3-46
S3C2400 RISC MICROPROCESSOR
INSTRUCTION
SINGLE DATA SWAP (SWP)
Cond
00010
0000
[3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word
Swap word quantity Swap word quantity
[31:28] Condition Field
Figure 3-23. Swap Instruction instruction only executed condition true. various conditions defined Table 3-2. instruction encoding shown Figure 3-23. data swap instruction used swap byte word quantity between register external memory. This instruction implemented memory read followed memory write which "locked" together (the processor cannot interrupted until both operations have completed, memory manager warned treat them inseparable). This class instruction particularly us
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