The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

SDRAM Buffer Desktop with DIMMS Generates output buffer from inpu


Datasheet Thumbnail

  

Download PDF



Top Searches for this datasheet



PLL103-02
SDRAM Buffer Desktop with DIMMS
Generates output buffer from input. Supports four DIMMS SDRAM DIMMS. Supports 266MHz SDRAM. additional output feedback. Less than delay. Skew between outputs less than 2.5V 3.3V Supply range. Enhanced SDRAM Output Drive selected I2C. Available SSOP.
CONFIGURATION
FBOUT VDD3.3_2.5 DDR0T DDR0C DDR1T_SDRAM0 DDR1C_SDRAM1 VDD3.3_2.5 DDR2T_SDRAM2 DDR2C_SDRAM3 VDD3.3_2.5 BUF_IN DDR3T_SDRAM4 DDR3C_SDRAM5 VDD3.3_2.5 DDR4T_SDRAM6 DDR4C_SDRAM7 DDR5T
DDR0T
SEL_DDR VDD2.5 DDR11T DDR11C DDR10T DDR10C VDD2.5 DDR9T DDR9C VDD2.5 DDR8T DDR8C VDD2.5 DDR7T DDR7C DDR6T DDR6C SCLK
PLL103-02
BLOCK DIAGRAM
DDR5C VDD3.3_2.5 SDATA
SDATA SCLK
Control
DDR0C DDR1T_SDRAM0 DDR1C_SDRAM1 DDR2T_SDRAM2 DDR2C_SDRAM3 DDR3T_SDRAM4 DDR3C_SDRAM5 DDR4T_SDRAM6
Note: Active
DESCRIPTIONS
PLL103-02 designed 3.3V/2.5V buffer distribute high-speed clocks applications. device outputs. These outputs configured support four unbuffered DIMMS support unbuffered standard SDRAM DIMMS DIMMS. PLL103-02 used conjunction with PLL202-04 similar clock synthesizer chipset. PLL103-02 also interface, which enable disable each output clock. When power output clocks enabled (has internal pull up).
BUF_IN
DDR4C_SDRAM7 DDR5T DDR5C DDR6T DDR6C DDR7T DDR7C DDR8T DDR8C DDR9T DDR9C DDR10T DDR10C DDR11T DDR11C
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/07/00 Page
PLL103-02
SDRAM Buffer Desktop with DIMMS
DESCRIPTIONS
Name
FBOUT BUF_IN
Number
Type
Description
Feedback clock chipset. Output voltage depends VDD3.3_2.5V. Reference input from chipset. 3.3V input STANDARD SDRAM mode; 2.5V input DDR-ONLY mode. Power Down Control input. When low, will tri-state outputs.
SEL_DDR
Input configure DDR-ONLY mode STANDARD SDRAM mode. DDR-ONLY mode (when VDD3.3_2.5 select 2.5V); STANDARD SDRAM mode (when VDD3.3_2.5 select 3.3V). DDR-ONLY mode, will configured outputs. STANDARD SDRAM mode, will configured STANDARD SDRAM outputs. will configured outputs. will Tri-stated.
These outputs provide True copies BUF_IN. These outputs provide complementary copies BUF_IN. When SEL_DDR=1, these outputs provide mode outputs; when SEL_DDR=0, these outputs provide standard SDRAM mode outputs. Voltage swing depends VDD3.3_2.5. When SEL_DDR=1, these outputs provide complementary copies BUF_IN; when SEL_DDR=0, these outputs provide standard SDRAM mode outputs. Voltage swing depends VDD3.3_2.5. When VDD=2.5V, SEL_DDR=1. DDR-ONLY mode selected; when VDD=3.3V, SEL_DDR=0. STANDARD SDRAM mode selected. 2.5V power supply. Ground.
DDR[0,5:11]T DDR[0,5:11]C DDR[1:4]T_SDRA [0,2,4,6] DDR[1:4]C_SDRA [1,3,5,7] VDD3.3_2.5 VDD2.5
4,21,28,30,34, 39,43,45 5,22,27,29,33, 38,42,44 6,10,15,19
7,11,16,20 2,8,12,17,23 32,37,41,47 3,9,14,18,26, 31,35,40,46
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/07/00 Page
PLL103-02
SDRAM Buffer Desktop with DIMMS
Address Assignment Receiver/Transmitter Data Transfer Rate
Provides both slave write Standard mode 100kbits/s This serial protocol designed allow both blocks write read from controller. bytes must accessed sequential order from lowest highest byte. Each byte transferred terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3). Following acknowledge this address byte, Write Mode: Command Byte Byte Count Byte must sent master ignored slave, Read Mode: Byte Count Byte will read master then other Data Byte. Byte Count Byte default power-up (0x09).
CONTROL REGISTERS
BYTE Outputs Register (1=Enable, 0=Disable)
Pin#
Default
Description
SEL_DDR ready only, value through pin48 Enhanced SDRAM Drive. Enhanced Enhanced Drive. Enhanced Reserved DDR11T, DDR11C DDR10T, DDR10C DDR9T, DDR9C DDR8T, DDR8C
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/07/00 Page
PLL103-02
SDRAM Buffer Desktop with DIMMS
BYTE Outputs Register (1=Enable, 0=Disable)
Pin#
Default
Description
DDR7T, DDR7C DDR6T, DDR6C DDR5T, DDR5C DDR4T_SDRAM6, DDR4C_SDRAM7 DDR3T_SDRAM4, DDR3C_SDRAM5 DDR2T_SDRAM2, DDR2C_SDRAM3 DDR1T_SDRAM0, DDR1C_SDRAM1 DDR0T, DDR0C
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/07/00 Page
PLL103-02
SDRAM Buffer Desktop with DIMMS
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
Operating Conditions PARAMETERS
Supply Voltage Supply Voltage Input Capacitance Output Capacitance
SYMBOL
DD3.3 DD2.5
MIN.
3.135 2.375
MAX.
3.465 2.625
UNITS
Electrical Specifications PARAMETERS
Input High Voltage Input Voltage Input High Current Input Current Output High Voltage Output Voltage Output High Current Output Current
Note: TBM: measured
SYMBOL
CONDITIONS
Inputs except inputs except -12mA, 12mA, 2.375V 2.375V
MIN.
-0.3
TYP.
MAX.
+0.3
UNITS
2.375V, VOUT=1V 2.375V, VOUT=1.2V
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/07/00 Page
PLL103-02
SDRAM Buffer Desktop with DIMMS
Electrical Specifications (Continued) PARAMETERS
Supply Current (DDR-only mode) Supply Current (SDRAM mode) Supply Current Output Crossing Voltage Output Voltage Swing Duty Cycle Max. Operating Frequency Rising Edge Rate Falling Edge Rate Clock Skew Stabilization Time
Note: TBM: measured
SYMBOL
CONDITIONS
Unloaded outputs, 133MHz Unloaded outputs, 133MHz
MIN.
TYP.
MAX.
UNITS
V/ns V/ns
(VDD/2) -0.1 Measured 1.5V
VDD/2
(VDD/2)+ VDD-0.4
SKEW
Measured Measured
0.4V 2.4V 2.4V 0.4V
outputs equally loaded
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/07/00 Page
PLL103-02
SDRAM Buffer Desktop with DIMMS
PACKAGE INFORMATION
0.400 0.410 10.160 10.414
0.292 0.299 7.417 7.959
0.008 0.0135 0.203 0.343
0.025 0.835
0.015 (0.381) 0.010 0.016 (0.25 0.41) 0.620 0.630 (15.75 16.00)
0.088 0.096 (2.250 2.450)
0.097 0.104 (2.467 2.642) 30-6 0.050 (1.346) 0.008 0.016 (0.20 0.41)
48PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL103-02
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished PhaseLink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/07/00 Page

Other recent searches


TK717xx - TK717xx   TK717xx Datasheet
S6U1 - S6U1   S6U1 Datasheet
N02L163WN1A - N02L163WN1A   N02L163WN1A Datasheet
MDF5N50 - MDF5N50   MDF5N50 Datasheet
KRX104U - KRX104U   KRX104U Datasheet
IRF520PbF - IRF520PbF   IRF520PbF Datasheet
HIP6602A - HIP6602A   HIP6602A Datasheet
EM6517 - EM6517   EM6517 Datasheet
BU2508AW - BU2508AW   BU2508AW Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive