28/40/44-Pin Enhanced Flash Microcontrollers with ECANTechnology, 10-B
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PIC18F2480/2580/4480/4580 Data Sheet
28/40/44-Pin Enhanced Flash Microcontrollers with ECANTechnology, 10-Bit nanoWatt Technology
2004 Microchip Technology Inc.
DS39637A
Note following details code protection feature Microchip devices: Microchip products meet specification contained their particular Microchip Data Sheet. Microchip believes that family products most secure families kind market today, when used intended manner under normal conditions. There dishonest possibly illegal methods used breach code protection feature. these methods, knowledge, require using Microchip products manner outside operating specifications contained Microchip's Data Sheets. Most likely, person doing engaged theft intellectual property. Microchip willing work with customer concerned about integrity their code. Neither Microchip other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable."
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel Total Endurance trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2004, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona Mountain View, California October 2003. Company's quality system processes procedures PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
28/40/44-Pin Enhanced Flash Microcontrollers with ECANTechnology, 10-Bit nanoWatt Technology
Power Managed Modes:
Run: peripherals Idle: off, peripherals Sleep: off, peripherals Idle mode currents down typical Sleep mode current down typical Timer1 Oscillator: kHz, Watchdog Timer: Two-Speed Oscillator Start-up
Peripheral Highlights:
High current sink/source mA/25 Three external interrupts Capture/Compare/PWM (CCP) module Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only): One, four outputs Selectable polarity Programmable dead time Auto-Shutdown Auto-Restart Master Synchronous Serial Port (MSSP) module supporting 3-wire SPI(all modes) I2CMaster Slave modes Enhanced Addressable USART module Supports RS-485, RS-232 RS-232 operation using internal oscillator block external crystal required) Auto-Wake-up Start Auto-Baud detect 10-bit, 11-channel Analog-to-Digital Converter module (A/D), Ksps Auto-acquisition capability Conversion available during Sleep Dual analog comparators with input multiplexing
Flexible Oscillator Structure:
Four Crystal modes, Phase Lock Loop (PLL) available crystal internal oscillators) External modes, External Clock modes, Internal oscillator block: user selectable frequencies, from Provides complete range clock speeds, from when used with User tunable compensate frequency drift Secondary oscillator using Timer1 Fail-Safe Clock Monitor Allows safe shutdown peripheral clock stops
Special Microcontroller Features:
compiler optimized architecture with optional extended instruction 100,000 erase/write cycle Enhanced Flash program memory typical 1,000,000 erase/write cycle Data EEPROM memory typical Flash/Data EEPROM Retention: years Self-programmable under software control Priority levels interrupts Single Cycle Hardware Multiplier Extended Watchdog Timer (WDT): Programmable period from 131s Single-Supply In-Circuit Serial Programming(ICSPTM) pins In-Circuit Debug (ICD) pins Wide operating voltage range: 2.0V 5.5V
Program Memory Device PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580 Data Memory
ECAN Module Features:
Message rates Mbps Conforms 2.0B ACTIVE Specification Fully backward compatible with PIC18XXX8 modules Three modes operation: Legacy, Enhanced Legacy, FIFO Three dedicated transmit buffers with prioritization dedicated receive buffers programmable receive/transmit buffers Three full 29-bit acceptance masks full 29-bit acceptance filters dynamic association DeviceNetdata byte filter support Automatic remote frame handling Advanced error management features
Flash Single-Word SRAM EEPROM (bytes) Instructions (bytes) (bytes) 8192 16384 8192 16384 1536 1536
10-bit (ch)
CCP/ ECCP (PWM)
MSSP SPIY Master I2CY
EUSART
Comp.
Timers 8/16-bit
2004 Microchip Technology Inc.
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PIC18F2480/2580/4480/4580
Diagrams
28-Pin SPDIP, SOIC
MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC1/CLKI/RA7 OSC2/CLKO/RA6 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 RC7/RX/DT
40-Pin PDIP
MCLR/VPP/RE3 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN RE0/RD/AN5 RE1/WR/AN6/C1OUT RE2/CS/AN7/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RD0/PSP0/C1IN+ RD1/PSP1/C1IN-
RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK
RA1/AN1 RA0/AN0 MCLR/VPP/RE3 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9
28-Pin
PIC18F2480 PIC18F2580
PIC18F2480 PIC18F2580
RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/FLT0/AN10 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4/ECCP1/P1A RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+
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PIC18F4480 PIC18F4580
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PIC18F2480/2580/4480/4580
Diagrams (Continued)
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ RD1/PSP1/C1INRD0/PSP0/C1IN+ RC3/SCK/SCL RC2/CCP1 RC1/T1OSI
44-Pin TQFP
44-Pin
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2INRD2/PSP2/C2IN+ RD1/PSP1/C1INRD0/PSP0/C1IN+ RC3/SCK/SCL RC2/CCP1 RC1/T1OSI RC0/T1OSO/T13CKI
2004 Microchip Technology Inc.
RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+
RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D AVDD RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX
RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+
RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX
PIC18F4480 PIC18F4580
RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI
PIC18F4480 PIC18F4580
OSC2/CLKO/RA6 OSC1/CLKI/RA7 AVSS AVDD RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI
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Table Contents
Device Overview Oscillator Configurations Power Managed Modes Reset Memory Organization Flash Program Memory Data EEPROM Memory Hardware Multiplier. Interrupts 10.0 Ports 11.0 Timer0 Module 12.0 Timer1 Module 13.0 Timer2 Module 14.0 Timer3 Module 15.0 Capture/Compare/PWM (CCP) Modules 16.0 Enhanced Capture/Compare/PWM (ECCP) Module. 17.0 Master Synchronous Serial Port (MSSP) Module 18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART) 19.0 10-Bit Analog-to-Digital Converter (A/D) Module 20.0 Comparator Module. 21.0 Comparator Voltage Reference Module 22.0 High/Low-Voltage Detect (HLVD). 23.0 ECAN Module. 24.0 Special Features 25.0 Instruction Summary 26.0 Development Support. 27.0 Electrical Characteristics 28.0 Characteristics Graphs Tables 29.0 Packaging Information. Appendix Revision History. Appendix Device Differences. Appendix Conversion Considerations Appendix Migration from Baseline Enhanced Devices. Appendix Migration From Mid-Range Enhanced Devices Appendix Migration From High-End Enhanced Devices. Index On-Line Support. Systems Information Upgrade Line Reader Response PIC18F2480/2580/4480/4580 Product Identification System
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PIC18F2480/2580/4480/4580
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting sales office literature center, please specify which device, revision silicon data sheet (include literature number) using.
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2004 Microchip Technology Inc.
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NOTES:
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2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
DEVICE OVERVIEW
1.1.2
This document contains device specific information following devices: PIC18F2480 PIC18F2580 PIC18F4480 PIC18F4580
MULTIPLE OSCILLATOR OPTIONS FEATURES
devices PIC18F2480/2580/4480/4580 family offer different oscillator options, allowing users wide range choices developing application hardware. These include: Four Crystal modes, using crystals ceramic resonators External Clock modes, offering option using pins (oscillator input divide-by-4 clock output) (oscillator input, with second reassigned general I/O) External Oscillator modes with same options External Clock modes internal oscillator block which provides clock (±2% accuracy) INTRC source (approximately kHz, stable over temperature VDD), well range user selectable clock frequencies, between MHz, total clock frequencies. This option frees oscillator pins additional general purpose I/O. Phase Lock Loop (PLL) frequency multiplier, available both high-speed crystal internal oscillator modes, which allows clock speeds MHz. Used with internal oscillator, gives users complete selection clock speeds, from without using external crystal clock circuit. Besides availability clock source, internal oscillator block provides stable reference source that gives family additional features robust operation: Fail-Safe Clock Monitor: This option constantly monitors main clock source against reference signal provided internal oscillator. clock failure occurs, controller switched internal oscillator block, allowing continued low-speed operation safe application shutdown. Two-Speed Start-up: This option allows internal oscillator serve clock source from Power-on Reset, wake-up from Sleep mode, until primary clock source available.
This family devices offers advantages PIC18 microcontrollers namely, high computational performance economical price with addition high-endurance, Enhanced Flash program memory. addition these features, PIC18F2480/2580/4480/4580 family introduces design enhancements that make these microcontrollers logical choice many high-performance, power sensitive applications.
1.1.1
Core Features
nanoWatt TECHNOLOGY
devices PIC18F2480/2580/4480/4580 family incorporate range features that significantly reduce power consumption during operation. items include: Alternate Modes: clocking controller from Timer1 source internal oscillator block, power consumption during code execution reduced much 90%. Multiple Idle Modes: controller also with core disabled peripherals still active. these states, power consumption reduced even further, little normal operation requirements. On-the-fly Mode Switching: power managed modes invoked user code during operation, allowing user incorporate power-saving ideas into their application's software design. Lower Consumption Modules: power requirements both Timer1 Watchdog Timer have been reduced 80%, with typical values respectively. Extended Instruction Set: addition standard instructions PIC18 instruction set, PIC18F2480/2580/4480/4580 devices also provide optional extension core functionality. added features include eight additional instructions that augment indirect indexed addressing operations implementation Indexed Literal Offset Addressing mode many standard PIC18 instructions.
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Other Special Features
Memory Endurance: Enhanced Flash cells both program memory data EEPROM rated last many thousands erase/write cycles 100,000 program memory 1,000,000 EEPROM. Data retention without refresh conservatively estimated greater than years. Self-programmability: These devices write their program memory spaces under internal software control. using bootloader routine located protected Boot Block program memory, becomes possible create application that update itself field. Extended Instruction Set: PIC18F2480/2580/4480/4580 family introduces optional extension PIC18 instruction set, which adds instructions Indexed Addressing mode. This extension, enabled device configuration option, been specifically designed optimize re-entrant application code originally developed high-level languages, such Enhanced module: mode, this module provides modulated outputs controlling half-bridge full-bridge drivers. Other features include Auto-Shutdown, disabling outputs interrupt other select conditions Auto-Restart, reactivate outputs once condition cleared. Enhanced Addressable USART: This serial communication module capable standard RS-232 operation provides support protocol. Other enhancements include automatic baud rate detection 16-bit Baud Rate Generator improved resolution. When microcontroller using internal oscillator block, EUSART provides stable operation applications that talk outside world without using external crystal accompanying power requirement). 10-bit Converter: This module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period thus, reduce code overhead. Extended Watchdog Timer (WDT): This enhanced version incorporates 16-bit prescaler, allowing time-out range from over seconds, that stable across operating voltage temperature.
Details Individual Family Members
Devices PIC18F2480/2580/4480/4580 family available 28-pin (PIC18F2X80) 40/44-pin (PIC18F4X80) packages. Block diagrams groups shown Figure Figure 1-2. devices differentiated from each other ways: Flash program memory Kbytes PIC18FX480 devices; Kbytes PIC18FX580). channels PIC18F2X80 devices; PIC18F4X80 devices). ports bidirectional ports input only port PIC18F2X80 devices; bidirectional ports PIC18F4X80 devices). Enhanced implementation (PIC18F2X80 devices have standard module; PIC18F4X80 devices have standard module ECCP module). Parallel Slave Port (present only PIC18F4X80 devices). PIC18F4X80 devices provide comparators.
other features devices this family identical. These summarized Table 1-1. pinouts devices listed Table Table 1-3. Like Microchip PIC18 devices, members PIC18F2480/2580/4480/4580 family available both standard low-voltage devices. Standard devices with Enhanced Flash memory, designated with part number (such PIC18F2580), accommodate operating range 4.2V 5.5V. Low-voltage parts, designated "LF" (such PIC18LF2580), function over extended range 2.0V 5.5V.
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TABLE 1-1: DEVICE FEATURES
PIC18F2480 16384 8192 Ports MSSP, Enhanced USART Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), Instructions; with Extended Instruction enabled 28-pin SPDIP 28-pin SOIC 28-pin PIC18F2580 32768 16384 1536 Ports MSSP, Enhanced USART Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), Instructions; with Extended Instruction enabled 28-pin SPDIP 28-pin SOIC 28-pin PIC18F4480 16384 8192 MSSP, Enhanced USART Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), Instructions; with Extended Instruction enabled 40-pin PDIP 44-pin 44-pin TQFP PIC18F4580 32768 16384 1536 MSSP, Enhanced USART Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), Instructions; with Extended Instruction enabled 40-pin PDIP 44-pin 44-pin TQFP Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Data EEPROM Memory (Bytes) Interrupt Sources Ports Timers Capture/Compare/PWM Modules Enhanced Capture/ Compare/PWM Modules ECAN Module Serial Communications Parallel Communications (PSP) 10-bit Analog-to-Digital Module Comparators Resets (and Delays)
Ports Ports
Programmable High/Low-Voltage Detect Programmable Brown-out Reset Instruction
Packages
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FIGURE 1-1:
Table Pointer<21> inc/dec logic Program Counter
PCLATU PCLATH
PIC18F2480/2580 (28-PIN) BLOCK DIAGRAM
Data Bus<8> Data Latch Data Memory (.7, Kbytes) Address Latch Data Address<12> FSR0 FSR1 FSR2 inc/dec logic Access Bank PORTB RB0/INT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7
Level Stack Address Latch Program Memory (16/32 Kbytes) Data Latch
Table Latch
STKPTR
Latch
Instruction <16>
Address Decode
Instruction Decode Control State machine control signals PRODH PRODL PORTC BITOP OSC1(2) OSC2(2) T1OSI T1OSO MCLR(1) VDD, Internal Oscillator Block INTRC Oscillator Oscillator Single-Supply Programming In-Circuit Debugger Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor Band Reference PORTE MCLR/VPP/RE3(1) ALU<8> Multiply RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
HLVD
Data EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
CCP1
ECCP1
MSSP
EUSART
10-bit
ECAN
Note
multiplexed with MCLR only available when MCLR Resets disabled. OSC1/CLKI OSC2/CLKO only available select oscillator modes when these pins being used digital I/O. Refer Section "Oscillator Configurations" additional information.
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FIGURE 1-2:
Table Pointer<21> inc/dec logic Program Counter
PCLATU PCLATH
PIC18F4480/4580 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8> Data Latch Data Memory (.7, Kbytes) Address Latch Data Address<12> PORTB Level Stack FSR0 FSR1 FSR2 inc/dec logic PORTC RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Access Bank RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTA RA0/AN0/CVREF RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7
Address Latch Program Memory (16/32 Kbytes) Data Latch
Table Latch
STKPTR
Latch
Instruction <16>
Address Decode
Instruction Decode Control State machine control signals PRODH PRODL BITOP OSC1(2) OSC2
Multiply ALU<8> PORTE PORTD RD0/PSP0 /C1IN+ RD1/PSP1/C1INRD2/PSP2/C2IN+ RD3/PSP3/C2INRD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D
Internal Oscillator Block INTRC Oscillator Oscillator Single-Supply Programming In-Circuit Debugger
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor
T1OSI T1OSO MCLR(1) VDD,
Band Reference
RE0/RD/AN5 RE1/WR/AN6/C1OUT RE2/CS/AN7/C2OUT MCLR/VPP/RE3(1)
HLVD
Data EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
CCP1
ECCP1
MSSP
EUSART
10-bit
ECAN
Note
multiplexed with MCLR only available when MCLR Resets disabled. OSC1/CLKI OSC2/CLKO only available select oscillator modes when these pins being used digital I/O. Refer Section "Oscillator Configurations" additional information.
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TABLE 1-2:
Name MCLR/VPP/RE3 MCLR OSC1/CLKI/RA7 OSC1 CLKI OSC2/CLKO/RA6 OSC2 CLKO
PIC18F2480/2580 PINOUT DESCRIPTIONS
SPDIP, Type SOIC Number Buffer Type Description Master Clear (input) programming voltage (input). Master Clear (Reset) input. This active-low Reset device. Programming voltage input. Digital input.
Oscillator crystal external clock input. Oscillator crystal input external clock source input. buffer when configured mode; CMOS otherwise. CMOS External clock source input. Always associated with function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose pin. Oscillator crystal clock output. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. mode, OSC2 outputs CLKO which frequency OSC1 denotes instruction cycle rate. General purpose pin. CMOS CMOS compatible input output Input Power
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-2:
Name
PIC18F2480/2580 PINOUT DESCRIPTIONS (CONTINUED)
SPDIP, Type SOIC Analog Analog Digital I/O. Analog input SPISlave Select input. High/Low-Voltage Detect input. OSC2/CLKO/RA6 pin. OSC1/CLKI/RA7 pin. CMOS CMOS compatible input output Input Power Digital I/O. Timer0 external clock input. Analog Analog Digital I/O. Analog input Reference Voltage (High) input. Analog Analog Digital I/O. Analog input Reference Voltage (Low) input. Analog Digital I/O. Analog input Analog Digital I/O. Analog input Number Buffer Type Description PORTA bidirectional port.
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA2 VREFRA3/AN3/VREF+ VREF+ RA4/T0CKI T0CKI RA5/AN4/SS/HLVDIN HLVDIN
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-2:
Name
PIC18F2480/2580 PINOUT DESCRIPTIONS (CONTINUED)
SPDIP, Type SOIC Number Buffer Type Description PORTB bidirectional port. PORTB software programmed internal weak pull-ups inputs.
RB0/INT0/ AN10 INT0 AN10 RB1/INT1/AN8 INT1 RB2/INT2/CANTX INT2 CANTX RB3/CANRX CANRX RB4/KBI0/AN9 KBI0 RB5/KBI1/PGM KBI1 RB6/KBI2/PGC KBI2 RB7/KBI3/PGD KBI3
Analog Analog Analog Digital I/O. External interrupt Analog input Digital I/O. External interrupt Analog input Digital I/O. External interrupt Digital I/O. Digital I/O. Interrupt-on-change pin. Analog input Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPprogramming enable pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSP programming clock pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSP programming data pin. CMOS CMOS compatible input output Input Power
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-2:
Name
PIC18F2480/2580 PINOUT DESCRIPTIONS (CONTINUED)
SPDIP, Type SOIC Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). MCLR/VPP/RE3 pin. Ground reference logic pins. Positive supply logic pins. CMOS CMOS compatible input output Input Power Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). Digital I/O. data out. Digital I/O. data data I/O. Digital I/O. Synchronous serial clock input/output SPImode. Synchronous serial clock input/output I2Cmode. Digital I/O. Capture1 input/Compare1 output/PWM1 output. CMOS Digital I/O. Timer1 oscillator input. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Number Buffer Type Description PORTC bidirectional port.
RC0/T1OSO/T13CKI T1OSO T13CKI RC1/T1OSI T1OSI RC2/CCP1 CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-3:
Name MCLR/VPP/RE3 MCLR OSC1/CLKI/RA7 OSC1
PIC18F4480/4580 PINOUT DESCRIPTIONS
Number PDIP Buffer TQFP Type Type Description Master Clear (input) programming voltage (input). Master Clear (Reset) input. This active-low Reset device. Programming voltage input. Digital input.
CLKI
OSC2/CLKO/RA6 OSC2 CLKO
Oscillator crystal external clock input. Oscillator crystal input external clock source input. buffer when configured mode; CMOS otherwise. CMOS External clock source input. Always associated with function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose pin. Oscillator crystal clock output. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. mode, OSC2 outputs CLKO which frequency OSC1 denotes instruction cycle rate. General purpose pin. CMOS CMOS compatible input output Input Power
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-3:
Name
PIC18F4480/4580 PINOUT DESCRIPTIONS (CONTINUED)
Number PDIP Buffer TQFP Type Type Analog Analog Digital I/O. Analog input SPISlave Select input. High/Low-Voltage Detect input. OSC2/CLKO/RA6 pin. OSC1/CLKI/RA7 pin. CMOS CMOS compatible input output Input Power Digital I/O. Timer0 external clock input. Analog Analog Digital I/O. Analog input Reference Voltage (High) input. Analog Analog Digital I/O. Analog input Reference Voltage (Low) input. Analog Digital I/O. Analog input Analog Analog Digital I/O. Analog input Analog Comparator Reference output. Description PORTA bidirectional port.
RA0/AN0/CVREF CVREF RA1/AN1 RA2/AN2/VREFRA2 VREFRA3/AN3/VREF+ VREF+ RA4/T0CKI T0CKI RA5/AN4/SS/HLVDIN HLVDIN
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-3:
Name
PIC18F4480/4580 PINOUT DESCRIPTIONS (CONTINUED)
Number PDIP Buffer TQFP Type Type Description PORTB bidirectional port. PORTB software programmed internal weak pull-ups inputs.
RB0/INT0/FLT0/ AN10 INT0 FLT0 AN10 RB1/INT1/AN8 INT1 RB2/INT2/CANTX INT2 CANTX RB3/CANRX CANRX RB4/KBI0/AN9 KBI0 RB5/KBI1/PGM KBI1 RB6/KBI2/PGC KBI2 RB7/KBI3/PGD KBI3
Analog Digital I/O. External interrupt Enhanced Fault input (ECCP1 module). Analog input
Analog Analog Digital I/O. External interrupt Analog input Digital I/O. External interrupt Digital I/O. Digital I/O. Interrupt-on-change pin. Analog input Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPProgramming enable pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSP programming clock pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSP programming data pin. CMOS CMOS compatible input output Input Power
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-3:
Name
PIC18F4480/4580 PINOUT DESCRIPTIONS (CONTINUED)
Number PDIP Buffer TQFP Type Type Digital I/O. EUSART asynchronous receive. EUSART synchronous data (see related TX/CK). CMOS CMOS compatible input output Input Power Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock (see related RX/DT). Digital I/O. data out. Digital I/O. data data I/O. Digital I/O. Synchronous serial clock input/output SPImode. Synchronous serial clock input/output I2Cmode. Digital I/O. Capture1 input/Compare1 output/PWM1 output. CMOS Digital I/O. Timer1 oscillator input. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Description PORTC bidirectional port.
RC0/T1OSO/T13CKI T1OSO T13CKI RC1/T1OSI T1OSI RC2/CCP1 CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-3:
Name
PIC18F4480/4580 PINOUT DESCRIPTIONS (CONTINUED)
Number PDIP Buffer TQFP Type Type Description PORTD bidirectional port Parallel Slave Port (PSP) interfacing microprocessor port. These pins have input buffers when module enabled.
RD0/PSP0/C1IN+ PSP0 C1IN+ RD1/PSP1/C1INRD1 PSP1 C1INRD2/PSP2/C2IN+ PSP2 C2IN+ RD3/PSP3/C2INRD3 PSP3 C2INRD4/PSP4/ECCP1/ PSP4 ECCP1 RD5/PSP5/P1B PSP5 RD6/PSP6/P1C PSP6 RD7/PSP7/P1D PSP7
Analog Analog Analog Analog Digital I/O. Parallel Slave Port data. Comparator input (+). Digital I/O. Parallel Slave Port data. Comparator input Digital I/O. Parallel Slave Port data. Comparator input (+). Digital I/O. Parallel Slave Port data. Comparator input (-).
Digital I/O. Parallel Slave Port data. Capture2 input/Compare output/PWM2 output. ECCP1 output Digital I/O. Parallel Slave Port data. ECCP1 output Digital I/O. Parallel Slave Port data. ECCP1 output Digital I/O. Parallel Slave Port data. ECCP1 output CMOS CMOS compatible input output Input Power
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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TABLE 1-3:
Name
PIC18F4480/4580 PINOUT DESCRIPTIONS (CONTINUED)
Number PDIP Buffer TQFP Type Type Analog Digital I/O. Chip Select control Parallel Slave Port (see related WR). Analog input Comparator output. MCLR/VPP/RE3 pin. Ground reference logic pins. Positive supply logic pins. connect. CMOS CMOS compatible input output Input Power Analog Digital I/O. Write control Parallel Slave Port (see pins). Analog input Comparator output. Analog Digital I/O. Read control Parallel Slave Port (see also pins). Analog input Description PORTE bidirectional port.
RE0/RD/AN5 RE1/WR/AN6/C1OUT C1OUT RE2/CS/AN7/C2OUT C2OUT
Legend: compatible input Schmitt Trigger input with CMOS levels Output
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NOTES:
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OSCILLATOR CONFIGURATIONS
Oscillator Types
FIGURE 2-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (XT, HSPLL CONFIGURATION)
OSC1 Internal Logic Sleep
PIC18F2480/2580/4480/4580 devices operated different oscillator modes. user program configuration bits, FOSC3:FOSC0, Configuration Register select these modes: Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with enabled External Resistor/Capacitor with FOSC/4 output RCIO External Resistor/Capacitor with INTIO1 Internal Oscillator with FOSC/4 output INTIO2 Internal Oscillator with External Clock with FOSC/4 output ECIO External Clock with HSPLL
C1(1)
XTAL
RS(2) C2(1) OSC2
RF(3)
PIC18FXXXX
Note Table Table initial values series resistor (RS) required strip crystals. varies with oscillator mode chosen.
TABLE 2-1:
CAPACITOR SELECTION CERAMIC RESONATORS
Typical Capacitor Values Used: Mode Freq 16.0 OSC1 OSC2
Crystal Oscillator/Ceramic Resonators
HSPLL Oscillator modes, crystal ceramic resonator connected OSC1 OSC2 pins establish oscillation. Figure shows connections. oscillator design requires parallel crystal. Note: series crystal give frequency crystal manufacturer's specifications.
Capacitor values design guidance only. These capacitors were tested with resonators listed below basic start-up operation. These values optimized. Different capacitor values required produce acceptable oscillator operation. user should test performance oscillator over expected temperature range application. notes page additional information. Resonators Used: 16.0 Note: When using resonators with frequencies above MHz, mode, rather than mode, recommended. mode used which controller rated. selected, possible that gain oscillator will overdrive resonator. Therefore, series resistor should placed between OSC2 resonator. good starting point, recommended value 330.
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TABLE 2-2: CAPACITOR SELECTION CRYSTAL OSCILLATOR
Crystal Freq Typical Capacitor Values Tested:
Clock from Ext. System Open OSC1
external clock source also connected OSC1 mode, shown Figure 2-2.
FIGURE 2-2:
Type
EXTERNAL CLOCK INPUT OPERATION OSCILLATOR CONFIGURATION)
PIC18FXXXX
OSC2 Mode)
Capacitor values design guidance only. These capacitors were tested with crystals listed below basic start-up operation. These values optimized. Different capacitor values required produce acceptable oscillator operation. user should test performance oscillator over expected temperature range application. notes following this table additional information. Crystals Used:
External Clock Input
ECIO Oscillator modes require external clock source connected OSC1 pin. There oscillator start-up time required after Power-on Reset after exit from Sleep mode. Oscillator mode, oscillator frequency divided available OSC2 pin. This signal used test purposes synchronize other logic. Figure shows connections Oscillator mode.
FIGURE 2-3:
EXTERNAL CLOCK INPUT OPERATION CONFIGURATION)
OSC1/CLKI
Note Higher capacitance increases stability oscillator also increases start-up time. When operating below VDD, when using certain ceramic resonators voltage, necessary mode switch crystal oscillator. Since each resonator/crystal characteristics, user should consult resonator/crystal manufacturer appropriate values external components. required avoid overdriving crystals with drive level specification. Always verify oscillator performance over temperature range that expected application.
Clock from Ext. System FOSC/4
PIC18FXXXX
OSC2/CLKO
ECIO Oscillator mode functions like mode, except that OSC2 becomes additional general purpose pin. becomes PORTA (RA6). Figure shows connections ECIO Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)
OSC1/CLKI
Clock from Ext. System
PIC18FXXXX
(OSC2)
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Oscillator Frequency Multiplier
timing insensitive applications, "RC" "RCIO" device options offer additional cost savings. actual oscillator frequency function several factors: supply voltage values external resistor (REXT) capacitor (CEXT) operating temperature Given same device, operating voltage temperature component values, there will also unit-to-unit frequency variations. These factors such normal manufacturing variation difference lead frame capacitance between package types (especially CEXT values) variations within tolerance limits REXT CEXT Oscillator mode, oscillator frequency divided available OSC2 pin. This signal used test purposes synchronize other logic. Figure shows combination connected. Phase Locked Loop (PLL) circuit provided option users wish lower frequency oscillator circuit clock device highest rated frequency from crystal oscillator. This useful customers concerned with high-frequency crystals users require higher clock speeds from internal oscillator.
2.5.1
HSPLL OSCILLATOR MODE
HSPLL mode makes mode oscillator frequencies MHz. then multiplies oscillator output frequency produce internal clock frequency MHz. only available crystal oscillator when FOSC3:FOSC0 configuration bits programmed HSPLL mode 0110).
FIGURE 2-7:
BLOCK DIAGRAM MODE)
Enable Enable (from Configuration Register OSC2
Mode OSC1 Crystal
FIGURE 2-5:
REXT
OSCILLATOR MODE
FOUT
Phase Comparator
OSC1 CEXT FOSC/4 OSC2/CLKO
Internal Clock
Loop Filter
PIC18FXXXX
SYSCLK
Recommended values: REXT CEXT
RCIO Oscillator mode (Figure 2-6) functions like mode, except that OSC2 becomes additional general purpose pin. becomes PORTA (RA6).
2.5.2
INTOSC
FIGURE 2-6:
REXT
RCIO OSCILLATOR MODE
also available internal oscillator block selected oscillator modes. this configuration, enabled software generates clock output MHz. operation INTOSC with described Section 2.6.4 "PLL INTOSC Modes".
OSC1 CEXT (OSC2)
Internal Clock
PIC18FXXXX
Recommended values: REXT CEXT
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Internal Oscillator Block
PIC18F2480/2580/4480/4580 devices include internal oscillator block which generates different clock signals; either used microcontroller's clock source. This eliminate need external oscillator circuits OSC1 and/or OSC2 pins. main output (INTOSC) clock source, which used directly drive device clock. also drives postscaler, which provide range clock frequencies from MHz. INTOSC output enabled when clock frequency from selected. other clock source internal oscillator (INTRC), which provides nominal output. INTRC enabled selected device clock source; also enabled automatically when following enabled: Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up When OSCTUNE register modified, INTOSC INTRC frequencies will begin shifting frequency. INTRC clock will reach frequency within clock cycles (approximately µs). INTOSC clock will stabilize within Code execution continues during this shift. There indication that shift occurred. OSCTUNE register also implements INTSRC PLLEN bits, which control certain features internal oscillator block. INTSRC allows users select which internal oscillator provides clock source when frequency option selected. This covered greater detail Section 2.7.1 "Oscillator Control Register". PLLEN controls operation frequency multiplier, PLL, internal oscillator modes.
2.6.4
INTOSC MODES
frequency multiplier used with internal oscillator block produce faster device clock speeds than normally possible with internal oscillator. When enabled, produces clock speed MHz. Unlike HSPLL mode, controlled through software. control bit, PLLEN (OSCTUNE<6>), used enable disable operation. available when device configured internal oscillator block primary clock source (FOSC3:FOSC0 1001 1000). Additionally, will only function when selected output frequency either (OSCCON<6:4> 110). both these conditions met, disabled. PLLEN control only functional those internal oscillator modes where available. other modes, forced effectively unavailable.
These features discussed greater detail Section 24.0 "Special Features CPU". clock source frequency (INTOSC direct, INTRC direct INTOSC postscaler) selected configuring IRCF bits OSCCON register (Register 2-2).
2.6.1
INTIO MODES
Using internal oscillator clock source eliminates need external oscillator pins, which then used digital I/O. distinct configurations available: INTIO1 mode, OSC2 outputs FOSC/4, while OSC1 functions digital input output. INTIO2 mode, OSC1 functions OSC2 functions RA6, both digital input output.
2.6.5
INTOSC FREQUENCY DRIFT
2.6.2
INTOSC OUTPUT FREQUENCY
internal oscillator block calibrated factory produce INTOSC output frequency MHz. INTRC oscillator operates independently INTOSC source. changes INTOSC across voltage temperature necessarily reflected changes INTRC vice versa.
factory calibrates internal oscillator block output (INTOSC) MHz. However, this frequency drift temperature changes, which affect controller operation variety ways. possible adjust INTOSC frequency modifying value OSCTUNE register. This effect INTRC clock source frequency. Tuning INTOSC source requires knowing when make adjustment, which direction should made some cases, large change needed. Three compensation techniques discussed Section 2.6.5.1 "Compensating with EUSART", Section 2.6.5.2 "Compensating with Timers" Section 2.6.5.3 "Compensating with Module Capture Mode", other techniques used.
2.6.3
OSCTUNE REGISTER
internal oscillator's output been calibrated factory adjusted user's application. This done writing OSCTUNE register (Register 2-1). tuning sensitivity constant throughout tuning range.
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REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 INTSRC INTSRC: Internal Oscillator Low-Frequency Source Select 31.25 device clock derived from INTOSC source (divide-by-256 enabled) device clock derived directly from INTRC internal oscillator PLLEN: Frequency Multiplier INTOSC Enable bit(1) enabled INTOSC only) disabled Note Available only certain oscillator configurations; otherwise, this unavailable reads `0'. text details. Unimplemented: Read TUN4:TUN0: Frequency Tuning bits 01111 Maximum frequency 00001 00000 Center frequency. Oscillator module running calibrated frequency. 11111 10000 Minimum frequency Legend: Readable Value R/W-0(1) PLLEN(1) R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0
Writable
Unimplemented bit, read cleared unknown
2.6.5.1
Compensating with EUSART
2.6.5.3
adjustment required when EUSART begins generate framing errors receives data with errors while Asynchronous mode. Framing errors indicate that device clock frequency high. adjust this, decrement value OSCTUNE reduce clock frequency. other hand, errors data suggest that clock speed low. compensate, increment OSCTUNE increase clock frequency.
Compensating with Module Capture Mode
2.6.5.2
Compensating with Timers
module free running Timer1 Timer3), clocked internal oscillator block external event with known period (i.e., power frequency). time first event captured CCPRxH:CCPRxL registers recorded later. When second event causes capture, time first event subtracted from time second event. Since period external event known, time difference between events calculated. measured time much greater than calculated time, internal oscillator block running fast. compensate, decrement OSCTUNE register. measured time much less than calculated time, internal oscillator block running slow. compensate, increment OSCTUNE register.
This technique compares device clock speed some reference clock. timers used; timer clocked peripheral clock, while other clocked fixed reference source, such Timer1 oscillator. Both timers cleared, timer clocked reference generates interrupts. When interrupt occurs, internally clocked timer read both timers cleared. internally clocked timer value greater than expected, then internal oscillator block running fast. adjust this, decrement OSCTUNE register.
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Clock Sources Oscillator Switching
secondary oscillators those external sources connected OSC1 OSC2 pins. These sources continue operate even after controller placed power managed mode. PIC18F2480/2580/4480/4580 devices offer Timer1 oscillator secondary oscillator. This oscillator, power managed modes, often time base functions such real-time clock. Most often, 32.768 watch crystal connected between RC0/T1OSO/T13CKI RC1/T1OSI pins. Like mode oscillator circuit, loading capacitors also connected from each ground. Timer1 oscillator discussed greater detail Section 12.3 "Timer1 Oscillator". addition being primary clock source, internal oscillator block available power managed mode clock source. INTRC source also used clock source several special features, such Fail-Safe Clock Monitor. clock sources PIC18F2480/2580/4480/4580 devices shown Figure 2-8. Section 24.0 "Special Features CPU" Configuration register details.
Like previous PIC18 devices, PIC18F2480/2580/4480/4580 family includes feature that allows device clock source switched from main oscillator alternate low-frequency clock source. PIC18F2480/2580/4480/4580 devices offer alternate clock sources. When alternate clock source enabled, various power managed operating modes available. Essentially, there three clock sources these devices: Primary oscillators Secondary oscillators Internal oscillator block primary oscillators include external crystal resonator modes, external modes, external clock modes internal oscillator block. particular mode defined FOSC3:FOSC0 configuration bits. details these modes covered earlier this chapter.
FIGURE 2-8:
PIC18F2480/2580/4480/4580 CLOCK DIAGRAM
PIC18F2X80/4X80
Primary Oscillator OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator OSCCON<6:4> Internal Oscillator Block Source INTRC Source OSCTUNE<6> T1OSC Peripherals
HSPLL, INTOSC/PLL
T1OSI
OSCCON<6:4> Postscaler
Internal Oscillator
IDLEN Clock Control FOSC3:FOSC0 OSCCON<1:0>
(INTOSC)
(INTRC)
OSCTUNE<7>
Clock Source Option other Modules
WDT, PWRT, FSCM Two-Speed Startup
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2.7.1 OSCILLATOR CONTROL REGISTER
OSCCON register (Register 2-2) controls several aspects device clock's operation, both full power operation power managed modes. System Clock Select bits, SCS1:SCS0, select clock source. available clock sources primary clock (defined FOSC3:FOSC0 configuration bits), secondary clock (Timer1 oscillator) internal oscillator block. clock source changes immediately after more bits written following brief clock transition interval. bits cleared forms Reset. Internal Oscillator Frequency Select bits, IRCF2:IRCF0, select frequency output internal oscillator block drive device clock. choices INTRC source, INTOSC source MHz) frequencies derived from INTOSC postscaler MHz). internal oscillator block supplying device clock, changing states these bits will have immediate change internal oscillator's output. device Resets, default output frequency internal oscillator block MHz. When output frequency selected (IRCF2:IRCF0 000), users choose which internal oscillator acts source. This done with INTSRC OSCTUNE register (OSCTUNE<7>). Setting this selects INTOSC 31.25 clock source enabling divide-by-256 output INTOSC postscaler. Clearing INTSRC selects INTRC (nominally kHz) clock source. This option allows users select tunable more precise INTOSC clock source, while maintaining power savings with very clock speed. Regardless setting INTSRC, INTRC always remains clock source features such Watchdog Timer Fail-Safe Clock Monitor. OSTS, IOFS T1RUN bits indicate which clock source currently providing device clock. OSTS indicates that Oscillator Start-up Timer timed primary clock providing device clock primary clock modes. IOFS indicates when internal oscillator block stabilized providing device clock Clock modes. T1RUN (T1CON<6>) indicates when Timer1 oscillator providing device clock secondary clock modes. power managed modes, only these three bits will time. none these bits set, INTRC providing clock internal oscillator block just started stable. IDLEN determines device goes into Sleep mode Idle modes when SLEEP instruction executed. flag control bits OSCCON register discussed more detail Section "Power Managed Modes". Note Timer1 oscillator must enabled select secondary clock source. Timer1 oscillator enabled setting T1OSCEN Timer1 Control register (T1CON<3>). Timer1 oscillator enabled, then attempt select secondary clock source when executing SLEEP instruction will ignored. recommended that Timer1 oscillator operating stable before executing SLEEP instruction, very long delay occur while Timer1 oscillator starts.
2.7.2
OSCILLATOR TRANSITIONS
PIC18F2480/2580/4480/4580 devices contain circuitry prevent clock "glitches" when switching between clock sources. short pause device clock occurs during clock switch. length this pause cycles clock source three four cycles clock source. This formula assumes that clock source stable. Clock transitions discussed greater detail Section 3.1.2 "Entering Power Managed Modes".
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REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 IDLEN IDLEN: Idle Enable Device enters Idle mode SLEEP instruction Device enters Sleep mode SLEEP instruction IRCF2:IRCF0: Internal Oscillator Frequency Select bits (INTOSC drives clock directly) MHz(3) (from either INTOSC/256 INTRC directly)(2) OSTS: Oscillator Start-up Time-out Status bit(1) Oscillator start-up time-out timer expired; primary oscillator running Oscillator start-up time-out timer running; primary oscillator ready IOFS: INTOSC Frequency Stable INTOSC frequency stable frequency provided modes INTOSC frequency stable SCS1:SCS0: System Clock Select bits Internal oscillator block Timer1 oscillator Primary oscillator Note Depends state IESO configuration bit. Source selected INTSRC (OSCTUNE<7>), text. Default output frequency INTOSC Reset. Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-1 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 R(1) OSTS IOFS R/W-0 SCS1 R/W-0 SCS0
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Effects Power Managed Modes Various Clock Sources
real-time clock. Other features operating that require device clock source (i.e., slave, PSP, INTn pins others). Peripherals that significant current consumption listed Section 27.2 Characteristics: Power Down Supply Current".
When PRI_IDLE mode selected, designated primary oscillator continues without interruption. other power managed modes, oscillator using OSC1 disabled. OSC1 (and OSC2 pin, used oscillator) will stop oscillating. secondary clock modes (SEC_RUN SEC_IDLE), Timer1 oscillator operating providing device clock. Timer1 oscillator also power managed modes required clock Timer1 Timer3. internal oscillator modes (RC_RUN RC_IDLE), internal oscillator block provides device clock source. INTRC output used directly provide clock enabled support various special features, regardless power managed mode (see Section 24.2 "Watchdog Timer (WDT)", Section 24.3 "Two-Speed Start-up" Section 24.4 "Fail-Safe Clock Monitor" more information WDT, Two-Speed Start-up Fail-Safe Clock Monitor. INTOSC output used directly clock device divided down postscaler. INTOSC output disabled clock provided directly from INTRC output. Sleep mode selected, clock sources stopped. Since transistor switching currents have been stopped, Sleep mode achieves lowest current consumption device (only leakage currents). Enabling on-chip feature that will operate during Sleep will increase current consumed during Sleep. INTRC required support operation. Timer1 oscillator operating support
Power-up Delays
Power-up delays controlled timers, that external Reset circuitry required most applications. delays ensure that device kept Reset until device power supply stable under normal circumstances primary clock operating stable. additional information power-up delays, Section "Device Reset Timers". first timer Power-up Timer (PWRT), which provides fixed delay power-up (parameter Table 27-10). enabled clearing PWRTEN configuration bit. second timer Oscillator Start-up Timer (OST), intended keep chip Reset until crystal oscillator stable (LP, modes). does this counting 1024 oscillator cycles before allowing oscillator clock device. When HSPLL Oscillator mode selected, device kept Reset additional following mode delay, lock incoming clock frequency. There delay interval TCSD (parameter Table 27-10), following POR, while controller becomes ready execute instructions. This delay runs concurrently with other delays. This only delay that occurs when INTIO modes used primary clock source.
TABLE 2-3:
INTIO1 RCIO, INTIO2 ECIO Note:
OSC1 OSC2 STATES SLEEP MODE
OSC1 Floating, external resistor should pull high Floating, external resistor should pull high Floating, pulled external clock Floating, pulled external clock Feedback inverter disabled quiescent voltage level OSC2 logic (clock/4 output) Configured PORTA, Configured PORTA, logic (clock/4 output) Feedback inverter disabled quiescent voltage level
Mode
Table Section "Reset", time-outs Sleep MCLR Reset.
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POWER MANAGED MODES
3.1.1 CLOCK SOURCES
PIC18F2480/2580/4480/4580 devices offer total seven operating modes more efficient power management. These modes provide variety options selective power conservation applications where resources limited (i.e., battery-powered devices). There three categories power managed modes: modes Idle modes Sleep mode These categories define which portions device clocked sometimes, what speed. Idle modes three available clock sources (primary, secondary internal oscillator block); Sleep mode does clock source. power managed modes include several power saving features offered previous PICmicro® devices. clock switching feature, offered other PIC18 devices, allowing controller Timer1 oscillator place primary oscillator. Also included Sleep mode, offered PICmicro devices, where device clocks stopped. SCS1:SCS0 bits allow selection three clock sources power managed modes. They are: primary clock, defined FOSC3:FOSC0 configuration bits secondary clock (the Timer1 oscillator) internal oscillator block (for modes)
3.1.2
ENTERING POWER MANAGED MODES
Switching from power managed mode another begins loading OSCCON register. SCS1:SCS0 bits select clock source determine which Idle mode used. Changing these bits causes immediate switch clock source, assuming that running. switch also subject clock transition delays. These discussed Section 3.1.3 "Clock Transitions Status Indicators" subsequent sections. Entry Power Managed Idle Sleep modes triggered execution SLEEP instruction. actual mode that results depends status IDLEN bit. Depending current mode mode being switched change power managed mode does always require setting these bits. Many transitions done changing oscillator select bits, changing IDLEN bit, prior issuing SLEEP instruction. IDLEN already configured correctly, only necessary perform SLEEP instruction switch desired mode.
Selecting Power Managed Modes
Selecting power managed mode requires decisions: clocked selection clock source. IDLEN (OSCCON<7>) controls clocking, while SCS1:SCS0 bits (OSCCON<1:0>) select clock source. individual modes, settings, clock sources affected modules summarized Table 3-1.
TABLE 3-1:
Mode Sleep PRI_RUN SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note
POWER MANAGED MODES
OSCCON bits IDLEN<7>
Module Clocking Available Clock Oscillator Source Clocked Clocked Clocked Peripherals Clocked Clocked Clocked Clocked Clocked Clocked None clocks disabled Primary HSPLL, INTRC(2): This normal full power execution mode. Secondary Timer1 Oscillator Internal Oscillator Block(2) Primary HSPLL, Secondary Timer1 Oscillator Internal Oscillator Block(2)
SCS1:SCS0<1:0>
IDLEN reflects value when SLEEP instruction executed. Includes INTOSC INTOSC postscaler, well INTRC source.
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3.1.3 CLOCK TRANSITIONS STATUS INDICATORS
Modes
length transition between clock sources cycles clock source three four cycles clock source. This formula assumes that clock source stable. Three bits indicate current clock source status. They are: OSTS (OSCCON<3>) IOFS (OSCCON<2>) T1RUN (T1CON<6>) general, only these bits will while given power managed mode. When OSTS set, primary clock providing device clock. When IOFS set, INTOSC output providing stable clock source divider that actually drives device clock. When T1RUN set, Timer1 oscillator providing clock. none these bits set, then either INTRC clock source clocking device, INTOSC source stable. internal oscillator block configured primary clock source FOSC3:FOSC0 configuration bits, then both OSTS IOFS bits when PRI_RUN PRI_IDLE modes. This indicates that primary clock (INTOSC output) generating stable output. Entering another power managed mode same frequency would clear OSTS bit. Note Caution should used when modifying single IRCF bit. less than possible select higher clock speed than supported VDD. Improper device operation result VDD/FOSC specifications violated. Executing SLEEP instruction does necessarily place device into Sleep mode. acts trigger place controller into either Sleep mode Idle modes, depending setting IDLEN bit.
modes, clocks both core peripherals active. difference between these modes clock source.
3.2.1
PRI_RUN MODE
PRI_RUN mode normal, full power execution mode microcontroller. This also default mode upon device Reset, unless Two-Speed Start-up enabled (see Section 24.3 "Two-Speed Start-up" details). this mode, OSTS set. IOFS internal oscillator block primary clock source (see Section 2.7.1 "Oscillator Control Register").
3.2.2
SEC_RUN MODE
SEC_RUN mode compatible mode "clock switching" feature offered other PIC18 devices. this mode, peripherals clocked from Timer1 oscillator. This gives users option lower power consumption while still using high accuracy clock source. SEC_RUN mode entered setting SCS1:SCS0 bits `01'. device clock source switched Timer1 oscillator (see Figure 3-1), primary oscillator shut down, T1RUN (T1CON<6>) OSTS cleared. Note: Timer1 oscillator should already running prior entering SEC_RUN mode. T1OSCEN when SCS1:SCS0 bits `01', entry SEC_RUN mode will occur. Timer1 oscillator enabled running, device clocks will delayed until oscillator started. such situations, initial oscillator operation from stable unpredictable operation result.
3.1.4
MULTIPLE SLEEP COMMANDS
power managed mode that invoked with SLEEP instruction determined setting IDLEN time instruction executed. another SLEEP instruction executed, device will enter power managed mode specified IDLEN that time. IDLEN changed, device will enter power managed mode specified setting.
transitions from SEC_RUN mode PRI_RUN, peripherals continue clocked from Timer1 oscillator while primary clock started. When primary clock becomes ready, clock switch back primary clock occurs (see Figure 3-2). When clock switch complete, T1RUN cleared, OSTS primary clock providing clock. IDLEN bits affected wake-up; Timer1 oscillator continues run.
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FIGURE 3-1: TRANSITION TIMING ENTRY SEC_RUN MODE
T1OSI OSC1 Clock Peripheral Clock Program Counter Clock Transition
FIGURE 3-2:
TRANSITION TIMING FROM SEC_RUN MODE PRI_RUN MODE (HSPLL)
T1OSI OSC1 TOST(1) TPLL(1)
Clock Output Clock Peripheral Clock Program Counter SCS1:SCS0 bits changed OSTS
Clock Transition
Note TOST 1024 TOSC; TPLL (approx). These intervals shown scale.
3.2.3
RC_RUN MODE
RC_RUN mode, peripherals clocked from internal oscillator block using INTOSC multiplexer; primary clock shut down. When using INTRC source, this mode provides best power conservation modes, while still executing code. works well user applications which highly timing sensitive require high-speed clocks times. primary clock source internal oscillator block (either INTRC INTOSC), there distinguishable differences between PRI_RUN RC_RUN modes during execution. However, clock switch delay will occur during entry exit from RC_RUN mode. Therefore, primary clock source internal oscillator block, RC_RUN mode recommended.
This mode entered setting SCS1 `1'. Although ignored, recommended that SCS0 also cleared; this maintain software compatibility with future devices. When clock source switched INTOSC multiplexer (see Figure 3-3), primary oscillator shut down OSTS cleared. IRCF bits modified time immediately change clock speed. Note: Caution should used when modifying single IRCF bit. less than possible select higher clock speed than supported VDD. Improper device operation result VDD/FOSC specifications violated.
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IRCF bits INTSRC clear, INTOSC output enabled IOFS will remain clear; there will indication current clock source. INTRC source providing device clocks. IRCF bits changed from clear (thus, enabling INTOSC output) INTSRC set, IOFS becomes after INTOSC output becomes stable. Clocks device continue while INTOSC source stabilizes after interval TIOBST. IRCF bits were previously non-zero value INTSRC before setting SCS1 INTOSC source already stable, IOFS will remain set. transitions from RC_RUN mode PRI_RUN mode, device continues clocked from INTOSC multiplexer while primary clock started. When primary clock becomes ready, clock switch primary clock occurs (see Figure 3-4). When clock switch complete, IOFS cleared, OSTS primary clock providing device clock. IDLEN bits affected switch. INTRC source will continue either Fail-Safe Clock Monitor enabled.
FIGURE 3-3:
TRANSITION TIMING RC_RUN MODE
Clock Transition
INTRC OSC1 Clock Peripheral Clock Program Counter
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE PRI_RUN MODE
INTOSC Multiplexer OSC1 TOST(1) Clock Output TPLL(1)
Clock Transition Clock Peripheral Clock Program Counter SCS1:SCS0 bits changed OSTS
Note TOST 1024 TOSC; TPLL (approx). These intervals shown scale.
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Sleep Mode Idle Modes
Power Managed Sleep mode PIC18F2480/2580/4480/4580 devices identical legacy Sleep mode offered other PICmicro devices. entered clearing IDLEN (the default state device Reset) executing SLEEP instruction. This shuts down selected oscillator (Figure 3-5). clock source status bits cleared. Entering Sleep mode from other mode does require clock switch. This because clocks needed once controller entered Sleep. selected, INTRC source will continue operate. Timer1 oscillator enabled, will also continue run. When wake event occurs Sleep mode interrupt, Reset time-out), device will clocked until clock source selected SCS1:SCS0 bits becomes ready (see Figure 3-6), will clocked from internal oscillator block either Two-Speed Start-up Fail-Safe Clock Monitor enabled (see Section 24.0 "Special Features CPU"). either case, OSTS when primary clock providing device clocks. IDLEN bits affected wake-up. Idle modes allow controller's selectively shut down while peripherals continue operate. Selecting particular Idle mode allows users further manage power consumption. IDLEN when SLEEP instruction executed, peripherals will clocked from clock source selected using SCS1:SCS0 bits; however, will clocked. clock source status bits affected. Setting IDLEN executing SLEEP instruction provides quick method switching from given mode corresponding Idle mode. selected, INTRC source will continue operate. Timer1 oscillator enabled, will also continue run. Since executing instructions, only exits from Idle modes interrupt, time-out Reset. When wake event occurs, execution delayed interval TCSD (parameter Table 27-10) while becomes ready execute code. When begins executing code, resumes with same clock source current Idle mode. example, when waking from RC_IDLE mode, internal oscillator block will clock peripherals other words, RC_RUN mode). IDLEN bits affected wake-up. While Idle mode Sleep mode, time-out will result wake-up mode currently specified SCS1:SCS0 bits.
FIGURE 3-5:
OSC1 Clock Peripheral Clock Sleep Program Counter
TRANSITION TIMING ENTRY SLEEP MODE
FIGURE 3-6:
TRANSITION TIMING WAKE FROM SLEEP (HSPLL)
OSC1 Clock Output Clock Peripheral Clock Program Counter Wake Event OSTS TOST(1) TPLL(1)
Note1: TOST 1024 TOSC; TPLL (approx). These intervals shown scale.
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3.4.1 PRI_IDLE MODE 3.4.2 SEC_IDLE MODE
This mode unique among three Low-Power Idle modes, that does disable primary device clock. timing sensitive applications, this allows fastest resumption device operation with more accurate primary clock source, since clock source does have "warm transition from another oscillator. PRI_IDLE mode entered from PRI_RUN mode setting IDLEN executing SLEEP instruction. device another mode, IDLEN first, then clear bits execute SLEEP. Although disabled, peripherals continue clocked from primary clock source specified FOSC3:FOSC0 configuration bits. OSTS remains (see Figure 3-7). When wake event occurs, clocked from primary clock source. delay interval TCSD required between wake event when code execution starts. This required allow become ready execute instructions. After wake-up, OSTS remains set. IDLEN bits affected wake-up (see Figure 3-8). SEC_IDLE mode, disabled peripherals continue clocked from Timer1 oscillator. This mode entered from SEC_RUN setting IDLEN executing SLEEP instruction. device another mode, IDLEN first, then SCS1:SCS0 bits `01' execute SLEEP. When clock source switched Timer1 oscillator, primary oscillator shut down, OSTS cleared T1RUN set. When wake event occurs, peripherals continue clocked from Timer1 oscillator. After interval TCSD following wake event, begins executing code being clocked Timer1 oscillator. IDLEN bits affected wake-up; Timer1 oscillator continues (see Figure 3-8). Note: Timer1 oscillator should already running prior entering SEC_IDLE mode. T1OSCEN when SLEEP instruction executed, SLEEP instruction will ignored entry SEC_IDLE mode will occur. Timer1 oscillator enabled running, peripheral clocks will delayed until oscillator started. such situations, initial oscillator operation from stable unpredictable operation result.
FIGURE 3-7:
TRANSITION TIMING ENTRY IDLE MODE
OSC1 Clock Peripheral Clock Program Counter
FIGURE 3-8:
TRANSITION TIMING WAKE FROM IDLE MODE
OSC1 TCSD Clock Peripheral Clock Program Counter Wake Event
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3.4.3 RC_IDLE MODE
RC_IDLE mode, disabled peripherals continue clocked from internal oscillator block using INTOSC multiplexer. This mode allows controllable power conservation during Idle periods. From RC_RUN, this mode entered setting IDLEN executing SLEEP instruction. device another mode, first IDLEN, then SCS1 execute SLEEP. Although value ignored, recommended that SCS0 also cleared; this maintain software compatibility with future devices. INTOSC multiplexer used select higher clock frequency, modifying IRCF bits, before executing SLEEP instruction. When clock source switched INTOSC multiplexer, primary oscillator shut down OSTS cleared. IRCF bits non-zero value INTSRC set, INTOSC output enabled. IOFS becomes set, after INTOSC output becomes stable, after interval TIOBST (parameter Table 27-10). Clocks peripherals continue while INTOSC source stabilizes. IRCF bits were previously non-zero value, INTSRC before SLEEP instruction executed INTOSC source already stable, IOFS will remain set. IRCF bits INTSRC clear, INTOSC output will enabled, IOFS will remain clear there will indication current clock source. When wake event occurs, peripherals continue clocked from INTOSC multiplexer. After delay TCSD following wake event, begins executing code being clocked INTOSC multiplexer. IDLEN bits affected wake-up. INTRC source will continue either Fail-Safe Clock Monitor enabled. exits from Idle Sleep modes interrupt, code execution branches interrupt vector GIE/GIEH (INTCON<7>) set. Otherwise, code execution continues resumes without branching (see Section "Interrupts"). fixed delay interval TCSD following wake event required when leaving Sleep Idle modes. This delay required prepare execution. Instruction execution resumes first clock cycle following this delay.
3.5.2
EXIT TIME-OUT
time-out will cause different actions depending which power managed mode device when time-out occurs. device executing code (all Idle modes Sleep mode), time-out will result exit from power managed mode (see Section "Run Modes" Section "Sleep Mode"). device executing code (all modes), time-out will result Reset (see Section 24.2 "Watchdog Timer (WDT)"). timer postscaler cleared executing SLEEP CLRWDT instruction, loss currently selected clock source Fail-Safe Clock Monitor enabled) modifying IRCF bits OSCCON register internal oscillator block device clock source.
3.5.3
EXIT RESET
Normally, device held Reset Oscillator Start-up Timer (OST) until primary clock becomes ready. that time, OSTS device begins executing code. internal oscillator block clock source, IOFS instead. exit delay time from Reset start code execution depends both clock sources before after wake-up type oscillator clock source primary clock. Exit delays summarized Table 3-2. Code execution begin before primary clock becomes ready. either Two-Speed Start-up (see Section 24.3 "Two-Speed Start-up") Fail-Safe Clock Monitor (see Section 24.4 "Fail-Safe Clock Monitor") enabled, device begin execution soon Reset source cleared. Execution clocked INTOSC multiplexer driven internal oscillator block. Execution clocked internal oscillator block until either primary clock becomes ready power managed mode entered before primary clock becomes ready; primary clock then shut down.
Exiting Idle Sleep Modes
exit from Sleep mode Idle modes triggered interrupt, Reset time-out. This section discusses triggers that cause exits from power managed modes. clocking subsystem actions discussed each power managed modes (see Section "Run Modes", Section "Sleep Mode" Section "Idle Modes").
3.5.1
EXIT INTERRUPT
available interrupt sources cause device exit from Idle mode Sleep mode mode. enable this functionality, interrupt source must enabled setting enable INTCON registers. exit sequence initiated when corresponding interrupt flag set.
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3.5.4 EXIT WITHOUT OSCILLATOR START-UP DELAY
Certain exits from power managed modes invoke all. There cases: PRI_IDLE mode where primary clock source stopped; primary clock source HSPLL modes. these instances, primary clock source either does require oscillator start-up delay, since already running (PRI_IDLE), normally does require oscillator start-up delay (RC, INTIO Oscillator modes). However, fixed delay interval TCSD following wake event still required when leaving Sleep Idle modes allow prepare execution. Instruction execution resumes first clock cycle following this delay.
TABLE 3-2:
EXIT DELAY WAKE-UP RESET FROM SLEEP MODE IDLE MODE CLOCK SOURCES)
Clock Source After Wake-up HSPLL OSTS TCSD(2) IOFS TOST(4) TOST trc(4) TCSD(2) TIOBST(5) TOST(5) TOST trc(4) TCSD(2) None TOST(4) TOST trc(4) TCSD(2) TIOBST(5) OSTS IOFS OSTS IOFS OSTS IOFS Exit Delay Clock Ready Status (OSCCON)
Clock Source before Wake-up
Primary Device Clock (PRI_IDLE mode)
INTRC(1) INTOSC(3) HSPLL
T1OSC
INTRC(1)
INTRC(1) INTOSC(2) HSPLL
INTOSC(3)
INTRC(1) INTOSC(2) HSPLL INTRC(1) INTOSC
None (Sleep mode)
Note
this instance, refers specifically INTRC clock source. TCSD (parameter required delay when waking from Sleep Idle modes runs concurrently with other required delays (see Section "Idle Modes"). Includes both INTOSC source postscaler derived frequencies. TOST Oscillator Start-up Timer (parameter 32). Lock-out Timer (parameter F12); also designated TPLL. Execution continues during TIOBST (parameter 39), INTOSC stabilization period.
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RESET
simplified block diagram On-Chip Reset Circuit shown Figure 4-1. PIC18F2480/2580/4480/4580 devices differentiate between various kinds Reset: Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset
RCON Register
Device Reset events tracked through RCON register (Register 4-1). lower five bits register indicate that specific Reset event occurred. most cases, these bits only cleared event must application after event. state these flag bits, taken together, read indicate type Reset that just occurred. This described more detail Section "Reset State Registers". RCON register also control bits setting interrupt priority (IPEN) software control (SBOREN). Interrupt priority discussed Section "Interrupts". covered Section "Brown-out Reset (BOR)".
This section discusses Resets generated MCLR, covers operation various start-up timers. Stack Reset events covered Section 5.1.2.4 "Stack Full Underflow Resets". Resets covered Section 24.2 "Watchdog Timer (WDT)".
FIGURE 4-1:
RESET Instruction Stack Pointer
SIMPLIFIED BLOCK DIAGRAM ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset MCLR MCLRE )_IDLE Sleep Time-out Rise Detect Brown-out Reset BOREN OST/PWRT OSC1 INTRC(1) 1024 Cycles 10-bit Ripple Counter Chip_Reset Pulse
PWRT
65.5
11-bit Ripple Counter
Enable PWRT Enable OST(2) Note This INTRC source from internal oscillator block separate from oscillator CLKI pin. Table time-out situations.
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REGISTER 4-1: RCON: RESET CONTROL REGISTER
R/W-0 IPEN IPEN: Interrupt Priority Enable Enable priority levels interrupts Disable priority levels interrupts (16CXXX Compatibility mode) SBOREN: Software Enable bit(1) BOREN1:BOREN0 enabled disabled BOREN1:BOREN0 disabled read `0'. Unimplemented: Read RESET Instruction Flag RESET instruction executed (set firmware only) RESET instruction executed causing device Reset (must software after Brown-out Reset occurs) Watchdog Time-out Flag power-up, CLRWDT instruction SLEEP instruction time-out occurred Power-down Detection Flag power-up CLRWDT instruction execution SLEEP instruction POR: Power-on Reset Status bit(2) Power-on Reset occurred (set firmware only) Power-on Reset occurred (must software after Power-on Reset occurs) BOR: Brown-out Reset Status Brown-out Reset occurred (set firmware only) Brown-out Reset occurred (must software after Brown-out Reset occurs) Note SBOREN enabled, Reset state `1'; otherwise, `0'. actual Reset value determined type device Reset. notes following this register Section "Reset State Registers" additional information. Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-1(1) SBOREN R/W-1 R/W-0(2) R/W-0
Note recommended that after Power-on Reset been detected that subsequent Power-on Resets detected. Brown-out Reset said have occurred when (assuming that software immediately after POR).
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Master Clear Reset (MCLR)
FIGURE 4-2:
MCLR provides method triggering external Reset device. Reset generated holding low. These devices have noise filter MCLR Reset path which detects ignores small pulses. MCLR driven internal Resets, including WDT. PIC18F2480/2580/4480/4580 devices, MCLR input disabled with MCLRE configuration bit. When MCLR disabled, becomes digital input. Section 10.5 "PORTE, TRISE LATE Registers" more information.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW POWER-UP)
MCLR
PIC18FXXXX
Note
Power-on Reset (POR)
Power-on Reset pulse generated on-chip whenever rises above certain threshold. This allows device start initialized state when adequate operation. take advantage circuitry, MCLR through resistor VDD. This will eliminate external components usually needed create Power-on Reset delay. minimum rise rate specified (parameter D004). slow rise time, Figure 4-2. When device starts normal operation (i.e., exits Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must ensure operation. these conditions met, device must held Reset until operating conditions met. events captured (RCON<1>). state whenever occurs; does change other Reset event. reset hardware event. capture multiple events, user manually resets software following POR.
External Power-on Reset circuit required only power-up slope slow. diode helps discharge capacitor quickly when powers down. recommended make sure that voltage drop across does violate device's electrical specification. will limit current flowing into MCLR from external capacitor event MCLR/VPP breakdown, Electrostatic Discharge (ESD) Electrical Overstress (EOS).
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Brown-out Reset (BOR)
PIC18F2480/2580/4480/4580 devices implement circuit that provides user with number configuration power-saving options. controlled BORV1:BORV0 BOREN1:BOREN0 configuration bits. There total four configurations which summarized Table 4-1. threshold BORV1:BORV0 bits. enabled (any values BOREN1:BOREN0, except `00'), drop below VBOR (parameter D005) greater than TBOR (parameter will reset device. Reset occur falls below VBOR less than TBOR. chip will remain Brown-out Reset until rises above VBOR. Power-up Timer enabled, will invoked after rises above VBOR; then will keep chip Reset additional time delay, TPWRT (parameter 33). drops below VBOR while Power-up Timer running, chip will back into Brown-out Reset Power-up Timer will initialized. Once rises above VBOR, Power-up Timer will execute additional time delay. Power-on Timer (PWRT) independently configured. Enabling Reset does automatically enable PWRT. Placing under software control gives user additional flexibility tailoring application environment without having reprogram device change configuration. also allows user tailor device power consumption software eliminating incremental current that consumes. While current typically very small, have some impact low-power applications. Note: Even when under software control, Reset voltage level still BORV1:BORV0 configuration bits. cannot changed software.
4.4.2
DETECTING
When enabled, always resets event. This makes difficult determine event occurred just reading state alone. more reliable method simultaneously check state both BOR. This assumes that reset software immediately after event. while `1', reliably assumed that event occurred.
4.4.3
DISABLING SLEEP MODE
4.4.1
SOFTWARE ENABLED
When BOREN1:BOREN0 enabled disabled user software. This done with control bit, SBOREN (RCON<6>). Setting SBOREN enables function previously described. Clearing SBOREN disables entirely. SBOREN operates only this mode; otherwise read `0'.
When BOREN1:BOREN0 remains under hardware control operates previously described. Whenever device enters Sleep mode, however, automatically disabled. When device returns other operating mode, automatically re-enabled. This mode allows applications recover from brown-out situations, while actively executing code, when device requires protection most. same time, saves additional power Sleep mode eliminating small incremental current.
TABLE 4-1:
CONFIGURATIONS
Status SBOREN (RCON<6>) Unavailable Available Unavailable Unavailable Operation disabled; must enabled reprogramming configuration bits. enabled software; operation controlled SBOREN. enabled hardware Idle modes, disabled during Sleep mode. enabled hardware; must disabled reprogramming configuration bits.
Configuration BOREN1 BOREN0
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Device Reset Timers
4.5.3 LOCK TIME-OUT
PIC18F2480/2580/4480/4580 devices incorporate three separate on-chip timers that help regulate Power-on Reset process. Their main function ensure that device clock stable before code executed. These timers are: Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Lock Time-out With enabled mode, time-out sequence following Power-on Reset slightly different from other oscillator modes. separate timer used provide fixed time-out that sufficient lock main oscillator frequency. This lock time-out (TPLL) typically follows oscillator start-up time-out.
4.5.4
TIME-OUT SEQUENCE
4.5.1
POWER-UP TIMER (PWRT)
power-up, time-out sequence follows: After pulse cleared, PWRT time-out invoked enabled). Then, activated.
Power-up Timer (PWRT) PIC18F2480/2580/ 4480/4580 devices 11-bit counter which uses INTRC source clock input. This yields approximate time interval 2048 65.6 While PWRT counting, device held Reset. power-up time delay depends INTRC clock will vary from chip-to-chip temperature process variation. parameter details. PWRT enabled clearing PWRTEN configuration bit.
total time-out will vary based oscillator configuration status PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure Figure depict time-out sequences power-up, with Power-up Timer enabled device operating Oscillator mode. Figures through also apply devices operating modes. devices mode with PWRT disabled, other hand, there will time-out all. Since time-outs occur from pulse, MCLR kept long enough, time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This useful testing purposes synchronize more than PIC18FXXXX device operating parallel.
4.5.2
OSCILLATOR START-UP TIMER (OST)
Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after PWRT delay over (parameter 33). This ensures that crystal oscillator resonator started stabilized. time-out invoked only HSPLL modes only Power-on Reset exit from most power managed modes.
TABLE 4-2:
TIME-OUT VARIOUS SITUATIONS
Power-up(2) Brown-out PWRTEN ms(1) 1024 TOSC ms(1) ms(1) ms(1) ms(2) ms(1) 1024 TOSC PWRTEN 1024 TOSC ms(2) 1024 TOSC Exit from Power Managed Mode 1024 TOSC ms(2) 1024 TOSC
Oscillator Configuration HSPLL ECIO RCIO INTIO1, INTIO2 Note
(65.5 nominal Power-up Timer (PWRT) delay. nominal time required lock.
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FIGURE 4-3:
MCLR INTERNAL TPWRT PWRT TIME-OUT
TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD, RISE TPWRT)
TOST
TIME-OUT
INTERNAL RESET
FIGURE 4-4:
TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD): CASE
MCLR INTERNAL TPWRT PWRT TIME-OUT
TOST
TIME-OUT
INTERNAL RESET
FIGURE 4-5:
TIME-OUT SEQUENCE POWER-UP (MCLR TIED VDD): CASE
MCLR INTERNAL TPWRT PWRT TIME-OUT
TOST
TIME-OUT
INTERNAL RESET
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FIGURE 4-6: SLOW RISE TIME (MCLR TIED VDD, RISE TPWRT)
MCLR INTERNAL TPWRT PWRT TIME-OUT TOST TIME-OUT INTERNAL RESET
FIGURE 4-7:
TIME-OUT SEQUENCE W/PLL ENABLED (MCLR TIED VDD)
MCLR INTERNAL TPWRT PWRT TIME-OUT
TOST TPLL
TIME-OUT
TIME-OUT INTERNAL RESET
Note:
TOST 1024 clock cycles. TPLL max. First three stages PWRT timer.
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Reset State Registers
Most registers unaffected Reset. Their status unknown unchanged other Resets. other registers forced "Reset state" depending type Reset that occurred. Most registers affected wake-up, since this viewed resumption normal operation. Status bits from RCON register, BOR, cleared differently different Reset situations, indicated Table 4-3. These bits used software determine nature Reset. Table describes Reset states Special Function Registers. These categorized Power-on Brown-out Resets, Master Clear Resets wake-ups.
TABLE 4-3:
STATUS BITS, THEIR SIGNIFICANCE INITIALIZATION CONDITION RCON REGISTER
Program Counter 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h RCON Register SBOREN u(2) u(2) u(2) u(2) u(2) u(2) u(2)
STKPTR Register STKFUL STKUNF
Condition Power-on Reset RESET Instruction Brown-out MCLR during Power Managed modes MCLR during Power Managed Idle modes Sleep mode Time-out during Full Power Power Managed modes MCLR during Full Power Execution Stack Full Reset (STVREN Stack Underflow Reset (STVREN Stack Underflow Error (not actual Reset, STVREN Time-out during Power Managed Idle Sleep modes Interrupt Exit from Power Managed modes
u(2) u(2) u(2)
Legend: unchanged Note When wake-up interrupt GIEH GIEL bits set, loaded with interrupt vector (008h 0018h). Reset state unchanged other Resets when software enabled (BOREN1:BOREN0 configuration bits SBOREN Otherwise, Reset state `0'.
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TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS
Applicable Devices Power-on Reset, Brown-out Reset 0000 0000 0000 0000 0000 00-0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 -1-1 11-0 0-00 0000 xxxx xxxx xxxx xxxx 0000 xxxx xxxx MCLR Resets, Reset, RESET Instruction, Stack Resets 0000 0000 0000 0000 0000 uu-0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 -1-1 11-0 0-00 0000 uuuu uuuu uuuu uuuu 0000 uuuu uuuu Wake-up Interrupt uuuu(3) uuuu uuuu(3) uuuu uuuu(3) uu-u uuuu(3) uuuu uuuu uuuu 2(2) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1) uuuu -u-u(1) uu-u u-uu(1) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TOSU TOSH TOSL STKPTR PCLATU PCLATH TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L
2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled, depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'. This register reads `0's until ECANtechnology Mode Mode
2004 Microchip Technology Inc.
DS39637A-page
PIC18F2480/2580/4480/4580
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset 0000 0000 xxxx xxxx xxxx 0000 0000 xxxx xxxx 1111 1111 0100 q000 0-00 0101 0q-1 11q0 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0qqq 0-00 0000 MCLR Resets, Reset, RESET Instruction, Stack Resets 0000 0000 uuuu uuuu uuuu 0000 0000 uuuu uuuu 1111 1111 0100 00q0 0-00 0101 0q-q qquu uuuu uuuu uuuu uuuu u0uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0qqq 0-00 0000 Wake-up Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuqu 0-uu uuuu uq-u qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu
INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON HLVDCON WDTCON RCON
2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580
TMR1H TMR1L T1CON TMR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled, depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'. This register reads `0's until ECANtechnology Mode Mode
DS39637A-page
2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx 0000 0000 01-0 0-00 0000 0000 0000 0000 0000 0000 0000 0111 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x 0000 0000 0000 0000 0000 0000 xx-0 x000 1111 1111 0000 0000 0000 0000 11-1 1111 11100-0 0000 000MCLR Resets, Reset, RESET Instruction, Stack Resets uuuu uuuu uuuu uuuu 0000 uuuu uuuu uuuu uuuu 0000 0000 01-0 0-00 0000 0000 0000 0000 0000 0000 0000 0111 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x 0000 0000 0000 0000 0000 0000 uu-0 u000 1111 1111 0000 0000 0000 0000 11-1 1111 11100-0 0000 000Wake-up Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uu-0 u000 uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuuu-u uuuu(1) uuu-(1)
CCPR1H CCPR1L CCP1CON ECCPR1H ECCPR1L ECCP1CON BAUDCON ECCP1DEL ECCP1AS CVRCON CMCON TMR3H TMR3L T3CON SPBRGH SPBRG RCREG TXREG TXSTA RCSTA EEADR EEDATA EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2
2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled, depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'. This register reads `0's until ECANtechnology Mode Mode
2004 Microchip Technology Inc.
DS39637A-page
PIC18F2480/2580/4480/4580
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset 00-0 0000 0001111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 0000 0000 -111 1111 1111 1111 1111 1111 1111 1111 1111(5) -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx(5) x000 xxxx xxxx xxxx xxxx xxxx xxxx xx0x 0000(5) 0001 0000 0000 0000 0000 0000 0000 0000 -00- -000 0000 0000 0000 0000 MCLR Resets, Reset, RESET Instruction, Stack Resets 00-0 0000 0001111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 0000 0000 -111 1111 1111 1111 1111 1111 1111 1111 1111(5) -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) x000 uuuu uuuu uuuu uuuu uuuu uuuu uu0u 0000(5) 0001 0000 0000 0000 0000 0000 0000 0000 -00- -000 0000 0000 0000 0000 Wake-up Interrupt uu-u uuuu uuuuuuu uuuu -uuu uuuu uuuu uuuu(1) -uuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(5) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uu- -uuu uuuu uuuu uuuu uuuu
PIE2 IPR1 PIR1 PIE1 OSCTUNE TRISE TRISD TRISC TRISB TRISA LATE LATD LATC LATB LATA(5) PORTE PORTD PORTC PORTB PORTA
2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580
ECANCON TXERRCNT RXERRCNT COMSTAT CIOCON BRGCON3 BRGCON2 BRGCON1
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled, depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'. This register reads `0's until ECANtechnology Mode Mode
DS39637A-page
2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset 1000 000100- 000xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 000- 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 000- 0000 xxxx xxxx xxxx xxxx MCLR Resets, Reset, RESET Instruction, Stack Resets 1000 000100- 000uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 000- 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 000- 0000 uuuu uuuu uuuu uuuu Wake-up Interrupt uuuu uuuuuu- uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuu- uuuu uuuu uuuu uuuu uuuu
CANCON CANSTAT RXB0D7 RXB0D6 RXB0D5 RXB0D4 RXB0D3 RXB0D2 RXB0D1 RXB0D0 RXB0DLC RXB0EIDL RXB0EIDH RXB0SIDL RXB0SIDH RXB0CON RXB1D7 RXB1D6 RXB1D5 RXB1D4 RXB1D3 RXB1D2 RXB1D1 RXB1D0 RXB1DLC RXB1EIDL RXB1EIDH RXB1SIDL RXB1SIDH RXB1CON TXB0D7 TXB0D6
2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled, depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'. This register reads `0's until ECANtechnology Mode Mode
2004 Microchip Technology Inc.
DS39637A-page
PIC18F2480/2580/4480/4580
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx 0000 0-00 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx 0000 0-00 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx MCLR Resets, Reset, RESET Instruction, Stack Resets uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu 0000 0-00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu 0000 0-00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Wake-up Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuu- u-uu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uu-u -uuu uuuu uuuu u-uu 0uuu uuuu 0uuu uuuu 0uuu uuuu 0uuu uuuu 0uuu uuuu 0uuu uuuu
TXB0D5 TXB0D4 TXB0D3 TXB0D2 TXB0D1 TXB0D0 TXB0DLC TXB0EIDL TXB0EIDH TXB0SIDL TXB0SIDH TXB0CON TXB1D7 TXB1D6 TXB1D5 TXB1D4 TXB1D3 TXB1D2 TXB1D1 TXB1D0 TXB1DLC TXB1EIDL TXB1EIDH TXB1SIDL TXB1SIDH TXB1CON TXB2D7 TXB2D6 TXB2D5 TXB2D4 TXB2D3 TXB2D2
2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled, depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'. This register reads `0's until ECANtechnology Mode Mode
DS39637A-page
2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxx- x-xx 0000 0-00 xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx MCLR Resets, Reset, RESET Instruction, Stack Resets uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuu- u-uu 0000 0-00 uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu Wake-up Interrupt 0uuu uuuu 0uuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuu- u-uu uuuu u-uu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu
TXB2D1 TXB2D0 TXB2DLC TXB2EIDL TXB2EIDH TXB2SIDL TXB2SIDH TXB2CON RXM1EIDL RXM1EIDH RXM1SIDL RXM1SIDH RXM0EIDL RXM0EIDH RXM0SIDL RXM0SIDH RXF5EIDL RXF5EIDH RXF5SIDL RXF5SIDH RXF4EIDL RXF4EIDH RXF4SIDL RXF4SIDH RXF3EIDL RXF3EIDH RXF3SIDL RXF3SIDH RXF2EIDL RXF2EIDH RXF2SIDL RXF2SIDH
2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled, depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'. This register reads `0's until ECANtechnology Mode Mode
2004 Microchip Technology Inc.
DS39637A-page
PIC18F2480/2580/4480/4580
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx x-xx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx MCLR Resets, Reset, RESET Instruction, Stack Resets uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu u-uu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu Wake-up Interrupt uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu
RXF1EIDL RXF1EIDH RXF1SIDL RXF1SIDH RXF0EIDL RXF0EIDH RXF0SIDL RXF0SIDH B5D7(6) B5D6(6) B5D5(6) B5D4
2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580 2480 2580 4480 4580
B5D3(6) B5D2(6) B5D1(6) B5D0(6) B5DLC(6) B5EIDL
B5EIDH(6) B5SIDL(6) B5SIDH(6) B5CON(6) B4D7(6) B4D6
B4D5(6) B4D4(6) B4D3(6) B4D2(6) B4D1(6) B4D0
B4DLC(6) B4EIDL(6)
Legend: unchanged, unknown, unimplemented bit, read `0', value depends condition. Shaded cells indicate conditions apply designated device. Note more bits INTCONx PIRx registers will affected cause wake-up). When wake-up interrupt GIEL GIEH set, loaded with interrupt vector (0008h 0018h). When wake-up interrupt GIEL GIEH set, TOSU, TOSH TOSL updated with current value STKPTR modified point next location hardware stack. Table Reset value specific condition. Bits PORTA, LATA TRISA enabled, depending oscillator mode selected. When enabled PORTA pins, they disabled read `0'. This register reads `0's until ECANtechnology Mode Mode
DS39637A-page
2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
TABLE 4-4:
Register
INITIALIZATION CONDITIONS REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx x
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