Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller
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MSC1210
Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller Flash Memory
ANALOG Peripheral Features Pins Additional 32-Bit Accumulator Three 16-Bit Timer/Counters System Timers Programmable Watchdog Timer Full-Duplex Dual USARTs Master/Slave 16-Bit Power Management Control Idle Mode Current Stop Mode Current Programmable Brownout Reset Programmable Voltage Detect Interrupt Sources Hardware Breakpoints
Bits Missing Codes Bits Effective Resolution 10Hz
Noise: 75nV From Precision On-Chip Voltage Reference Accuracy: 0.2% Drift: 5ppm/°C Differential/Single-Ended Channels On-Chip Offset/Gain Calibration Offset Drift: 0.02ppm/°C Gain Drift: 0.5ppm/°C On-Chip Temperature Sensor Burnout Sensor Detection Single-Cycle Conversion Selectable Buffer Input
GENERAL
DIGITAL Microcontroller Core 8051-Compatible High-Speed Core Clocks Instruction Cycle 33MHz Single Instruction 121ns Dual Data Pointer Memory 32kB Flash Memory Flash Memory Partitioning Endurance Erase/Write Cycles, Year Data Retention In-System Serially Programmable External Program/Data Memory (64kB) 1,280 Bytes Data SRAM Flash Memory Security Boot Programmable Wait State Control
Pin-Compatible with MSC1211/12/13/14 Package: TQFP-64 Power: Industrial Temperature Range: -40°C +85°C Power Supply: 2.7V 5.25V
APPLICATIONS
Industrial Process Control Instrumentation Liquid/Gas Chromatography Blood Analysis Smart Transmitters Portable Instruments Weigh Scales Pressure Transducers Intelligent Sensors Portable Applications Systems
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2002-2004, Texas Instruments Incorporated
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PACKAGE/ORDERING INFORMATION(1)
PRODUCT MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5 FLASH MEMORY PACKAGE-LEAD TQFP-64 TQFP-64 TQFP-64 TQFP-64 PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C PACKAGE MARKING MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5
most current package ordering information, Package Option Addendum this datasheet, refer site www.ti.com.
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
MSC1210Yx Analog Inputs Momentary Input current Input voltage Power Supply DVDD DGND AVDD AGND AGND DGND VREF AGND Digital input voltage DGND Digital output voltage DGND Maximum junction temperature Operating temperature range Storage temperature range Lead temperature (soldering, 10s) Package power dissipation Output current, pins Output short-circuit High Thermal Resistance Digital Outputs Output current source/sink current Power maximum Continuous Junction ambient (qJA) Junction case (qJC) (1s) -0.3 -0.3 -0.3 +0.3 -0.3 AVDD -0.3 DVDD -0.3 DVDD +150 +235 TAMBIENT)/qJA 62.9 78.2 13.8 °C/W °C/W °C/W Continuous AGND AVDD UNITS
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. Exposure absolute maximum conditions extended periods affect device reliability.
MSC1210YX FAMILY FEATURES(1) Flash Program Memory (Bytes) Flash Data Memory (Bytes) Internal Scratchpad (Bytes) Internal MOVX (Bytes) Externally Accessible Memory (Bytes) MSC1210Y2(2) 1024 Program, Data MSC1210Y3(2) 1024 Program, Data MSC1210Y4(2) 1024 Program, Data MSC1210Y5(2) 1024 Program, Data
peripheral features same devices; flash memory size only difference. last digit part number represents onboard flash size (2N)kBytes.
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ELECTRICAL CHARACTERISTICS: AVDD
specifications from TMIN TMAX, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +2.5V, unless otherwise noted. MSC1210Yx PARAMETER Analog Input (AIN0-AIN7, AINCOM) Buffer Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Fast Settling Filter Bandwidth Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources Offset Offset Range Offset Monotonicity Offset Gain Error Offset Gain Error Drift System Performance Resolution ENOB Output Noise Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection 60Hz, fDATA 10Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz Normal-Mode Rejection Power-Supply Rejection
CONDITIONS
UNITS
AGND AGND 50mV
AVDD AVDD ±VREF/PGA 7/PGA(5) 0.469 fDATA 0.318 fDATA 0.262 fDATA
Buffer (In+) (In-) Buffer Buffer -3dB -3dB -3dB User-Selectable Gain Range Buffer Modulator OFF, +25°C Buffer
±1.5
Bits Range ppm/°C
Typical Characteristics Typical Characteristics Sinc3 Filter, Decimation Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration 0.02 0.002 ±0.0015
Bits Bits
Bits
FS/°C ppm/°C
fSIG 50Hz, fDATA 50Hz fSIG 60Hz, fDATA 60Hz -20log(VOUT/VDD)(3)
Calibration minimize these errors. gain calibration cannot have more than AVDD -1.5V with Buffer calibrate gain, turn Buffer OFF. VOUT change digital result. switched capacitor SAMP clock frequency (see Figure 13). input impedance same that (that 7M/64).
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ELECTRICAL CHARACTERISTICS: AVDD (continued)
specifications from TMIN TMAX, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +2.5V, unless otherwise noted. MSC1210Yx PARAMETER Voltage Reference Input Reference Input Range VREF VREF Common-Mode Rejection Input Current(4) On-Chip Voltage Reference VREFH +25°C, ACLK 1MHz Output Voltage Power-Supply Rejection Ratio Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Output Impedance Startup Time from Power Temperature Sensor Voltage Temperature Sensor Coefficient Analog Power-Supply Requirements Analog Power-Supply Voltage Analog Current (IADC IVREF) Analog Power-Supply Current AVDD PDADC ALVDIS Buffer Current (IADC) 128, Buffer Buffer 128, Buffer VREF Supply Current (IVREF)
CONDITIONS
UNITS
IN+, VREF (REF IN+) (REF IN-) 60Hz, fDATA 60Hz VREF 2.5V
AGND
AVDD(2) AVDD
2.495
1.25
2.505
VREFH +25°C, ACLK 1MHz
Sink Source
Indefinite ppm/°C µV/°C
Sourcing 100µA CREF 0.1µF +25°C
4.75
5.25
VDAC
Calibration minimize these errors. gain calibration cannot have more than AVDD -1.5V with Buffer calibrate gain, turn Buffer OFF. change digital result. switched capacitor SAMP clock frequency (see Figure 13). input impedance same that (that 7M/64).
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specifications from TMIN TMAX, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +1.25V, unless otherwise noted. MSC1210Yx PARAMETER ANALOG INPUT (AIN0-AIN7, AINCOM) Buffer Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Fast Settling Filter Bandwidth Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET Offset Range Offset Monotonicity Offset Gain Error Offset Gain Error Drift SYSTEM PERFORMANCE Resolution ENOB Output Noise Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection 60Hz, fDATA 10Hz 50Hz, fDATA 50Hz 60Hz, fDATA 60Hz Normal-Mode Rejection Power-Supply Rejection
ELECTRICAL CHARACTERISTICS: AVDD
CONDITIONS
UNITS
AGND AGND 50mV
AVDD AVDD ±VREF/PGA 7/PGA(5) 0.469 fDATA 0.318 fDATA 0.262 fDATA
Buffer (In+) (In-) Buffer Buffer -3dB -3dB -3dB User-Selectable Gain Range
Modulator OFF, +25°C Sensor Input Open Circuit
±1.5
Bits Range ppm/°C
Typical Characteristics Sinc3 Filter Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration )(3) 0.02 0.005 ±0.0015
Bits Bits
Bits
FS/°C ppm/°C
fSIG 50Hz, fDATA 50Hz fSIG 60Hz, fDATA 60Hz -20log(VOUT/VDD
Calibration minimize these errors. gain calibration cannot have more than AVDD -1.5V with Buffer calibrate gain, turn Buffer OFF. VOUT change digital result. switched capacitor fSAMP clock frequency (see Figure 13). input impedance same that (that 7M/64).
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specifications from TMIN TMAX, DVDD +2.7V 5.25V, fMOD 15.625kHz, Buffer fDATA 10Hz, Bipolar, VREF (REF IN+) (REF IN-) +1.25V, unless otherwise noted. MSC1210Yx PARAMETER VOLTAGE REFERENCE INPUT Reference Input Range VREF VREF Common-Mode Rejection Input Current(4) ON-CHIP VOLTAGE REFERENCE Output Voltage Power-Supply Rejection Ratio Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Output Impedance Startup Time from Power Temperature Sensor Voltage Temperature Sensor Coefficient ANALOG POWER-SUPPLY REQUIREMENTS Analog Power-Supply Voltage Analog Current (IADC IVREF) Analog Power-Supply Current AVDD PDADC ALVDIS Buffer Current (IADC) 128, Buffer Buffer 128, Buffer VREF Supply Current (IVREF)
ELECTRICAL CHARACTERISTICS: AVDD (continued)
CONDITIONS
UNITS
IN+, VREF (REF IN+) (REF IN-) 60Hz, fDATA 60Hz VREF 1.25V
AGND 1.25
AVDD(2) AVDD
VREFH +25°C, ACLK 1MHz
1.245
1.25
1.255
Sink Source
Indefinite ppm/°C µV/°C
Sourcing 100µA CREF 0.1µF +25°C
Calibration minimize these errors. gain calibration cannot have more than AVDD -1.5V with Buffer calibrate gain, turn Buffer OFF. VOUT change digital result. switched capacitor SAMP clock frequency (see Figure 13). input impedance same that (that 7M/64).
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DIGITAL CHARACTERISTICS: DVDD 2.7V 5.25V
specifications from TMIN TMAX, fOSC 1MHz, unless otherwise specified. MSC1210Yx PARAMETER DIGITAL POWER-SUPPLY REQUIREMENTS Digital Power-Supply Voltage DVDD Normal Mode, fOSC 1MHz Normal Mode, fOSC 8MHz Crystal Operation Stop Mode(1) Digital Power-Supply Current DVDD Normal Mode, fOSC 1MHz Normal Mode, fOSC 8MHz Crystal Operation Stop Mode(1) DIGITAL INPUT/OUTPUT (CMOS) Logic Level Hysteresis Ports 0-3, Input Leakage Current, Input Mode Pins Input Leakage Current VOL, ALE, PSEN, Ports 0-3, Output Modes 30mA 30mA DVDD DGND DVDD DVDD Flash Programming Mode Only DVDD DVDD (except pin) (except pin) DVDD DGND DVDD DVDD 4.75 5.25 CONDITIONS UNITS
VOH, ALE, PSEN, Ports 0-3, Strong Drive Output Ports 0-3, Pull-Up Resistors Pins ALE, PSEN, Pull-Up Resistors RST, Pull-Down Resistor
Digital Brownout Detect disabled (HCR1.2 Voltage Detect disabled (LVDCON.3 =1). Ports configured input CMOS output.
FLASH MEMORY CHARACTERISTICS: DVDD 2.7V 5.25V
MSC1210Yx PARAMETER Flash Memory Endurance Flash Memory Data Retention Mass Page Erase Time Flash Memory Write Time Flash Programming Current with FTCON with FTCON DVDD 3.0V DVDD 5.0V CONDITIONS 100,000 1,000,000 UNITS cycles years
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ELECTRICAL CHARACTERISTICS(1)(2): DVDD 2.7V 5.25V
2.7V 3.6V SYMBOL FIGURE PARAMETER External Crystal Frequency (fOSC) External Clock Frequency (fOSC) External Ceramic Resonator Frequency (fOSC) Pulse Width Address Valid Address Hold After Valid Instruction PSEN PSEN Pulse Width PSEN Valid Instruction Input Instruction Hold After PSEN Input Instruction Float After PSEN Address Valid Instruction PSEN Address Float Pulse Width (tMCS 0)(5) Pulse Width (tMCS 0)(5) Pulse Width (tMCS 0)(5) Pulse Width (tMCS 0)(5) Valid Data (tMCS 0)(5) Valid Data (tMCS 0)(5) Data Hold After Read Data Float After Read (tMCS 0)(5) Data Float After Read (tMCS 0)(5) Valid Data (tMCS 0)(5) Valid Data (tMCS 0)(5) Address Valid Data (tMCS 0)(5) Address Valid Data (tMCS 0)(5) (tMCS 0)(5) (tMCS 0)(5) Address (tMCS 0)(5) Address (tMCS 0)(5) Data Valid Transition Data Hold After Address Float HIGH HIGH (tMCS 0)(5) HIGH HIGH (tMCS 0)(5) HIGH Time(3) Time(3) Rise Time(3) Fall Time(3) tCLK 0.5tCLK tCLK tCLK 2tCLK tCLK -0.5tCLK tCLK tCLK 2tCLK 2.5tCLK tCLK tMCS 3tCLK
1.5tCLK tMCS
4.75V 5.25V 1.5tCLK 0.5tCLK 0.5tCLK UNITS 2.5tCLK 0.5tCLK 2tCLK 2tCLK tCLK 3tCLK 2tCLK tMCS 2tCLK tMCS 2tCLK tMCS tCLK 2tCLK 2.5tCLK tCLK tMCS 3tCLK
1.5tCLK tMCS
1.5tCLK 0.5tCLK 0.5tCLK
System Clock 1/tCLK(4)
Program Memory tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH External Clock tHIGH tLOW
2.5tCLK 0.5tCLK 2tCLK 2tCLK tCLK 3tCLK 2tCLK tMCS 2tCLK tMCS 2tCLK tMCS
0.5tCLK tCLK
0.5tCLK tCLK tCLK 2tCLK tCLK tCLK
0.5tCLK tCLK
-0.5tCLK tCLK
Parameters valid over operating temperature range, unless otherwise specified. Load capacitance Port ALE, PSEN 100pF; load capacitance other outputs 80pF. These values characterized 100% production tested. tCLK 1/fosc oscillator clock period. tMCS time period related Stretch MOVX selection. following table shows value tMCS each stretch selection: MOVX DURATION Machine Cycles Machine Cycles (default) tMCS 4tCLK 8tCLK 12tCLK 16tCLK 20tCLK 24tCLK 28tCLK
Machine Cycles Machine Cycles Machine Cycles Machine Cycles Machine Cycles Machine Cycles
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EXPLANATION SYMBOLS
Each Timing Symbol five characters. first character always time). other characters, depending their positions, indicate name signal logical status that signal. designators are: Signal AAddress CClock DInput Data HLogic Level HIGH IInstruction (program memory contents) LLogic Level LOW, PPSEN QOutput Data tTime VValid Signal Longer Valid Logic Level ZFloat Examples: tAVLL Time address valid LOW. tLLPL Time PSEN LOW.
tLHLL tAVLL tLLPL tLLIV PSEN LLAX PORT A0-A7 tPLAZ tPLIV tPXIZ tPXIX INSTR A0-A7 PLPH
tAVIV PORT A8-A15 A8-A15
Figure External Program Memory Read Cycle
tWHLH PSEN
tLLDV tLLWL tRLRH
tAVLL LLAX tRLAZ PORT A0-A7 from AVWL tAVDV PORT P2.0-P2.7 A8-A15 from A8-A15 from tRLDV RHDX DATA A0-A7from INSTR tRHDZ
Figure External Data Memory Read Cycle
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tWHLH PSEN tLLWL tWLWH
tAVLL tLLAX
tWHQX
PORT
A0-A7 from tAVWL
DATA
A0-A7 from
INSTR
PORT
P2.0-P2.7or A8-A15 from
8-A15 from
Figure External Data Memory Write Cycle
HIGH VIH1 0.8V VIH1 0.8V tLOW VIH1 0.8V
VIH1 0.8V
Figure External Clock Drive
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RESET POWER-ON TIMING
tRRD PSEN tRRD NOTE: PSEN internally pulled with during high. tRFD tRFD
Figure Reset Timing
tRRD PSEN tRRD NOTE: PSEN internally pulled with during high. tRFD
Figure Parallel Flash Programming Power-On Timing ignored)
tRRD PSEN NOTE: PSEN internally pulled with during high.
Figure Serial Flash Programming Power-On Timing ignored)
SYMBOL tRRD tRFD width
PARAMETER
2tOSC tOSC (217 512)tOSC
(217 512)tOSC
UNIT
rise PSEN internal pull HIGH falling PSEN start Input signal falling setup time falling input signal hold time
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ASSIGNMENTS
PACKAGE (TOP VIEW)
P1.5/INT3/MOSI
P1.6/INT4/MISO
P1.7/INT5/SCK
P1.4/INT2/SS
P1.2/RxD1
P1.1/T2EX
P1.3/TxD1
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
XOUT P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1/TONE/PWM P3.4/T0 P3.5/T1 P3.6/WR
P0.6/AD6 P0.7/AD7 PSEN/OSCCLK/MODCLK P2.7/A15 DGND
MSC1210
P0.5/AD5 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A09 P2.0/A08
P3.7/RD DGND
AGND AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6/EXTD AIN7/EXTA AINCOM AGND
P1.0/T2
DGND
DVDD
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DESCRIPTIONS
3-10 NAME XOUT P3.0-P3.7 DESCRIPTION crystal oscillator XOUT supports parallel resonant fundamental frequency crystals ceramic resonators. XOUT serves output crystal amplifier. crystal oscillator supports parallel resonant fundamental frequency crystals ceramic resonators. also input there external clock source instead crystal. Port bidirectional port. alternate functions Port listed below. PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 34-40, DVDD DGND AGND AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6, EXTD AIN7, EXTA AINCOM AVDD P2.0-P2.7 Digital power supply Digital ground HIGH reset input tOSC periods resets device. connection Analog ground Analog input channel Analog input channel Analog input channel Analog input channel Analog input channel Analog input channel Analog input channel digital low-voltage detect input, generates DLVD interrupt Analog input channel analog low-voltage detect input, generates ALVD interrupt Analog common single-ended inputs analog input differential inputs Analog power supply. AVDD must rise above 2.0V disable Analog Brownout Reset function. Voltage reference negative input (must tied AGND internal VREF) Voltage reference positive input Voltage reference output (tie internal VREF use) Port bidirectional port. alternate functions Port listed below. Refer P2DDR, B1h-B2h. PORT P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 Alternate Name Alternate Address Address Address Address Address Address Address Address Alternate Name(s) RxD0 TxD0 INT0 INT1/TONE/PWM Alternate Serial port input Serial port output External interrupt External interrupt 1/TONE/PWM output Timer external input Timer external input External data memory write strobe External data memory read strobe
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DESCRIPTIONS (continued)
NAME PSEN, OSCCLK, MODCLK DESCRIPTION Program store enable. Connected optional external memory chip enable. PSEN provides active pulse. programming mode, PSEN used input along with define serial parallel programming mode. PSEN held HIGH parallel programming mode serial programming. This also selected (when using external memory) output oscillator clock, modulator clock, HIGH, LOW. Care should taken that loading this does inadvertently cause device enter programming mode. PSEN Program Mode Selection Normal operation (User Application mode) Parallel programming Serial programming Reserved
Address Latch Enable: Used latching byte address during access external memory. emitted constant rate oscillator frequency, used external timing clocking. pulse skipped during each access external data memory. programming mode, used input along with PSEN define serial parallel programming mode. held HIGH parallel programming mode parallel programming. This also selected (when using external memory) output HIGH LOW. Care should taken that loading this does inadvertently cause device enter programming mode. External Access Enable: must externally held RESET enable device fetch code from external program memory locations starting with 0000h. internal pull-up this pin. Port bidirectional port. alternate functions Port listed below. Refer P1DDR, AEh-AFh. PORT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Alternate Name Alternate Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
49-54
P0.0-P0.7
59-64
P1.0-P1.7
Port bidirectional port. alternate functions Port listed below. Refer P1DDR, AEh-AFh. PORT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Alternate Name(s) T2EX RxD1 TxD1 INT2/SS INT3/MOSI INT4/MISO INT5/SCK Alternate input external input Serial port input Serial port output External Interrupt Slave Select External Interrupt Master Out-Slave External Interrupt Master In-Slave External Interrupt Serial Clock
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TYPICAL CHARACTERISTICS
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA1 PGA8 PGA32 PGA64 PGA128 PGA1 PGA2 PGA4 PGA8
EFFECTIVE NUMBER BITS DATA RATE
ENOB (rms)
PGA16 PGA32 PGA64 PGA128
ENOB (rms)
Sinc3 Filter, Buffer Data Rate (SPS) 1000
Sinc3 Filter, Buffer
1000 Decimation Ratio fMOD fDATA 1500 2000
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA1 PGA2 PGA4 PGA8
ENOB (rms)
PGA1
ENOB (rms)
PGA16 PGA32 PGA64 PGA128
1000 Decimation Ratio fDATA 1500 2000 Sinc3 Filter, Buffer
PGA32 PGA16 PGA64 PGA128
1000 Decimation Ratio fDATA 1500 2000 AVDD Sinc3 Filter, VREF 1.25V, Buffer
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
EFFECTIVE NUMBER BITS DECIMATION RATIO
PGA2 PGA4 PGA8
ENOB (rms)
PGA1
ENOB (rms)
PGA1
PGA32
PGA16
PGA64
PGA16
PGA32
PGA128
PGA64
PGA128
AVDD Sinc3 Filter, VREF 1.25V, Buffer 1000 Decimation Ratio fMOD fDATA 1500 2000
Sinc2 Filter
1000 Decimation Ratio 1500 fMOD fDATA 2000
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TYPICAL CHARACTERISTICS (Continued)
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. FAST SETTLING FILTER EFFECTIVE NUMBER BITS DECIMATION RATIO 1000 Decimation Ratio 1500 fMOD fDATA 2000 Data Rate (SPS) 100k Fast Settling Filter fMOD 62.5kHz ENOB (rms) ENOB (rms) fMOD 31.25kHz fMOD 15.6kHz fMOD 203kHz fMOD 110kHz EFFECTIVE NUMBER BITS fMOD (set with ACLK)
EFFECTIVE NUMBER BITS fMOD (set with ACLK) WITH FIXED DECIMATION 2020 Noise (rms, -2.5 -1.5
NOISE INPUT SIGNAL
ENOB (rms)
Data Rate (SPS) 100k
-0.5
OFFSET TEMPERATURE
PGA1 PGA16
GAIN TEMPERATURE 1.00010 1.00006 Gain (Normalized) 1.00002 0.99998 0.99994 0.99990 0.99986
Offset (ppm -100 -150 -200
PGA128 PGA64
Temperature (°C)
Temperature (°C)
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TYPICAL CHARACTERISTICS (Continued)
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
INTEGRAL NON-LINEARITY INPUT SIGNAL (ppm -2.5 -1.5 -0.5 (ppm
INTEGRAL NON-LINEARITY INPUT SIGNAL VREF AVDD, Buffer
-VREF
+VREF
INTEGRAL NONLINEARITY VREF (ppm AVDD AVDD VREF VREF Buffer (ppm
ERROR
Setting
MAXIMUM ANALOG SUPPLY CURRENT Analog Supply Current (mA) Analog Supply Voltage 128, Brownout Detect VDACs FFFFH VDACs AVDD +85°C +25°C IADC -40°C
CURRENT AVDD Buffer Buffer
AVDD Buffer Buffer
Setting
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TYPICAL CHARACTERISTICS (Continued)
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified. HISTOGRAM OUTPUT DATA 4500 4000 Number Occurrences 3500 3000 VREFOUT 2500 2000 1500 1000 -1.5 -0.5 2.510 2.508 2.506 2.504 2.502 2.500 2.498 2.496 2.494 2.492 2.490 VREFOUT Current Load (mA) VREFOUT LOAD CURRENT
OFFSET DAC: OFFSET TEMPERATURE Offset (ppm FSR) Normalized Gain 0.99994 Temperature (°C) 1.00004 1.00002 0.99998 0.99996 1.00006
OFFSET DAC: GAIN TEMPERATURE
Temperature (°C)
DIGITAL CURRENT FREQUENCY Periph Periph Periph IDLE Periph Periph Periph IDLE Digital Current (µA) 1000
DIGITAL STOP CURRENT FREQUENCY with CLOCK
Supply Current (mA)
Clock Frequency (MHz)
Clock Frequency (MHz)
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TYPICAL CHARACTERISTICS (Continued)
AVDD +5V, DVDD +5V, fOSC 8MHz, fDATA 10Hz, Buffer VREF (REF IN+) (REF IN-) +2.5V, unless otherwise specified.
DIGITAL SUPPLY CURRENT SUPPLY VOLTAGE Digital Supply Current (mA) +85°C -40°C Normalized Gain +25°C
NORMALIZED GAIN
Buffer
Supply Voltage
Setting
CMOS DIGITAL OUTPUT Output Voltage Output Current (mA) Output Output
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DESCRIPTION
MSC1210Yx completely integrated family mixed-signal devices incorporating high-resolution delta-sigma ADC, 8-channel multiplexer, burnout current sources, selectable buffered input, offset (Digital-to-Analog Converter), Programmable Gain Amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, Data SRAM, shown Figure On-chip peripherals include additional 32-bit accumulator, SPI-compatible serial port, dual USARTs, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, 16-bit PWM, system timers, brownout reset, three timer/counters. device accepts low-level differential single-ended signals directly from transducer. provides bits resolution bits no-missing-code performance using Sinc3 filter with programmable sample rate. also selectable filter that allows high-resolution single-cycle conversion.
microcontroller core 8051 instruction compatible. microcontroller core optimized 8051 core that executes three times faster than standard 8051 core, given same clock source. That makes possible device lower external clock frequency achieve same performance lower power than standard 8051 core. MSC1210Yx allows user uniquely configure Flash SRAM memory maps meet needs their application. Flash programmable down 2.7V using both serial parallel programming methods. Flash endurance million Erase/Write cycles. addition, 1280 bytes incorporated on-chip. part separate analog digital supplies, which independently powered from 2.7V +5.5V. operation, power dissipation part typically less than 4mW. MSC1210Yx packaged TQFP-64 package. MSC1210Yx designed high-resolution measurement applications smart transmitters, industrial process control, weigh scales, chromatography, portable instrumentation.
AVDD
AGND
DGND
+AVDD Timers/ Counters AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM FLASH 1.2K SRAM PORT2 8051 PORT3 Clock Generator AGND XOUT NOTE must tied AGND when using internal VREF. ADDR USART1 BUFFER Modulator Digital Filter PORT1 PORT0 Temperature Sensor Offset Alternate Functions ADDR DATA SPI/EXT USART2 PSEN
Figure Block Diagram
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instr_cycle
cpu_cycle
Figure Instruction Timing Cycle
ENHANCED 8051 CORE
instructions MSC1210 family perform exactly same functions they would standard 8051. effect bits, flags, registers same. However, timing different. MSC1210 family utilizes efficient 8051 core which results improved instruction execution speed between times faster than original core same external clock speed clock cycles instruction versus clock cycles instruction, shown Figure internal system clock equal external oscillator frequency. This translates into effective throughput improvement more than times, using same code same external clock speed. Therefore, device frequency 33MHz MSC1210Yx actually performs equivalent execution speed 82.5MHz compared standard 8051 core. This allows user device slower external clock speeds which reduces system noise power consumption, provides greater throughput. This performance difference seen Figure timing software loops will faster with MSC1210. However, timer/counter operation MSC1210 maintained clocks increment optionally clocks increment. MSC1210 also provides dual data pointers (DPTRs) speed block Data Memory moves. Additionally, stretch number memory cycles access external Data Memory from between nine instruction cycles order accommodate different speeds memory devices, shown Table MSC1210 provides external memory interface with 16-bit address P2). 16-bit address makes necessary multiplex address byte through port. enhance high-speed memory access, hardware configuration control provided configure ports external memory/peripheral interface general-purpose I/O. Furthermore, improvements were made peripheral features that off-load processing from core, user, further improve efficiency. instance, 32-bit accumulation done through summation register significantly reduce processing overhead multiple byte data from other sources. This
allows 32-bit addition shifting accomplished instruction cycles, compared hundreds instruction cycles through software implementation.
Table Memory Cycle Stretching. Stretching MOVX timing defined MD2, MD1, bits CKCON register (address 8Eh).
CKCON (8Eh) MD2:MD0 INSTRUCTION CYCLES (for MOVX) (default) STROBE WIDTH (SYS CLKs) STROBE WIDTH (ms) 12MHz 0.167 0.333 0.667 1.000 1.333 1.667 2.000 2.333
Single-Byte, Single-Cycle Instruction
MSC121 Timing
PSEN AD0- PORT Cycles Cycles
Standard 8051 Timing
PSEN AD0- PORT Single-Byte, Single-Cycle Instruction
Figure Comparison MSC1210 Timing Standard 8051 Timing
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Family Device Compatibility
hardware functionality configuration across MSC1210 family fully compatible. user only difference between family members memory configuration. This makes migration between family members simple. Code written MSC1210Y2 executed directly MSC1210Y3, MSC1210Y4, MSC1210Y5. This gives user ability subtract software functions freely migrate between family members. Thus, MSC1210 become standard device used across several application platforms.
OVERVIEW
MSC1210 structure shown Figure figure lists components that make ADC, along with corresponding special function register (SFR) associated with each component.
INPUT MULTIPLEXER
input multiplexer provides combination differential inputs selected input channel, shown Figure AIN0 selected positive differential input channel, other channel selected negative differential input channel. With this method, possible have eight fully differential input channels. also possible switch polarity differential input pair negate offset voltages. addition, current sources supplied that will source sink current detect open short circuits pins.
Family Development Tools
MSC1210 fully compatible with standard 8051 instruction set. This means that user develop software MSC1210 with their existing 8051 development tools. Additionally, complete, integrated development environment provided with each demo board, third-party developers also provide support.
TEMPERATURE SENSOR
On-chip diodes provide temperature sensing capability. When configuration register input diodes connected input ADC. other channels open.
Power Down Modes
MSC1210 power several on-chip peripherals into IDLE. more information, page
Burnout Detect
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM
REFIN+
Input Multiplexer Temperature Sensor
Burnout Detect
Buffer
Sample Hold
REFIN- AGND ADC0N0 ACLK
Offset ODAC
ADMUX
REFIN+
FAST Modulator SINC2 SINC3 AUTO Offset Calibration Register Gain Calibration Register ADRES SUMR SSCON
Result Register
Summation Block
REFIN- ADCON1 ADCON2 ADCON3
Figure MSC1210 Structure
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input impedance MSC1210 without buffer 7M/PGA. buffer controlled state control register (ADCON0 DCh).
ANALOG INPUT
Burnout Detect Current Source
When buffer selected, input impedance analog input changes with ACLK clock frequency (ACLK F6h) gain (PGA). relationship
Impedance(W) ACLK Frequency
where ACLK frequency
modclk
(ACLK)1)
Burnout Detect Current Sink AGND Temperature Sensor
NOTE: input impedance same that that
ACLK
Figure shows basic input structure MSC1210.
Rswitch typical) High Impedance (9pF typical) Sampling Frequency fSAMP fSAMP modclk modclk modclk modclk modclk 18pF 36pF
AGND
Figure Input Multiplexer Configuration
BURNOUT DETECT
When Burnout Detect (BOD) control configuration register (ADCON0 DCh), current sources enabled. current source positive input channel sources approximately current. current source negative input channel sinks approximately 2µA. This allows detection open circuit (full-scale reading) short circuit (small differential reading) selected input differential pair. Buffer should sensor burnout detection.
Figure Analog Input Structure
MODULATOR
modulator single-loop 2nd-order system. modulator runs clock speed (fMOD) that derived from using value Analog Clock (ACLK) register (SFR F6h). data rate
INPUT BUFFER
analog input impedance always high, regardless setting (when buffer enabled). With buffer enabled, input voltage range reduced analog power-supply current higher. limitation input voltage range acceptable, then buffer always preferred.
Data Rate
Decimation Ratio (ACLK)1)
where
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gains 128. Using actually improve effective resolution ADC. instance, with ±2.5V full-scale range, resolve 1.5µV. With ±19mV full-scale range, resolve 75nV, shown Table
Calibration should performed after power change temperature, decimation ratio, buffer, change PGA. Calibration will remove effects Offset DAC; therefore, changes Offset register must done after calibration. completion calibration, Interrupt goes HIGH which indicates calibration finished valid data available.
Table ENOB versus (Bipolar Mode)
SETTING FULL-SCALE RANGE ENOB 10HZ MEASUREMENT RESOLUTION (nV)
DIGITAL FILTER
Digital Filter either Fast Settling, Sinc2, Sinc3 filter, shown Figure addition, Auto mode changes Sinc filter after input channel changed. When switching channel, will Fast Settling filter next conversions (the first which should discarded). will then Sinc2 followed Sinc3 filter improve noise performance.
±2.5V ±1.25 ±0.625 ±0.313 ±0.156 ±0.0781 ±0.039 ±0.019
21.7 21.5 21.4 21.2 20.8 20.4
1468 74.5 74.5
Adjustable Digital Filter Sinc3
OFFSET
analog input offset half full-scale input range using ODAC register (SFR E6h). ODAC (Offset DAC) register 8-bit value; sign seven LSBs provide magnitude offset. Since ODAC introduces analog (instead digital) offset PGA, using ODAC does reduce range ADC.
Modulator Sinc2 Data
Fast Settling FILTER SETTLING TIME SETTLING TIME FILTER (Conversion Cycles)(1) Sinc3 Sinc2 Fast
NOTE: change cycle.
CALIBRATION
offset gain errors MSC1210, complete system, reduced with calibration. Calibration controlled through ADCON1 register (SFR DDh), bits CAL2:CAL0. Each calibration process takes seven tDATA (data conversion time) periods complete. Therefore, takes tDATA periods complete both offset gain calibration. system calibration, appropriate signal must applied inputs. system offset command requires zero differential input signal. then computes offset value that will nullify offsets system. system gain command requires positive full-scale differential input signal. then computes value nullify gain errors system. Each these calibrations will take seven tDATA periods complete.
AUTO MODE FILTER SELECTION CONVERSION CYCLE Discard Fast Sinc2 Sinc3
Figure Filter Step Responses
This combines low-noise advantage Sinc3 filter with quick response Fast Settling Time filter. frequency response each filter shown Figure
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VOLTAGE REFERENCE
SINC3 Gain (dB) -100 -120 DATA FILTER RESPONSE (-3dB 0.262 fDATA)
MSC1210 either internal external voltage reference. voltage reference selection controlled Control Register (ADCON0, DCh). default power-up configuration voltage reference 2.5V internal. internal voltage reference selected either 1.25V 2.5V. analog power supply (AVDD) must within specified range selected internal voltage reference. valid ranges are: VREF internal (AVDD 3.3V 5.25V) VREF 1.25 internal (AVDD 2.7V 5.25V). internal VREF selected, then REFOUT must connected REFIN+, AGND must connected REFIN-. REFOUT should also have 0.1µF capacitor connected AGND, close possible pin. internal VREF used, then VREF should disabled ADCON0. external voltage reference selected, used either single-ended input differential input, ratiometric measures. When using external reference, important note that input current will increase VREF with higher settings with higher modulator frequency. external voltage reference used over input range specified Electrical Characteristics section.
SINC2 FILTER RESPONSE (-3dB 0.318 fDATA Gain (dB) -100 -120 fDATA
POWER-ON RESET
on-chip power-on reset (POR) circuitry releases device from reset approximately DVDD 2.0V. accommodates power-supply ramp rates slow 1V/10ms. ensure proper operation, power supply should ramp monotonically. Note that device released from reset program execution begins, device current consumption increase, which result power-supply voltage drop. power supply ramps slower rate, monotonic, brownout condition occurs (where supply does drop below 2.0V threshold), then improper device operation occur. on-chip brownout reset provide benefit these conditions. Figure shows circuit.
FAST SETTLING FILTER RESPONSE (-3dB 0.469 DATA) Gain (dB) -100 -120 DATA NOTE: fDATA Data Output Rate 1/tDATA
DVDD MSC1210 0.1µF
Figure Filter Frequency Responses
Figure Circuit
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BROWNOUT RESET
brownout reset (BOR) enabled through Hardware Configuration Register (HCR1). conditions proper device encounters brownout condition that does generate POR, used ensure proper device operation. will hold state device when power supply drops below threshold level programmed HCR1, then generate reset when supply rises above threshold level. Note that device released from reset, program execution begins, device current consumption increase, which result power-supply voltage drop, which initiate another brownout condition.
level should chosen match closely with application. example, with high external clock frequency, level should match minimum operating voltage range device, improper operation still occur. Note that AVDD must rise above 2.0V Analog Brownout Reset function disabled; otherwise, will enabled hold device reset.
POWER-DOWN MODES
MSC1210 power several on-chip peripherals into IDLE. This accomplished shutting clocks those sections, shown Figure lowest power, sure that FRCM FMCON set.
Clock Oscillator
STOP SPICON
PDCON.0 PWMHI PDCON.4 USEC FTCON Flash Write (30µs 40µs) [3:0] Timing PWMLOW Clock
MSECH MSECL
FTCON [7:4]
Flash Erase (5ms 11ms) Timing milliseconds interrupt seconds interrupt
MSINT PDCON.1
SECINT
HMSEC
100ms WDTCON PDCON.2
watchdog
ACLK Power Down PDCON.3
divide
ADCON3 ADCON2 Decimation Ratio ADCON0
Output Rate
fSAMP (see Figure fMOD
Timers 0/1/2 IDLE
USART0/1
Clock
Figure MSC1210 Timing Chain Clock Control
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MEMORY
MSC1210 contains on-chip SFR, Flash Memory, Scratchpad SRAM Memory, Boot ROM, SRAM. registers primarily used control status. standard 8051 features additional peripheral features MSC1210 controlled through SFR. Reading from undefined writing undefined registers recommended, will have indeterminate effects. Flash Memory used both Program Memory Data Memory. user ability select partition size Program Data Memories. partition size through hardware configuration bits, which programmed through either parallel serial programming methods. Both Program Data Flash Memories erasable writable (programmable) User Application mode (UAM). However, program execution only occur from Program Memory. added precaution, lock feature activated through hardware configuration bits, which disables erase writes Program Flash Memory entire Program Flash Memory UAM. MSC1210 includes SRAM on-chip. SRAM starts address accessed through MOVX instruction. This SRAM also located start 8400h accessed both Program Data Memory.
FLASH MEMORY
MSC1210 uses memory addressing scheme that separates Program Memory (FLASH/ROM) from Data Memory (FLASH/RAM). Each area 64kB beginning address 0000h ending FFFFh, shown Figure program data segments overlap since they accessed different ways. Program Memory fetched microcontroller automatically. There instruction (MOVC) that used explicitly read program area. This commonly used read lookup tables. Data Memory area accessed explicitly using MOVX instruction. This instruction provides multiple ways specifying target address. used access 64kB Data Memory. address data range devices with on-chip Program Data Memory overlap 64kB memory space. When on-chip memory enabled, accessing memory on-chip range will cause device access internal memory. Memory accesses beyond internal range will addressed externally Ports MSC1210 Hardware Configuration registers (HCR0 HCR1) that programmable only during Flash Memory Programming mode.
Program Memory
Select HCR0 Internal Boot FFFFh F800h
Data Memory
FFFFh
External Program Memory
Select MCON External External Memory
Mapped Either Memory Space 8800h 8400h, (Y5) 8000h, (Y5) Select MCON 4000h, (Y4) 2000h, (Y3) 1000h, (Y2) 0000h,
External Data Memory
External 8800h 8400h, (Y5) 4400h, (Y4)
On-Chip Flash
On-Chip Flash
2400h, (Y3) 1400h, (Y2)
External
0400h,
Figure Memory
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MSC1210 allows user partition Flash Memory between Program Memory Data Memory. instance, MSC1210Y5 contains 32kB Flash Memory on-chip. Through configuration registers, user define partition between Program Memory (PM) Data Memory (DM), shown Table Table MSC1210 family offers four memory configurations, shown.
Table MSC1210 Flash Partitioning
HCR0 DFSEL (default) MSC1210Y2 MSC1210Y3 MSC1210Y4 12kB 14kB 15kB 16kB 16kB 16kB 16kB MSC1210Y5 16kB 24kB 28kB 30kB 31kB 32kB 32kB 32kB 16kB
important note that Flash Memory readable writable user through MOVX instruction when configured either Program Data Memory (via MXWS MWS, 8Fh). This means that user partition device maximum Flash Program Memory size Flash Data Memory) Flash Program Memory Flash Data Memory. This lead undesirable behavior points area Flash Program Memory that being used data storage. Therefore, recommended Flash partitioning when Flash Memory used data storage. Flash partitioning prohibits execution code from Data Flash Memory. Additionally, Program Memory erase/write disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) Data Flash Memory. effect memory mapping Program Data Memory straightforward. Program Memory decreased size from internal Program Memory. Therefore, MSC1210Y5 partitioned with 31kB Flash Program Memory Flash Data Memory, external Program Memory execution will begin 7C00h (versus 8000h 32kB). Flash Data Memory added SRAM memory. Therefore, access Data Memory (through MOVX) will access SRAM addresses 0000h-03FFh access Flash Memory addresses 0400h-07FFh.
NOTE: When program memory configuration selected, program execution external.
Table MSC1210 Flash Memory Partitioning
HCR0 DFSEL
MSC1210Y2
0000 0000
MSC1210Y3
0000 0000
MSC1210Y4
0000 0000
MSC1210Y5
0000 0000 00003FFF 00005FFF 00006FFF 000077FF 00007BFF 00007FFF
040013FF 040013FF 040013FF 040013FF 040013FF 04000BFF 040007FF 0000
040023FF 040023FF 040023FF 040023FF 040013FF 04000BFF 040007FF 0000
040043FF 040043FF 040043FF 040023FF 040013FF 04000BFF 040007FF 0000
000083FF 040083FF 040043FF 040023FF 040013FF 04000BFF 040007FF 0000
Data Memory
MSC1210 address 64kB Data Memory. Scratchpad Memory provides bytes addition 64kB Data Memory. MOVX instruction used access Data SRAM Memory. This includes 1,024 bytes on-chip Data SRAM Memory. data values appear Port (during data timing) internal memory access. MSC1210 also on-chip Flash Data Memory which readable writable (depending Memory Write Select register) during normal operation (full range). This memory mapped into external Data Memory space directly above SRAM. MOVX instruction used write flash memory. Flash memory must erased before written. Flash memory erased byte pages.
0000 0000
0000 0000 00000FFF 000017FF 00001BFF 00001FFF
0000 00001FFF 00002FFF 000037FF 00003BFF 00003FFF
0000 000007FF 00000BFF 00000FFF
(default)
NOTE: Program memory accesses above highest listed address will access external program memory.
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REGISTER
Register illustrated Figure entirely separate from Program Data Memory areas mentioned before. separate class instructions used access registers. There potential register locations. practice, MSC1210 bytes Scratchpad SFRs. This possible, since upper Scratchpad locations only accessed indirectly. Thus, direct reference upper locations must access. Direct reached locations 127).
Indirect Direct 0000h Scratchpad Registers Direct Special Function Registers
selected bank will used instruction using R0-R7. This allows software change context simply switching banks. This controlled Program Status Word register (PSW; 0D0h) area described below. Registers also allow their contents used indirect addressing upper bytes RAM. Thus, instruction designate value stored (for example) address upper RAM. bytes immediately above R0-R7 registers addressable. bits this area directly accessed using addressable instructions.
Indirect Direct Addressable
Figure Register
SFRs accessed directly between (128 255). locations between reached through indirect reference those locations. Scratchpad available general-purpose data storage. commonly used place off-chip when total data contents small. When off-chip needed, Scratchpad area will still provide fastest general-purpose access. Within bytes RAM, there several special-purpose areas.
Addressable Locations
addition direct register access, some individual bits also accessible. These individually addressable bits both area. Scratchpad area, registers addressable. This provides individual bits available software. access distinguished from full-register access type instruction. area, register location ending addressable. Figure shows details on-chip addressing including locations individual bits.
Bank Bank Bank Bank 0000h
Working Registers
part lower bytes RAM, there four banks Working Registers, shown Figure Working Registers general-purpose locations that addressed special way. They designated through Since there four banks, currently
Figure Scratchpad Register Addressing
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Stack
Another Scratchpad area programmer's stack. This area selected using Stack Pointer (SP; 81h) SFR. Whenever call interrupt invoked, return address placed Stack. also available programmer variables, etc., since Stack moved there fixed location within designated Stack. Stack Pointer will default reset. user then move needed. convenient location would upper area 7Fh) since this only available indirectly. will point last used value. Therefore, next value placed Stack Each PUSH CALL will increment appropriate value. Each will decrement well.
ACCESSING EXTERNAL MEMORY
external memory used, configured address data lines. external memory used, configured general-purpose lines through Hardware Configuration Register. enable access external memory, bits HCR1 register must When these bits enabled memory addresses both internal external memory will appear ports During data portion cycle internal memory, Port will zero security purposes. Accesses external memory types: accesses external Program Memory accesses external Data Memory. Accesses external Program Memory signal PSEN (program store enable) read strobe. Accesses external Data Memory (alternate functions P3.7 P3.6) strobe memory. External Program Memory external Data Memory combined desired applying PSEN signals inputs gate using output gate read strobe external Program/Data Memory. Program fetches from external Program Memory always 16-bit address. Accesses external Data Memory either 16-bit address (MOVX @DPTR) 8-bit address (MOVX @RI). Port selected external memory (HCR1, cannot used general-purpose I/O. This HCR1) also forces bits P3.6 P3.7 used instead I/O. Port P3.6, P3.7 should written `1.' 8-bit address being used (MOVX @RI), contents MPAGE (92h) remain Port pins throughout external memory cycle. This will facilitate paging.
Program Memory
After reset, begins execution from Program Memory location 0000h. selection where Program Memory execution begins made tying DVDD internal access, DGND external access. When tied DVDD, fetches outside internal Program Memory address occur from external memory. tied DGND, then fetches address external memory. standard internal Program Memory size MSC1210 family members shown Table enabled Boot will appear from address F800h FFFFh.
Table MSC1210 Maximum Internal Program Memory Sizes
PRODUCT MSC1210Y5 MSC1210Y4 MSC1210Y3 MSC1210Y2 STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES)
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case, byte address time-multiplexed with data byte Port ADDR/DATA signals CMOS drivers Port Port output buffers. Thus, this application Port pins open-drain outputs, require external pull-ups high-speed access. Signal (Address Latch Enable) should used capture address byte into external latch. address byte valid negative transition ALE. Then, write cycle, data byte written appears Port just before activated, remains there until after deactivated. read cycle, incoming byte accepted Port just before read strobe deactivated. functions Port Port selected Hardware Configuration Register This only changed during Flash Program mode. There conflict these registers; they will either used general-purpose external memory access. default state Port Port used general-purpose I/O. external memory access attempted when they configured general-purpose I/O, values Port Port will affected. External Program Memory accessed under conditions:
Boot
There Boot that controls operation during serial parallel programming. Additionally, Boot routines accessed during user mode enabled. When enabled, Boot routines will located memory addresses F800h-FFFFh during user mode. program mode Boot located first Program Memory. additional information, refer Application Note SBAA085, available download from site (www.ti.com).
Flash Programming Mode
There programming modes: parallel serial. programming mode selected state PSEN signals during power-on reset. Serial programming mode selected with PSEN Parallel programming mode selected with PSEN (see Figure 21). they both HIGH, MSC1210 will operate normal user mode. Both signals reserved mode defined. Programming mode exited with reset (BOR, WDT, software, POR) normal mode selected.
MSC1210 PSEL P2[7] AddrHi[6:0] P2[6:0] PSEN P1[7:0] Data[7:0] P0[7:0] Cmd[2:0] P3[7:5] P3[4] P3[3] P3[2] Pass AddrLo[7:0]
HOST Flash Programmer
Whenever signal during reset, then future accesses external; Whenever Program Counter (PC) contains number that outside internal Program Memory address range, ports enabled.
Port Port selected external memory, bits Port Port well P3.6 P3.7, dedicated output function used general-purpose I/O. During external program fetches, Port outputs high byte
Programming Flash Memory
There four sections Flash Memory programming:
configuration bytes. Reset sector (4kB) (not confused with Boot ROM). Program Memory. Data Memory.
Figure Parallel Programming Configuration
MSC1210 shipped with Flash Memory erased (all 1s). Parallel programming methods typically involve third-party programmer. Serial programming methods typically involve in-system programming. allows Flash Program Data Memory programming. actual code Flash programming cannot execute from Flash. That code must execute from Boot ROM, internal (von Neumann) external memory.
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INTERRUPTS
MSC1210 uses three-priority interrupt system. shown Table each interrupt source independent priority bit, flag, interrupt vector, enable (except that nine interrupts share Auxiliary Interrupt [AI] highest priority). addition, interrupts globally enabled disabled. interrupt structure compatible with original 8051 family. standard interrupts available.
HARDWARE CONFIGURATION MEMORY
configuration bytes only written during program mode. bytes accessed through registers CADDR (SFR 93h) CDATA (SFR 94h). configuration bytes control Flash partitioning system control. security set, these bits changed except with Mass Erase command that erases Flash Memory including configuration bytes.
Table Interrupt Summary
INTERRUPT INTERRUPT/EVENT DVDD Voltage/HW Breakpoint AVDD Voltage Receive Transmit Milliseconds Timer Summation Register Seconds Timer External Interrupt Timer Overflow External Interrupt Timer Overflow Serial Port Timer Overflow Serial Port External Interrupt External Interrupt External Interrupt External Interrupt Watchdog ADDR PRIORITY HIGH FLAG EDLVB (AIE.0)(1) (BPCON.0)(1) EALV (AIE.1)(1) ESPIR (AIE.2)(1) ENABLE EDLVB (AIE.0)(1) (BPCON.0)(1) EALV (AIE.1)(1) ESPIR (AIE.2)(1) PRIORITY CONTROL (IP.0) (IP.1) (IP.2) (IP.3) (IP.4) (IP.5) (IP.6) (EIP.0) (EIP.1) (EIP.2) (EIP.3) PWDI (EIP.4)
ESPIT (AIE.3)(1) EMSEC EADC (AIE.4)(1)
ESPIT (AIE.3)(1) EMSEC EADC (AIE.4)(1)
(AIE.5)(1)
(AIE.5)(1)
ESUM (AIE.6)(1) ESEC (AIE.7)(1)
ESUM (AIE.6)(1) ESEC (AIE.7)(1)
(TCON.1)(2) (TCON.5)(3) (TCON.3)(2)
(IE.0)(4) (IE.1)(4) (IE.2)(4)
(TCON.7)(3) RI_0 (SCON0.0) TI_0 (SCON0.1) (T2CON.7) RI_1 (SCON1.0) TI_1 (SCON1.1) (EXIF.4) (EXIF.5) (EXIF.6) (EXIF.7) WDTI (EICON.3)
(IE.3)(4) (IE.4)(4)
(IE.5)(4) (IE.6)(4)
(EIE.0)(4) (EIE.1)(4)
(EIE.2)(4) (EIE.3)(4) EWDI (EIE.4)(4)
These interrupts flag (EICON.4) enabled (EICON.5). edge-triggered, cleared automatically hardware when service routine vectored level-triggered, flag follows state pin. Cleared automatically hardware when interrupt vector occurs. Globally enabled (IE.7).
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Hardware Configuration Register (HCR0)-Accessed Using Registers CADDR CDATA.
CADDR EPMA EWDR DFSEL2 DFSEL1 DFSEL0
read this register during normal operation, refer register descriptions CADDR CDATA.
EPMA Enable Programming Memory Access (Security Bit). After reset programming modes, Flash Memory only accessed until mass erase done. Fully Accessible (default) Program Memory Lock (PML Priority Over RSL). Enable Flash Programming modes program mode, written UAM. Enable read-only program mode; cannot written (default). Reset Sector Lock. reset sector used provide another method Flash Memory programming. This will allow Program Memory updates without changing jumpers in-circuit code updates program development. code this boot sector would then provide monitor programming routines with ability jump into main Flash code when programming finished. Enable Reset Sector Writing Enable Read-Only Mode Reset Sector (4kB) (default) Enable Boot ROM. Boot code located ROM, confused with Boot Sector located Flash Memory. Disable Internal Boot Enable Internal Boot (default)
EWDR
Enable Watchdog Reset. Disable Watchdog Reset Enable Watchdog Reset (default)
DFSEL bits
Data Flash Memory Size (see Table 000: Reserved 001: 32kB, 16kB, 8kB, Data Flash Memory 010: 16kB, 8kB, Data Flash Memory 011: Data Flash Memory 100: Data Flash Memory 101: Data Flash Memory 110: Data Flash Memory 111: Data Flash Memory (default)
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Hardware Configuration Register (HCR1)
CADDR DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 EGP0 EGP23
read this register during normal operation, refer register descriptions CADDR CDATA.
DBLSEL bits Digital Brownout Level Select 4.5V 4.2V 2.7V 2.5V (default) Analog Brownout Level Select 4.5V 4.2V 2.7V 2.5V (default) Disable Analog Power-Supply Brownout Reset Enable Analog Brownout Reset Disable Analog Brownout Reset (default) (will disable unless AVDD 2.0V) Disable Digital Power-Supply Brownout Reset Enable Digital Brownout Reset Disable Digital Brownout Reset (default) Enable General-Purpose Port Port Used External Memory, P3.6 P3.7 Used Port Used General-Purpose (default) Enable General-Purpose Ports Port Used External Memory, P3.6 P3.7. Used Port Port3 Used General-Purpose (default)
ABLSEL bits
EGP0
EGP23
Configuration Memory Programming
Certain functions such Brownout Reset Watchdog Timer controlled hardware configuration bits. These bits nonvolatile only changed through serial parallel programming. Other peripheral control status functions, such configuration, timer setup, Flash control, controlled through SFRs.
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Definitions (Boldface definitions indicate that register unique MSC1210Yx)
ADDRESS REGISTER DPL0 DPH0 DPL1 DPH1 PCON TCON TMOD SMOD STOP IDLE P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 RESET VALUES
Timer GATE
Timer GATE
CKCON EXIF MPAGE CADDR CDATA MCON BPSEL RAMMAP P1.7 INT5/SCK P1.6 INT4/MISO P1.5 INT3/MOSI P1.4 INT2/SS P1.3 TXD1 P1.2 RXD1 P1.1 T2EX MXWS P1.0
SCON0 SBUF0 SPICON SPIDATA SPITCON PWMCON PWMLOW TONELOW PWMHI TONEHI
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
SCK2
SCK1
SCK0
ORDER
MSTR
CPHA
CPOL
CLK_EN P2.7 P2.6 P2.5 PPOL PWM7 TDIV7 PWM15 TDIV15 PWM6 TDIV6 PWM14 TDIV14 PWM5 TDIV5 PWM13 TDIV13
DRV_DLY P2.4 PWMSEL PWM4 TDIV4 PWM12 TDIV12
DRV_EN P2.3 SPDSEL PWM3 TDIV3 PWM11 TDIV11 P2.2 TPCNTL2 PWM2 TDIV2 PWM10 TDIV10 P2.1 TPCNTL1 PWM1 TDIV1 PWM9 TDIV9 P2.0 TPCNTL0 PWM0 TDIV0 PWM8 TDIV8
AISTAT BPCON P0DDRL P0DDRH
ESEC
ESUM
EADC
EMSEC MSEC
PAI3 ESPIT SPIT
PAI2 ESPIR SPIR
PAI1 EALV ALVD PMSEL
PAI0 EDLVB DLVD
P03H P07H
P03L P07L
P02H P06H
P02L P06L
P01H P05H
P01L P05L
P00H P04H
P00L P04L
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Definitions (continued) (Boldface definitions indicate that register unique MSC1210Yx)
ADDRESS ADMUX EICON ADRESL ADRESM INP3 SMOD1 INP2 INP1 INP0 INN3 WDTI INN2 INN1 INN0 RCAP2L RCAP2H T2CON EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2 EWUWDT EWUEX1 EWUEX0 SCON1 SBUF1 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 REGISTER P1DDRL P1DDRH P2DDRL P2DDRH P3DDRL P3DDRH P13H P17H P3.7 P23H P27H P33H P37H P13L P17L P3.6 P23L P27L P33L P37L P12H P16H P3.5 P22H P26H P32H P36H P12L P16L P3.4 P22L P26L P32L P36L P11H P15H P3.3 INT1 P21H P25H P31H P35H P11L P15L P3.2 INT0 P21L P25L P31L P35L P10H P14H P3.1 TXD0 P20H P24H P30H P34H P10L P14L P3.0 RXD0 P20L P24L P30L P34L RESET VALUES
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Definitions (continued) (Boldface definitions indicate that register unique MSC1210Yx)
ADDRESS ACLK SRST SECINT MSINT USEC MSECL MSECH HMSEC WDTCON EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 FREQ6 SECINT6 MSINT6 FREQ5 SECINT5 MSINT5 FREQ4 PWDI SECINT4 MSINT4 FREQ4 FREQ3 SECINT3 MSINT3 FREQ3 FREQ2 SECINT2 MSINT2 FREQ2 FREQ1 SECINT1 MSINT1 FREQ1 FREQ0 RSTREQ SECINT0 MSINT0 FREQ0 REGISTER ADRESH ADCON0 ADCON1 ADCON2 ADCON3 SSCON SUMR0 SUMR1 SUMR2 SUMR3 ODAC LVDCON HWPC0 HWPC1 HDWVER Reserved Reserved FMCON FTCON PDCON PASEL FER3 PGERA FER2 FER1 PSEN2 FRCM FER0 PDPWM PSEN1 FWR3 PDADC PSEN0 BUSY FWR2 PDWDT FWR1 PDST ALE1 FWR0 PDSPI ALE0 ALVDIS ALVD2 ALVD1 ALVD0 EWDI DLVDIS DLVD2 DLVD1 DLVD0 MEMORY SIZE SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 OF_UF EVREF VREFH EBUF PGA2 CAL2 DR10 PGA1 CAL1 PGA0 CAL0 RESET VALUES 0000_0000b 0000_00xxb
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Port (P0)
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Reset Value
P0.7-0 bits
Port This port functions multiplexed address/data during external memory access, generalpurpose port when external memory access needed. During external memory cycles, this port will contain address when HIGH, Data when LOW. When used general-purpose I/O, this port drive selected P0DDRL P0DDRH (ACh, ADh). Whether Port used general-purpose external memory access determined Flash Configuration Register (HCR1.1)
Stack Pointer (SP)
SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 Reset Value
SP.7-0 bits
Stack Pointer. stack pointer identifies location where stack will begin. stack pointer incremented before every PUSH CALL operation decremented after each RET/RETI. This register defaults after reset.
Data Pointer (DPL0)
DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 Reset Value
DPL0.7-0 bits
Data Pointer This register byte standard 8051 16-bit data pointer. DPL0 DPH0 used point non-scratchpad data RAM. current data pointer selected (SFR 86h).
Data Pointer High (DPH0)
DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 Reset Value
DPH0.7-0 bits
Data Pointer High This register high byte standard 8051 16-bit data pointer. DPL0 DPH0 used point non-scratchpad data RAM. current data pointer selected (SFR 86h).
Data Pointer (DPL1)
DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 Reset Value
DPL1.7-0 bits
Data Pointer This register byte auxiliary 16-bit data pointer. When (DPS.0, 86h) set, DPL1 DPH1 used place DPL0 DPH0 during DPTR operations.
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Data Pointer High (DPH1)
DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 Reset Value
DPH1.7-0 bits
Data Pointer High. This register high byte auxiliary 16-bit data pointer. When (DPS.0, 86h) set, DPL1 DPH1 used place DPL0 DPH0 during DPTR operations.
Data Pointer Select (DPS)
Reset Value
Data Pointer Select. This selects active data pointer. Instructions that DPTR will DPL0 DPH0. Instructions that DPTR will DPL1 DPH1.
Power Control (PCON)
SMOD STOP IDLE Reset Value
SMOD
Serial Port Baud Rate Doubler Enable. serial baud rate doubling function Serial Port Serial Port baud rate will standard baud rate. Serial Port baud rate will double that defined baud rate generation equation when using Timer General-Purpose User Flag This general-purpose flag software control.
STOP IDLE
General-Purpose User Flag This general-purpose flag software control.
Stop Mode Select. Setting this will halt oscillator block external clocks. This will always read Exit with RESET. Idle Mode Select. Setting this will freeze CPU, Timer USARTs; other peripherals remain active. This will always read Exit with (A6h) (C6h) interrupts.
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Timer/Counter Control (TCON)
Reset Value
Timer Overflow Flag. This indicates when Timer overflows maximum count defined current mode. This cleared software automatically cleared when vectors Timer interrupt service routine. Timer overflow been detected. Timer overflowed maximum count. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH1, TL1. Timer halted. Timer enabled. Timer Overflow Flag. This indicates when Timer overflows maximum count defined current mode. This cleared software automatically cleared when vectors Timer interrupt service routine. Timer overflow been detected. Timer overflowed maximum count. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH0, TL0. Timer halted. Timer enabled. Interrupt Edge Detect. This when edge/level type defined detected. this will remain until cleared software start External Interrupt service routine. this will inversely reflect state INT1 pin. Interrupt Type Select. This selects whether INT1 will detect edge level triggered interrupts. INT1 level triggered. INT1 edge triggered. Interrupt Edge Detect. This when edge/level type defined detected. this will remain until cleared software start External Interrupt service routine. this will inversely reflect state INT0 pin. Interrupt Type Select. This selects whether INT0 will detect edge level triggered interrupts. INT0 level triggered. INT0 edge triggered.
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Timer Mode Control (TMOD)
TIMER GATE GATE TIMER Reset Value
GATE
Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT1. Timer will clock only when INT1 Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.6, 88h) Timer Mode Select. These bits select operating mode Timer
MODE Mode 8-bit counter with 5-bit prescale. Mode bits. Mode 8-bit counter with auto reload. Mode Timer halted, holds count.
bits
GATE
Timer Gate Control. This enables/disables ability Timer increment. Timer will clock when regardless state INT0 (software control). Timer will clock only when INT0 (hardware control). Timer Counter/Timer Select. Timer incremented internal clocks. Timer incremented pulses when (TCON.4, 88h) Timer Mode Select. These bits select operating mode Timer
MODE Mode 8-bit counter with 5-bit prescale. Mode bits. Mode 8-bit counter with auto reload. Mode 8-bit counters.
bits
Timer (TL0)
TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 Reset Value
TL0.7-0 bits
Timer LSB. This register contains least significant byte Timer
Timer (TL1)
TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 Reset Value
TL1.7-0 bits
Timer LSB. This register contains least significant byte Timer
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Timer (TH0)
TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 Reset Value
TH0.7-0 bits
Timer MSB. This register contains most significant byte Timer
Timer (TH1)
TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 Reset Value
TH1.7-0 bits
Timer MSB. This register contains most significant byte Timer
Clock Control (CKCON)
Reset Value
Timer Clock Select. This controls division system clock that drives Timer This effect when timer baud rate generator clock output mode. Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide-by-12 crystal frequency. Timer uses divide-by-4 crystal frequency. Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide-by-12 crystal frequency. Timer uses divide-by-4 crystal frequency. Timer Clock Select. This controls division system clock that drives Timer Clearing this maintains 8051 compatibility. This effect instruction cycle timing. Timer uses divide-by-12 crystal frequency. Timer uses divide-by-4 crystal frequency. Stretch MOVX Select 2-0. These bits select time which external MOVX cycles stretched. This allows slower memory peripherals accessed without using ports manual software intervention. width strobe will stretched specified interval, which will transparent software except increased time execute MOVX instruction. internal MOVX instructions devices containing MOVX SRAM performed instruction cycle rate.
STRETCH VALUE MOVX DURATION Instruction Cycles Instruction Cycles (default) Instruction Cycles Instruction Cycles Instruction Cycles Instruction Cycles Instruction Cycles Instruction Cycles STROBE WIDTH (SYS CLKs) STROBE WIDTH (ms) 12MHz 0.167 0.333 0.667 1.000 1.333 1.667 2.000 2.333
MD2, MD1, bits
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Memory Write Select (MWS)
MXWS Reset Value
MXWS
MOVX Write Select. This allows writing internal Flash program memory. writes allowed internal Flash program memory. Writing allowed internal Flash program memory, unless (HCR0) (HCR0)
Port (P1)
P1.7 INT5/SCK P1.6 INT4/MISO P1.5 INT3/MOSI P1.4 INT2/SS P1.3 TXD1 P1.2 RXD1 P1.1 T2EX P1.0 Reset Value
P1.7-0 bits
General-Purpose Port This register functions general-purpose port. addition, pins have alternative function listed below. Each functions controlled several other SFRs. associated Port latch must contain logic before used alternate function capacity. alternate function, appropriate mode P1DDRL (SFR AEh), P1DDRH (SFR AFh). External Interrupt falling edge this will cause external interrupt enabled. Clock. master clock data transfers.
INT5/SCK
INT4/MISO External Interrupt rising edge this will cause external interrupt enabled. Master Slave Out. data transfers, this receives data master transmits data from slave. INT3/MOSI External Interrupt falling edge this will cause external interrupt enabled. Master Slave data transfers, this transmits master data receives slave data. INT2/SS External Interrupt rising edge this will cause external interrupt enabled. Slave Select. During operation, this provides select signal slave device does control output drive MISO. Serial Port Transmit. This transmits serial Port data serial port modes emits synchronizing clock serial port mode Serial Port Receive. This receives serial Port data serial port modes bidirectional data transfer serial port mode Timer Capture/Reload Trigger. transition this will cause value registers transferred into capture registers, enabled EXEN2 (T2CON.3, C8h). When auto-reload mode, transition this will reload Timer registers with value RCAP2L RCAP2H enabled EXEN2 (T2CON.3, C8h). Timer External Input. transition this will cause Timer increment.
TXD1 RXD1 T2EX
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External Interrupt Flag (EXIF)
Reset Value
External Interrupt Flag. This will when falling edge detected INT5. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when rising edge detected INT4. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when falling edge detected INT3. This must cleared manually software. Setting this software will cause interrupt enabled. External Interrupt Flag. This will when rising edge detected INT2. This must cleared manually software. Setting this software will cause interrupt enabled.
Memory Page (MPAGE)
Reset Value
MPAGE bits
8051 uses Port upper bits external data memory access MOVX A,@Ri MOVX @Ri,A instructions. MSC1210 uses register MPAGE instead Port access external data memory using MOVX A,@Ri MOVX @Ri,A instructions, user should preload upper byte address into MPAGE (versus preloading into standard 8051).
Configuration Address Register (CADDR) (write-only)
Reset Value
CADDR bits
Configuration Address Register. This register supplies address reading bytes bytes Flash Configuration memory. This write-only register.
CAUTION: this register written while executing from Flash Memory, CDATA register will incorrect. faddr_data_read routine Boot used this purpose.
Configuration Data Register (CDATA) (read-only)
Reset Value
CDATA bits
Configuration Data Register. This register will contain data bytes Flash Configuration memory that located last written address CADDR register. This read-only register.
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Memory Control (MCON)
BPSEL RAMMAP Reset Value
BPSEL
Breakpoint Address Selection Write: Select Breakpoint registers: Select breakpoint register Select breakpoint register Read: Provides Breakpoint register that created last interrupt: Memory extended SRAM. Address 0000h-03FFh (default) (Data Memory) Address 8400h-87FFh (Data Program Memory)
RAMMAP
Serial Port Control (SCON0)
SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 Reset Value
SM0-2 bits
Serial Port Mode. These bits control mode serial Port Modes have start stop addition data bits.
MODE 1(2) 1(2) 3(2) 3(2) FUNCTION Synchronous Synchronous Asynchronous Valid Stop Required(3) Asynchronous Asynchronous with Multiprocessor Communication(4) Asynchronous Asynchronous with Multiprocessor Communication(4) LENGTH bits bits bits bits bits bits bits bits PERIOD pCLK(1) pCLK(1) Timer Baud Rate Equation Timer Baud Rate Equation pCLK(1) (SMOD pCLK(1) (SMOD pCLK(1) (SMOD pCLK(1) (SMOD Timer Baud Rate Equation Timer Baud Rate Equation
pCLK will equal tCLK, except that pCLK will stop IDLE. modes selection Timer baud rate specified T2CON (C8h) register. RI_0 will only activated when valid STOP received. RI_0 will activated
REN_0
Receive Enable. This enables/disables serial Port received shift register. Serial Port reception disabled. Serial Port received enabled (modes Initiate synchronous reception (mode Transmission State. This defines state transmission serial Port modes
TB8_0 RB8_0 TI_0
Received State. This identifies state reception received data serial Port modes serial port mode when SM2_0 RB8_0 state stop bit. RB8_0 used mode Transmitter Interrupt Flag. This indicates that data serial Port buffer been completely shifted out. serial port mode TI_0 data bit. other modes, this last data bit. This must manually cleared software. Receiver Interrupt Flag. This indicates that byte data been received serial Port buffer. serial port mode RI_0 bit. serial port mode RI_0 after last sample incoming stop subject state SM2_0. modes RI_0 after last sample RB8_0. This must manually cleared software.
RI_0
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Serial Data Buffer (SBUF0)
Reset Value
SBUF0 bits
Serial Data Buffer Data Serial Port read from written this location. serial transmit receive buffers separate registers, both addressed this location.
Control (SPICON). change resets interface, counters, pointers. PDCON controls which enabled.
SCK2 SCK1 SCK0 ORDER MSTR CPHA CPOL Reset Value
bits
Selection. Selection tCLK divider generation Master mode.
SCK2 SCK1 SCK0 PERIOD tCLK/2 tCLK/4 tCLK/8 tCLK/16 tCLK/32 tCLK/64 tCLK/128 tCLK/256
ORDER
Order Transmit Receive. Most Significant Bits First Least Significant Bits First Master Mode. Slave Mode Master Mode Serial Clock Phase Control. Valid data starting from half period before first edge Valid data starting from first edge Serial Clock Polarity. idle logic idle logic HIGH
MSTR
CPHA
CPOL
Data Register (SPIDATA)
Reset Value
SPIDATA bits
Data Register. Data read from written this location. transmit receive buffers separate registers, both addressed this location. Read clear receive interrupt write clear transmit interrupt.
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Transmit Control Register (SPITCON)
CLK_EN DRV_DLY DRV_EN Reset Value
CLK_EN
Driver Enable. Disable Driver (Master Mode) Enable Driver (Master Mode) Drive Delay. (Refer DRV_EN bit) Drive output immediately Drive output after current byte transfer Drive Enable.
DRV_DLY DRV_EN MOSI MISO OUTPUT CONTROL Tristate immediately Drive immediately Tristate after current byte transfer Drive after current byte transfer
DRV_DLY
DRV_EN
Port (P2)
Reset Value
bits
Port This port functions address during external memory access, general-purpose port. During external memory cycles, this port will contain address. Whether Port used general-purpose external memory access determined Flash Configuration Register (HCR1.0).
Control (PWMCON)
PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 Reset Value
PPOL
Period Polarity. Specifies starting level pulse. Period. Duty register programs period. Period. Duty register programs period. Register Select. Select which 16-bit register accessed PWMLOW/PWMHIGH. Period (must TONE mode) Duty Speed Select. 1MHz (the USEC Clock) SYSCLK Tone Generator/Pulse Width Modulation Control.
TPCNTL.2 TPCNTL.1 TPCNTL.0 MODE Disable (default) TONE-Square TONE-Staircase
PWMSEL
SPDSEL
TPCNTL bits
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Tone (TONELOW)/PWM (PWMLOW)
TDIV7 PWM7 TDIV6 PWM6 TDIV5 PWM5 TDIV4 PWM4 TDIV3 PWM3 TDIV2 PWM2 TDIV1 PWM1 TDIV0 PWM0 Reset Value
TDIV7-0 bits PWMLOW bits
Tone Divisor. order bits that define half-time period. staircase mode output high impedance last this period. Pulse Width Modulator Bits. These bits least significant bits register.
Tone High (TONEHI)/PWM High (PWMHI)
TDIV15 PWM15 TDIV14 PWM14 TDIV13 PWM13 TDIV12 PWM12 TDIV11 PWM11 TDIV10 PWM10 TDIV9 PWM9 TDIV8 PWM8 Reset Value
TDIV15-8 bits PWMHI bits
Tone Divisor. high order bits that define half time period. staircase mode output high impedance last this period. Pulse Width Modulator High Bits. These bits high order bits register.
Pending Auxiliary Interrupt (PAI)
PAI3 PAI2 PAI1 PAI0 Reset Value
bits
Pending Auxiliary Interrupt Register. results this register used index vector appropriate interrupt routine. these interrupts vector through address 0033h.
PAI3 PAI2 PAI1 PAI0 AUXILIARY INTERRUPT STATUS Pending Auxiliary Digital Voltage Pending Analog Voltage Pending Receive Pending. Transmit Pending. Millisecond System Timer Pending. Analog-to-Digital Conversion Pending. Accumulator Pending. Second System Timer Pending.
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Auxiliary Interrupt Enable (AIE)
ESEC ESUM EADC EMSEC ESPIT ESPIR EALV EDLVB Reset Value
Interrupts enabled EICON.4 (SFR D8H). other interrupts controlled registers.
ESEC Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). Write: mask this interrupt masked, enabled. Read: Current value Seconds Timer Interrupt before masking. Enable Summation Interrupt. Write: mask this interrupt masked, enabled. Read: Current value Summation Interrupt before masking. Enable Interrupt. Write: mask this interrupt masked, enabled. Read: Current value Interrupt before masking. Enable Millisecond System Timer Interrupt. Write: mask this interrupt masked, enabled. Read: Current value Millisecond System Timer Interrupt before masking. Enable Transmit Interrupt. Write: mask this interrupt masked, enabled. Read: Current value Transmit Interrupt before masking. Enable Receive Interrupt. Write: mask this interrupt masked, enabled. Read: Current value Receive Interrupt before masking. Enable Analog Voltage Interrupt. Write: mask this interrupt masked, enabled. Read: Current value Analog Voltage Interrupt before masking. Enable Digital Voltage Breakpoint Interrupt (highest priority auxiliary interrupt). Write: mask this interrupt masked, enabled. Read: Current value Digital Voltage Breakpoint Interrupt before masking.
ESUM
EADC
EMSEC
ESPIT
ESPIR
EALV
EDLVB
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Auxiliary Interrupt Status Register (AISTAT)
MSEC SPIT SPIR ALVD DLVD Reset Value
Second System Timer Interrupt Status Flag (lowest priority AI). interrupt inactive masked. Interrupt active. inactive reading SECINT register.) Summation Register Interrupt Status Flag. interrupt inactive masked. interrupt active. inactive reading lowest byte Summation register.) Interrupt Status Flag. interrupt inactive masked active, inactive reading lowest byte Data Output Register). interrupt active. active, data will written Data Output Register.) Millisecond System Timer Interrupt Status Flag. MSEC interrupt inactive masked. MSEC interrupt active. inactive reading MSINT register.) Transmit Interrupt Status Flag. transmit interrupt inactive masked. transmit interrupt active. inactive writing SPIDATA register.) Receive Interrupt Status Flag. receive interrupt inactive masked. receive interrupt active. inactive reading from SPIDATA register.) Analog Voltage Detect Interrupt Status Flag. ALVD interrupt inactive masked. ALVD interrupt active. (Interrupt stays active until AVDD voltage exceeds threshold.) Digital Voltage Detect Breakpoint Interrupt Status Flag (highest priority AI). DLVD interrupt inactive masked. DLVD interrupt active. (Interrupt stays active until DVDD voltage exceeds threshold Breakpoint cleared.)
MSEC
SPIT
SPIR
ALVD
DLVD
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Interrupt Enable (IE)
Reset Value
Global Interrupt Enable. This controls global masking interrupts except those (SFR A6h). Disable interrupt sources. This overrides individual interrupt mask settings this register. Enable individual interrupt masks. Individual interrupts this register will occur enabled. Enable Serial Port Interrupt. This controls masking serial Port interrupt. Disable serial Port interrupts. Enable interrupt requests generated RI_1 (SCON1.0, C0h) TI_1 (SCON1.1, C0h) flags. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupts. Enable interrupt requests generated flag (T2CON.7, C8h). Enable Serial port interrupt. This controls masking serial Port interrupt. Disable serial Port interrupts. Enable interrupt requests generated RI_0 (SCON0.0, 98h) TI_0 (SCON0.1, 98h) flags. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupt. Enable interrupt requests generated flag (TCON.7, 88h). Enable External Interrupt This controls masking external interrupt Disable external interrupt Enable interrupt requests generated INT1 pin. Enable Timer Interrupt. This controls masking Timer interrupt. Disable Timer interrupts. Enable interrupt requests generated flag (TCON.5, 88h). Enable External Interrupt This controls masking external interrupt Disable external interrupt Enable interrupt requests generated INT0 pin.
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Breakpoint Control (BPCON)
PMSEL Reset Value
Writing register sets breakpoint condition specified MCON, BPL, BPH.
Breakpoint Interrupt. This indicates that break condition been recognized hardware breakpoint register(s). Read: Status Breakpoint Interrupt. Will indicate breakpoint match breakpoint registers. Write: effect. Clear Breakpoint breakpoint register selected MCON (SFR 95h). Program Memory Select. Write this select memory address breakpoints register selected MCON (SFR 95h). Break address data memory. Break address program memory. Enable Breakpoint. This enables this breakpoint register. Address breakpoint register selected MCON (SFR 95h). Breakpoint disabled. Breakpoint enabled.
PMSEL
Breakpoint (BPL) Address Register Selected MCON (95h)
BPL.7 BPL.6 BPL.5 BPL.4 BPL.3 BPL.2 BPL.1 BPL.0 Reset Value
BPL.7-0 bits
Breakpoint Address. bits 16-bit breakpoint address.
Breakpoint High Address (BPH) Address Register Selected MCON (95h)
BPH.7 BPH.6 BPH.5 BPH.4 BPH.3 BPH.2 BPH.1 BPH.0 Reset Value
BPH.7-0 bits
Breakpoint High Address. high bits 16-bit breakpoint address.
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Port Data Direction Register (P0DDRL)
P03H P03L P02H P02L P01H P01L P00H P00L Reset Value
P0.3 bits
Port Control.
P03H P03L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P0.2 bits
Port Control.
P02H P02L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P0.1 bits
Port Control.
P01H P01L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P0.0 bits
Port Control.
P00H P00L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
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Port Data Direction High Register (P0DDRH)
P07H P07L P06H P06L P05H P05L P04H P04L Reset Value
P0.7 bits
Port Control.
P07H P07L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P0.6 bits
Port Control.
P06H P06L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P0.5 bits
Port Control.
P05H P05L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P0.4 bits
Port Control.
P04H P04L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
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Port Data Direction Register (P1DDRL)
P13H P13L P12H P12L P11H P11L P10H P10L Reset Value
P1.3 bits
Port Control.
P13H P13L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P1.2 bits
Port Control.
P12H P12L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P1.1 bits
Port Control.
P11H P11L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P1.0 bits
Port Control.
P10H P10L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
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Port Data Direction High Register (P1DDRH)
P17H P17L P16H P16L P15H P15L P14H P14L Reset Value
P1.7 bits
Port Control.
P17H P17L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P1.6 bits
Port Control.
P16H P16L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P1.5 bits
Port Control.
P15H P15L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P1.4 bits
Port Control.
P14H P14L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
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Port (P3)
P3.7 P3.6 P3.5 P3.4 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 Reset Value
P3.7-0 bits
General-Purpose Port This register functions general-purpose port. addition, pins have alternative function listed below. Each functions controlled several other SFRs. associated Port latch must contain logic before used alternate function capacity. External Data Memory Read Strobe. This provides active read strobe external memory device. Port Port selected external memory HCR1 register, this function will enabled even written this latch bit. When external memory selected, settings P3DRRH ignored. External Data Memory Write Strobe. This provides active write strobe external memory device. Port Port selected external memory HCR1 register, this function will enabled even written this latch bit. When external memory selected, settings P3DRRH ignored. Timer/Counter External Input. transition this will increment Timer
INT1 INT0 TXD0 RXD0
Timer/Counter External Input. transition this will increment Timer
External Interrupt falling edge/low level this will cause external interrupt enabled.
External Interrupt falling edge/low level this will cause external interrupt enabled.
Serial Port Transmit. This transmits serial Port data serial port modes emits synchronizing clock serial port mode Serial Port Receive. This receives serial Port data serial port modes bidirectional data transfer serial port mode
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Port Data Direction Register (P2DDRL)
P23H P23L P22H P22L P21H P21L P20H P20L Reset Value
P2.3 bits
Port Control.
P23H P23L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P2.2 bits
Port Control.
P22H P22L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P2.1 bits
Port Control.
P21H P21L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P2.0 bits
Port Control.
P20H P20L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
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Port Data Direction High Register (P2DDRH)
P27H P27L P26H P26L P25H P25L P24H P24L Reset Value
P2.7 bits
Port Control.
P27H P27L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P2.6 bits
Port Control.
P26H P26L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P2.5 bits
Port Control.
P25H P25L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P2.4 bits
Port Control.
P24H P24L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
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Port Data Direction Register (P3DDRL)
P33H P33L P32H P32L P31H P31L P30H P30L Reset Value
P3.3 bits
Port Control.
P33H P33L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P3.2 bits
Port Control.
P32H P32L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P3.1 bits
Port Control.
P31H P31L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P3.0 bits
Port Control.
P30H P30L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
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Port Data Direction High Register (P3DDRH)
P37H P37L P36H P36L P35H P35L P34H P34L Reset Value
P3.7 bits
Port Control.
P37H P37L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
P3.6 bits
Port Control.
P36H P36L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
NOTE: Port also controlled Memory Access Control HCR1.1.
P3.5 bits
Port Control.
P35H P35L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
P3.4 bits
Port Control.
P34H P34L Standard 8051 (Pull-Up) CMOS Output Open Drain Output Input
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Interrupt Priority (IP)
Reset Value
Serial Port Interrupt. This controls priority serial Port interrupt. Serial Port priority determined natural priority order. Serial Port high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. Serial Port Interrupt. This controls priority serial Port interrupt. Serial Port priority determined natural priority order. Serial Port high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. External Interrupt This controls priority external interrupt External interrupt priority determined natural priority order. External interrupt high priority interrupt. Timer Interrupt. This controls priority Timer interrupt. Timer priority determined natural priority order. Timer priority high priority interrupt. External Interrupt This controls priority external interrupt External interrupt priority determined natural priority order. External interrupt high priority interrupt.
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Serial Port Control (SCON1)
SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 Reset Value
SM0-2 bits
Serial Port Mode. These bits control mode serial Port Modes have start stop addition data bits.
MODE 1(2) FUNCTION Synchronous Synchronous Asynchronous Valid Stop Required(3) Asynchronous Asynchronous with Multiprocessor Communication(4) Asynchronous Asynchronous with Multiprocessor Communication(4) LENGTH bits bits bits bits bits bits bits bits PERIOD pCLK(1) pCLK(1) Timer Baud Rate Equation Timer Baud Rate Equation pCLK(1) (SMOD pCLK(1) (SMOD pCLK(1) (SMOD pCLK(1) (SMOD Timer Baud Rate Equation Timer Baud Rate Equation
pCLK will equal tCLK, except that pCLK will stop IDLE. modes selection Timer baud rate specified T2CON (C8h) register. RI_0 will only activated when valid STOP received. RI_0 will activated
REN_1
Receive Enable. This enables/disables serial Port received shift register. Serial Port reception disabled. Serial Port received enabled (modes Initiate synchronous reception (mode Transmission State. This defines state transmission serial Port modes
TB8_1 RB8_1 TI_1
Received State. This identifies state reception received data serial Port modes serial port mode when SM2_1 RB8_1 state stop bit. RB8_1 used mode Transmitter Interrupt Flag. This indicates that data serial Port buffer been completely shifted out. serial port mode TI_1 data bit. other modes, this last data bit. This must cleared software transmit next byte. Receiver Interrupt Flag. This indicates that byte data been received serial Port buffer. serial port mode RI_1 bit. serial port mode RI_1 after last sample incoming stop subject state SM2_1. modes RI_1 after last sample RB8_1. This must cleared software receive next byte.
RI_1
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Serial Data Buffer (SBUF1)
Reset Value
SBUF1.7-0 Serial Data Buffer Data serial Port read from written this location. serial transmit receive bits buffers separate registers, both addressed this location.
Enable Wake (EWU) Waking from IDLE Mode
EWUWDT EWUEX1 EWUEX0 Reset Value
Auxiliary interrupts will wake from IDLE. They enabled with (EICON.5, D8h).
EWUWDT Enable Wake Watchdog Timer. Wake using watchdog timer interrupt. Don't wake watchdog timer interrupt. Wake watchdog timer interrupt. Enable Wake External Wake using external interrupt source Don't wake external interrupt source Wake external interrupt source Enable Wake External Wake using external interrupt source Don't wake external interrupt source Wake external interrupt source
EWUEX1
EWUEX0
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Timer Control (T2CON)
EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2 Reset Value
EXF2
Timer Overflow Flag. This flag will when Timer overflows from FFFFh. must cleared software. will only RCLK TCLK both cleared Writing forces Timer interrupt enabled. Timer External Flag. negative transition T2EX (P1.1) will cause this flag based EXEN2 (T2CON.3) bit. negative transition, this flag must cleared software. Setting this software will force timer interrupt enabled. Receive Clock Flag. This determines serial Port timebase when receiving data serial modes Timer overflow used determine receiver baud rate USART0. Timer overflow used determine receiver baud rate USART0. Setting this will force Timer into baud rate generation mode. timer will operate from divide external clock. Transmit Clock Flag. This determines serial Port timebase when transmitting data serial modes Timer overflow used determine transmitter baud rate USART0. Timer overflow used determine transmitter baud rate USART0. Setting this will force Timer into baud rate generation mode. timer will operate from divide external clock. Timer External Enable. This enables capture/reload function T2EX Timer generating baud rates serial port. Timer will ignore external events T2EX. Timer will capture reload value negative transition detected T2EX pin. Timer Control. This enables/disables operation Timer Halting this timer will preserve current count TH2, TL2. Timer halted. Timer enabled. Counter/Timer Select. This determines whether Timer will function timer counter. Independent this bit, Timer runs clocks tick when used baud rate generator mode. Timer functions timer. speed Timer determined (CKCON.5). Timer will count negative transitions (P1.0). Capture/Reload Select. This determines whether capture reload function used Timer either RCLK TCLK set, this will function timer will function auto-reload mode following each overflow. Auto-reloads will occur when Timer overflows falling edge detected T2EX EXEN2 Timer captures will occur when falling edge detected T2EX EXEN2
RCLK
TCLK
EXEN2
C/T2
CP/RL2
Timer Capture (RCAP2L)
Reset Value
RCAP2L bits
Timer Capture LSB. This register used capture value when Timer configured capture mode. RCAP2L also used 16-bit reload value when Timer configured auto-reload mode.
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Timer Capture (RCAP2H)
Reset Value
RCAP2H bits
Timer Capture MSB. This register used capture value when Timer configured capture mode. RCAP2H also used 16-bit reload value when Timer configured auto-reload mode.
Timer (TL2)
Reset Value
bits
Timer LSB. This register contains least significant byte Timer
Timer (TH2)
Reset Value
bits
Timer MSB. This register contains most significant byte Timer
Program Status Word (PSW)
Reset Value
RS1, bits
Carry Flag. This when last arithmetic operation resulted carry (during addition) borrow (during subtraction). Otherwise, cleared arithmetic operations. Auxiliary Carry Flag. This last arithmetic operation resulted carry into (during addition), borrow (during subtraction) from high-order nibble. Otherwise, cleared arithmetic operations. User Flag This bit-addressable, general-purpose flag software control.
Register Bank Select 1-0. These bits select which register bank addressed during register accesses.
REGISTER BANK ADDRESS
Overflow Flag. This last arithmetic operation resulted carry (addition), borrow (subtraction), overflow (multiply divide). Otherwise cleared arithmetic operations. User Flag This bit-addressable, general-purpose flag software control.
Parity Flag. This modulo-2 bits accumulator (odd parity); cleared even parity.
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Offset Calibration Register Byte (OCL)
Reset Value
bits
Offset Calibration Register Byte. This byte 24-bit word that contains offset calibration. value that written this location will offset calibration value.
Offset Calibration Register Middle Byte (OCM)
Reset Value
bits
Offset Calibration Register Middle Byte. This middle byte 24-bit word that contains offset calibration. value that written this location will offset calibration value.
Offset Calibration Register High Byte (OCH)
Reset Value
bits
Offset Calibration Register High Byte. This high byte 24-bit word that contains offset calibration. value that written this location will offset calibration value.
Gain Calibration Register Byte (GCL)
Reset Value
bits
Gain Calibration Register Byte. This byte 24-bit word that contains gain calibration. value that written this location will gain calibration value.
Gain Calibration Register Middle Byte (GCM)
Reset Value
bits
Gain Calibration Register Middle Byte. This middle byte 24-bit word that contains gain calibration. value that written this location will gain calibration value.
Gain Calibration Register High Byte (GCH)
Reset Value
bits
Gain Calibration Register High Byte. This high byte 24-bit word that contains gain calibration. value that written this location will gain calibration value.
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Multiplexer Register (ADMUX)
INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 Reset Value
INP3-0 bits
Input Multiplexer Positive Channel. This selects positive signal input.
INP3 INP2 INP1 INP0 POSITIVE INPUT AIN0 (default) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Temperature Sensor (requires ADMUX FFh)
INN3-0 bits
Input Multiplexer Negative Channel. This selects negative signal input.
INN3 INN2 INN1 INN0 NEGATIVE INPUT AIN0 AIN1 (default) AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Temperature Sensor (requires ADMUX FFh)
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Enable Interrupt Control (EICON)
SMOD1 WDTI Reset Value
SMOD1
Serial Port Mode. When this serial baud rate Port will doubled. Standard baud rate Port (default). Double baud rate Port Enable Auxiliary Interrupt. Auxiliary Interrupt accesses nine different interrupts which masked identified registers (SFR A5h), (SFR A6h), AISTAT (SFR A7h). Auxiliary Interrupt disabled (default). Auxiliary Interrupt enabled. Auxiliary Interrupt Flag. must cleared software before exiting interrupt service routine, after source interrupt cleared. Otherwise, interrupt occurs again. Setting software generates Auxiliary Interrupt, enabled. Auxiliary Interrupt detected (default). Auxiliary Interrupt detected. Watchdog Timer Interrupt Flag. WDTI must cleared software before exiting interrupt service routine. Otherwise, interrupt will occur again. Setting WDTI software generates watchdog time interrupt, enabled. Watchdog timer generate interrupt reset. interrupt available only reset action disabled HCR0. Watchdog Timer Interrupt detected (default). Watchdog Timer Interrupt detected.
WDTI
Results Register Byte (ADRESL)
Reset Value
ADRESL bits
Results Byte. This byte 24-bit word that contains converter results. Reading from this register clears interrupt.
Results Register Middle Byte (ADRESM)
Reset Value
ADRESM bits
Results Middle Byte. This middle byte 24-bit word that contains converter results.
Results Register High Byte (ADRESH)
Reset Value
ADRESH bits
Results High Byte. This high byte 24-bit word that contains converter results.
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Control Register (ADCON0)
EVREF VREFH EBUF PGA2 PGA1 PGA0 Reset Value
Burnout Detect. When enabled this connects positive current source positive channel negative current source negative channel. channel open circuit then results will full-scale. Burnout Current Sources (default). Burnout Current Sources Enable Internal Voltage Reference. internal voltage reference used, should turned save power reduce noise. Internal Voltage Reference Off. Internal Voltage Reference (default). Note that REFIN- must connected AGND. Voltage Reference High Select. internal voltage reference selected 2.5V 1.25V. REFOUT 1.25V. REFOUT 2.5V (default). Enable Buffer. Enable input buffer provide higher input impedance limits input voltage range dissipates more power. Buffer disabled (default). Buffer enabled. Programmable Gain Amplifier. Sets gain from 128.
PGA2 PGA1 PGA0 GAIN (default)
EVREF
VREFH
EBUF
PGA2-0 bits
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Control Register (ADCON1)
OF_UF CAL2 CAL1 CAL0 Reset Value 0000 0000b
OF_UF
Overflow/Underflow. this set, data summation register invalid. Either overflow underflow occurred. cleared writing Polarity. Polarity result Summation register. Bipolar. Unipolar. size size bipolar (twice resolution).
ANALOG INPUT +FSR ZERO -FSR +FSR ZERO -FSR DIGITAL OUTPUT 0x7FFFFF 0x000000 0x800000 0xFFFFFF 0x000000 0x000000
SM1-0 bits
Settling Mode. Selects type filter auto select which defines digital filter settling characteristics.
SETTLING MODE Auto Fast Settling Filter Sinc2 Filter Sinc3 Filter
CAL2-0 bits
Calibration Mode Control Bits.
CAL2 CAL1 CAL0 CALIBRATION MODE Calibration (default) Self-Calibration, Offset Gain Self-Calibration, Offset only Self-Calibration, Gain only System Calibration, Offset only (requires external connection) System Calibration, Gain only (requires external connection) Reserved Reserved
NOTE: Read Value-000b.
Control Register (ADCON2)
Reset Value
DR7-0 bits
Decimation Ratio LSB.
Control Register (ADCON3)
DR10 Reset Value
DR10-8 bits
Decimation Ratio Most Significant Bits. output data rate (ACLK 1)/64/Decimation Ratio.
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Accumulator ACC)
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Reset Value
ACC.7-0 bits
Accumulator. This register serves accumulator arithmetic logic operations.
Summation/Shifter Control (SSCON)
SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 Reset Value
Summation register powered down when powered down. zeroes written this register 32-bit SUMR3-0 registers will cleared. Summation registers will sign extend Bipolar selected ADCON1.
SSCON1-0 Summation/Shift Count. bits
SOURCE SSCON1 SSCON0 MODE Values written registers accumulated when SUMR0 value written (sum/shift ignored) Summation register Enabled. Source ADC, summation count working. Shift Enabled. Summation register shifted Count bits. takes four system clocks execute. Accumulate Shift Enable. Values accumulated Count times then shifted Count.
SCNT2-0 bits
Summation Count. When summation complete interrupt will generated unless masked. Reading SUMR0 register clears interrupt.
SCNT2 SCNT1 SCNT0 SUMMATION COUNT
SHF2-0 bits
Shift Count.
SHF2 SHF1 SHF0 SHIFT DIVIDE
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Summation Register (SUMR0)
Reset Value
SUMR0 bits
Summation Register This least significant byte 32-bit summation register bits Write: Will cause values SUMR3-0 added summation register. Read: Will clear Summation Count Interrupt.
Summation Register (SUMR1)
Reset Value
SUMR1 bits
Summation Register This most significant byte lowest bits summation register bits 8-15.
Summation Register (SUMR2)
Reset Value
SUMR2 bits
Summation Register This most significant byte lowest bits summation register bits 16-23.
Summation Register (SUMR3)
Reset Value
SUMR3 bits
Summation Register This most significant byte 32-bit summation register bits 24-31.
Offset Register (ODAC)
Reset Value
ODAC bits
Offset Register. This register will shift input half full-scale input range. offset value summed with input prior conversion. Writing ODAC turns offset DAC. Offset Sign bit. Positive Negative
Offset
ODAC
bit7
NOTE: ODAC cannot used offset input that buffer used AGND signals.
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Voltage Detect Control (LVDCON)
ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 Reset Value
ALVDIS
Analog Voltage Detect Disable. Enable Detection Analog Supply Voltage Disable Detection Analog Supply Voltage Analog Voltage Detection Level.
ALVD2 ALVD1 ALVD0 VOLTAGE LEVEL AVDD 2.7V (default) AVDD 3.0V AVDD 3.3V AVDD 4.0V AVDD 4.2V AVDD 4.5V AVDD 4.7V External Voltage AIN7 compared 1.2V
ALVD2-0 bits
DLVDIS
Digital Voltage Detect Disable. Enable Detection Digital Supply Voltage Disable Detection Digital Supply Voltage Digital Voltage Detection Level.
DLVD2 DLVD1 DLVD0 VOLTAGE LEVEL DVDD 2.7V (default) DVDD 3.0V DVDD 3.3V DVDD 4.0V DVDD 4.2V DVDD 4.5V DVDD 4.7V External Voltage AIN6 compared 1.2V
DLVD2-0 bits
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Extended Interrupt Enable (EIE)
EWDI Reset Value
EWDI
Enable Watchdog Interrupt. This enables/disables watchdog interrupt. Watchdog timer enabled (SFR FFh) PDCON (SFR F1h) registers. Disable Watchdog Interrupt Enable Interrupt Request Generated Watchdog Timer External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt External Interrupt Enable. This enables/disables external interrupt Disable External Interrupt Enable External Interrupt
Hardware Product Code Register (HWPC0) (read-only)
Reset Value 0000_00xxb MEMORY SIZE
HWPC1.7-0 Hardware Product Code LSB. Read-only. bits
MEMORY SIZE MODEL MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5 FLASH MEMORY 16kB 32kB
Hardware Product Code Register (HWPC1) (read-only)
Reset Value
HWPC1.7-0 Hardware Product Code MSB. Read-only. bits
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Hardware Version Register (HDWVER)
Reset Value
Flash Memory Control (FMCON)
PGERA FRCM BUSY Reset Value
PGERA
Page Erase. MOVX Flash will perform byte write operation MOVX Flash will perform page erase operation Frequency Control Mode. Bypass (default) Delay Line. Saves power when reading Flash (recommended) Write/Erase BUSY Signal. Idle Available Busy
FRCM
BUSY
Flash Memory Timing Control Register (FTCON)
FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 Reset Value
Refer Flash Timing Characteristics.
FER3-0 bits Erase. Flash Erase Time FER) (MSEC tCLK. minimum 10ms needed industrial temperature range. minimum needed commercial temperature range. Write. Flash Write Time FWR) (USEC tCLK. Write time should 30-40µs.
FWR3-0 bits
Register
Reset Value
B.7-0 bits
Register. This register serves second accumulator certain arithmetic operations.
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Power-Down Control Register (PDCON)
PDPWM PDADC PDWDT PDST PDSPI Reset Value
Turning peripheral modules puts MSC1210 lowest power mode.
PDPWM Pulse Width Module Control. Power Down Control. ADC, VREF, Summation registers, Analog Brownout powered down. Analog current Watchdog Timer Control. Watchdog Timer Watchdog Timer Power Down System Timer Control. System Timer System Timer Power Down System Control. System System Power Down
PDADC
PDWDT
PDST
PDSPI
PSEN/ALE Select (PASEL)
PSEN2 PSEN1 PSEN0 ALE1 ALE0 Reset Value
PSEN2-0 bits
PSEN Mode Select.
PSEN2 PSEN1 PSEN0 PSEN MODCLK HIGH
ALE1-0 bits
Mode Select.
ALE1 ALE0 HIGH
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Analog Clock (ACLK)
FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 Reset Value
FREQ6-0
Clock Frequency This value divides system clock create clock.
ACLK frequency
FREQ
(ACLK Decimation
Data Rate
System Reset Register (SRST)
RSTREQ Reset Value
RSTREQ
Reset Request. Setting this then clearing will generate system reset.
Extended Interrupt Priority (EIP)
PWDI Reset Value
PWDI
Watchdog Interrupt Priority. This controls priority watchdog interrupt. watchdog interrupt priority. watchdog interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority. External Interrupt Priority. This controls priority external interrupt External interrupt priority. External interrupt high priority.
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Seconds Timer Interrupt (SECINT)
SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 Reset Value
This system clock divided value 16-bit register MSECH:MSECL. Then, timer tick divided register HMSEC that provides 100
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