3.3V Communications Clock MK2049-45 dual Phase-Locked Loop (PLL)

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

3.3V Communications Clock MK2049-45 dual Phase-Locked Loop (PLL)

Datasheet Thumbnail

Top Searches for this datasheet

MK2049-45
3.3V Communications Clock
MK2049-45 dual Phase-Locked Loop (PLL) device which provide frequency synthesis jitter attenuation. first VCXO based uses pullable crystal track signal wander attenuate input jitter. second translator frequency multiplication. Basic configuration determined Mode/Frequency Selection Table. Loop bandwidth damping factor programmable external loop filter component selection. Buffer Mode accepts 50MHz input will provide jitter attenuated output ICLK, ICLK ICLK. this mode MK2049-45 ideal filtering jitter from high frequency clocks. External Mode, ICLK accepts clock will produce output frequencies from table common communciations clock rates, CLK/2. This allows generation clocks frequency-locked backplane clock, simplifying clock synchronization communications systems. MK2049-45 dynamically switched between outputs with same 24.576 crystal. customize these devices many other different frequencies. Contact your representative more details.
Features
Packaged SOIC operation Meets TR62411, ETS300 011, GR-1244
specification MTIE, Pull-in/Hold-in Range, Phase Transients, Jitter Generation Stratum Accepts multiple inputs: backplane clock, Locks (External mode) Buffer Mode allows jitter attenuation input x0.5 outputs Exact internal ratios enable zero error Output rates include submultiples Available (lead) free package also MK2049-34 MK2049-36
Block Diagram
RSET ISET CAP2 CAP1 Optional Crystal Load Caps External Pullable Crystal
ICLK
Reference Divider (used buffer mode only)
Phase Detector
VCXO
Charge Pump
Reference Divider
Output Divider Divide
CLK/2
VCXO
Feedback Divider
Translator
Feedback Divider
FS3:0
Divider Value Look-up Table
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2049-45 3.3V Communications Clock
Assignment
FCAP CLK/2 CAP2 CAP1 ICLK
Descriptions
Number
Name
FCAP CLK/2 ICLK CAP1
Type
Input Input Input Power Power Power Output Output Output Input Input Input Power Power Loop Filter Power
Frequency select Determines input/outputs table page Internal pull-up resistor. Crystal connection. Connect crystal shown table page Crystal connection. Connect crystal shown table page Power supply. Connect +3.3V. Filter capacitor. Connect 1000 ceramic capacitor ground. Power supply. Connect +3.3V. Connect ground Clock output determined status FS3:0 tables page Clock output determined status FS3:0 tables page Always CLK. Recovered clock output. Frequency select Determines input/outputs table page Internal pull-up resistor. Frequency select Determines input/outputs table page Internal pull-up resistor. Input clock connection. Connect backplane clock. Connect ground. Power Supply. Connect +3.3V. Connect loop filter capacitors resistor between this CAP2. Connect ground.
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2049-45 3.3V Communications Clock
Number
Name
CAP2
Type
Loop Filter Input
Connect loop filter capacitors resistor between this CAP1. Connect resistor ground. table. Frequency select Determines input/outputs table page Internal pull-up resistor.
Output Decoding Table External Mode (MHz)
ICLK CLK/2 1.544 2.048 22.368 17.184 19.44 12.8 25.92 4.096 18.528 12.352 24.576 16.384 17.28 62.5 3.088 4.096 44.736 34.368 38.88 25.6 51.84 8.192 37.056 24.704 49.152 32.768 34.56 Crystal Used (MHz) 24.576 24.576 24.576 24.576 19.44 25.6 17.28 16.384 24.704 24.704 16.384 16.384 17.28 3072 3072 3072 3072 2430 3200 2160 2048 3088 3088 2048 2048 2160 3125
Output Decoding Table Buffer Mode (MHz)
ICLK CLK/2 ICLK ICLK/2 2*ICLK ICLK Crystal ICLK/2 ICLK
connect directly ground, connect directly Crystal connected pins clock input applied
Functional MK2049-45 clock generator that generates output clock directly from internal VCXO circuit which works conjunction with external quartz crystal. VCXO controlled internal (Phase Locked Loop) circuit, enabling device perform clock regeneration from input reference clock. MK2049-45 configured provide high frequency communications reference clock output from input clock jitter attenuate buffer high frequency input clock. There selectable output frequencies buffer mode selections. Please refer Output Clock Selection Table Page Most typical clock devices internal (Voltage Controlled Oscillator) output clock generation. using VCXO with external crystal,
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2049-45 3.3V Communications Clock
MK2049-45 able generate jitter, phase-noise output clock within bandwidth PLL. This serves provide input clock jitter attenuation enables stable operation with frequency reference clock. VCXO circuit requires external pullable crystal operation. External loop filter components enable configuration with loop bandwidth.
obtain list qualified crystal devices please visit website
Loop Filter Components
analog circuits loop filter establish operating stability. MK2049-45 uses external loop filter components following reasons: Larger loop filter capacitor values used, allowing lower loop bandwidth. This enables lower input clock reference frequencies also input clock jitter attenuation capabilities. Larger loop filter capacitors also allow higher loop damping factors when less passband peaking desired. loop filter values user selected optimize loop response characteristics given application. Referencing External Component Schematic this page, external loop filter made components RSET establishes charge pump current therefore influences loop filter characteristics. Tools optimizing values these four components found
Application Information
Output Frequency Configuration
MK2049-45 configured generate output frequencies from input clock. Please refer Output Clock Selection Table Page Input bits FS3:0 according this table, external crystal frequency. Please refer Quartz Crystal section this page regarding external crystal requirements.
Quartz Crystal
important that correct type quartz crystal used with MK2049-45. Failure result reduced frequency pullability range, inability loop lock, excessive output phase jitter. MK2049-45 operates phase-locking VCXO circuit input signal selected ICLK input. VCXO consists external crystal integrated VCXO oscillator circuit. achieve best performance reliability, crystal device with recommended parameters (shown below) must used, layout guidelines discussed Layout Recommendations section must followed. frequency oscillation quartz crystal determined external load capacitance. MK2049-45 incorporates variable load capacitors on-chip which "pull", change, frequency crystal. crystals specified with MK2049-45 designed have zero frequency error when total on-chip stray capacitance achieve this, layout should short traces between MK2049-45 crystal. complete description recommended crystal parameters application note, MAN05.
CAP2 0.0003 CAP1 kohms
Figure Typical Loop Filter
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2049-45 3.3V Communications Clock
Charge Pump Current Table
RSET 13.02 Charge Pump Current (ICP) (µA)
Connection 3.3V Power Plane Bulk Decoupling Capacitor (such Tantalum) Ferrite Bead
Recommended Power Supply Connection Optimal Device Performance
0.01 Decoupling Capacitors
Crystal Load Capacitors
device crystal connections should include pads small capacitors from ground from ground, shown External Component Schematic. These capacitors used adjust stray capacitance board match nominally required crystal load capacitance. Because load capacitance only increased this trimming process, important keep stray capacitance minimum using very short traces (and vias) been crystal device. Please refer MAN05 procedure determine capacitor values.
Special considerations must made choosing loop components These recommendations found
Series Termination Resistor
Clock output traces over inch should series termination. series terminate trace commonly used trace impedance), place resistor series with clock line, close clock output possible. nominal impedance clock output (The optional series termination resistor shown External Component Schematic.)
Layout Recommendations
optimum device performance lowest output phase noise, following guidelines should observed. Please also refer Recommended Layout drawing Page Each 0.01 decoupling capacitor should mounted component side board close possible. via's should used between decoupling capacitor pin. trace should kept short possible, should trace ground via. Distance ferrite bead bulk decoupling from device less critical. loop filter components must also placed close CHGP pins. should closest device. Coupling noise from other system
Decoupling Capacitors
with high performance mixed-signal MK2049-45 must isolated from system power supply noise perform optimally. Decoupling capacitors 0.01µF must connected between each ground plane. further guard against interfering system supply noise, MK2049-45 should common connection power plane shown diagram next page. ferrite bead bulk capacitor help reduce lower frequency noise supply that lead output clock phase modulation.
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2049-45 3.3V Communications Clock
signal traces should minimized keeping traces short away from active signal traces. vias should avoided. external crystal should mounted just next device with short traces. traces should routed next each other with minimum spaces, instead they should separated away from other traces. minimize series termination resistor, needed, should placed close clock output. optimum layout with components same side board, minimizing vias through other
signal layers (the ferrite bead bulk decoupling capacitor mounted back). Other signal traces should routed away from MK2049-45. This includes signal traces just underneath device, layers adjacent ground plane layer used device. MAN05 also referenced additional suggestions layout crystal section.
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK2049-45. These ratings, which standard values commercially rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5 VDD+0.5 +85°C +150°C 125°C 250°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
+3.3
Max.
+3.45
Units
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2049-45 3.3V Communications Clock
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +85°C
Parameter
Operating Voltage Supply Current Input High Voltage Input Voltage Input High Current Input Current Input Capacitance, except Output High Voltage (CMOS Level) Output High Voltage Output Voltage Short Circuit Current VIN, VCXO Control Voltage
Symbol
Conditions
Clock outputs unloaded, 3.3V
Min.
3.15
Typ.
Max.
3.45
Units
VDD-0.4
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +85°
Parameter
VCXO Crystal Pull Range Input Jitter Tolerance Input pulse width Output Duty Cycle high time) Output Rise Time Output Fall Time Skew, ICLK Output Clock Note Timing Jitter, Filtered 500Hz-1.3MHz (OC-3)
Symbol
Conditions
Using Recommended Crystal reference input clock period
Min.
-115
Typ.
Max. Units
+115
Measured VDD/2, CL=15pF 2.0V, CL=15 0.8V, CL=15 output clock selections except 1.544 2.048 Referenced Mitel/Zarlink MT9045, Note
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2049-45 3.3V Communications Clock
Parameter
Timing Jitter, Filtered 65kHz-1.3MHz (OC-3) Frequency Error Nominal Output Impedance
Symbol
Conditions
Referenced Mitel/Zarlink MT9045, Note Relative ICLK
Min.
Typ.
Max. Units
ZOUT
Note Minimum high time input clock. Note 1.544 2.048 output selections, input output clock skew controlled predictable will change between power cycles. Because dependent phase relationship between output feedback divider states following power input output clock skew will remain stable during given power cycle. controlled input output skew desired this output clock frequency please refer MK2049 MK2069 products. Note Input reference output from Mitel/Zarlink MT9045 device freerun mode (SEL2:0 100, 19.44 external crystal).
Marking Diagram
MK2049-45SI ###### YYWW
Marking Diagram free)
MK2049-45SILF ###### YYWW
Notes: ###### number. YYWW last digits year week that part assembled. "LF" designates (lead) free package.
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com
MK2049-45 3.3V Communications Clock
Package Outline Package Dimensions SOIC, Mil. Wide Body)
Package dimensions kept current with JEDEC Publication
Millimeters Symbol Inches
-2.65 1.10 -2.05 2.55 0.33 0.51 0.18 0.32 12.60 13.00 7.40 7.60 1.27 Basic 10.00 10.65 0.25 0.75 0.40 1.27
-0.104 0.0040 -0.081 0.100 0.013 0.020 0.007 0.013 0.496 0.512 0.291 0.299 0.050 Basic 0.394 0.419 0.010 0.029 0.016 0.050
Ordering Information
Part Order Number
MK2049-45SI MK2049-45SITR MK2049-45SILF MK2049-45SILFTR
Marking
MK2049-45SI MK2049-45SI MK2049-45SILF MK2049-45SILF
Shipping Packaging
Tubes Tape Reel Tubes Tape Reel
Package
20-pin SOIC 20-pin SOIC 20-pin SOIC 20-pin SOIC
Temperature
+85° +85° +85° +85°
"LF" denotes (lead) free package. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
2049-45
Revision 101904
Integrated Circuit Systems, Inc. Race Street, Jose, 95126 (408) 297-1201 www.icst.com

3.3V Communications Clock MK2049-45 dual Phase-Locked Loop (PLL)

Top Searches for this datasheet

Other recent searches