16/32-bit microcontrollers; flashless with with 10-bit external memory

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16/32-bit microcontrollers; flashless with with 10-bit external memory

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LPC2210/2220
16/32-bit microcontrollers; flashless with with 10-bit external memory interface
Rev. 2005 Product data sheet
LPC2210/2220 microcontrollers based 32/16 ARM7TDMI-S with real-time emulation embedded trace support. critical code size applications, alternative 16-bit Thumb mode reduces code more than with minimal performance penalty. With package, power consumption, various 32-bit timers, 8-channel 10-bit ADC, channels nine external interrupt pins this microcontroller particularly suitable industrial control, medical systems, access control point-of-sale. LPC2210/2220 provide GPIOs depending configuration. With wide range serial communications interfaces, also very well suited communication gateways, protocol converters embedded soft modems well many other general-purpose applications.
Features
features
16/32-bit ARM7TDMI-S microcontroller LQFP144 TFBGA144 package. 16/64 on-chip static (LPC2210/2220). Serial boot-loader using UART0 provides in-system download programming capabilities. EmbeddedICE-RT Embedded Trace interfaces offer real-time debugging with on-chip RealMonitor software well high speed real-time tracing instruction execution. Eight channel 10-bit converter with conversion time 2.44 32-bit timers (LPC2220 also external event counters) with four capture four compare channels, unit (six outputs), Real-Time Clock (RTC) watchdog. Multiple serial interfaces including UARTs (16C550), Fast I2C-bus (400 kbit/s) SPIs. LPC2220 Synchronous Serial Port (SSP) with data buffers variable length transfers selected replace SPI. Vectored Interrupt Controller (VIC) with configurable priorities vector addresses. Configurable external memory interface with four banks, each 8/16/32 data width. general purpose pins tolerant). nine edge level sensitive external interrupt pins available.
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
60/75 (LPC2210/2220) maximum clock available from programmable on-chip Phase-Locked Loop (PLL) with settling time On-chip integrated oscillator operates with external crystal range with external oscillator MHz. Power saving modes include Idle Power-down. Processor wake-up from Power-down mode external interrupt. Individual enable/disable peripheral functions power optimization. Dual power supply: operating voltage range 1.65 1.95 (1.8 0.15 power supply range (3.3 with tolerant pads. 16/32-bit ARM7TDMI-S processor.
Ordering information
Table Ordering information Package Name LPC2210FBD144 LPC2220FBD144 LPC2220FET144 LQFP144 LQFP144 TFBGA144 Description plastic profile quad flat package; leads; body plastic profile quad flat package; leads; body plastic thin fine-pitch ball grid array package; balls; body Version SOT486-1 SOT486-1 SOT569-1 Type number
Ordering options
Table Ordering options Flash memory Temperature range (°C) Type number
LPC2210FBD144 LPC2220FBD144 LPC2220FET144
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Block diagram
TMS(1) TDI(1) TRST(1) TCK(1) TDO(1) XTAL2 XTAL1
LPC2210/2220
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
system clock
SYSTEM FUNCTIONS VECTORED INTERRUPT CONTROLLER
ARM7TDMI-S
BRIDGE ARM7 local
AMBA (Advanced High-performance Bus)
INTERNAL SRAM CONTROLLER
DECODER BRIDGE DIVIDER CS0(2) A0(2) BLS3 BLS0(2) WE(2) D0(2) SCK0, SCK1
16/64 SRAM
EXTERNAL MEMORY CONTROLLER
(VLSI peripheral bus) EINT3 EINT0 EXTERNAL INTERRUPTS SERIAL INTERFACE
CAP0 CAP1 MAT0 MAT1
CAPTURE/ COMPARE TIMER 0/TIMER
SERIAL INTERFACES
MOSI0, MOSI1 MISO0, MISO1 SSEL0, SSEL1 TXD0, TXD1
AIN3 AIN0 CONVERTER AIN7 AIN4 P0[30:0] P1[31:16], P1[1:0] P2[31:0] P3[31:0] WATCHDOG TIMER GENERAL PURPOSE REAL TIME CLOCK UART0/UART1
RXD0, RXD1 DSR1, CTS1, DCD1,
PWM6 PWM1
PWM0
SYSTEM CONTROL
002aaa793
When test/debug interface used, GPIO/other functions sharing these pins available. Shared with GPIO.
Block diagram
9397 14061 Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Pinning information
Pinning
002aaa794
LPC2210FBD144 LPC2220FBD144
configuration LQFP144
ball index area
LPC2220FET144
002aab245
Transparent view
Ball configuration diagram TFBGA144
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
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Table P2.22/ VDD(3V3) Ball allocation VDDA(1V8) P1.27/ P1.28/ XTAL2 P2.21/ VSSA(PLL) P2.18/ P2.19/ P2.14/ P2.15/ P1.29/ P2.12/ P2.11/ P0.20/ MAT1.3/ SSEL1/ EINT3 P0.19/ MAT1.2/ MOSI1/ CAP1.2 P0.18/ CAP1.3/ MISO1/ MAT1.3 P2.10/ VDD(3V3) P2.7/D7 P2.6/D6 VDD(3V3) VDD(1V8) P2.3/D3 P2.4/D4
Product data sheet Rev. 2005
Koninklijke Philips Electronics N.V. 2005. rights reserved. 9397 14061
Philips Semiconductors
Column
P0.21/ PWM5/ CAP1.3 P0.24
XTAL1
VSSA
RESET
P2.16/
P2.13/
P2.9/D9
P2.5/D5
P2.2/D2
P2.1/D1
VDD(3V3)
P1.19/ TRACEP P2.24/
P0.23
P0.22/ CAP0.0/ MAT0.0
P2.20/
P2.17/
P2.8/D8
P1.30/
P1.20/ TRACES P2.0/D0
P0.17/ CAP1.2/ SCK1/ MAT1.2 P3.30/ BLS1
16/32-bit microcontrollers with external memory interface
P2.25/
P2.23
P0.16/ EINT0/ MAT0.2/ CAP0.2 P3.31/ BLS0 P0.14/ DCD1/ EINT1 P0.13/ DTR1/ MAT1.1 P3.3/A3
P0.15/ RI1/ EINT2
P2.27/ D27/ BOOT1 P2.29/ P0.25
P1.18/ TRACEP P2.28/ n.c.
VDDA(3V3)
P2.26/ D26/ BOOT0
P1.21/ VDD(3V3) PIPESTAT P1.0/CS0
P2.30/ P2.31/ D30/AIN4 D31/AIN5 P0.27/ AIN0/ CAP0.1/ MAT0.1 P3.29/ BLS2/ AIN6 VDD(3V3) P1.17/ TRACEP P3.28/ BLS3/ AIN7 P3.22/ P3.20/ P0.1/ RXD0/ PWM3/ EINT0 P3.14/ P1.25/ EXTIN0 P3.11/
P1.1/OE
P1.22/ P3.2/A2 PIPESTAT P1.23/ P0.11/ PIPESTAT CTS1/ CAP1.1 P0.10/ RTS1/ CAP1.0
P3.1/A1
LPC2210/2220
P0.28/ AIN1/ CAP0.2/ MAT0.2
P0.12/ DSR1/ MAT1.0 P3.4/A4
P3.27/WE P3.26/
VDD(3V3)
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Table P0.29/ AIN2/ CAP0.3/ MAT0.3 P3.25/ Ball allocation .continued P0.30/ AIN3/ EINT3/ CAP0.0 P3.24/ P1.16/ TRACEP VDD(3V3) P0.0/ TXD0/ PWM1 P1.31/ TRST P3.19/ P0.2/ SCL/ CAP0.0 VDD(3V3) P3.15/ P0.4/ SCK0/ CAP0.1 P0.3/ SDA/ MAT0.0/ EINT1 VDD(3V3) P3.12/ P1.24/ TRACEC P0.7/ SSEL0/ PWM2/ EINT2 P0.6/ MOSI0/ CAP0.2 P0.8/ TXD1/ PWM4 P3.7/A7 P0.9/ RXD1/ PWM6/ EINT3 P3.5/A5
Product data sheet Rev. 2005
Koninklijke Philips Electronics N.V. 2005. rights reserved. 9397 14061
Philips Semiconductors
Column
P3.18/
P3.16/
P3.13/
P3.9/A9
VDD(1V8)
P3.23/ A23/ XCLK
P3.21/
P3.17/
P1.26/ RTCK
P0.5/ MISO0/ MAT0.1
P3.10/
P3.8/A8
P3.6/A6
16/32-bit microcontrollers with external memory interface
LPC2210/2220
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
description
Table Symbol P0.0 P0.31 description (LQFP) (TFBGA) Type Description Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins port available. P0.0/TXD0/ PWM1 P0.1/RXD0/ PWM3/EINT0 P0.2/SCL/ CAP0.0 P0.3/SDA/ MAT0.0/EINT1 P0.4/SCK0/ CAP0.1 P0.5/MISO0/ MAT0.1 P0.6/MOSI0/ CAP0.2 P0.7/SSEL0/ PWM2/EINT2 P0.8/TXD1/ PWM4 P0.9/RXD1/ PWM6/EINT3 P0.10/RTS1/ CAP1.0 P0.11/CTS1/ CAP1.1 P0.12/DSR1/ MAT1.0 TXD0 Transmitter output UART0. PWM1 Pulse Width Modulator output RXD0 Receiver input UART0. PWM3 Pulse Width Modulator output EINT0 External interrupt input I2C-bus clock input/output. Open drain output (for I2C-bus compliance). CAP0.0 Capture input Timer channel I2C-bus data input/output. Open drain output (for I2C-bus compliance). MAT0.0 Match output Timer channel EINT1 External interrupt input. SCK0 Serial clock SPI0. clock output from master input slave. CAP0.1 Capture input Timer channel MISO0 Master Slave SPI0. Data input master data output from slave. MAT0.1 Match output Timer channel MOSI0 Master Slave SPI0. Data output from master data input slave. CAP0.2 Capture input Timer channel SSEL0 Slave Select SPI0. Selects interface slave. PWM2 Pulse Width Modulator output EINT2 External interrupt input. TXD1 Transmitter output UART1. PWM4 Pulse Width Modulator output RXD1 Receiver input UART1. PWM6 Pulse Width Modulator output EINT3 External interrupt input. RTS1 Request Send output UART1. CAP1.0 Capture input Timer channel CTS1 Clear Send input UART1. CAP1.1 Capture input Timer channel DSR1 Data Ready input UART1. MAT1.0 Match output Timer channel
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Table Symbol
description .continued (LQFP) (TFBGA) Type Description DTR1 Data Terminal Ready output UART1. MAT1.1 Match output Timer channel DCD1 Data Carrier Detect input UART1. EINT1 External interrupt input. Note: this while RESET forces on-chip boot-loader take over control part after reset.
P0.13/DTR1/ MAT1.1 P0.14/DCD1/ EINT1
P0.15/RI1/ EINT2
Ring Indicator input UART1. EINT2 External interrupt input. EINT0 External interrupt input. MAT0.2 Match output Timer channel CAP0.2 Capture input Timer channel CAP1.2 Capture input Timer channel SCK1 Serial Clock SPI1/SSI/Microwire. SPI/SSI/Microwire clock output from master input slave. MAT1.2 Match output Timer channel CAP1.3 Capture input Timer channel MISO1 Master Slave SPI1. Data input master data output from slave. MAT1.3 Match output Timer channel MAT1.2 Match output Timer channel MOSI1 Master Slave SPI1. Data output from master data input slave.
P0.16/EINT0/ MAT0.2/CAP0.2
P0.17/CAP1.2/ SCK1/MAT1.2
P0.18/CAP1.3/ MISO1/MAT1.3
P0.19/MAT1.2/ MOSI1/CAP1.2
P0.20/MAT1.3/ SSEL1/ EINT3
interface: MOSI line. SSI: DX/RX line (SPI1 master/slave). Microwire: SO/SI line (SPI1 master/slave).
CAP1.2 Capture input Timer channel MAT1.3 Match output Timer channel SSEL1 Slave Select SPI1/Microwire. Used select Microwire interface slave. Frame synchronization case 4-wire SSI. EINT3 External interrupt input. PWM5 Pulse Width Modulator output CAP1.3 Capture input Timer channel CAP0.0 Capture input Timer channel MAT0.0 Match output Timer channel General purpose bidirectional digital port only. General purpose bidirectional digital port only. General purpose bidirectional digital port only. AIN0 converter, input This analog input always connected pin. CAP0.1 Capture input Timer channel MAT0.1 Match output Timer channel
P0.21/PWM5/ CAP1.3 P0.22/CAP0.0/ MAT0.0 P0.23 P0.24 P0.25 P0.27/AIN0/ CAP0.1/MAT0.1
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Table Symbol
description .continued (LQFP) (TFBGA) Type Description AIN1 converter, input This analog input always connected pin. CAP0.2 Capture input Timer channel MAT0.2 Match output Timer channel AIN2 converter, input This analog input always connected pin. CAP0.3 Capture input Timer Channel MAT0.3 Match output Timer channel AIN3 converter, input This analog input always connected pin. EINT3 External interrupt input. CAP0.0 Capture input Timer channel Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. Pins through port available. LOW-active Chip Select signal. (Bank addresses range 8000 0000 80FF FFFF) LOW-active Output Enable signal. TRACEPKT0 Trace Packet, Standard port with internal pull-up. TRACEPKT1 Trace Packet, Standard port with internal pull-up. TRACEPKT2 Trace Packet, Standard port with internal pull-up. TRACEPKT3 Trace Packet, Standard port with internal pull-up. TRACESYNC Trace Synchronization. Standard port with internal pull-up. Note: this while RESET LOW, enables pins P1[25:16] operate Trace port after reset.
P0.28/AIN1/ CAP0.2/MAT0.2
P0.29/AIN2/ CAP0.3/MAT0.3
P0.30/AIN3/ EINT3/CAP0.0
P1.0 P1.31
P1.0/CS0 P1.1/OE P1.16/ TRACEPKT0 P1.17/ TRACEPKT1 P1.18/ TRACEPKT2 P1.19/ TRACEPKT3 P1.20/ TRACESYNC
P1.21/ PIPESTAT0 P1.22/ PIPESTAT1 P1.23/ PIPESTAT2 P1.24/ TRACECLK P1.25/EXTIN0
PIPESTAT0 Pipeline Status, Standard port with internal pull-up. PIPESTAT1 Pipeline Status, Standard port with internal pull-up. PIPESTAT2 Pipeline Status, Standard port with internal pull-up. TRACECLK Trace Clock. Standard port with internal pull-up. EXTIN0 External Trigger Input. Standard with internal pull-up.
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Table Symbol
description .continued (LQFP) (TFBGA) Type Description RTCK Returned Test Clock output. Extra signal added JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional with internal pull-up. Note: this while RESET LOW, enables pins P1[31:26] operate Debug port after reset.
P1.26/RTCK
P1.27/TDO P1.28/TDI P1.29/TCK P1.30/TMS P1.31/TRST P2.0 P2.31
Test Data JTAG interface. Test Data JTAG interface. Test Clock JTAG interface. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line External memory data line
P2.0/D0 P2.1/D1 P2.2/D2 P2.3/D3 P2.4/D4 P2.5/D5 P2.6/D6 P2.7/D7 P2.8/D8 P2.9/D9 P2.10/D10 P2.11/D11 P2.12/D12 P2.13/D13 P2.14/D14 P2.15/D15 P2.16/D16 P2.17/D17 P2.18/D18 P2.19/D19 P2.20/D20 P2.21/D21 P2.22/D22 P2.23/D23 P2.24/D24 P2.25/D25
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Table Symbol P2.26/D26/ BOOT0
description .continued (LQFP) (TFBGA) Type Description External memory data line BOOT0 While RESET LOW, together with BOOT1 controls booting internal operation. Internal pull-up ensures HIGH state left unconnected. External memory data line BOOT1 While RESET LOW, together with BOOT0 controls booting internal operation. Internal pull-up ensures HIGH state left unconnected. BOOT1:0 selects 8-bit memory boot. BOOT1:0 selects 16-bit memory boot. BOOT1:0 selects 32-bit memory boot. BOOT1:0 selects 16-bit memory boot.
P2.27/D27/ BOOT1
P2.28/D28 P2.29/D29 P2.30/D30/ AIN4 P2.31/D31/ AIN5 P3.0 P3.31
External memory data line External memory data line External memory data line AIN4 converter, input This analog input always connected pin. External memory data line AIN5 converter, input This analog input always connected pin. Port Port 32-bit bidirectional port with individual direction controls each bit. operation port pins depends upon function selected Connect Block. External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line External memory address line
P3.0/A0 P3.1/A1 P3.2/A2 P3.3/A3 P3.4/A4 P3.5/A5 P3.6/A6 P3.7/A7 P3.8/A8 P3.9/A9 P3.10/A10 P3.11/A11 P3.12/A12 P3.13/A13 P3.14/A14 P3.15/A15 P3.16/A16 P3.17/A17 P3.18/A18
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Table Symbol P3.19/A19 P3.20/A20 P3.21/A21 P3.22/A22 P3.23/A23/ XCLK P3.24/CS3 P3.25/CS2 P3.26/CS1 P3.27/WE
description .continued (LQFP) (TFBGA) Type Description External memory address line External memory address line External memory address line External memory address line External memory address line XCLK Clock output. LOW-active Chip Select signal. (Bank addresses range 8300 0000 83FF FFFF) LOW-active Chip Select signal. (Bank addresses range 8200 0000 82FF FFFF) LOW-active Chip Select signal. (Bank addresses range 8100 0000 81FF FFFF) LOW-active Write enable signal. BLS3 LOW-active Byte Lane Select signal (Bank AIN7 converter, input This analog input always connected pin. BLS2 LOW-active Byte Lane Select signal (Bank AIN6 converter, input This analog input always connected pin. BLS1 LOW-active Byte Lane Select signal (Bank BLS0 LOW-active Byte Lane Select signal (Bank connected. This MUST pulled device might operate properly. External reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Ground: reference.
P3.28/BLS3/ AIN7 P3.29/BLS2/ AIN6 P3.30/BLS1 P3.31/BLS0 n.c. RESET
XTAL1 XTAL2
103, 107, 111,
L10, K12, F13, D11, B13, B11,
VSSA
Analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. core power supply: This power supply voltage internal circuitry.
VSSA(PLL)
VDD(1V8)
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Table Symbol VDDA(1V8)
description .continued (LQFP) (TFBGA) Type Description Analog core power supply: This power supply voltage internal circuitry. This should nominally same voltage VDD(1V8) should isolated minimize noise error. power supply: This power supply voltage ports.
VDD(3V3)
K10, 104, 112, F12, C13, A11,
VDDA(3V3)
Analog power supply: This should nominally same voltage VDD(3V3) should isolated minimize noise error.
tolerant providing digital functions with levels hysteresis slew rate control. tolerant providing digital functions with levels hysteresis slew rate control. configured input function, this utilizes built-in glitch filter that blocks pulses shorter than Open drain tolerant digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. tolerant providing digital (with levels hysteresis slew rate control) analog input function. configured digital input function, this utilizes built-in glitch filter that blocks pulses shorter than When configured input, digital section disabled. tolerant with built-in pull-up resistor providing digital functions with levels hysteresis slew rate control. pull-up resistor's value ranges from tolerant providing digital input (with levels hysteresis) function only. provides special analog functionality.
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Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Functional description
Architectural overview
ARM7TDMI-S general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit set. 16-bit Thumb set.
Thumb set's 16-bit instruction length allows approach twice density standard code while retaining most ARM's performance advantage over traditional 16-bit processor using 16-bit registers. This possible because Thumb code operates same 32-bit register code. Thumb code able provide code size ARM, performance equivalent processor connected 16-bit memory system.
On-chip static
On-chip static used code and/or data storage. SRAM accessed 8-bits, 16-bits, 32-bits. LPC2210/2220 provides static LPC2220 provides static RAM.
Memory
LPC2210/2220 memory maps incorporate several distinct regions, shown following figures. addition, interrupt vectors re-mapped allow them reside either on-chip boot-loader, external memory BANK0 on-chip static RAM. This described Section 6.20 "System control".
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Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF RESERVED ADDRESS SPACE
EXTERNAL MEMORY BANK3 EXTERNAL MEMORY BANK2 EXTERNAL MEMORY BANK1 EXTERNAL MEMORY BANK0 BOOT BLOCK (RE-MAPPED FROM ON-CHIP MEMORY RESERVED ADDRESS SPACE
0x8400 0000 0x83FF FFFF 0x8300 0000 0x82FF FFFF 0x8200 0000 0x81FF FFFF 0x8100 0000 0x80FF FFFF 0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
KBYTE ON-CHIP STATIC (LPC2220) KBYTE ON-CHIP STATIC (LPC2210)
0x4001 0000 0x4000 FFFF 0x4000 4000 0x4000 3FFF 0x4000 0000 0x3FFF FFFF
RESERVED ADDRESS SPACE
0x0000 0000
002aaa795
LPC2210/2220 memory
Interrupt controller
accepts interrupt request inputs categorizes them Fast Interrupt reQuest (FIQ), vectored IRQ, non-vectored defined programmable settings. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. highest priority. more than request assigned FIQ, combines requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs have middle priority. Sixteen interrupt requests assigned this category. interrupt requests assigned vectored slots, among which slot highest priority slot lowest.
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Product data sheet
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Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Non-vectored IRQs have lowest priority. combines requests from vectored non-vectored IRQs produce signal processor. service routine start reading register from jumping there. vectored IRQs requesting, provides address highest-priority requesting IRQs service routine, otherwise provides address default routine that shared non-vectored IRQs. default routine read another register what IRQs active.
6.4.1 Interrupt sources
Table lists interrupt sources each peripheral function. Each peripheral device interrupt line connected Vectored Interrupt Controller, have several internal interrupt flags. Individual interrupt flags also represent more than interrupt source.
Table Block Core Core TIMER0 TIMER1 UART0 Interrupt sources Flag(s) Watchdog Interrupt (WDINT) Reserved software interrupts only Embedded ICE, DbgCommRX Embedded ICE, DbgCommTX Match (MR0, MR1, MR2, MR3) Match (MR0, MR1, MR2, MR3) Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) UART1 Line Status (RLS) Transmit Holding Register empty (THRE) Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) PWM0 SPI0 SPI1 System Control Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) (state change) SPIF, MODF SPIF, MODF TXRIS, RXRIS, RTRIS, RORRIS Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt (EINT0) External Interrupt (EINT1) External Interrupt (EINT2) External Interrupt (EINT3) converter channel
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated, prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined. control module contains three registers shown Table
Table Address 0xE002 C000 0xE002 C004 0xE002 C014 control module registers Name PINSEL0 PINSEL1 PINSEL2 Description function select register function select register function select register Access read/write read/write read/write
function select register (PINSEL0 0xE002 C000)
PINSEL0 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions, direction controlled automatically. Settings other than those shown Table reserved, should used
Table PINSEL0 function select register (PINSEL0 0xE002 C000) name P0.0 Value P0.1 P0.2 P0.3 P0.4 Function GPIO Port (UART0) PWM1 reserved GPIO Port (UART0) PWM3 EINT0 GPIO Port (I2C-bus) Capture (Timer reserved GPIO Port (I2C-bus) Match (Timer EINT1 GPIO Port (SPI0) Capture (Timer reserved Value after reset
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16/32-bit microcontrollers with external memory interface
function select register (PINSEL0 0xE002 C000) .continued name P0.5 Value Function GPIO Port MISO (SPI0) Match (Timer reserved GPIO Port MOSI (SPI0) Capture (Timer reserved GPIO Port SSEL (SPI0) PWM2 EINT2 GPIO Port UART1 PWM4 reserved GPIO Port (UART1) PWM6 EINT3 GPIO Port 0.10 (UART1) Capture (Timer reserved GPIO Port 0.11 (UART1) Capture (Timer reserved GPIO Port 0.12 (UART1) Match (Timer reserved GPIO Port 0.13 (UART1) Match (Timer reserved GPIO Port 0.14 (UART1) EINT1 reserved Value after reset
Table PINSEL0 11:10
13:12
P0.6
15:14
P0.7
17:16
P0.8
19:18
P0.9
21:20
P0.10
23:22
P0.11
25:24
P0.12
27:26
P0.13
29:28
P0.14
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function select register (PINSEL0 0xE002 C000) .continued name P0.15 Value Function GPIO Port 0.15 (UART1) EINT2 reserved Value after reset
Table PINSEL0 31:30
function select register (PINSEL1 0xE002 C004)
PINSEL1 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown Table reserved, should used.
Table PINSEL1 function select register (PINSEL1 0xE002 C004) name P0.16 Value P0.17 P0.18 P0.19 P0.20 11:10 P0.21 13:12 P0.22 Function GPIO Port 0.16 EINT0 Match (Timer Capture (Timer GPIO Port 0.17 Capture (Timer (SPI1) Match (Timer GPIO Port 0.18 Capture (Timer MISO (SPI1) Match (Timer GPIO Port 0.19 Match (Timer MOSI (SPI1) Capture (Timer GPIO Port 0.20 Match (Timer SSEL (SPI1) EINT3 GPIO Port 0.21 PWM5 reserved Capture (Timer GPIO Port 0.22 reserved Capture (Timer Match (Timer Value after reset
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function select register (PINSEL1 0xE002 C004) .continued name P0.23 Value Function GPIO Port 0.23 reserved reserved reserved GPIO Port 0.24 reserved reserved reserved GPIO Port 0.25 reserved reserved reserved reserved reserved reserved reserved GPIO Port 0.27 AIN0 (A/D input Capture (Timer Match (Timer GPIO Port 0.28 AIN1 (A/D input Capture (Timer Match (Timer GPIO Port 0.29 AIN2 (A/D input Capture (Timer Match (Timer GPIO Port 0.30 AIN3 (A/D input EINT3 Capture (Timer reserved reserved reserved reserved Value after reset
Table PINSEL1 15:14
17:16
P0.24
19:18
P0.25
21:20
P0.26
23:22
P0.27
25:24
P0.28
27:26
P0.29
29:28
P0.30
31:30
P0.31
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function select register (PINSEL2 0xE002 C014)
PINSEL2 register controls functions pins settings listed Table direction control IODIR register effective only when GPIO function selected pin. other functions direction controlled automatically. Settings other than those shown Table reserved, should used.
Table function select register (PINSEL2 0xE002 C014) Description reserved. When pins P1[36:26] used GPIO pins. When P1[31:26] used Debug port. When pins P1[25:16] used GPIO pins. When P1[25:16] used Trace port. Controls data strobe pins: Pins P2[7:0] P1.0 P1.1 P3.31 Pins P2[15:8] P3.30 Pins P2[27:16] Pins P2[29:28] Pins P2[31:30] Pins P3[29:28] 10:9 15:14 17:16 19:18 P2[7:0] P1.0 P1.1 P3.31 P2[15:8] P3.30 P2[27:16] P2[29:28] reserved P2[31:30] AIN5:4 P3[29:28] AIN6:7 BLS0 D15:8 BLS1 D29, D31, BLS2, BLS3 Reset value P1.26/RTCK P1.20/ TRACESYNC BOOT1:0
PINSEL2 bits
bits controls P3.29: enables P3.29, enables AIN6. bits controls P3.28: enables P3.28, enables AIN7. Controls P3.27: enables P3.27, enables reserved. Controls P3.26: enables P3.26, enables CS1. reserved.
bits 27:25 111, controls P3.23/A23/XCLK: enables P3.23, enables XCLK. Controls P3.25: enables P3.25, enables CS2, reserved values. Controls P3.24: enables P3.24, enables CS3, reserved values. reserved. bits controls P2[29:28]: enables P2[29:28], reserved bits controls P2.30: enables P2.30, enables AIN4. bits controls P2.31: enables P2.31, enables AIN5.
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Table
function select register (PINSEL2 0xE002 C014) .continued Description Controls whether P3.0/A0 port address line (1). Reset value BOOT1:0 RESET otherwise BOOT1 during Reset BOOT1:0 Reset, otherwise
PINSEL2 bits
27:25
Controls whether P3.1/A1 port address line (1). Controls number pins among P3.23/A23/XCLK P3[22:2]/A2[22:2] that address lines: None A11:2 address lines. A3:2 address lines. A15:2 address lines. A5:2 address lines. A19:2 address lines. A7:2 address lines. A23:2 address lines.
31:28
reserved.
External memory controller
external Static Memory Controller module which provides interface between system external (off-chip) memory devices. provides support four independently configurable memory banks each with byte lane enable control) simultaneously. Each memory bank capable supporting SRAM, ROM, Flash EPROM, Burst memory, some external devices. Each memory bank bits wide.
6.10 General purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back, well current state port pins.
6.10.1 Features
Direction control individual bits. Separate control output clear. default inputs after reset. 6.11 10-bit converter
LPC2210/2220 contains single 10-bit successive approximation analog digital converter with eight multiplexed channels.
6.11.1 Features
Measurement range Capable performing more than 400,000 10-bit samples second. Burst conversion mode single multiple inputs. Optional conversion transition input Timer Match signal.
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6.12 UARTs
LPC2210/2220 contains UARTs. UART provides full modem control handshake interface, other provides only transmit receive data lines.
6.12.1 Features
byte Receive Transmit FIFOs. Register locations conform `550' industry standard. Receiver FIFO trigger points bytes Built-in baud rate generator. Standard modem interface signals included UART1. LPC2220 provides enhanced UARTs with fractional baud-rate generators, mechanism software flow control, hardware (CTS/RTS) flow control UART1 only.
6.13 I2C-bus serial controller
I2C-bus bidirectional inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver transmitter with capability both receive send information (such memory)). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master bus, controlled more than master connected I2C-bus implemented LPC2210/2220 supports rate kbit/s (Fast I2C-bus).
6.13.1 Features
Compliant with standard I2C-bus interface. Easy configure Master, Slave, Master/Slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial
data bus.
Serial clock synchronization allows devices with different rates communicate
serial bus.
Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes.
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6.14 serial controller
LPC2210/2220 contains SPIs. full duplex serial interface, designed able handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends byte data slave, slave always sends byte data master.
6.14.1 Features
Compliant with specification. Synchronous, Serial, Full Duplex, Communication. Combined master slave. Maximum data rate eighth input clock rate. 6.15 controller
This peripheral available LPC2220 only.
6.15.1 Features
Compatible with Motorola's SPI, TI's 4-wire SSI, National Semiconductor's
Microwire buses.
Synchronous Serial Communication. Master slave operation. 8-frame FIFOs both transmit receive. Four bits frame.
6.15.2 Description
controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. Data transfers principle full duplex, with frames four bits data flowing from master slave from slave master. While SPI1 peripherals share same physical pins, possible have both these peripherals active same time. Application switch from SPI1 back.
6.16 General purpose timers
Timer/Counter designed count cycles peripheral clock (PCLK) externally supplied clock optionally generate interrupts perform other actions specified timer values, based four match registers. also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt. Multiple pins selected perform single capture match function, providing application with `or' `and', well `broadcast' functions among them.
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LPC2220 count external events capture inputs minimum external pulse equal longer than period PCLK. this configuration, unused capture lines selected regular timer capture inputs.
6.16.1 Features
32-bit Timer/Counter with programmable 32-bit Prescaler. Timer operation (LPC2210/2220) external Event Counter (LPC2220 only). Four 32-bit capture channels timer/counter that take snapshot timer
value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Four external outputs timer/counter corresponding match registers, with
following capabilities: match. HIGH match. Toggle match. nothing match.
6.17 Watchdog timer
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
6.17.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal pre-scaler. Selectable time period from (tpclk (tpclk multiples tpclk
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6.18 Real-time clock
designed provide counters measure time when normal idle operating mode selected. been designed little power, making suitable battery powered systems where running continuously (Idle mode).
6.18.1 Features
Measures passage time maintain calendar clock. Ultra-low power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Programmable Reference Clock Divider allows adjustment match
various crystal frequencies.
6.19 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2210/2220. Timer designed count cycles peripheral clock (PCLK) optionally generate interrupts perform other actions when specified timer values occur, based seven match registers. function also based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. match register (MR0) controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when match occurs. Three match registers used provide output with both edges controlled. Again, match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
6.19.1 Features
Seven match registers allow single edge controlled three double edge
controlled outputs, both types.
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match registers also allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs HIGH beginning each cycle unless output constant LOW. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 6.20 System control
6.20.1 Crystal oscillator
On-chip integrated oscillator operates with external crystal range with external oscillator MHz. oscillator output frequency called fosc processor clock frequency referred CCLK purposes rate equations, etc. fosc CCLK same value unless running connected. Refer Section 6.20.2 "PLL" additional information.
6.20.2
accepts input clock frequency range MHz. input frequency multiplied into range 60/75 (LPC2210/2220) with Current Controlled Oscillator (CCO). multiplier integer value from practice, multiplier value cannot higher than this family microcontrollers upper frequency limit CPU). operates range MHz, there additional divider loop keep within frequency range while providing desired output frequency. output divider divide produce output clock. Since minimum output divider value insured that output duty cycle. turned bypassed following chip Reset enabled software. program must configure activate PLL, wait Lock, then connect clock source. settling time
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6.20.3 Reset wake-up timer
Reset sources LPC2210/2220: RESET watchdog reset. RESET Schmitt trigger input with additional glitch filter. Assertion chip Reset source starts wake-up timer (see wake-up timer description below), causing internal chip reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, on-chip circuitry completed initialization. When internal Reset removed, processor begins executing address which Reset vector. that point, processor peripheral registers have been initialized predetermined values. wake-up timer ensures that oscillator other analog functions required chip operation fully functional before processor allowed execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up timer. wake-up timer monitors crystal oscillator means checking whether safe begin code execution. When power applied chip, some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g. capacitors), characteristics oscillator itself under existing ambient conditions.
6.20.4 External interrupt inputs
LPC2210/2220 includes nine edge level sensitive External Interrupt Inputs selectable functions. When pins combined, external events processed four independent interrupt signals. External Interrupt Inputs optionally used wake processor from Power-down mode.
6.20.5 Memory mapping control
Memory Mapping Control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom BANK0 external memory, on-chip static RAM. This allows code running different memory spaces have control interrupts.
6.20.6 Power control
LPC2210/2220 supports reduced power modes: Idle mode Power-down mode. Idle mode, execution instructions suspended until either reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates power used processor itself, memory systems related controllers, internal buses.
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Power-down mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Power-down mode logic levels chip output pins remain static. Power-down mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Power-down mode reduces chip power consumption nearly zero. Power Control Peripherals feature allows individual peripherals turned they needed application, resulting additional power savings.
6.20.7
divider determines relationship between processor clock (CCLK) clock used peripheral devices (PCLK). divider serves purposes. first provide peripherals with desired PCLK that they operate speed chosen processor. order achieve this, slowed down processor clock rate. Because must work properly power-up (and timing cannot altered does work since divider control registers reside bus), default condition reset processor clock rate. second purpose divider allow power savings when application does require peripherals full processor rate. Because divider connected output, remains active running) during Idle mode.
6.21 Emulation debugging
LPC2210/2220 supports emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs Port This means that communication, timer interface peripherals residing Port available during development debugging phase they when application embedded system itself.
6.21.1 Embedded
Standard EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access core. core Debug Communication Channel function built-in. debug communication channel allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. debug communication channel accessed co-processor program running ARM7TDMI-S core. debug communication channel allows JTAG port used sending receiving data without affecting normal program flow. debug communication channel data control registers mapped addresses EmbeddedICE logic.
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6.21.2 Embedded trace
Since LPC2210/2220 significant amounts on-chip memory, possible determine processor core operating simply observing external pins. Embedded Trace Macrocell (ETM) provides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external trace port analyzer must capture trace information under software debugger control. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers. Since trace information compressed software debugger requires static image code being executed. Self-modifying code cannot traced because this restriction.
6.21.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using Debug Communications Channel (DCC), which present EmbeddedICE logic. LPC2210/2220 contains specific configuration RealMonitor software programmed into on-chip memory.
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Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol VDD(1V8) VDD(3V3) VDDA(3V3) Parameter supply voltage, internal rail supply voltage, external rail analog supply voltage analog input voltage related pins input voltage, tolerant pins input voltage, other pins Tstg Ptot(pack) supply current supply ground current ground storage temperature based package heat transfer, device power consumption total power dissipation
Conditions
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5
+2.5 +3.6 VDD(3V3)
Unit
following applies Limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted. Including voltage outputs 3-state mode. Only valid when VDD(3V3) supply voltage present. exceed peak current limited times corresponding maximum current. Dependent package type.
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Static characteristics
Table Static characteristics Tamb commercial applications, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) Parameter supply voltage external rail supply voltage Conditions 1.65 1.95 Unit
VDDA(3V3) analog supply voltage Standard port pins, RESET, RTCK Ilatch LOW-state input current HIGH-state input current 3-state output leakage current latch-up current pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3)) Vhys IOHS IOLS input voltage output voltage HIGH-state input voltage LOW-state input voltage hysteresis voltage HIGH-state output voltage VDD(3V3) VDD(3V3) output active
VDD(3V3)
VDD(3V3)
LOW-state output voltage LOW-state output current
HIGH-state output current VDD(3V3) HIGH-state short circuit current LOW-state short circuit current pull-down current pull-up current (applies P1[25:16])
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Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol Parameter active mode supply current Conditions VDD(1V8) Tamb code Unit
while(1){}
executed from on-chip RAM, active peripherals CCLK (LPC2210) CCLK (LPC2220) Power-down mode VDD(1V8) Tamb VDD(1V8) Tamb RPDB pull-down boot resistor BOOT1:0 pins system configuration selection unloaded data lines and/or data lines and/or loaded with external memory and/or memory mapped I/Os leaking total additional current Ilkgt I2C-bus pins Vhys HIGH-state input voltage LOW-state input voltage hysteresis voltage LOW-state output voltage IOLS Oscillator pins VXTAL1 VXTAL2
lkgt
0.7VDD(3V3)
0.3VDD(3V3)
0.5VDD(3V3)
input leakage current VDD(3V3)
XTAL1 input voltages XTAL2 output voltages
Typical ratings guaranteed. values listed room temperature (+25 °C), nominal supply voltages. Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition
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Table converter static characteristics VDDA(3V3) Tamb unless otherwise specified. converter frequency MHz. Symbol Ciss EL(adj)
Parameter analog input voltage analog input capacitance differential non-linearity integral non-linearity offset error gain error absolute error
Conditions
VDDA(3V3) ±0.5
Unit
Conditions: VSSA VDDA(3V3) monotonic, there missing codes. differential non-linearity (ED) difference between actual step width ideal step width. Figure integral no-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute voltage error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure
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offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
(LSBideal) offset error
VDDA VSSA 1024
002aaa668
Example actual transfer curve. ideal transfer curve. Differential non-linearity (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
conversion characteristics
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Dynamic characteristics
Table Dynamic characteristics Tamb commercial applications, industrial applications, VDD(1V8), VDD(3V3) over specified ranges Symbol External clock fosc oscillator frequency supplied external oscillator (signal generator) external clock frequency supplied external crystal oscillator external clock frequency on-chip used external clock frequency on-chip boot-loader used initial code download Tclk tCHCX tCLCX tCLCH tCHCL I2C-bus
Parameter
Conditions
Unit
clock period clock HIGH time clock time clock rise time clock fall time rise time fall time pins (P0.2 P0.3) fall time
Tclk Tclk
1000
Port pins (except P0.2 P0.3)
Parameters valid over operating temperature range unless otherwise specified. capacitance from
Table External memory interface dynamic characteristics Tamb Symbol tCHAVR tCHCSL tCHCSH tCHANV tCSLAV tOELAVR tCSLOEL Parameter XCLK HIGH address valid XCLK HIGH XCLK HIGH HIGH XCLK HIGH address invalid address valid address valid
Conditions
Unit
Common Read Write Cycles
Read cycle parameters
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Table External memory interface dynamic characteristics .continued Tamb Symbol tAVDV Parameter memory access time (latest address valid, LOW, data valid) burst-ROM initial memory access time (latest address valid, LOW, data valid) burst-ROM subsequent memory access time (address valid data valid) tSTHDNV data hold time (earliest HIGH, HIGH, address change data invalid) HIGH HIGH HIGH address invalid XCLK HIGH XCLK HIGH HIGH address valid data valid data valid data valid HIGH HIGH address invalid HIGH data invalid HIGH address invalid XCLK HIGH data valid XCLK HIGH XCLK HIGH XCLK HIGH HIGH XCLK HIGH HIGH XCLK HIGH data invalid
Conditions
Unit
Tcclk WST1) (-20)
Tcclk WST1) (-20)
Tcclk (-20)
tCSHOEH tOEHANV tCHOEL tCHOEH tAVCSLW tCSLDVW tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tWEHANV tWEHDNV tBLSHANV tCHDV tCHWEL tCHHBLSL tCHWEH tCHBLSH tCHDNV
Tcclk Tcclk WST2) Tcclk WST2) Tcclk Tcclk) Tcclk Tcclk)
Write cycle parameters
Tcclk WST2) Tcclk WST2) Tcclk Tcclk) Tcclk Tcclk)
tBLSLBLSH HIGH
tBLSHDNV HIGH data invalid
Except initial access, which case address Tcclk earlier.
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16/32-bit microcontrollers with external memory interface
Table
Standard read access specifications frequency setting round integer Memory access time requirement WRITE INIT
Access cycle
standard read
WRITE INIT
WRITE INIT
standard write
burst read initial
burst read subsequent
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Timing
XCLK tCSLAV tCSHOEH
addr tAVDV data tCSLOEL tOELAVR tCHOEL tCHOEH
002aaa749
tSTHDNV
tOEHANV
External memory read access
XCLK tCSLDVW
tAVCSLW tWELWEH tBLSLBLSH tCSLWEL tWEHANV tCSLBLSL tWELDV tBLSHANV
BLS/WE
addr tCSLDV data tWEHDNV tBLSHDNV
002aaa750
External memory write access
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
0.45
0.2VDD 0.2VDD tCHCX tCHCL tCLCX Tclk
002aaa416
tCLCH
External clock timing
LPC2210 power consumption measurements
current (mA)
002aab452
frequency (MHz)
Test conditions: code executed from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) 1.65 core (typical)
LPC2210 IDD(1V8) active measured different frequencies (CCLK) temperatures
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
current (mA)
002aab453
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) 1.65 core (typical)
LPC2210 IDD(1V8) idle measured different frequencies (CCLK) temperatures
current (µA)
002aab454
-100
temp (°C)
Test conditions: Power-down mode entered executing code from on-chip RAM; peripherals enabled PCONP register. 1.95 core core 1.65 core
LPC2210 IDD(1V8) power-down measured different temperatures
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
LPC2220 power consumption measurements
002aab455
current (mA)
frequency (MHz)
Test conditions: code executed from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) core (typical) 1.65 core (typical)
LPC2220 IDD(1V8) active measured different frequencies (CCLK) temperatures
current (mA)
002aab456
frequency (MHz)
Test conditions: Idle mode entered executing code from on-chip RAM; peripherals enabled PCONP register; PCLK CCLK/4. core (typical) core (typical) 1.65 core (typical)
LPC2220 IDD(1V8) idle measured different frequencies (CCLK) temperatures
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
current (mA)
002aab457
temp (°C)
Test conditions: Power-down mode entered executing code from on-chip RAM; peripherals enabled PCONP register. core (typical) 1.65 core (typical)
LPC2220 IDD(1V8) power-down measured different temperatures
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Package outline
LQFP144: plastic profile quad flat package; leads; body SOT486-1
detail
index
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.75 0.45 0.08 0.08 D(1) E(1)
22.15 22.15 21.85 21.85
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT486-1 REFERENCES 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
Package outline SOT486-1 (LQFP144)
9397 14061 Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
TFBGA144: plastic thin fine-pitch ball grid array package; balls; body
SOT569-1
ball index area detail
ball index area
shape optional
scale
DIMENSIONS original dimensions) UNIT max. 0.36 0.24 0.84 0.74 0.53 0.43 12.2 11.8 11.9 11.7 12.2 11.8 11.9 11.7 0.15 0.08
OUTLINE VERSION SOT569-1
REFERENCES JEDEC MO-216 JEITA
EUROPEAN PROJECTION
ISSUE DATE 03-03-03 03-07-09
Package outline SOT569-1 (TFBGA144)
9397 14061 Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Abbreviations
Table Acronym FIFO GPIO SRAM UART Acronym list Description Analog-to-Digital Converter Central Processing Unit First First General Purpose Input/Output Pulse Width Modulator Random Access Memory Serial Peripheral Interface Serial Synchronous Interface Static Random Access Memory Universal Asynchronous Receiver/Transmitter VLSI Peripheral
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Revision history
Table Revision history Release date 20050530 Data sheet status Product data sheet Change notice Doc. number 9397 14061 Supersedes LPC2210-01 Document LPC2210_2220_2 Modifications:
format this data sheet been redesigned comply with presentation information standard Philips Semiconductors. Added devices LPC2220FET144 LPC2220FBD144. Section 6.20.2: updated Section 6.20.7: updated Table "Static characteristics" page adjusted typical value Preliminary data 9397 12872
LPC2210-01
20040209
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Data sheet status
Level Data sheet status Objective data Preliminary data Product status Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status.
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys license title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Trademarks
Notice referenced brands, product names, service names trademarks property their respective owners. I2C-bus wordmark logo trademarks Koninklijke Philips Electronics N.V.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors
Contact information
additional information, please visit: sales office addresses, send email
9397 14061
Koninklijke Philips Electronics N.V. 2005. rights reserved.
Product data sheet
Rev. 2005
Philips Semiconductors
LPC2210/2220
16/32-bit microcontrollers with external memory interface
Contents
6.4.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.15.2 6.16 6.16.1 6.17 6.17.1 6.18 6.18.1 6.19 6.19.1 6.20 6.20.1 6.20.2 General description Features features Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview. On-chip static RAM. Memory map. Interrupt controller Interrupt sources. connect block function select register (PINSEL0 0xE002 C000) function select register (PINSEL1 0xE002 C004) function select register (PINSEL2 0xE002 C014) External memory controller. General purpose parallel I/O. Features 10-bit converter Features UARTs Features I2C-bus serial controller Features serial controller. Features controller. Features Description General purpose timers Features Watchdog timer. Features Real-time clock Features Pulse width modulator Features System control Crystal oscillator 6.20.3 6.20.4 6.20.5 6.20.6 6.20.7 6.21 6.21.1 6.21.2 6.21.3 Reset wake-up timer External interrupt inputs Memory mapping control Power control Emulation debugging. Embedded ICE. Embedded trace. RealMonitor Limiting values Static characteristics Dynamic characteristics Timing LPC2210 power consumption measurements LPC2220 power consumption measurements Package outline Abbreviations Revision history Data sheet status. Definitions Disclaimers Trademarks Contact information
Koninklijke Philips Electronics N.V. 2005
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights. Date release: 2005 Document number: 9397 14061
Published Netherlands

16/32-bit microcontrollers; flashless with with 10-bit external memory

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