MEMS INERTIAL SENSOR 3-Axis ±2g/±6g Digital Output Voltage Linear Acce
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LIS3LV02DQ
MEMS INERTIAL SENSOR 3-Axis ±2g/±6g Digital Output Voltage Linear Accelerometer
2.16V 3.6V SINGLE SUPPLY OPERATION 1.8V COMPATIBLE I2C/SPI DIGITAL OUTPUT INTERFACES PROGRAMMABLE DATA REPRESENTATION INTERRUPT ACTIVATED MOTION PROGRAMMABLE INTERRUPT THRESHOLD EMBEDDED SELF TEST HIGH SHOCK SURVIVABILITY ECO-PACK COMPLIANT QFPN-28 trimmed better match sensing element characteristics. LIS3LV02DQ user selectable full scale ±2g, capable measuring acceleration over bandwidth axes. device bandwidth selected accordingly application requirements. self-test capability allows user check functioning system device configured generate inertial wake-up/free-fall interrupt signal when programmable acceleration threshold crossed least three axes. LIS3LV02DQ available plastic package specified over temperature range extending from -40°C +85°C. LIS3LV02DQ belongs family products suitable variety applications:
Description
LIS3LV02DQ three axes digital output linear accelerometer that includes sensing element interface able take information from sensing element provide measured acceleration signals external world through I2C/SPI serial interface. sensing element, capable detecting acceleration, manufactured using dedicated process developed produce inertial sensors actuators silicon. interface instead manufactured using CMOS process that allows high level integration design dedicated circuit which factory
Free-Fall detection Motion activated functions portable terminals Antitheft systems Inertial navigation Gaming Virtual Reality input devices Vibration Monitoring Compensation
Order codes
Part number LIS3LV02DQ LIS3LV02DQ-TR Temp. range, Package QFPN-28 QFPN-28 Packing Tray Tape Reel
October 2005
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LIS3LV02DQ
Contents
Block Diagram Description
Block diagram description
Mechanical Electrical specifications
Mechanical characteristics1 Electrical characteristics1 Absolute maximum ratings Terminology
2.4.1 2.4.2 2.4.3 Sensitivity Zero-g level Self Test
Functionality
Sensing element Interface Factory calibration
Application Hints
Soldering Information
Digital Interfaces
Serial Interface
5.1.1 Operation
Interface
5.2.1 5.2.2 5.2.3 Read Write Read 3-wires mode
Register mapping Register Description
WHO_AM_I (0Fh)
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LIS3LV02DQ 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 OFFSET_X (16h) OFFSET_Y (17h) OFFSET_Z (18h) GAIN_X (19h) GAIN_Y (1Ah) GAIN_Z (1Bh) CTRL_REG1 (20h) CTRL_REG2 (21h) CTRL_REG3 (22h) HP_FILTER_RESET (23h) STATUS_REG (27h) OUTX_L (28h) OUTX_H (29h) OUTY_L (2Ah) OUTY_H (2Bh) OUTZ_L (2Ch) OUTZ_H (2Dh) FF_WU_CFG (30h) FF_WU_SRC (31h) FF_WU_ACK (32h) FF_WU_THS_L (34h) FF_WU_THS_H (35h) FF_WU_DURATION (36h) DD_CFG (38h) DD_SRC (39h) DD_ACK (3Ah) DD_THSI_L (3Ch) DD_THSI_H (3Dh) DD_THSE_L (3Eh) DD_THSE_H (3Fh)
Typical performance characteristics
Mechanical Characteristics 25°C
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LIS3LV02DQ Mechanical Characteristics derived from measurement -40°C +85°C temperature range
Electro-Mechanical characteristics 25°C
Package Information Revision history
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Block Diagram Description
Block Diagram Description
Block diagram
Figure Block Diagram
CHARGE AMPLIFIER
Reconstruction Filter
SCL/SPC SDA/SDO/SDI
Reconstruction Filter
Regs Array
Reconstruction Filter
SELF TEST
REFERENCE
TRIMMING CIRCUITS
CLOCK
CONTROL LOGIC INTERRUPT GEN.
RDY/INT
QFPN-28 description
Figure Connection
Reserved
Reserved
RDY/INT
LIS3LV02DQ (TOP VIEW)
Reserved
DIRECTION DETECTABLE ACCELERATIONS
SDA/SDI/SDO
VDD_IO
SCL/SPC
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Block Diagram Description
LIS3LV02DQ
Table
Pin#
description
Name Reserved RDY/INT SDA/ SDI/ Vdd_IO SCL/SPC Internally connected supply Power supply Either leave unconnected connect supply Data ready/inertial wake-up free-fall interrupt Internally connected Serial Data Output Serial Data (SDA) Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) Power supply pads Serial Clock (SCL) Serial Port Clock (SPC) enable I2C/SPI mode selection mode; enabled) Internally connected Optional External clock, used either leave unconnected connect supply Either leave unconnected connect Vdd_IO Power supply Connect Internally connected Function
21-28
Reserved Reserved
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Mechanical Electrical specifications
Table
Symbol
Mechanical Electrical specifications
Mechanical characteristics1
Mechanical Characteristics (All parameters specified Vdd=2.5V, T=25°C unless otherwise noted)
Parameter Measurement range3 Test conditions Full-scale BW=40Hz Full-scale representation Sensitivity Full-scale representation TCS0 Sensitivity Change Temperature Full-scale representation Full-scale axis Full-scale axis Full-scale axis Full-scale axis Full-scale axis Full-scale axis Full-scale axis Full-scale axis TCOff Zero-g Level Change Temperature Delta from 25°C 0.025 LSb/g %/°C mg/°C Min. ±1.8 ±5.6 Typ.2 ±2.0 ±6.0 1024 1074 Max. Unit LSb/g
Dres
Device Resolution
Zero-g Level Offset Accuracy4,5
LTOff
Zero-g Level Offset Long Term Accuracy6
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Mechanical Electrical specifications
LIS3LV02DQ
Table
Symbol
Mechanical Characteristics (continued) (All parameters specified Vdd=2.5V, T=25°C unless otherwise noted)
Parameter Test conditions Best straight line axis Full-scale BW=40Hz Min. Typ.2 Max. Unit
Linearity Best straight line axis Full-scale BW=40Hz
CrAx
Cross Axis Full-scale=2g axis Full-scale=2g axis Full-scale=2g axis Full-scale=6g axis Full-scale=6g axis Full-scale=6g axis
-3.5 ODRx/4
Self test Output Change
System Bandwidth9 Operating Temperature Range Product Weight
gram
Note: product factory calibrated 2.5V. device used from 2.16V 3.6V Typical specifications guaranteed Verified wafer level test measurement initial offset sensitivity Zero-g level offset value after MSL3 preconditioning Offset eliminated enabling built-in high pass filter (HPF) Results accelerated reliability tests. Report available upon request Self Test output changes with power supply. Self test "output change" defined OUTPUT[LSb](Self-test ctrl_reg1=0). 1LSb=1g/1024 12bit representation, Full-Scale Output data reach final value after 5/ODR when enabling Self-Test mode device filtering output data rate. Refer table specifications
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Table
Symbol
Mechanical Electrical specifications
Mechanical Characteristics (All parameters specified Vdd=3.3V, T=25°C unless otherwise noted)
Parameter Measurement range3 Test conditions Full-scale BW=40Hz Full-scale representation Min. ±1.7 ±5.3 Typ.2 ±2.0 ±6.0 1024 0.025 -100 -4.5 -1.8 -2.2 +4.5 +1.8 +2.2 1126 Max. Unit LSb/g LSb/g %/°C mg/°C
Dres
Device Resolution
Sensitivity Full-scale representation
TCS0
Sensitivity Change Temperature
Full-scale representation Full-scale axis Full-scale axis Full-scale axis Full-scale axis Full-scale axis Full-scale axis Full-scale axis Full-scale axis
Zero-g Level Offset Accuracy4,5
LTOff
Zero-g Level Offset Long Term Accuracy6
TCOff
Zero-g Level Change Temperature
Delta from 25°C Best straight line axis Full-scale BW=40Hz
Linearity Best straight line axis Full-scale BW=40Hz
CrAx
Cross Axis
-3.5
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Mechanical Electrical specifications
LIS3LV02DQ
Table
Symbol
Mechanical Characteristics (continued) (All parameters specified Vdd=3.3V, T=25°C unless otherwise noted)
Parameter Test conditions Full-scale=2g axis Full-scale=2g axis Full-scale=2g axis Full-scale=6g axis Full-scale=6g axis Full-scale=6g axis Min. Typ.2 ODRx/4 Max. Unit gram
Self test Output Change
System Bandwidth9 Operating Temperature Range Product Weight
Note: product factory calibrated 2.5V. device used from 2.16V 3.6V Typical specifications guaranteed Verified wafer level test measurement initial offset sensitivity Zero-g level offset value after MSL3 preconditioning Offset eliminated enabling built-in high pass filter (HPF) Results accelerated reliability tests Self Test output changes with power supply. Self test "output change" defined OUTPUT[LSb](Self-test ctrl_reg1=0). 1LSb=1g/1024 12bit representation, Full-Scale Output data reach final value after 5/ODR when enabling Self-Test mode device filtering output data rate. Refer table specifications
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Mechanical Electrical specifications
Table
Symbol Vdd_IO
Electrical characteristics1
Electrical Characteristics (All parameters specified Vdd=2.5V, T=25°C unless otherwise noted)
Parameter Supply voltage pads Supply voltage 25°C, Vdd=2.5V Supply current 25°C, Vdd=3.3V 0.65 0.8*Vdd 0.2*Vdd 0.9*Vdd 0.1*Vdd 25°C factor factor factor factor 2560 ODRx/4 5/ODRx 0.80 Digital High level Input voltage Digital level Input voltage High level Output Voltage level Output Voltage Current consumption Power-down mode Output Data Rate1 Output Data Rate Output Data Rate Output Data Rate System Bandwidth3 Turn-on time4 Operating Temperature Range Test conditions Min. 2.16 1.71 0.60 Typ.2 Max. 0.75 Unit
IddPdn ODR1 ODR2 ODR3 ODR4
Note: product factory calibrated 2.5V. device used from 2.16V 3.6V Typical specifications guaranteed Digital filter cut-off frequency Time obtain valid data after exiting Power-Down mode
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Mechanical Electrical specifications
LIS3LV02DQ
Absolute maximum ratings
Stresses above those listed "absolute maximum ratings" cause permanent damage device. This stress rating only functional operation device under these conditions implied. Exposure maximum rating conditions extended periods affect device reliability. Table
Symbol Vdd_IO Supply voltage pins Supply voltage Input voltage control (CS, SCL/SPC, SDA/SDI/SDO, Acceleration (Any axis, Powered, Vdd=2.5V) 10000g 3000g Acceleration (Any axis, Unpowered) 10000g Operating Temperature Range Storage Temperature Range +125 (HBM) Electrostatic discharge protection (MM) (CDM)
Absolute maximum ratings
Ratings Maximum Value -0.3 -0.3 +0.1 -0.3 Vdd_IO +0.3 3000g Unit
APOW
AUNP TSTG
Note: Supply voltage should never exceed 6.0V.
This Mechanical Shock sensitive device, improper handling cause permanent damages part This sensitive device, improper handling cause permanent damages part
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Mechanical Electrical specifications
2.4.1
Terminology
Sensitivity
Sensitivity describes gain sensor determined e.g. applying acceleration sensor measure accelerations this done easily pointing axis interest towards center earth, noting output value, rotating sensor degrees (point sky) noting output value again. doing acceleration applied sensor. Subtracting larger output value from smaller divide result leads actual sensitivity sensor. This value changes very little over temperature also very little over time. Sensitivity Tolerance describes range Sensitivities large population sensor.
2.4.2
Zero-g level
Zero-g level Offset (Off) describes deviation actual output signal from ideal output signal there acceleration present. sensor steady state horizontal surface will measure axis axis whereas axis will measure output ideally middle dynamic range sensor (content registers 00h, with representation, data expressed complement number). deviation from ideal value this case called Zero-g offset. Offset some extent result stress precise MEMS sensor therefore offset slightly change after mounting sensor onto printed circuit board exposing extensive mechanical stress. Offset changes little over temperature, "Zero-g level change temperature". Zero-g level individual sensor stable over lifetime. Zero-g level tolerance describes range Zero-g levels population sensors.
2.4.3
Self Test
Self Test allows test mechanical electric part sensor, allowing seismic mass moved means electrostatic test-force. Self Test function when self-test ctrl_reg1 (control register programmed `0`. When self-test ctrl_reg1 programmed actuation force applied sensor, simulating definite input acceleration. this case sensor outputs will exhibit change their levels which related selected full scale depending Supply Voltage through device sensitivity. When Self Test activated, device output level given algebraic signals produced acceleration acting sensor electrostatic testforce. output signals change within amplitude specified inside table table than sensor working properly parameters interface chip within defined specification.
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Functionality
LIS3LV02DQ
Functionality
LIS3LV02DQ high performance, low-power, digital output 3-axis linear accelerometer packaged package. complete device includes sensing element interface able take information from sensing element provide signal external world through I2C/SPI serial interface.
Sensing element
proprietary process used create surface micro-machined accelerometer. technology allows carry suspended silicon structures which attached substrate points called anchors free move direction sensed acceleration. compatible with traditional packaging techniques placed sensing element avoid blocking moving parts during moulding phase plastic encapsulation. When acceleration applied sensor proof mass displaces from nominal position, causing imbalance capacitive half-bridge. This imbalance measured using charge integration response voltage pulse applied sense capacitor. steady state nominal value capacitors when acceleration applied maximum variation capacitive load 100fF.
Interface
complete measurement chain composed low-noise capacitive amplifier which converts into analog voltage capacitive unbalancing MEMS sensor three analog-to-digital converters, each axis, that translate produced signal into digital bitstream. converters coupled with dedicated reconstruction filters which remove high frequency components quantization noise provide rate high resolution digital words. charge amplifier converters operated respectively 61.5 20.5 kHz. data rate output reconstruction depends user selected Decimation Factor (DF) spans from 2560 acceleration data accessed through I2C/SPI interface thus making device particularly suitable direct interfacing with microcontroller. LIS3LV02DQ features Data-Ready signal (RDY) which indicates when measured acceleration data available thus simplifying data synchronization digital system employing device itself. LIS3LV02DQ also configured generate inertial Wake-Up, Direction Detection Free-Fall interrupt signal accordingly programmed acceleration event along enabled axes.
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Functionality
Factory calibration
interface factory calibrated sensitivity (So) Zero-g level (Off). trimming values stored inside device volatile structure. time device turned trimming parameters downloaded into registers employed during normal operation. This allows user employ device without further calibration.
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Application Hints
LIS3LV02DQ
Application Hints
Figure LIS3LV02DQ Electrical Connection
10uF
LIS3LV02DQ
(TOP VIEW)
100nF
DIRECTION DETECTABLE ACCELERATIONS
Vdd_IO
SDA/SDI/SDO
RDY/INT
SCL/SPC
Digital signal from/to signal controller.Signal's levels defined proper selection Vdd_IO
device core supplied through line while pads supplied through Vdd_IO line. Power supply decoupling capacitors (100 ceramic, should placed near possible device (common design practice). voltage ground supplies must present same time have proper behavior (refer Fig. possible remove mantaining Vdd_IO without blocking communication busses. functionality device measured acceleration data selectable accessible through I2C/SPI interface.When using I2C, must tied high while must left floating. Refer application note AN2041 further information device usage.
Soldering Information
QFN-28 package lead free green package qualified soldering heat resistance according JEDEC J-STD-020C. Central indicator physically connected GND. Land pattern soldering recommendations available upon request.
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Digital Interfaces
Digital Interfaces
registers embedded inside LIS3LV02DQ accessed through both serial interfaces. latter configured operate either 3-wire 4-wire interface mode. serial interfaces mapped onto same pads. select/exploit interface, line must tied high (i.e connected Vdd_IO). Table Serial interface description
Description enable I2C/SPI mode selection mode; enabled) Serial Clock (SCL) Serial Port Clock (SPC) Serial Data (SDA) Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) Serial Data Output (SDO)
Name
SCL/SPC
SDA/SDI/SDO
Serial Interface
LIS3LV02DQ slave. employed write data into registers whose content also read back. relevant terminology given table below Table
Term Transmitter Receiver Master Slave
Serial interface description
Description device which sends data device which receives data from device which initiates transfer, generates clock signals terminates transfer device addressed master
There signals associated with bus: Serial Clock Line (SCL) Serial DAta line (SDA). latter bidirectional line used sending receiving data to/from interface. Both lines connected Vdd_IO through pull-up resistor embedded inside LIS3LV02DQ. When free both lines high. interface compliant with Fast Mode (400 kHz) standards well Normal Mode.
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Digital Interfaces
LIS3LV02DQ
5.1.1
Operation
transaction started through START (ST) signal. START condition defined HIGH transition data line while line held HIGH. After this been transmitted Master, considered busy. next byte data transmitted after start condition contains address slave first bits eighth tells whether Master receiving data from slave transmitting data slave. When address sent, each device system compares first seven bits after start condition with address. they match, device considers itself addressed Master. Slave ADdress (SAD) associated LIS3LV02DQ 0011101b. Data transfer with acknowledge mandatory. transmitter must release line during acknowledge pulse. receiver must then pull data line that remains stable during HIGH period acknowledge clock pulse. receiver which been addressed obliged generate acknowledge after each byte data been received. embedded inside LIS3LV02DQ behaves like slave device following protocol must adhered After start condition (ST) salve address sent, once slave acknowledge (SAK) been returned, 8-bit sub-address will transmitted: represent actual register address while enables address auto increment. field (register address) will automatically incremented allow multiple data read/write. slave address completed with Read/Write bit. (Read), repeated START (SR) condition will have issued after sub-address bytes; (Write) Master will transmit slave with direction unchanged. Transfer when Master writing byte slave
Master Slave DATA
Transfer when Master writing multiple bytes slave:
Master Slave DATA DATA
Transfer when Master receiving (reading) byte data from slave:
Master Slave DATA NMAK
Transfer when Master receiving (reading) multiple bytes data from slave
Master Slave Master Slave DATA DATA NMAK DATA
Data transmitted byte format (DATA). Each data transfer contains bits. number bytes transferred transfer unlimited. Data transferred with Most Significant (MSb) first. receiver can't receive another complete byte data until performed some other
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Digital Interfaces
function, hold clock line, force transmitter into wait state. Data transfer only continues when receiver ready another byte releases data line. slave receiver doesn't acknowledge slave address (i.e. able receive because performing some real time function) data line must left HIGH slave. Master then abort transfer. HIGH transition line while line HIGH defined STOP condition. Each data transfer must terminated generation STOP (SP) condition. order read multiple bytes, necessary assert most significant subaddress field. other words, SUB(7) must equal while SUB(6-0) represents address first register read. presented communication format Master Acknowledge NMAK Master Acknowledge.
Interface
LIS3LV02DQ slave. allows write read registers device. Serial Interface interacts with outside world with wires: SPC, SDO. Figure Read write protocol
Serial Port Enable controlled master. goes start transmission goes back high end. Serial Port Clock controlled master. stopped high when high transmission). respectively Serial Port Data Input Output. Those lines driven falling edge should captured rising edge SPC. Both Read Register Write Register commands completed clock pulses multiple case multiple byte read/write. duration time between falling edges SPC. first (bit starts first falling edge after falling edge while last (bit starts last falling edge just before rising edge
bit. When data DI(7:0) written into device. When data DO(7:0) from device read. latter case, chip will drive start bit. When address will remain unchanged multiple read/write commands. When address will auto incremented multiple read/write commands. 2-7: address AD(5:0). This address field indexed register.
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Digital Interfaces
LIS3LV02DQ
8-15: data DI(7:0) (write mode). This data that will written into device (MSb first). 8-15: data DO(7:0) (read mode). This data that will read from device (MSb first).
multiple read/write commands further blocks clock periods will added. When address used read/write data remains same every block. When address used read/write data incremented every block. function behavior remain unchanged.
5.2.1
Read
Figure Read protocol
Read command performed with clock pulses. Multiple byte read command performed adding blocks clock pulses previous one.
READ bit. value bit. When increment address, when increment address multiple reading. 2-7: address AD(5:0). This address field indexed register. 8-15: data DO(7:0) (read mode). This data that will read from device (MSb first). 16-. data DO(.-8). Further data multiple byte reading.
Figure
Multiple bytes Read Protocol bytes example)
DO15 DO14 DO13 DO12 DO11 DO10
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Digital Interfaces
5.2.2
Write
Figure Write protocol
Write command performed with clock pulses. Multiple byte write command performed adding blocks clock pulses previous one.
WRITE bit. value bit. When increment address, when increment address multiple writing. address AD(5:0). This address field indexed register. 8-15: data DI(7:0) (write mode). This data that will written inside device (MSb first). 16-. data DI(.-8). Further data multiple byte writing.
Figure
DI15 DI14 DI13 DI12 DI11 DI10
Multiple bytes Write Protocol bytes example)
5.2.3
Read 3-wires mode
3-wires mode entered setting (SPI Serial Interface Mode selection) CTRL_REG2. Figure Read protocol 3-wires mode
SDI/O
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Digital Interfaces
LIS3LV02DQ
Read command performed with clock pulses:
READ bit. value bit. When increment address, when increment address multiple reading. 2-7: address AD(5:0). This address field indexed register. 8-15: data DO(7:0) (read mode). This data that will read from device (MSb first).
Multiple read command also available 3-wires mode.
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Register mapping
Register mapping
table given below provides listing registers embedded device related address. Table Registers address
Register Address Reg. Name Type Binary WHO_AM_I OFFSET_X OFFSET_Y OFFSET_Z GAIN_X GAIN_Y GAIN_Z 0000000 0001110 0001111 0010000 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 -0011111 CTRL_REG1 CTRL_REG2 CTRL_REG3 HP_FILTER RESET 0100000 0100001 0100010 0100011 0100100-0100110 STATUS_REG OUTX_L OUTX_H OUTY_L OUTY_H OUTZ_L OUTZ_H 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 FF_WU_CFG FF_WU_SRC FF_WU_ACK 0110000 0110001 0110010 0110011 FF_WU_THS_L 0110100 1C-1F 24-26 00000000 00000000 00000000 dummy Dummy register Used 00000000 output output output output output output Reserved Used 00000111 00000000 00001000 dummy Dummy register Used Calibration Calibration Calibration Calibration Calibration Calibration 00111010 Reserved Dummy register Reserved Loaded boot Loaded boot Loaded boot Loaded boot Loaded boot Loaded boot Reserved Default Comment
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Register mapping
LIS3LV02DQ
Registers address (continued)
Register Address Type Binary 40-7F 00000000 00000000 00000000 00000000 Reserved 00000000 00000000 dummy Dummy register Used 00000000 00000000 Used 0110101 0110110 0110111 Default Comment
Table
Reg. Name FF_WU_THS_H FF_WU_DURATION
DD_CFG DD_SRC DD_ACK
0111000 0111001 0111010 0111011
DD_THSI_L DD_THSI_H DD_THSE_L DD_THSE_H
0111100 0111101 0111110 0111111 1000000-1111111
Registers marked reserved must changed. writing those registers cause permanent damages device. content registers that loaded boot should changed. They contain factory calibration values. Their content automatically restored when device poweredup.
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Register Description
Register Description
device contains registers which used control behavior retrieve acceleration data. registers contain factory calibration values, necessary change their value normal device operation.
WHO_AM_I (0Fh)
LIS3LV02DQ Physical Address equal
Addressing this register physical address device returned. LIS3LV02DQ physical address assigned factory 3Ah.
OFFSET_X (16h)
OX7,
Digital Offset Trimming X-Axis
OFFSET_Y (17h)
DOY7, DOY0
Digital Offset Trimming Y-Axis
OFFSET_Z (18h)
OZ7,
Digital Offset Trimming Z-Axis
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Register Description
LIS3LV02DQ
GAIN_X (19h)
GX7,
Digital Gain Trimming X-Axis
GAIN_Y (1Ah)
GY7,
Digital Gain Trimming Y-Axis
GAIN_Z (1Bh)
GZ7,
Digital Gain Trimming Z-Axis
CTRL_REG1 (20h)
PD1, DF1,
Power Down Control (00: power-down mode; device Decimation Factor Control (00: decimate 512; decimate 128; decimate decimate Self Test Enable normal mode; self-test active) Z-axis enable axis off; axis Y-axis enable axis off; axis X-axis enable axis off; axis
PD1, allows turn turn device power-down mode. device power-down mode when PD1, PD0= "00" (default value after boot). device normal mode when either DF1, allows select data rate which acceleration samples produced. default value which corresponds data-rate 40Hz. changing content DF1, "01", "10" "11" selected data-rate will respectively equal 160Hz, 640Hz 2560Hz.
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Register Description
used activate self test function. When one, output change will occur device outputs (refer table specification) thus allowing check functionality whole measurement chain. enables Z-axis measurement channel when default value enables Y-axis measurement channel when default value enables X-axis measurement channel when default value
CTRL_REG2 (21h)
BOOT DRDY
BOOT DRDY
Full Scale selection ±2g; ±6g) Block Data Update continuous update; output registers updated until reading) Big/Little Endian selection little endian; endian) Reboot memory content Interrupt ENable data ready pad; pad) Enable Data-Ready generation Serial Interface Mode selection 4-wire interface; 3-wire interface) Data Alignment Selection right justified; left justified)
used select Full Scale value. After device power-up default full scale value +/-2g. order obtain +/-6g full scale necessary `1'. used inhibit output registers update until both upper lower register parts read. default mode (BDU= `0') output register values updated continuously. reason sure read faster than output data rate recommended `1'. this content output registers updated until both read avoiding read values related different sample time. used select Endian Little Endian representation output registers. Endian's acceleration value located addresses (X-axis), (Y-axis) (Z-axis) while acceleration value located addresses (X-axis), (Y-axis) (Z-axis). Little Endian representation (Default, BLE=`0`) order inverted (refer data register description more details). BOOT used refresh content internal registers stored flash memory block. device power content flash memory block transferred internal registers related trimming functions permit good behavior device itself. reason content trimming registers changed sufficient this restore correct values. When BOOT content internal flash copied inside corresponding internal registers used calibrate device. These values factory
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Register Description
LIS3LV02DQ
trimmed they different every accelerometer. They permit good behavior device normally they have changed. boot process BOOT again `0'. used switch value present data-ready between Data-Ready signal Interrupt signal. power Data-ready signal chosen. however necessary modify DRDY enable Data-Ready signal generation. DRDY used enable Data-Ready (RDY/INT) activation. DRDY (default value) Data-Ready value present. Data-Ready signal desired necessary DRDY bit. Data-Ready signal goes whenever data available enabled axis. example Z-axis disabled, Data-Ready signal goes when values available both axis. Data-Ready signal comes back when registers containing values enabled axis read. sure loose data coming from accelerometer data registers must read before Data-Ready rising edge generated. this case Data-ready signal will have same frequency data rate chosen. selects Serial Interface Mode. When (default value) 4-wire interface mode selected. data coming from device sent pad. 3-wire interface mode output data sent SDA_SDI pad. permits decide between right justified left justified representation data coming from device. first case default case most significant bits replaced representing sign.
7.10
CTRL_REG3 (22h)
HPDD HPFF CFS1 CFS0
HPDD HPFF
External Clock. Default value: clock from internal oscillator; clock from external pad) High Pass filter enabled Direction Detection. Default value: filter bypassed; filter enabled) High Pass filter enabled Free-Fall Wake-Up. Default value: filter bypassed; filter enabled) Filtered Data Selection. Default value: internal filter bypassed; data from internal filter) High-pass filter Cut-off Frequency Selection. Default value: (00: Hpc=512 Hpc=1024 Hpc=2048 Hpc=4096)
CFS1, CFS0
enables (FDS=1) bypass (FDS=0) high pass filter signal chain sensor CFS1, CFS0 bits defines coefficient used calculate -3dB cut-off frequency high pass filter: 0.318 ODRx toff -Hpc
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Register Description
7.11
HP_FILTER_RESET (23h)
Dummy register. Reading this address zeroes instantaneously content internal high pass-filter. Read data significant.
7.12
STATUS_REG (27h)
ZYXOR ZYXOR ZYXDA ZYXDA
axis Data Overrun axis Data Overrun axis Data Overrun axis Data Overrun axis Data Available axis Data Available axis Data Available axis Data Available
7.13
OUTX_L (28h)
XD7,
axis acceleration data
Endian Mode (bit CTRL_REG2 `1') content this register acceleration data depends CTR_REG2 described following section.
7.14
OUTX_H (29h)
XD15 XD14 XD13 XD12 XD11 XD10 XD15, axis acceleration data
When reading register right justified" mode most significant bits (15:12) replaced with (i.e. XD15-XD12=XD11, XD11, XD11, XD11). Endian Mode (bit CTRL_REG2 `1') content this register acceleration data.
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Register Description
LIS3LV02DQ
7.15
OUTY_L (2Ah)
YD7,
axis acceleration data
Endian Mode (bit CTRL_REG2 `1') content this register acceleration data depends CTR_REG2 described following section.
7.16
OUTY_H (2Bh)
YD15 YD14 YD13 YD12 YD11 YD10 YD15, axis acceleration data
When reading register right justified" mode most significant bits (15:12) replaced with (i.e. YD15-YD12=YD11, YD11, YD11, YD11). Endian Mode (bit CTRL_REG2 `1') content this register acceleration data.
7.17
OUTZ_L (2Ch)
ZD7,
axis acceleration data
Endian Mode (bit CTRL_REG2 `1') content this register acceleration data depends CTR_REG2 described following section.
7.18
OUTZ_H (2Dh)
ZD15 ZD15, ZD14 ZD13 ZD12 ZD11 ZD10
axis acceleration data
When reading register right justified" mode most significant bits (15:12) replaced with (i.e. ZD15-ZD12=ZD11, ZD11, ZD11, ZD11). Endian Mode (bit CTRL_REG2 `1') content this register acceleration data
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Register Description
7.19
FF_WU_CFG (30h)
ZHIE ZLIE YHIE YLIE XHIE XLIE
And/Or combination Interrupt events interrupt request. Default value: combination interrupt events; combination interrupt events) Latch interrupt request. Default value: interrupt request latched; interrupt request latched) Enable Interrupt request high event. Default value: disable interrupt request; enable interrupt request measured accel. value higher than preset threshold) Enable Interrupt request event. Default value: disable interrupt request; enable interrupt request measured accel. value lower than preset threshold) Enable Interrupt request high event. Default value: disable interrupt request; enable interrupt request measured accel. value higher than preset threshold) Enable Interrupt request event. Default value: disable interrupt request; enable interrupt request measured accel. value lower than preset threshold) Enable Interrupt request high event. Default value: disable interrupt request; enable interrupt request measured accel. value higher than preset threshold) Enable Interrupt request event. Default value: disable interrupt request; enable interrupt request measured accel. value lower than preset threshold)
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Free-fall inertial wake-up configuration register.
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Register Description
LIS3LV02DQ
7.20
FF_WU_SRC (31h)
Interrupt Active. Default value: interrupt been generated; more interrupt event been generated) High. Default value: interrupt; event occurred) Low. Default value: interrupt; event occurred) High. Default value: interrupt; event occurred) Low. Default value: interrupt; event occurred) High. Default value: interrupt; event occurred) Low. Default value: interrupt; event occurred)
7.21
FF_WU_ACK (32h)
Dummy register. FF_WU_CFG=1 allows refresh FF_WU_SRC. Read data significant.
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Register Description
7.22
FF_WU_THS_L (34h)
THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0 THS7, THS0 Free-fall Inertial Wake Acceleration Threshold
7.23
FF_WU_THS_H (35h)
THS15 THS14 THS13 THS12 THS11 THS10 THS9 THS15, THS8 Free-fall Inertial Wake Acceleration Threshold THS8
7.24
FF_WU_DURATION (36h)
FWD7 FWD6 FWD5 FWD4 FWD3 FWD2 FWD1 FWD0 FWD7, FWD0 Minimum duration Free-fall/Wake-up event
minimum duration free-fall/wake-up event recognized. FF_WU_Duration (Dec) Duration -ODR
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Register Description
LIS3LV02DQ
7.25
DD_CFG (38h)
IEND ZHIE ZLIE YHIE YLIE XHIE XLIE
IEND
Interrupt enable Direction change. Default value: disabled; interrupt signal enabled) Latch Interrupt request into DD_SRC with DD_SRC cleared reading DD_ACK reg. Default value: interrupt request latched; interrupt request latched) Enable interrupt generation high event. Default value: disable interrupt request; enable interrupt request measured accel. value higher than preset threshold) Enable interrupt generation event. Default value: disable interrupt request; enable interrupt request measured accel. value lower than preset threshold) Enable interrupt generation high event. Default value: disable interrupt request; enable interrupt request measured accel. value higher than preset threshold) Enable interrupt generation event. Default value: disable interrupt request; enable interrupt request measured accel. value lower than preset threshold) Enable interrupt generation high event. Default value: disable interrupt request; enable interrupt request measured accel. value higher than preset threshold) Enable interrupt generation event. Default value: disable interrupt request; enable interrupt request measured accel. value lower than preset threshold)
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Direction-detector configuration register
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Register Description
7.26
DD_SRC (39h)
Interrupt event from direction change. direction changes detected; direction changed from previous measurement) High. Default value: below THSI threshold; accel. exceeding THSE threshold along positive direction acceleration axis) Low. Default value: below THSI threshold; accel. exceeding THSE threshold along negative direction acceleration axis) High. Default value: below THSI threshold; accel. exceeding THSE threshold along positive direction acceleration axis) Low. Default value: below THSI threshold; accel. exceeding THSE threshold along negative direction acceleration axis) High. Default value: below THSI threshold; accel. exceeding THSE threshold along positive direction acceleration axis) Low. Default value: below THSI threshold; accel. exceeding THSE threshold along negative direction acceleration axis)
Direction detector source register
7.27
DD_ACK (3Ah)
Dummy register. DD_CFG=1 allows refresh DD_SRC. Read data significant.
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Register Description
LIS3LV02DQ
7.28
DD_THSI_L (3Ch)
THSI7 THSI7, THSI0 THSI6 THSI5 THSI4 THSI3 THSI2 THSI1 THSI0
Direction detection Internal Threshold
7.29
DD_THSI_H (3Dh)
THSI15 THSI15, THSI8 THSI14 THSI13 THSI12 THSI11 THSI10 THSI9 THSI8
Direction detection Internal Threshold
7.30
DD_THSE_L (3Eh)
THSE7 THSE7, THSE0 THSE6 THSE5 THSE4 THSE3 THSE2 THSE1 THSE0
Direction detection External Threshold
7.31
DD_THSE_H (3Fh)
THSE15 THSE14 THSE13 THSE12 THSE11 THSE10 THSE15, THSE8 Direction detection External Threshold THSE9 THSE8
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Typical performance characteristics
Typical performance characteristics
Mechanical Characteristics 25°C
Figure y-axis level 2.5V
Figure x-axis level 2.5V
Percent parts Percent parts LEVEL (mg)
LEVEL (mg)
Figure z-axis level 2.5V
Figure x-axis sensitivity 2.5V
Percent parts Percent parts LEVEL (mg)
1010
1015
1020 1025 sensitivity (LSb/g)
1030
Figure y-axis sensitivity 2.5V
Figure z-axis sensitivity 2.5V
Percent parts Percent parts 1015 1020 1025 sensitivity (LSb/g) 1030 1010
1010 1015 1020 1025 sensitivity (LSb/g) 1030
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Typical performance characteristics
LIS3LV02DQ
Mechanical Characteristics derived from measurement -40°C +85°C temperature range
Figure y-axis level change temperature 2.5V
Figure x-axis level change temperature 2.5V
Percent parts Percent parts level drift (mg/
-0.5
-0.05
0.05
0.15 0.25 level drift (mg/
0.35
Figure z-axis level change temperature 2.5V
Figure x-axis sensitivity change temperature 2.5V
Percent parts Percent parts -0.5 level drift (mg/C) Percent parts 0.006 0.007 0.008 sensitivity drift (%/C) 0.009 0.010
-0.035 -0.034 -0.033 -0.032 -0.031 -0.03 -0.029 -0.028 -0.027 sensitivity drift (%/C)
Figure y-axis sensitivity change temperature 2.5V
Percent parts 0.005
Figure z-axis sensitivity change temperature 2.5V
-0.05
-0.045
-0.04
-0.035 -0.03 -0.025 sensitivity drift (%/C)
-0.02
-0.015
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Typical performance characteristics
Electro-Mechanical characteristics 25°C
Figure axis level function Figure axis level function supply supply voltage voltage
level (mg) level (mg) Supply Voltage
Supply Voltage
Figure Current consumption PowerDown mode (Vdd=2.5V)
Figure Current consumption Operational mode (Vdd=2.5V)
Percent parts Percent parts current consumption (uA)
current consumption (uA)
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Package Information
LIS3LV02DQ
Package Information
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have Lead-free second level interconnect. category second Level Interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com.
Figure QFPN-28 Mechanical Data Package Dimensions
DIM. MIN. 0.45 0.30 6.85 4.90 6.85 4.90 0.203 0.35 5.00 5.00 0.80 0.55 0.65 0.10 0.08 0.40 7.15 5.10 7.15 5.10 0.012 0.270 0.192 0.270 0.192 0.014 0.275 0.197 0.275 0.197 0.0315 0.018 0.022 0.025 0.004 0.003 1.70 TYP. 1.80 MAX. 1.90 0.05 MIN. 0.067 TYP. 0.071 MAX. 0.075 0.002 0.008 0.016 0.281 0.20 0.281 0.20 inch
OUTLINE MECHANICAL DATA
QFPN-28 (7x7x1.8mm) Quad Flat Package lead
7787120
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Revision history
Revision history
Date 7-Oct-2005 Revision Initial release. Changes
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LIS3LV02DQ
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics. other names property their respective owners 2005 STMicroelectronics rights reserved STMicroelectronics group companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States America www.st.com
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