CMOS SRAM 256Kx4 (with High-Speed CMOS Static RAM(5.0V Operating)

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CMOS SRAM 256Kx4 (with High-Speed CMOS Static RAM(5.0V Operating)

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K6R1004C1D
CMOS SRAM
256Kx4 (with High-Speed CMOS Static RAM(5.0V Operating).
Revision History
Rev. Rev. Rev. Rev. History Initial release with Preliminary. Current modify Delete 15ns speed bin. Change Industrial mode. Item 10ns ICC(Industrial) 12ns Draft Data June. 2001 September. 2001 December. 2001 Previous 85mA 75mA Current 75mA 65mA June. 2002 Final Remark Preliminary Preliminary Preliminary
Rev.
Final datasheet release. Delete UB,LB releated characteristics timing diagram. Delete 12ns speed bin. Lead Free Package type.
Rev. Rev.
July. 2002 July. 2004
Final Final
attached data sheets prepared approved SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications. SAMSUNG Electronics will evaluate reply your requests questions parameters this device. have questions, please contact SAMSUNG branch office near your office, call contact Headquarters.
Rev. July 2004
K6R1004C1D
Async. Fast SRAM Ordering Information
Org. 256K Part Number K6R1004C1D-J(K)C(I) K6R1004V1D-J(K)C(I) 08/10 K6R1008C1D-J(K,T,U)C(I) 128K K6R1008V1D-J(K,T,U)C(I) 08/10 K6R1016C1D-J(K,T,U,E)C(I) K6R1016V1D-J(K,T,U,E)C(I) 08/10 8/10 8/10 VDD(V) Speed 8/10 32-SOJ 32-SOJ(LF)
32-SOJ 32-SOJ(LF) 32-TSOP2 32-TSOP2(LF) 44-SOJ 44-SOJ(LF) 44-TSOP2 44-TSOP2(LF) 48-TBGA
CMOS SRAM
Temp. Power
Commercial Temperature ,Normal Power Range Industrial Temperature ,Normal Power Range
Rev. July 2004
K6R1004C1D
256K (with High-Speed CMOS Static
FEATURES
Fast Access Time 10ns(Max.) Power Dissipation Standby (TTL) 20mA(Max.) (CMOS) 5mA(Max.) Operating K6R1004C1D-10: 65mA(Max.) Single 5.0V±10% Power Supply Compatible Inputs Outputs Compatible with 3.3V Device Fully Static Operation Clock Refresh required Three State Outputs Center Power/Ground Configuration Standard Configuration K6R1004C1C-J 32-SOJ-400 K6R1004C1C-K 32-SOJ-400(Lead-Free) Operating Commercial Industrial Temperature range.
CMOS SRAM
GENERAL DESCRIPTION
K6R1004C1D 1,048,576-bit high-speed Static Random Access Memory organized 262,144 words bits. K6R1004C1D uses common input output lines output enable which operates faster than address access time read cycle. device fabricated using SAMSUNGs advanced CMOS process designed highspeed circuit technology. particularly well suited high-density high-speed system applications. K6R1004C1D packaged 32-pin plastic SOJ.
CONFIGURATION(Top View)
FUNCTIONAL BLOCK DIAGRAM
Gen.
Pre-Charge Circuit
I/O1
I/O4
Select
I/O3
Memory Array Rows 512x4 Columns
I/O2
I/O1 I/O4
Data Cont. Gen.
Circuit Column Select
FUNCTION
Name I/O1 I/O4
Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground Connection
Rev. July 2004
K6R1004C1D
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT TSTG Rating
CMOS SRAM
Unit
-0.5 Vcc+0.5V -0.5
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operating sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
RECOMMENDED OPERATING CONDITIONS(TA=0 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Voltage Symbol -0.5* VCC+0.5** Unit
VIL(Min) -2.0V (Pulse Width 8ns) 20mA. VIH(Max) 2.0V (Pulse Width 8ns) 20mA.
OPERATING CHARACTERISTICS*(TA=0 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Standby Current Symbol ISB1 Output Voltage Level Output High Voltage Level VIN=VSS CS=VIH OE=VIH WE=VIL VOUT=VSS Min. Cycle, 100% Duty Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V VIN0.2V IOL=8mA IOH=-4mA Com. Ind. 10ns 10ns Test Conditions Unit
above parameters also guaranteed industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance
Capacitance sampled 100% tested.
Symbol CI/O
Test Conditions VI/O=0V VIN=0V
Unit
Rev. July 2004
K6R1004C1D
CHARACTERISTICS(TA=0 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter Input Pulse Levels Input Rise Fall Times Input Output timing Reference Levels Output Loads
CMOS SRAM
Value 1.5V below
Output Loads(A)
Output Loads(B) tHZ, tLZ, tWHZ, tOW, tOLZ tOHZ +5.0V
DOUT
1.5V
30pF* DOUT
5pF*
Capacitive Load consists components test environment.
Including Scope Capacitance
READ CYCLE*
Parameter Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Chip Enable Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Chip Selection Power Time Chip Selection Power DownTime Symbol tOLZ tOHZ
K6R1004C1D-10
Unit
above parameters also guaranteed industrial temperature range.
Rev. July 2004
K6R1004C1D
WRITE CYCLE*
Parameter Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z Symbol tWP1 tWHZ
K6R1004C1D-10
CMOS SRAM
Unit
above parameters also guaranteed industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address Data Previous Valid Data Valid Data
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tHZ(3,4,5)
tOHZ tOLZ Data
High-Z
Valid Data
tLZ(4,5)
Current
Rev. July 2004
K6R1004C1D
NOTES(READ CYCLE)
CMOS SRAM
high read cycle. read cycle timing referenced from last valid address first transition address. tOHZ defined time which outputs achieve open circuit condition referenced levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device. Transition measured ±200mV from steady state voltage with Load(B). This parameter sampled 100% tested. Device continuously selected with CS=VIL. common applications, minimization elimination contention conditions necessary during read write cycle.
TIMING WAVEFORM WRITE CYCLE(1) (OE= Clock)
Address tCW(3) tAS(4) Data High-Z tOHZ(6) Data High-Z(8) Valid Data tWP(2) tWR(5)
TIMING WAVEFORM WRITE CYCLE(2) (OE=Low Fixed)
Address tAS(4) Data High-Z tWHZ(6) Data High-Z(8) Valid Data
(10)
tWR(5) tCW(3) tWP1(2)
Rev. July 2004
K6R1004C1D
TIMING WAVEFORM WRITE CYCLE(3) (CS=Controlled)
Address tAS(4) Data tCW(3) tWP(2)
CMOS SRAM
tWR(5)
High-Z
tWHZ(6)
Valid Data
High-Z
Data
High-Z
High-Z(8)
NOTES(WRITE CYCLE) write cycle timing referenced from last valid address first transition address. write occurs during overlap write begins latest transition going going write ends earliest transition going high going high. measured from beginning write write. measured from later going write. measured from address valid beginning write. measured from write address change. applied case write ends going high. Read Mode during this period, pins output low-Z state. Inputs opposite phase output must applied because contention occur. common applications, minimization elimination contention conditions necessary during read write cycle. goes simultaneously with going after going low, outputs remain high impedance state. Dout read data address. 10.When pins output state. input signals opposite phase leading output should applied.
FUNCTIONAL DESCRIPTION
means Dont Care.
Mode Select Output Disable Read Write
High-Z High-Z DOUT
Supply Current ISB, ISB1
Rev. July 2004
K6R1004C1D
PACKAGE DIMENSIONS
32-SOJ-400
CMOS SRAM
Units:millimeters/Inches
10.16 0.400
11.18 ±0.12 0.440 ±0.005
9.40 ±0.25 0.370 ±0.010
0.20 21.36 0.841 20.95 ±0.12 0.825 ±0.005 1.30 0.051 1.30 0.051 0.95 0.0375
+0.10 -0.05 +0.004 0.017 -0.002
+0.10 -0.05
0.69 0.027
0.008 +0.004 -0.002
3.76 0.148
0.10 0.004
0.43
1.27 0.050
+0.10 -0.05 +0.004 0.028 -0.002
0.71
Rev. July 2004

CMOS SRAM 256Kx4 (with High-Speed CMOS Static RAM(5.0V Operating)

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