Frequency Generator Transmeta Efficeon Recommended Application: T

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Frequency Generator Transmeta Efficeon Recommended Application: T

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ICS952302
Frequency Generator Transmeta Efficeon
Recommended Application: Transmeta Efficion, Output Features: CPUs 3.3V including free running CPUCLK_F 3.3V, including free running PCICLK_F 27MHz clock 3.3V 48MHz clocks 3.3V clocks @3.3V Specifications: output jitter: 250ps output skew: 250ps CPUT output skew: 1-3ns 27MHz Accuracy 50ppm 48MHz Accuracy 50ppm
Features: Support Index read/write block read/write operations. Uses external 14.318MHz referience input XTAL. Full Load Power consumption reduced >10% compared reference device Power management SMBus
Functionality
Byte Byte Byte Spread
Configuration
VDDREF REF0 GNDREF
PCICLK1 PCICLK_F2 PCICLK_F3 VDDPCI PCICLK2 GNDPCI VDDCOR PCI_STOP# **PD# GND48 SDATA SCLK
ICS952302
+/-0.3 +/-0.6 +/-0.25 +/-0.45 -0.60% -1.20% -0.50% -0.90%
CENTER
VDDPCI PCICLK_F0 PCICLK_F1 GNDPCI PCICLK0
DOWN
REF1 VDDCPU CPUCLK0 GNDCPU CPUCLK1 CPUCLK_F CPU_STOP# VDD27 27MHZ GND48 VDD48 48MHZ_1 48MHZ_0
48-TSSOP
Internal Pull-Up Resistor **No Diode Clamp
0957B-10/05/04
ICS952302
Descriptions
NAME VDDREF REF0 GNDREF VDDPCI PCICLK_F0 PCICLK_F1 GNDPCI PCICLK0 PCICLK1 PCICLK_F2 PCICLK_F3 VDDPCI PCICLK2 GNDPCI VDDCOR PCI_STOP# **PD# GND48 SDATA SCLK 48MHZ_0 48MHZ_1 VDD48 GND48 27MHZ VDD27 CPU_STOP# CPUCLK_F CPUCLK1 GNDCPU CPUCLK0 VDDCPU REF1 TYPE DESCRIPTION Ref, XTAL power supply, nominal 3.3V 14.318 reference clock. Ground outputs. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power supply clocks, nominal 3.3V Free running clock affected PCI_STOP# Free running clock affected PCI_STOP# Ground outputs clock output. clock output. Free running clock affected PCI_STOP# Free running clock affected PCI_STOP# Power supply clocks, nominal 3.3V clock output. Ground outputs Connection. Connection. 3.3V power core. Stops PCICLKs logic level, when low. Free running PCICLKs effected this input. Asynchronous active input pin, with 120Kohm internal pull-up resistor, used power down device. internal clocks disabled crystal stopped. Ground 48MHz outputs Data SMBus circuitry, tolerant. Clock SMBus circuitry, tolerant. 48MHz clock output. 48MHz clock output. Power 48MHz output.3.3V Ground 48MHz outputs Connection. Connection. Connection. 27.0000MHz Video Clock Chipset Ground pin. Power 27MHz output.3.3V Connection. Power supply, nominal 3.3V Connection. Active high input enabling Memory Channel outputs. tri-state outputs, enable outputs Connection. Ground pin. Stops CPUCLK, except those free running clocks Free running clock. affected CPU_STOP#. clock outputs. 3.3V Ground outputs clock outputs. 3.3V Connection. Supply clocks, 3.3V nominal 14.318 reference clock.
Internal Pull-Up Resistor
diode clamp VDD.
0957B-10/05/04
ICS952302
General Description
Spread spectrum enabled through SMBus programming. Spread spectrum typically reduces system 10dB. This simplifies qualification without resorting board design iterations costly shielding. ICS952302 employs proprietary closed loop design, which tightly controls percentage spreading over process temperature variations.
Block Diagram
(1:0)
27MHz
(1:0)
(1:0)
(2:0)
(3:0)
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ICS952302
SMBus Table: Output Control Register Byte Name CPUCLK_F CPUCLK0 CPUCLK1 27MHZ 48MHZ_0 48MHZ_1 REF0 REF1 Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Type Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable
SMBus Table: Output Control Register Byte Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PCICLK_F3 PCICLK0 PCICLK1 PCICLK2 Spread Spectrum Mode Control Function Test Mode Output Enable Output Enable Output Enable Spread Control Output Enable Output Enable Spread Control PLL1 Type Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable
SMBus Table: Output Control Register Byte (note) Name CPUCLK_F CPUCLK0 CPUCLK1 Control Function Allow assertion CPU_STOP# setting CPU_STOP control SMBus register stop clocks Type Free Running Free Running Free Running Stoppable Stoppable Stoppable Disable
Reserved Reserved Reserved Reserved CPU_STOP Stop clocks Enable Reserved Reserved CPU_STOP# Select PCI_STOP# Note: Byte2bit2=0 (Enable) stop CPUCLK's ONLY when Byte2 bit(5:7) STOPPABLE MODE SMBus Table: Output Control Register Byte
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Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PCICLK_F3 PCICLK0 PCICLK1 PCICLK2 PCI_STOP
Control Function Allow assertion PCI_STOP# setting PCI_STOP control SMBus register stop clocks Stop clocks
Type
Free Running Free Running Free Running Free Running Free Running Free Running Free Running Enable
Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Disable
ICS952302
SMBus Table: Spread Spectrum Control Register Byte Name Spread Position Control Type Function Center Down Spread Spread Reserved Reserved Reserved Reserved Reserved Center Down
Table
SMBus Table: Control Register Byte Name Control Function Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Table: Control Register Byte Name Control Function Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBus Table: Vendor Revision Register Byte Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISION Type
VENDOR
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ICS952302
Absolute Maximum Ratings
Supply Voltage Logic Inputs Ambient Operating Temperature Case Temperature Storage Temperature -0.5 +0.5 +70°C 115°C -65°C +150°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only functional operation device these other conditions above those listed operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Electrical Characteristics Input/Supply/Common Output Parameters
70°C; Supply Voltage +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Voltage Input High Current Input Current Input Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Stabilization1 Skew1
SYMBOL IIL1 IIL2 IDD(op) IDDPD CINX TSTAB TCPU-PCI
CONDITIONS
UNITS
Inputs with pull-up resistors Inputs with pull-up resistors (full load); 66MHz With input address Logic Inputs pins From target Freq.
-200 14.3132
Guaranteed design, 100% tested production.
0957B-10/05/04
ICS952302
Electrical Characteristics
70°C; +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VOH2B Output High Voltage VOL2B Output Voltage VOUT IOH2B Output High Current VOUT 3.135V VOUT 1.95 IOL2B Output Current VOUT =0.4V tr2B Rise Time tf2B Fall Time1 dt2B Duty Cycle tsk2B Skew tjcyc-cyc2B Jitter, Cycle-to-cycle
0.25 51.5
UNITS
Guaranteed design, 100% tested production.
Electrical Characteristics PCICLK, PCICLK_F
70°C; +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS VOH2B Output High Voltage VOL2B Output Voltage VOUT IOH2B Output High Current VOUT 3.135V VOUT 1.95 IOL2B Output Current VOUT =0.4V tr2B Rise Time1 tf2B Fall Time1 dt2B Duty Cycle tsk2B Skew tjcyc-cyc2B Jitter, Cycle-to-cycle
0.25 50.5
UNITS
Guaranteed design, 100% tested production.
0957B-10/05/04
ICS952302
Electrical Characteristics 27MHz
70°C; +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS FACC Frequency Accuracy 14.31818MHz VOH2B Output High Voltage VOL2B Output Voltage VOUT IOH2B Output High Current VOUT 3.135V VOUT 1.95 IOL2B Output Current VOUT =0.4V tr2B Rise Time1 tf2B Fall Time1 dt2B Duty Cycle tjcyc-cyc2B Jitter, Cycle-to-cycle
0.25
UNITS
Guaranteed design, 100% tested production.
Electrical Characteristics 48MHz
70°C; +/-5%; (unless otherwise stated) CONDITIONS 14.31818MHz VOUT IOH2B Output High Current VOUT 3.135V VOUT 1.95 IOL2B Output Current VOUT =0.4V tr2B Rise Time1 tf2B Fall Time1 dt2B Duty Cycle tjcyc-cyc2B Jitter, Cycle-to-cycle Guaranteed design, 100% tested production. PARAMETER Frequency Accuracy Output High Voltage Output Voltage SYMBOL FACC VOH2B VOL2B 0.25 UNITS
0957B-10/05/04
ICS952302
Electrical Characteristics
70°C; +/-5%; (unless otherwise stated) CONDITIONS 14.31818MHz VOUT IOH2B Output High Current VOUT 3.135V VOUT 1.95 IOL2B Output Current VOUT =0.4V tr2B Rise Time1 tf2B Fall Time dt2B Duty Cycle tjcyc-cyc2B Jitter, Cycle-to-cycle Guaranteed design, 100% tested production. PARAMETER Frequency Accuracy Output High Voltage Output Voltage SYMBOL FACC VOH2B VOL2B 0.25 UNITS
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ICS952302
General SMBus serial interface information ICS952302 Write:
Controller (host) sends start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends begining byte location clock will acknowledge Controller (host) sends data byte count clock will acknowledge Controller (host) starts sending Byte through Byte (see Note clock will acknowledge each byte time Controller (host) sends Stop
Read:
Controller (host) will send start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends begining byte location clock will acknowledge Controller (host) will send separate start bit. Controller (host) sends read address clock will acknowledge clock will send data byte count clock sends Byte clock sends Byte through byte Controller (host) will need acknowledge each byte Controllor (host) will send acknowledge Controller (host) will send stop
Index Block Write Operation
Controller (Host) starT Slave Address D2(H) WRite Beginning Byte Data Byte Count Beginning Byte Byte (Slave/Receiver)
Index Block Read Operation
Controller (Host) starT Slave Address D2(H) WRite Beginning Byte Repeat starT Slave Address D3(H) ReaD Data Byte Count Beginning Byte Byte (Slave/Receiver)
Byte stoP
Byte
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acknowledge stoP
ICS952302
Shared Operation Input/Output Pins
pins designated (input/output) serve dual signal functions device. During initial power-up, they input pins. logic level (voltage) that present these pins this time read stored into 5-bit internal data latch. Power-On reset, (see characteristics timing values), device changes mode operations these pins output function. this mode pins produce specified buffered clocks external loads. program (load) internal configuration register these pins, resistor connected either (logic power supply (logic voltage potential. Kilohm (10K) resistor used provide both solid CMOS programming voltage needed during power-up programming period provide insignificant load output clock during subsequent operating period. Figure shows means implementing this function when switch header used. With jumper installed will pulled high. With jumper place will pulled low. programmability necessary, than only single resistor necessary. programming resistors should located close series termination resistor minimize current loop area. more important locate series termination resistor close driver than programming resistor.
Programming Header Device
8.2K Clock trace load Series Term. Res.
Fig.
0957B-10/05/04
ICS952302
Timing Diagram
power down selection used part into very power state without turning power part. asynchronous active input. This signal needs synchronized internal device prior powering down clock synthesizer. Internal clocks running after device power down. When active clocks need driven value held prior turning VCOs crystal. power latency needs less than power down latency should short possible conforming sequence requirements shown below. PCI_STOP# CLK_STOP# considered don't cares during power down operations. 48MHz clocks expected stopped state soon possible. state internal logic, stopping holding clock outputs state require more than clock cycle complete.
CPUCLK
PCICLK Crystal
Notes: timing referenced Internal CPUCLK (defined inside ICS952302 device). shown, outputs Stop next falling edge after goes low. asynchronous input metastable conditions exist. This signal synchronized inside this part. shaded sections Crystal signals indicate active clock.
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ICS952302
CLK_STOP# Timing Diagram
CLK_STOP# asychronous input clock synthesizer. used turn clocks power operation. CLK_STOP# synchronized ICS952302. minimum that clock enabled (CLK_STOP# high pulse) clocks. other clocks will continue while clocks disabled. clocks will always stopped state start such manner that guarantees high pulse width full pulse. clock latency less than clocks clock latency less than clocks.
INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High)
CPUCLK
Notes: timing referenced internal clock. CLK_STOP# asynchronous input metastable conditions exist. This signal synchronized clocks inside ICS952302. CLK_STOP# signal. other clocks continue undisturbed.
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ICS952302
PCI_STOP# Timing Diagram
PCI_STOP# asynchronous input ICS952302. used turn PCICLK clocks power operation. PCI_STOP# synchronized ICS952302 internally. minimum that PCICLK clocks enabled (PCI_STOP# high pulse) least PCICLK clocks. PCICLK clocks stopped state started with full high pulse width guaranteed. PCICLK clock latency cycles only three rising PCICLK clocks, latency PCICLK clock.
CPUCLK (Internal)
PCICLK_F (Internal) PCICLK_F (Free-running) CLK_STOP#
PCI_STOP#
PCICLK
Notes: timing referenced Internal CPUCLK (defined inside ICS952302 device.) PCI_STOP# asynchronous input, metastable conditions exist. This signal required synchronized inside ICS952302. other clocks continue undisturbed. CLK_STOP# shown high (true) state.
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ICS952302
INDEX AREA
Millimeters Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 VARIATIONS VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 VARIATIONS VARIATIONS -0.10 -.004 VARIATIONS
10-0039
SEATING PLANE
12.40 12.60
(inch) .488 .496
erence Doc.: JEDEC Publication O-153
(0.020 mil) (240 mil) 6.10 Body, 0.50 pitch TSSOP
Ordering Information
ICS952302yGLF-T
Example:
XXXX
Designation tape reel packaging Lead Free (Optional) Package Type TSSOP Revision Designator (will correlate with datasheet revision) Device Type Prefix Standard Device
0957B-10/05/04

Frequency Generator Transmeta Efficeon Recommended Application: T

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