Non-Volatile SRAM MODULE 1Mbit (128K 8-Bit),34Pin-JLCC, Part HMN1288J

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Non-Volatile SRAM MODULE 1Mbit (128K 8-Bit),34Pin-JLCC, Part HMN1288J

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HMN1288J
Non-Volatile SRAM MODULE 1Mbit (128K 8-Bit),34Pin-JLCC, Part HMN1288J
HMN1288J Nonvolatile SRAM 1,048,576-bit static organized 131,072 bytes bits. HMN1288J self-contained lithium energy source provide reliable non-volatility coupled with unlimited write cycles standard SRAM integral control circuitry which constantly monitors single supply out-oftolerance condition. When such condition occurs, lithium energy source automatically switched sustain memory until after returns valid write protection unconditionally enabled prevent garbled data. addition SRAM unconditionally write-protected prevent inadvertent write operation. this time integral energy source switched sustain memory until after returns valid. HMN1288J uses extremely standby current CMOS SRAM's, coupled with small lithium coin cells provide nonvolatility without long write-cycle times write-cycle limitations associated with EEPROM.
FEATURES
Access time High-density design 4Mbit Design Battery internally isolated until power applied Industry-standard 34-pin 128K pinout Unlimited write cycles Data retention absence 10-years minimum data retention absence power Automatic write-protection during power-up/power-down cycles Data automatically protected during power loss Conventional SRAM operation; unlimited write cycles /NBW A(15) A(16) /RST D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
ASSIGNMENT
A(14) A(13) A(12) A(11) A(10) A(9) A(8) A(7) A(6) A(5) A(4) A(3) A(2) A(1) A(0)
JLCC VIEW
OPTIONS
Timing
MARKING
URL: www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002)
HANBit Electronics Co.,Ltd.
HMN1288J
FUNCTIONAL DESCRIPTION
HMN1288J executes read cycle whenever inactive(high) active(low). address specified address inputs(A0-A16) defines which 131,072 bytes data accessed. Valid data will available eight data output drivers within tACC (access time) after last address input signal stable. When power valid, HMN1288J operates standard CMOS SRAM. During power-down power-up cycles, HMN1288J acts nonvolatile memory, automatically protecting preserving memory contents. HMN1288J write mode whenever signals active (low) state after address inputs stable. later occurring falling edge will determine start write cycle. write cycle terminated earlier rising edge /WE. address inputs must kept valid throughout write cycle. must return high state minimum recovery time (tWR) before another cycle initiated. control signal should kept inactive (high) during write cycles avoid contention. However, output been enabled (/CE active) then will disable outputs tODW from falling edge. HMN1288J provides full functional capability greater than 4.75 write protects nominal. Powerdown/power-up control circuitry constantly monitors supply power-fail-detect threshold VPFD. When falls below VPFD threshold, SRAM automatically write-protects data. inputs become "don't care" outputs high impedance. falls below approximately power switching circuit connects lithium energy soure retain data. During power-up, when rises above approximately volts, power switching circuit connects external disconnects lithium energy source. Normal operation resume after exceeds 4.75 volts.
BLOCK DIAGRAM
DESCRIPTION
/CE1
A(0:16) A0-A16 Address Input DQ(0:7) Chip Enable Ground DQ0-DQ7 Data Data Write Enable
Vout
/CE2
/RESET
/CE_con
Output Enable VCC: Power (+5V) Connection
URL: www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002)
HANBit Electronics Co.,Ltd.
HMN1288J
TRUTH TABLE
MODE selected Output disable Read Write OPERATION High High DOUT POWER Standby Active Active Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER voltage applied relative Voltage applied excluding relative Operating temperature Storage temperature Soldering temperature SYMBOL TOPR TSTG TSOLDER RATING -0.3V -0.3V Vcc+0.3 70°C -55°C 125°C 260°C second VCC+0.3 CONDITIONS
NOTE: Permanent device damage occur Absolute Maximum Ratings exceeded. Functional operation should restricted Recommended Operating Conditions detailed this data sheet. Exposure higher than recommended voltage extended periods time could affect device reliability.
RECOMMENDED OPERATING CONDITIONS TOPR
PARAMETER Supply Voltage Ground Input high voltage Input voltage SYMBOL 4.5V -0.3 TYPICAL 5.5V VCC+0.3 0.8V
NOTE: Typical values indicate operation
CAPACITANCE (TA=25 f=1MHz, VCC=5V)
DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage Output voltage SYMBOL CI/O UNIT
URL: www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002)
HANBit Electronics Co.,Ltd.
HMN1288J
ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin VCCmax
PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output voltage Trip Point (TOL=GND) Standby supply current Standby supply current Operating current VCC/VBAT Switch Point NOTE: Typical values indicate operation Power supply /CE=2.2v VCC-0.3V, /CE=VIL, II/O=0 VIH, Read CONDITIONS VIN=VSS /CE=VIH /OE=VIH /WE=VIL IOH=-1.0mA IOL= 2.0mA SYMBOL VCCTP ISB1 TYP. 4.62 4.75 UNIT
CHARACTERISTICS (Test Conditions)
PARAMETER Input pulse levels VALUE 2.4V 1.5V unless otherwise specified) Figures
CL1)
Input rise fall times Input output timing reference levels Output load =50pF+1TTL) =100pF+1TTL)
Including scope capacitance
READ CYCLE (TA= TOPR, VCCmin VCCmax
PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable Output valid Chip enable output Output enable output Chip disable output high Output disable output high Output hold from address change SYMBOL tACC tACE tCLZ tOLZ tCHZ tOHZ Output load Output load Output load Output load Output load Output load Output load Output load CONDITIONS UNIT
URL: www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002)
HANBit Electronics Co.,Ltd.
WRITE CYCLE (TA= TOPR, Vccmin Vccmax
PARAMETER Write Cycle Time Chip enable write Address setup time Address valid write Write pulse width Write recovery time (write cycle Write recovery time (write cycle Data valid write Data hold time (write cycle Data hold time (write cycle Write enabled output high Output active from write SYMBOL tWR1 tWR2 tDH1 tDH2 Note Note Note Note Note Note Note Note Note Note CONDITIONS
HMN1288J
UNIT
NOTE: write ends earlier transition going high going high. write occurs during overlap allow /WE. write begins later transition going going low. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met. goes simultaneously with going after going low, outputs remain highimpedance state.
TIMING WAVEFORM READ CYCLE NO.1 (Address Access)*1,2
Address tACC DOUT Previous Data Valid Data Valid
READ CYCLE NO.2 (/CE Access)*1,3,4
tACE tCLZ DOUT
URL: www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002)
tCHZ
High-Z
High-Z
HANBit Electronics Co.,Ltd.
READ CYCLE NO.3 (/OE Access)*1,5
Address tACC DOUT tOLZ High-Z tOHZ Data Valid
HMN1288J
High-Z
NOTES: held high read cycle. Device continuously selected: =VIL. Address valid prior coincident with transition low. VIL. Device continuously selected:
WRITE CYCLE NO.1 (/WE-Controlled)*1,2,3
Address DOUT Data Undefined Data-in Valid High-Z tDH1 tWR1
URL: www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002)
HANBit Electronics Co.,Ltd.
WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5
HMN1288J
Address DOUT Data
NOTE:
tWR2
tDH2 Data-in
Undefined
High-Z
must high during address transition. Because active (/OE low) during this period, data input signals opposite polarity outputs must applied. high, pins remain state high impedance. Either tWR1 tWR2 must met. Either tDH1 tDH2 must met.
POWER-DOWN/POWER-UP TIMING
4.75 VPFD
VPFD 4.25 tWPT tCER
URL: www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002)
HANBit Electronics Co.,Ltd.
PACKAGE DIMENSION
Unit
HMN1288J
24.52+/-0.2 1.50
1.50
1.27
10.82 13.31 3.05
70ns
ORDERING INFORMATION
Operating Temperature Industrial Temp. (-40~85 Blank Commercial Temp. (0~70°C)
Speed options
JLCC type package Device 128K Nonvolatile SRAM
HANBit Memory Module
URL: www.hbe.co.kr Rev.0.0 (FEBRUARY/ 2002)
23.50+/-0.2
.635
HANBit Electronics Co.,Ltd.

Non-Volatile SRAM MODULE 1Mbit (128K 8-Bit),34Pin-JLCC, Part HMN1288J

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