GF9320 Data Sheet Features broadcast quality 8-bit 24-tap poly-ph

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GF9320 Data Sheet Features broadcast quality 8-bit 24-tap poly-ph

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GF9320 Scaling Processor
GF9320 Data Sheet Features
broadcast quality 8-bit 24-tap poly-phase horizontal vertical scalar HDTV SDTV video images high performance scaling processor with separate control horizontal vertical scaling factors positions support arbitrary video formats 2048 2048 support multiplexed non-multiplexed video flexible 4:2:2 4:4:4 YCbCr output field merge separation inserted removed from progressive images using interlaced double banked control registers 'on-the-fly' dynamic effects external pull-down insertion extraction programmable output matrix with gain range film rate features include 1080p24 1080PsF support fully programmable colour background generator flexible F,V,H output insertion seamless interface GF9330 de-interlacer seamless interface common SDRAM user configuration through dedicated serial interface 3.3V supply
choices while programmable colour background generator customized appropriately match image content. fully programmable flexible output matrix allows colour difference over-sampling, gain controls well YCbCr conversions power nearly display device market. GF9320 also includes vertical interpolation filter perform stand alone cost-sensitive de-interlacing. Broadcast quality de-interlacing offered through seamless interface GF9330 GF9331 devices. Applications
HDTV Down Converters Production Equipment Video Walls Projection Systems Plasma Displays Home Theatre Systems Players
Description GF9320 Scaling Processor offers 8-bit broadcast quality scaling video images 2048 2048 pixels. GF9320 supports arbitrary display modes custom applications. Dynamic zoom effects allow variety aspect ratio conversion
Ordering Information
Part Number
GF9320-CBW
Package
TBGA
Temp. Range
70oC
YC/Y
Input Processing
Horizontal Scaling Filter
Input Processing
G/Y/YC B/Cb/C R/Cr
CTRL
Control Interface
External Memory Interface
Vertical Scaling Filter
External Memory Interface
Block Diagram
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GF9320 Data Sheet
Contents
Features Description Applications.1 Ordering Information Description Electrical Characteristics Detailed Device Description Device Overview Serial Interface Control Input Processing Scaling Processor SDRAM Memory Interface Output Processor Output Timing Control Package Dimensions Revision History
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GF9320 Data Sheet
Description
ADDR_A5
CS_A0
CS_A2
WE_A
DATA_A0
DATA_A4
DATA_A6
ADDR_B6
BA_B
CKEN_B
CS_B3
DATA_B0
DATA_B3
DATA_B6
DATA_B7
ADDR_A7 ADDR_A10
DATA_A12 DATA_A14
DATA_A15 DATA_A19 ADDR_B2
ADDR_A4 ADDR_A6 ADDR_A8 CS_A1 CAS_A CKEN_A DATA_A3 DATA_A5 DATA_A11 DATA_A13 DATA_A16 ADDR_B3 ADDR_B7 ADDR_B8 RAS_B CK_B CS_B0 DATAEN_AB DATA_B1 DATA_B5 DATA_B8 DATA_B9
ADDR_A1 ADDR_A3 ADDR_A9 RAS_A DATA_A2 DATA_A8 DATA_A10 DATA_A17 ADDR_B0 ADDR_B4 ADDR_B9 CAS_B CS_B1 DATA_B4 DATA_B10 DATA_B12
ADDR_A2 BA_A CS_A3 CK_A DATA_A1 DATA_A7 DATA_A9 DATA_A18 ADDR_B1 ADDR_B5 ADDR_B10 WE_B CS_B2 DATA_B2 DATA_B11 DATA_B14
OUT_FRST ADDR_A0 DATA_B13 DATA_B15 DATA_B16
DATA_B17 DATA_B18 DATA_B19
CK_IN CK_V
YIN9 FILM_FR
YIN5 YIN6 YIN7 YIN8 OUT_CK
YIN3 YIN4 GOUT9 GOUT8
CIN9 YIN0 YIN1 YIN2
CIN5 CIN6 CIN7 CIN8
VIEW
GF9320 TBGA
VDD: +3.3V GND:
GOUT7
GOUT6
GOUT5
GOUT4
GOUT3
GOUT2
GOUT1
CIN1 CIN2 CIN3 CIN4
GOUT0
CIN0 BOUT6 BOUT7 BOUT8 BOUT9
BOUT4
BOUT5
OUT_H OUT_V OUT_F
BOUT0
BOUT1
BOUT2
BOUT3
Connection
ROUT8 ROUT9
SIF_IN SIF_CK SIF_RST SIF_OUT ROUT5 ROUT6 ROUT7
ROUT1 ROUT2 ROUT3 ROUT4
ROUT0
TOUT1 TOUT2 DATA_D18 DATA_D19 CK_OUT
ADDR_C1 DATA_D13 DATA_D16 DATA_D17
ADDR_C0 ADDR_C3 CAS_C DATA_C1 DATA_C7 DATA_C11 DATA_C14 ADDR_D1 ADDR_D5 BA_D WE_D CS_D3 DATA_D2 DATA_D11 DATA_D14 DATA_D15
ADDR_C2 ADDR_C4 ADDR_C10 CS_C1 RAS_C DATA_C2 DATA_C8 DATA_C12 DATA_C15 ADDR_D0 ADDR_D4 ADDR_D10 CAS_D CS_D2 DATA_D4 DATA_D10 DATA_D12
ADDR_C5 ADDR_C6 ADDR_C9 CS_C0 CS_C3 CKEN_C DATA_C3 DATA_C5 DATA_C9 DATA_C16 DATA_C19 ADDR_D3 ADDR_D7 ADDR_D9 RAS_D CK_D CS_D1 DATAEN_CD DATA_D1 DATA_D5 DATA_D7 DATA_D9
ADDR_C7 ADDR_C8 BA_C CS_C2 WE_C CK_C DATA_C0 DATA_C4 DATA_C6 DATA_C10 DATA_C13 DATA_C17 DATA_C18 ADDR_D2 ADDR_D6 ADDR_D8 CKEN_D CS_D0 DATA_D0 DATA_D3 DATA_D6 DATA_D8
Figure 1-1: GF9320
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Table 1-1: Descriptions Symbol
YIN[9:0]
Grid
Type
Description
10-bit multiplexed signed luminance signed offset colour difference data input. Note that either input must include words.
CIN[9:0]
10-bit signed offset colour difference data input. Note that theinput must include words.
CK_IN
Input clock. Note that equal data rate separate inputs, equal data rate multiplexed input.
CK_V
Vertical processing clock. Note that usually higher CK_IN CK_OUT.
CK_OUT FILM_FR OUT_FRST GOUT[9:0]
AA26 K25, K26, L23, L24, L25, L26, M23, M25, M26,
Output clock. Input film sequence reset. Output frame reset. 8-bit unsigned green data output 8-bit unsigned luminance data output 8-bit multiplexed signed luminance signed offset colour difference data output.
BOUT[9:0]
P26, P25, P24, P23, R26, R23, T26, T25, T24,
8-bit unsigned blue data output 8-bit signed offset (B-Y) data output 10/8-bit multiplexed signed offset colour difference data output.
ROUT[9:0]
U26, U25, V25, V24, V23, W26, W25, W24, W23,
8-bit unsigned data output 8-bit signed offset (R-Y) data output.
OUT_CK OUT_F
Output clock timed clock output data. Output format frame field signal. Note that output clocks advance output video data.
OUT_V
Output format vertical signal. Note that output clocks advance output video data.
OUT_H
Output format horizontal signal. Note that output clocks advance output video data.
SIF_OUT SIF_IN SIF_CK SIF_RST DATA_A[19:0]
A15, D14, C14, B14, A14, A13, B13, A12, B12, C12, D12, C11, D11, A10, B10,
Serial interface control data out. Serial interface control data Serial interface clock. Serial interface reset. Power-on reset. Data memory array
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GF9320 Data Sheet
Table 1-1: Descriptions (Continued) Symbol
DATA_B[19:0]
Grid
F25, F24, F23, E26, E25, D26, E23, C26, D24, C25, B26, B25, A26, A25, B24, C23, A24, D22, B23, AE14, AF14, AF13, AE13, AD13, AC13, AF12, AD12, AC12, AF11, AE11, AD11, AC11, AF10, AE10, AF8, AE8, AD8, AC8, AA24, AA23, AB26, AB25, AC26, AC25, AB23, AD26, AC24, AD25, AE26, AF26, AE25, AF25, AE24, AD23, AF24, AC22, AE23, AF23 D18, C18, B18, B17, A17, D16, C16, B16, A16, D15, AD4, AE3, AF2, AF1, AE2, AE1, AD2, AC3, AD1, AB4, AD18, AE18, AF18, AE17, AF17, AC16, AD16, AE16, AF16, AC15, AD15 AC18 A22, D21, C21, AE5, AF4, AD5, AC21, AD21, AE21, AF21 AE19
Type
Description
Data memory array
DATA_C[19:0]
Data memory array
DATA_D[19:0]
Data memory array
ADDR_A[10:0] BA_A ADDR_B[10:0]
Address memory array SDRAM bank select memory array Address memory array
BA_B ADDR_C[10:0]
SDRAM bank select memory array Address memory array
BA_C ADDR_D[10:0]
SDRAM bank select memory array Address memory array
BA_D CS_A[3:0] CS_B[3:0] CS_C[3:0] CS_D[3:0] RAS_A RAS_B RAS_C RAS_D CAS_A CAS_B CAS_C
SDRAM bank select memory array Chip select memory array Chip select memory array Chip select memory array Chip select memory array address strobe memory array address strobe memory array address strobe memory array address strobe memory array Column address strobe memory array Column address strobe memory array Column address strobe memory array
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GF9320 Data Sheet
Table 1-1: Descriptions (Continued) Symbol
CAS_D WE_A WE_B WE_C WE_D CK_A CK_B CK_C CK_D CKEN_A CKEN_B CKEN_C CKEN_D DATAEN_AB DATAEN_CD
Grid
AD19 AC19 AE20 AF19 AE22 C10, A11, C13, C17, C20, AD3, AD7, AC9, AD10, AD14, AD17, C24, AD20, AF22, AD24, E24, Y24, G24, K24, N24, U24, R25, R24, U23, N23, K23, G26, G23, Y23, D25, AC20, AF20, AC17, D23, AC14, AC10, AC7, AC5, AC4, D20, A20, D17, B15, D13, B11, D10, AC23, J25, AE6, C22, AE12, M24, AD22, AB24, AA25, H26, J23, J24, A18, AA3, AA4, AB1, AB2, F26, AC1, AB3, N26, Y25, V26, AD9, H24, AE9, AF9, AE15, AF15, H23, H25, AA1,
Type
Description
Column address strobe memory array Write enable memory array Write enable memory array Write enable memory array Write enable memory array Clock memory array Clock memory array Clock memory array Clock memory array Clock enable memory array Clock enable memory array Clock enable memory array Clock enable memory array Data enable memory arrays Data enable memory arrays 3.3V supply.
Device ground.
connection.
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GF9320 Data Sheet
Electrical Characteristics
Table 2-1: Absolute Maximum Ratings Parameter
Power Supply Voltage Input Voltage Output Voltage Output Current Operating Temperature Storage Temperature
Symbol
TSTG
Conditions
Rated Value
-0.5 +4.6
Units
-0.5 +4.6 -0.5 +4.6 +150
Table 2-2: Recommend Operating Conditions Parameter
Power Supply Voltage High-Level Input Voltage Low-Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage Input Rise Time Input Fall Time
Symbol
Conditions
Min.
Typ.
Max.
Units
Interface Interface
Normal Input Normal Input
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GF9320 Data Sheet
Table 2-3: Characteristics 3.6V, 70oC, unless otherwise shown Parameter
Static Current Consumption Input Leakage Current Low-Level Output Current High-Level Output Current Low-Level Output Voltage High-Level Output Voltage Off-State Output Current Output Short-Circuit Current
Symbol
IDDS
Conditions
0.4V 2.4V
Min.
Typ.
±10-4
Max.
-250
Units
12.0 -2.0
Table 2-4: Capacitance 25oC; =1MHz Parameter
Input Capacitance Output Capacitance Capacitance
Symbol
Conditions
Min.
Typ.
Max.
Units
Table 2-5: Operating Current 3.6V, 70oC, unless otherwise shown Parameter
Operating Current
Symbol
Conditions
CK_IN 90MHz CK_OUT 90MHz CK_V 88MHz
Min.
Typ.
Max.
Units
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GF9320 Data Sheet
Table 2-6: Characteristics Setup Hold Times 3.6V, 70oC, unless otherwise shown Signal Name Min.
YIN[9:0] CIN[9:0] FILM_FR SIF_IN SIF_RST OUT_FRST DATA_A DATA_B DATA_C DATA_D
Setup Max.
Hold Min.
Reference Clock Max.
CK_IN CK_IN CK_IN SIF_CK SIF_CK CK_OUT CK_A CK_B CK_C CK_D
Units
Table 2-7: Characteristics Pulse Signal 3.6V, 70oC, unless otherwise shown Signal Name Pulse Width Min.
110a
Units
Max.
a.The minimum pulse width 64Mb SDRAMs. 16Mb used them 10µs width used.
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GF9320 Data Sheet
Table 2-8: Output Signal Timing Specifications Signal Name Valid Output Delay Min. (ns)
OUT_CK GOUT[9:0] BOUT[9:0] ROUT[9:0] ADDR_A, RAS_A, CAS_A, WE_A, CKEN_A, DATA_A ADDR_B, RAS_B, CAS_B, WE_B, CKEN_B, DATA_B ADDR_C, RAS_C, CAS_C, WE_C, CKEN_C, DATA_C ADDR_D, RAS_D, CAS_D, WE_D, CKEN_D, DATA_D 1.81 0.15 0.15 0.15 1.25 1.25 1.25 1.25
Reference Clock
Max. (ns)
3.97 CK_OUT OUT_CK OUT_CK OUT_CK CK_A CK_B CK_C CK_D
Table 2-9: Clock Frequency Clock Name Min. (MHz)
CK_IN CK_V CK_OUT SIF_CK
Frequency Max. (MHz)
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GF9320 Data Sheet
Detailed Device Description
Device Overview
system level block diagram shown "Block Diagram" page scaling performed cascading 1D-scaling filters. number horizontal input samples greater than number horizontal output samples (i.e. down sampling), then advantageous perform horizontal resizing first. Otherwise, horizontal resizing performed last. This minimizes number operations required, reduces intermediate image size thus lowers SDRAM requirements. addition, SDRAMs used field merge separation operations perform simple frame rate conversions (e.g. film applications. This minimizes chip memory required perform format conversion low-cost, high-quality format conversion. GF9320 fields frames delay depending selected operating mode. Processing performed simultaneously fields frames. Input processing performed field frame vertical processing performed field frame (N1) output processing performed field frame (N-2). input processor decodes input determine input video timing information. area input video selected according downloaded parameters. input video resized horizontally down sampling indicated. video passed picture memory control stored SDRAM. Field frame (N-1) read picture memory processed vertically, stored picture memory process video vertically read address picture memory transposes video data while write address picture memory transposes video data back. This transpose operation allows vertical processing done rows instead columns. Field frame (N-2) read picture memory resized horizontally sampling indicated. flexible output processor selected perform 4:2:2 4:4:4 colour difference over sampling, YCbCr conversion, colour background insertion output insertion.
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GF9320 Data Sheet
Serial Interface Control
serial interface download control parameters grouped into sets given Table 3-1: Serial Interface Download Groups. parameters downloaded once each downloaded individually. This grouping allows quick downloading dynamic parameters (e.g. zoom, pan, gain, etc.) only requires that static parameters downloaded once. Details individual control parameters provided Table 3-2: Serial Interface Download Parameters.
Table 3-1: Serial Interface Download Groups Name
Parametersa
00000000b
Bytes
Number Bits
1176
Description
download parameters.
Word
AP[1175:0]
Format Parameters
00100000b 01000000 01100000 10000000b 10100000b
(fill)
Input static output parameters. These parameters tend remain fixed once input output format selected. Resizing parameters. These parameters change with zoom, pan, crop controls.
IO[87:0]
Scaling Parameters
(fill)
RS[151:0]
Dynamic Output Parameters
(fill)
Dynamic output parameters. These parameters change with gain, position, line advance, etc.
OD[159:0]
Horizontal Filter Coefficients Vertical Filter Coefficients
(fill)
Horizontal filter.
HF[343:0]
(fill)
Vertical filter.
VF[431:0]
GF9320 download parameters grouped into sets. b.Each group will extended with zeros make integer number bytes. each group sent first. instance, format parameter group sends zero followed PROC_8_BITS followed OUT_8_BITS bit. download parameters (CMD sends word: AP[1175:0] IO[87:0] RS[151:0] OD[159:0] HF[343:0] VF[431:0] where represents concatenation. with other words AP[1175:0] sent first. CMD_ID word listed above binary form from LSB. with other words CMD_ID sent first. example, download dynamic output parameters (CMD_ID=3) sends zeros followed ones followed zero followed followed followed OD2.OD159. Note that CMD_IDs have zeros least significant bits that each download command starts with zeros.
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters Parameter Name
Format Parameters Input Format Parameters IN_PROGRESSIVE
Bits
Total Sub-total
Description
Word Position
Used
Time Frame
Indicates that input progressive. Interlaced Progressive
IO[87]
Input Control
IN_TOP_ACT_FLD
Used interlaced formats only. Indicates which field contains first active line frame. (i.e. which field top) Field Field
IO[86]
Input Control
IN_TOP_ACT_LONGER
Used interlaced formats only. Indicates field line longer than bottom field. Bottom fields contain same number active lines field more active line
IO[85]
Input Control
IN_YC_MUXED
Indicates input 10-bit muxed data. 10-bit buses CbCr Muxed data 10-bit
IO[84]
Input Control
IN_FILM_RATE
Input film frame rate. Used film inputs only. Input from film with pull-down Input from film with pull-down Input film rate (24/25 from film
IO[83:82]
Input Control
IN_REFR_LEFT
This indicates left memory array refresh required normally indicates that input from film. refresh Refresh
IO[81]
Memory Control
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
Memory Configuration MEM_CONFIG_LEFT
Bits
Sub-total
Description
Word Position
Used
Time Frame
Indicates number SDRAMs array left bank excluding chips needed LSBs necessary. (i.e. 8-bit processing) chips chips chips chip
IO[80:79]
Memory Control
MODE_16_LEFT
Maximum number left bank SDRAM memory rows used store horizontal active line. memory rows memory rows
IO[78]
Memory Control
MEM_CONFIG_RIGHT
Indicates number SDRAMs array right bank excluding chips needed LSBs necessary. (i.e. processing) chips chips chips chip
IO[77:76]
Memory Control
MODE_16_RIGHT
Maximum number right bank SDRAM memory rows used store horizontal active line. memory rows memory rows
IO[75]
Memory Control
PIX2READ
Number pixels pre-read. Vertical processing requires prereading samples that hits occur while processing column data. This indicates right memory array refresh required normally indicates that input from film. refresh Refresh
IO[74:68]
Memory Control
OUT_REFR_RIGHT
IO[67]
Memory Control
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
Static Output Format Parameters OUT_HLEN_TOT OUT_VLEN_TOT OUT_HLEN_ACT
Bits
Sub-total
Description
Word Position
Used
Time Frame
total number samples line. (e.g. 2200) total number output lines frame. (e.g. 1125) number active samples line minus (e.g. 1919 implies 1920 active samples) number active output lines minus (e.g. 1079 implies 1080 active lines) Indicates that output progressive. Interlaced Progressive
IO[66:55] IO[54:43] IO[42:32]
Output Timing Output Timing Output Timing Output Timing Output Timing Input Control Output Timing
OUT_VLEN_ACT
IO[31:21]
OUT_PROGRESSIVE
IO[20]
OUT_TOP_ACT_FLD
Used interlaced formats only. Indicates which field contains first active line frame. (i.e. which field top) Field Field
IO[19]
OUT_TOP_ACT_LONGER
Used interlaced formats only. Indicates field line longer than bottom field. Both fields have same number active lines field more active line
IO[18]
Output Timing
OUT_VACT_POS
position first active output line relative start frame. interlaced inputs this implies field
IO[17:10]
Output Timing
OUT_FLD_LONGER
Used interlaced formats only. Indicates which field longer. Interlaced formats contain number lines. field contains more lines. Field longer Field longer
IO[9]
Output Timing
OUT_REF
Input Output Reset GF9320 (OUT_FRST)
IO[8]
Output Timing
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
OUT_FILM_RATE
Bits
Description
Output film frame rate. Output pull-down sequence Output pull-down sequence Output film rate (24/25 Output film rate sequence
Word Position
IO[7:6]
Used
Output Timing Input Control
Time Frame
OUT_MODE
Indicates output port configuration. 4:4:4 Triple output 4:4:4 YCbCr Triple output 4:2:2 YCbCr Muxed single output 4:2:2 YCbCr Muxed dual output
IO[5:4]
Output
OUT_TRS_ON
Indicates inserted into output. inserted inserted
IO[3]
Output
OUT_8_BITS
Indicates that output rounded bits. 10-bit output 8-bit output
IO[2]
Output
PROC_8_BITS
Indicates that processing rounded 8-bits. 10-bit processing (Requires memory) 8-bit processing
IO[1]
Int. Filters
IO_FILL
used.
IO[0]
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
Resizing Parameters H_PROC_FIRST
Bits
Total
Description
Word Position
Used
Time Frame
Indicates horizontal processing performed first. Horizontal processing last (H_ZOOM_RATIO 524288) Horizontal processing first (H_ZOOM_RATIO 524288)
RS[151]
Glue Logic (Mux) Control
H_FLT_DEC
Horizontal filter decimate. Non-decimate mode Decimate mode
RS[150]
Control Filter
H_ZOOM_RATIO
Horizontal zoom ratio. IN_HLIVE 524288 -OUT_HLIVE H_FLT_DEC IN_HLIVE 524288 -OUT_HLIVE H_FLT_DEC
RS[149:128]
Control
IN_HSTART_PHASE IN_HSTART
Indicates starting horizontal phase used resampling. Indicates first sample used resampling.
RS[127:121] RS[120:110]
Control Input Timing Control Control Input Timing Control Control Output Timing Control Control Output Timing Control Control Filter
IN_HSTOP
Indicates last sample used resampling.
RS[109:99]
OUT_HSTART
Indicates placement first output sample with live data. This value must even.
RS[98:88]
OUT_HSTOP
Indicates placement last output sample with live data. This value must odd.
RS[87:77]
V_FLT_DEC
Vertical filter decimate. Non-decimate mode Decimate mode
RS[76]
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
V_ZOOM_RATIO
Bits
Description
Vertical zoom ratio. IN_VLIVE 524288 -OUT_VLIVE V_FLT_DEC IN_VLIVE 524288 -OUT_VLIVE V_FLT_VLIVE
Word Position
RS[75:54]
Used
Control
Time Frame
IN_VSTART_PHASE IN_VSTART
Indicates starting vertical phase used resampling. Indicates first line used resampling. Indicates last line used resampling. Indicates placement first output line with live data. Indicates placement last output line with live data. used.
RS[53:47] RS[46:36]
Control Input Timing Control Input Timing Control Output Timing Control Output Timing Control
IN_VSTOP
RS[35:25]
OUT_VSTART
RS[24:14]
OUT_VSTOP
RS[13:3]
RS_FILL Dynamic Output Parametersa Matrix Coefficients
Total Sub-total
RS[2:0]
matrix coefficient format ±2.10. (i.e. sign bit, integer bits fractional bits) Matrix coefficient. G1*Y G2*Cb G3*Cr Matrix coefficient. G1*Y G2*Cb G3*Cr Matrix coefficient. G1*Y G2*Cb G3*Cr Matrix coefficient. B1*Y B2*Cb B3*Cr Matrix coefficient. B1*Y B2*Cb B3*Cr Matrix coefficient. B1*Y B2*Cb B3*Cr Matrix coefficient. R1*Y R2*Cb R3*Cr OD[81:69] Output OD[94:82] Output OD[107:95] Output OD[120:108] Output OD[133:121] Output OD[146:134] Output OD[159:147] Output
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GF9320 Data Sheet
Table 3-2: Serial Interface Download Parameters (Continued) Parameter Name
Bits
Description
Matrix coefficient. R1*Y R2*Cb R3*Cr
Word Position
OD[68:56]
Used
Output
Time Frame
Matrix coefficient. R1*Y R2*Cb R3*Cr
OD[55:43]
Output
Background Colour Y_BKGD
Sub-total Background colour Unsigned integer. OD[42:35] Output
CB_BKGD
Background colour Signed integer.
OD[34:27]
Output
CR_BKGD
Background colour Signed integer.
OD[26:19]
Output
Output Timing LINE_ADV H_POS OD_FILL Filter Coefficients Horizontal Filter H_Y_FLT_COEF HYBANK: 12|12|11|10|10|9|9|9|9|8|8 filters (107 bits) H_C_FLT_COEF HCBANK: 12|11|9|9|8|8|8 filters bits) Vertical Filter V_Y_FLT_COEF HYBANK: 12|12|11|10|10|9|9|9|9|8|8 filters (107 bits) V_C_FLT_COEF HCBANK: 12|12|11|10|10|9|9|9|9|8|8 filters (107 bits) VYF_FILL
Sub-total Total Sub-total Horizontal filter coefficients. Center coefficient ±1.10. (i.e. sign bit, integer fractional bits) HY[343:130] (See footnoteb) Filter Line advance with respect input timing. Horizontal position with respect input timing. used. OD[18:15] OD[14:3] OD[2:0] Output Timing Output Timing
Horizontal filter coefficients. Center coefficient ±1.10. (i.e. sign bit, integer fractional bits)
HY[129:0] (See footnote
Filter
Sub-total Vertical filter coefficients. Center coefficient ±1.10. (i.e. sign bit, integer fractional bits) VY[431:218] (See footnotec) Filter
Vertical filter coefficients. Center coefficient ±1.10. (i.e. sign bit, integer fractional bits)
VY[217:4] (See footnotec)
Filter
used.
VY[3:0]
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GF9320 Data Sheet
a.The resizing parameters, dynamic output parameters, filter coefficients adjustable (dynamic). Format parameters static, i.e. once input output format selected format parameters tend remain fixed. b.HORIZONTAL COEFFICIENT DOWNLOAD FORMAT: HF[343:0] HYBANK1[106:0] HYBANK0[106:0] HCBANK1[64:0] HCBANK0[64:0] NON-DECIMATE MODE (H_FLT_DEC HYBANK0 contains coefficients 21-tap symmetric filter HCBANK0 contains coefficients 13-tap symmetric filter. HYBANK1 HCBANK1 used when H_FLT_DEC should contain HYBANK0[106:0] HYT0[11:0] HYT1[11:0] HYT2[10:0] HYT3[9:0] HYT4[9:0] HYT5[8:0] HYT6[8:0] HYT7[8:0] HYT8[8:0] HYT9[7:0] HYT10[7:0] HYBANK1[106:0] HCBANK0[64:0] HCT0[11:0] HCT1[10:0] HCT2[8:0] HCT3[8:0] HCT4[7:0] HCT5[7:0] HCT6[7:0] HCBANK1[64:0] DECIMATE MODE (H_FLT_DEC HYBANK0 HYBANK1 contain coefficients 41-tap symmetric decimation filter while HCBANK0 HCBANK1 contain coefficients 25-tap symmetric decimation filter. BANK0s contain center (tap taps (e.g. while BANK1s contain zero even taps (e.g. 6.). HYBANK0[106:0] HYT0[11:0] HYT1[11:0] HYT3[10:0] HYT5[9:0] HYT7[9:0] HYT9[8:0] HYT11[8:0] HYT13[8:0] HYT15[8:0] HYT17[7:0] HYT19[7:0] HYBANK1[106:0] "000000000000" HYT2[11:0] HYT4[10:0] HYT6[9:0] HYT8[9:0] HYT10[8:0] HYT12[8:0] HYT14[8:0] HYT16[8:0] HYT18[7:0] HYT20[7:0] HCBANK0[64:0] HCT0[11:0] HCT1[10:0] HCT3[8:0] HCT5[8:0] HCT7[7:0] HCT9[7:0] HCT11[7:0] HCBANK1[64:0] "000000000000" HCT2[10:0] HCT4[8:0] HCT6[8:0] HCT8[7:0] HCT10[7:0] HCT12[7:0] Further information horizontal filter coefficients given Filter Parameters (3.4.2.2 Filter Parameters). c.VERTICAL COEFFICIENT DOWNLOAD FORMAT: VF[431:0] VYBANK1[106:0] VYBANK0[106:0] VCBANK1[106:0] VCBANK0[106:0] "0000" NON-DECIMATE MODE (V_FLT_DEC VYBANK0 VCBANK0 both contain coefficients 21-tap symmetric filter. VYBANK1 VCBANK1 used when V_FLT_DEC should contain VYBANK0[106:0] VYT0[11:0] VYT1[11:0] VYT2[10:0] VYT3[9:0] VYT4[9:0] VYT5[8:0] VYT6[8:0] VYT7[8:0] VYT8[8:0] VYT9[7:0] VYT10[7:0] VYBANK1[106:0] VCBANK0[106:0] VCT0[11:0] VCT1[11:0] VCT2[10:0] VCT3[9:0] VCT4[9:0] VCT5[8:0] VCT6[8:0] VCT7[8:0] VCT8[8:0] VCT9[7:0] VCT10[7:0] VCBANK1[106:0] DECIMATE MODE (V_FLT_DEC VYBANK0 VYBANK1 together contain coefficients 41-tap symmetric decimation filter while VCBANK0 VCBANK1 together also contain coefficients 41-tap symmetric decimation filter. BANK0s contain center (tap taps (e.g. 5.19) while BANK1s contain zero even taps (e.g. 6.20). VYBANK0[106:0] VYT0[11:0] VYT1[11:0] VYT3[10:0] VYT5[9:0] VYT7[9:0] VYT9[8:0] VYT11[8:0] VYT13[8:0] VYT15[8:0] VYT17[7:0] VYT19[7:0] VYBANK1[106:0] "000000000000" VYT2[11:0] VYT4[10:0] VYT6[9:0] VYT8[9:0] VYT10[8:0] VYT12[8:0] VYT14[8:0] VYT16[8:0] VYT18[7:0] VYT20[7:0] VCBANK0[106:0] VCT0[11:0] VCT1[11:0] VCT3[10:0] VCT5[9:0] VCT7[9:0] VCT9[8:0] VCT11[8:0] VCT13[8:0] VCT15[8:0] VCT17[7:0] VCT19[7:0] VCBANK1[106:0] "000000000000" VCT2[11:0] VCT4[10:0] VCT6[9:0] VCT8[9:0] VCT10[8:0] VCT12[8:0] VCT14[8:0] VCT16[8:0] VCT18[7:0] VCT20[7:0]
GF9320 parameters downloaded using 3-pin serial interface. serial interface consists clock, data reset shown Figure 3-1: Serial Interface Download Signal Specification. serial interface reset (SIF_RST) provided re-synchronise download operation event that interrupted.
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GF9320 Data Sheet
clock gated flow control
SIF_CK
bits)
Data Message
Stop Bits
bits)
Data Message
Stop Bits
SIF_IN
SERIAL
DATA
Data
Held
Data
SIF_RST
SIF_IN: Serial Data Input. Must held high (logic message being sent SIF_CLK running. First byte sent CMD_ID. data including CMD_ID sent first. Valid choices CMD_ID are: 01234567 (00000000) download parameters (1176 data bits) (00000100): download parameters data bits) (00000010): download resizing parameters (152 data bits) (00000110): download Dynamic Output parameters (160 data bits) (00000001): download Horizontal Filter coefficients (344 data bits) (00000101): download Vertical Filter coefficients (432 data bits) SIF_CK: Serial Clock. data from SIF_IN clocked positive edge SIF_CK. SIF_CK held pause transmission (i.e. implement flow control). SIF_RST: Message Reset. Active asynchronous. Used recover from transmission error message abort. asserted between each message ensure correct initialization download, necessary general long correct message format indicated above) followed.
Figure 3-1: Serial Interface Download Signal Specification
Input Processing
input processor decodes input from incoming video stream. This provides input video timing information GF9320. area input video data selected scaling according downloaded parameters (i.e. IN_HSTART, IN_HSTOP, IN_VSTART, IN_VSTOP). This operation called windowing operation. Based input field frame timing format parameters memory enable signal generated input controller. This signal controls field frame switching SDRAM memory controller. Also, frame-reset signal sent output controller internal lock mode (OUT_REF=0). frame reset signal field frame switch point based input F-bit interlaced modes (non-film). Otherwise, (i.e. progressive film modes) frame reset signal field frame switch point based line after input V-bit. Note that film modes frame reset signal field frame switch point vary according input output frame rates.
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GF9320 Data Sheet
Scaling Processor
heart GF9320 scaling processor. here where input image selected from input video translated into output image selected size according user controlled scaling parameters. described Device Overview, general scaling performed cascading 1D-scaling filters. This section describes both horizontal vertical scaling filters. block diagram horizontal resizing filter shown Figure 3-2: Horizontal Scaling Filter. block diagram vertical resizing filter shown Figure 3-3: Vertical Scaling Filter.
RANGE ADJUST -512
±9.0
PASS FILTER DECIMATION FILTER
ROUND CLIP (11-BITS)
±10.0
INTERPOLATION FILTER PHASES
RANGE ADJUST +512
ROUND CLIP (10-BITS)
YADDR SCALE CONTROL CADDR
±9.0
PASS FILTER DECIMATION FILTER
ROUND CLIP (10-BITS)
±9.0
INTERPOLATION FILTER PHASES
ROUND CLIP (10-BITS)
±9.0
Figure 3-2: Horizontal Scaling Filter
RANGE ADJUST -512
±9.0
PASS FILTER DECIMATION FILTER
ROUND CLIP (11-BITS)
±10.0
INTERPOLATION FILTER PHASES
RANGE ADJUST +512
ROUND CLIP (10-BITS)
YADDR SCALE CONTROL CADDR
±9.0
PASS FILTER DECIMATION FILTER
ROUND CLIP (10-BITS)
±9.0
INTERPOLATION FILTER PHASES
ROUND CLIP (10-BITS)
±9.0
Figure 3-3: Vertical Scaling Filter
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GF9320 Data Sheet
3.4.1 Scalar Processing
General scaling performed cascading filter with interpolation filter. filter needed band limit input signal when output Nyquist frequency less than input Nyquist frequency. interpolation filter used resample input signal output rate. 3.4.1.1 Filter purpose filters band limit shape input signal. Each filter user programmable, with coefficients derived depending required frequency response. filter used modes: decimate non-decimate. Decimate mode used when output rate half input rate. advantage using decimate mode that number taps approximately doubled using input clocks compute output sample. non-decimate mode filter taps horizontal colour difference 4:2:2 input video structure). decimate mode filter taps horizontal colour difference). Vertically same modes available however 4:2:2 sampling structure both luma colour difference have equal numbers taps, i.e. taps decimate taps non-decimate. filter operation described
HYT0_0 1024 HYT0_0
H_FLT_DEC
H_FLT_DEC
HCT0_0 1024 HCT0_0
H_FLT_DEC
H_FLT_DEC
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GF9320 Data Sheet
VYT0_0 1024 VYT0_0
V_FLT_DEC
V_FLT_DEC
VCT0_0 1024 VCT0_0
V_FLT_DEC
V_FLT_DEC
where HYI(n), HCI(n), VYI(n) VCI(n) filter inputs, HYO(n), HCO(n), VYO(n) VCO(n) filter outputs, HYT, HCT, VYT, filter coefficients given Table 3-3: Horizontal Filter Coefficients Table 3-4: Vertical Filter Coefficients, 1024 gain filter. non-decimate mode only bank coefficients used (Bank decimate mode both banks coefficients used (Bank Bank 3.4.1.2 Interpolation Filter After filtering video data passed interpolation filter where rate conversion performed. interpolation filter polyphase filter that allows output phase adjusted every clock cycle. interpolation filter contains phases phases horizontal colour difference). phase selection allows generation output anywhere between inputs with 1/128 input pixel resolution (1/64 horizontal colour difference). scaling control unit takes input scaling ratio (input output), starting phase (starting position first output pixel with respect input). With these parameters, scaling control chooses correct phasing sequence interpolator, determines which input samples should held long sampling), which interpolator outputs should discarded (down sampling), generates output.
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GF9320 Data Sheet
3.4.2 Resizing Parameters
order understand program GF9320 perform necessary conversions explanation window parameters, zoom parameters filter parameters necessary. 3.4.2.1 Window Parameters Figure 3-4: Input Window Definition Progressive through Figure 3-7: Output Window Definition Interlaced show GF9320 places window over input output active video. This window selected using offsets from active video area (HSTART, HSTOP, VSTART, VSTOP). Note that VSTART VSTOP interlaced video refers field based offsets. windowed portion referred live video cover entire active video just portion size windowed portion HLIVE VLIVE pixels where: HLIVE HSTOP HSTART VLIVE VSTOP VSTART interlaced video field have more active line that other. This means that VLIVE longer that field. Also, interlaced film modes VSTART VSTOP still field-based offsets VLIVE frame based since fields merged processed frame. input video window determined IN_HSTART, IN_HSTOP, IN_VSTART, IN_VSTOP. size input windowed portion IN_HLIVE IN_VLIVE pixels. output video window determined OUT_HSTART, OUT_HSTOP, OUT_VSTART, OUT_VSTOP. size output windowed portion OUT_HLIVE OUT_VLIVE pixels.
HLEN_TOT HLEN_ACT FRAME START VACT_POS
VLEN_TOT
ACTIVE VIDEO
VLEN_ACT
VACT_POS VLEN_TOT VACT_POS VLEN_ACT
Figure 3-4: Input Window Definition Progressive
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GF9320 Data Sheet
HLEN_TOT HLEN_ACT FRAME START VACT_POS
Digital First Field
VLEN_TOT
Denotes integer division FLD_LONGER
ACTIVE VIDEO (VLEN_ACT+1)
TOP_ACT_FLD
VLEN_TOT
TOP_ACT_LONGER TOP_ACT_FLD
VACT_POS VACT_DIF
(FLD_LONGER TOP_ACT_FLD) (FLD_LONGER (TOP_ACT_FLD (FLD_LONGER (TOP_ACT_FLD
Digital Second Field
VLEN_TOT
FLD_LONGER
ACTIVE VIDEO TOP_ACT_LONGER TOP_ACT_FLD
(VLEN_ACT +1)\
VACT_POS VLEN_TOT 2*VACT_POS VLEN_ACT
VLEN_ACT even implies TOP_ACT_LONGER
Figure 3-5: Input Window Definition Interlaced
HLEN_TOT HLEN_ACT
VSTART
ACTIVE VIDEO
VLEN_TOT
VSTOP
LIVE VIDEO
VLEN_ACT+1
HSTOP HSTART HSTART HSTOP HLEN_ACT VSTART VSTOP VLEN_ACT
Figure 3-6: Output Window Definition Progressive
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GF9320 Data Sheet
HLEN_TOT HLEN_ACT
VSTART Digital First Field (F=0)
ACTIVE VIDEO
VLEN_TOT
Denotes integer division FLD_LONGER
TOP_ACT_LONGER TOP_ACT_FLD=0
VSTOP
LIVE VIDEO (VLEN_ACT+1)
TOP_ACT_LONGER TOP_ACT_FLD
VSTART Digital Second Field (F=1)
ACTIVE VIDEO VLEN_TOT LIVE VIDEO TOP_ACT_LONGER TOP_ACT_FLD FLD_LONGER
TOP_ACT_LONGER TOP_ACT_FLD=1
VSTOP
(VLEN_ACT+1)
HSTOP VLEN_ACT even implies TOP_ACT_LONGER HSTART HSTOP HLEN_ACT VSTART VSTOP (VLEN_ACT+1)
HSTART
Figure 3-7: Output Window Definition Interlaced
3.4.2.2 Filter Parameters filter shape programmable downloading filter coefficients. horizontal filter coefficients download positions given Table 3-3: Horizontal Filter Coefficients. vertical filter coefficients given Table 3-4: Vertical Filter Coefficients. overall gain filter 1024, range coefficients larger permit implementation enhancement filters. Note that coefficients change meaning depending filter structure (i.e. filter decimate mode not). filter structure determined FLT_DEC parameter. H_FLT_DEC then horizontal filter configured decimate mode. H_FLT_DEC then horizontal filter configured non-decimate mode. V_FLT_DEC then vertical filter configured decimate mode. V_FLT_DEC then vertical filter configured nondecimate mode.
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GF9320 Data Sheet
Table 3-3: Horizontal Filter Coefficients Parameter
twelve_zeros HYT2 HYT4 HYT6 HYT8 HYT10 HYT12 HYT14 HYT16 HYT18 HYT20 HYT0_0 HYT1_1 HYT3_2 HYT5_3 HYT7_4 HYT9_5 HYT11_6 HYT13_7 HYT15_8 HYT17_9 HYT19_10 twelve_zeros HCT2 HCT4 HCT6 HCT8 HCT10 HCT12 HCT0_0 HCT1_1 HCT3_2
Bits
Range
[-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-2048, 2047] [-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-1024, 1023] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-128, 127] [-2048, 2047] [-1024, 1023] [-256, 255]
Word Position
HF[343:332] HF[331:320] HF[319:309] HF[308:299] HF[298:289] HF[288:280] HF[279:271] HF[270:262] HF[261:253] HF[252:245] HF[244:237] HF[236:225] HF[224:213] HF[212:202] HF[201:192] HF[191:182] HF[181:173] HF[172:164] HF[163:155] HF[154:146] HF[145:138] HF[137:130] HF[129:118] HF[117:107] HF[106:98] HF[97:89] HF[88:81] HF[80:73] HF[72:65] HF[64:53] HF[52:42] HF[41:33]
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GF9320 Data Sheet
Table 3-3: Horizontal Filter Coefficients (Continued) Parameter
HCT5_3 HCT7_4 HCT9_5 HCT11_6
Bits
Range
[-256, 255] [-128, 127] [-128, 127] [-128, 127]
Word Position
HF[32:24] HF[23:16] HF[15:8] HF[7:0]
Table 3-4: Vertical Filter Coefficients Parameter
twelve_zeros VYT2 VYT4 VYT6 VYT8 VYT10 VYT12 VYT14 VYT16 VYT18 VYT20 VYT0_0 VYT1_1 VYT3_2 VYT5_3 VYT7_4 VYT9_5 VYT11_6 VYT13_7 VYT15_8 VYT17_9 VYT19_10 twelve_zeros VCT2 VCT4
Bits
Range
[-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-2048, 2047] [-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-2048, 2047] [-1024, 1023]
Word Position
VF[431:420] VF[419:408] VF[407:397] VF[396:387] VF[386:377] VF[376:368] VF[367:359] VF[358:350] VF[349:341] VF[340:333] VF[332:325] VF[324:313] VF[312:301] VF[300:290] VF[289:280] VF[279:270] VF[269:261] VF[260:252] VF[251:243] VF[242:234] VF[233:226] VF[225:218] VF[217:206] VF[205:194] VF[193:183]
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GF9320 Data Sheet
Table 3-4: Vertical Filter Coefficients (Continued) Parameter
VCT6 VCT8 VCT10 VCT12 VCT14 VCT16 VCT18 VCT20 VCT0_0 VCT1_1 VCT3_2 VCT5_3 VCT7_4 VCT9_5 VCT11_6 VCT13_7 VCT15_8 VCT17_9 VCT19_10 fill
Bits
Range
[-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127] [-2048, 2047] [-2048, 2047] [-1024, 1023] [-512, 511] [-512, 511] [-256, 255] [-256, 255] [-256, 255] [-256, 255] [-128, 127] [-128, 127]
Word Position
VF[182:173] VF[172:163] VF[162:154] VF[153:145] VF[144:136] VF[135:127] VF[126:119] VF[118:111] VF[110:99] VF[98:87] VF[86:76] VF[75:66] VF[65:56] VF[55:47] VF[46:38] VF[37:29] VF[28:20] VF[19:12] VF[11:4] VF[3:0]
3.4.2.3 Zoom Parameters zoom parameters (IN_HSTART_PHASE, IN_VSTART_PHASE, H_ZOOM_RATIO, V_ZOOM_RATIO) specify precise conversion from input live video output live video. IN_HSTART_PHASE IN_VSTART_PHASE allows starting interpolator with sub-pixel accuracy. This allows maintaining true center picture when zooming panning. zoom ratio approximately:
IN_HLIVE 524288 OUT_VLIVE H_ZOOM_RATIO IN_HLIVE 524288 OUT_HLIVE IN_VLIVE 524288 OUT_VLIVE V_ZOOM_RATIO IN_VLIVE 524288 OUT_VLIVE
H_FLT_DEC H_FLT_DEC V_FLT_DEC V_FLT_DEC
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GF9320 Data Sheet above equations hold only approximately because zoom ratio must adjusted maintain true center picture. When using GF9320 there preventable condition whereby certain memory configurations cause artifacts output image. dependent upon vertical parameters output video number SDRAMS employed right memory bank follows: OUT_VLIVE modulo Where number memories each array right bank, MEM_CONFIG_RIGHT, OUT_VLIVE OUT_VSTOP OUT_VSTART Artifacts avoided monitoring condition. When detected, subtract from OUT_VSTOP value while maintaining condition: OUT_VSTART OUT_VSTOP Note that both fields must checked this condition when output interlaced with field longer.
3.4.3 Dynamic Zoom Considerations
GF9320 designed perform frame accurate zooming panning. Some downloaded zoom parameters used multiple blocks within GF9320. These blocks operate video data different time frames. instance, input control block operates video data frame field while vertical scaling block operates video data frame field (N-1). Both these blocks need IN_VSTART parameter. IN_VSTART parameter must used scaling block field frame later than input block. Registering IN_VSTART parameter field frame boundary before scaling block uses does this. While most dynamic zoom situations taken care automatically GF9320, some dynamic zoom conditions require special downloading. 3.4.3.1 H_PROC_FIRST Switching H_PROC_FIRST download special because actually changes configuration GF9320. particular, changing H_PROC_FIRST from makes horizontal filter switch from operating field frame operating field frame (N-2) vice versa. Note that changing H_PROC_FIRST from changing from down sampling sampling. order handle this special case smoothly, horizontal zoom factor must downloaded.
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GF9320 Data Sheet recommended sequence switching from H_PROC_FIRST equal (i.e. down sampling sampling) Keep H_PROC_FIRST equal download H_ZOOM_RATIO equal 524,288 (down sampling). Wait least frames fields. Change H_PROC_FIRST download H_ZOOM_RATIO equal 524,287 sampling). Change desired H_ZOOM_RATIO. recommended sequence switching from H_PROC_FIRST equal (i.e. sampling down sampling) Keep H_PROC_FIRST equal download H_ZOOM_RATIO equal 524,287 sampling). Change H_PROC_FIRST download H_ZOOM_RATIO equal 524,288 (down sampling). Change desired H_ZOOM_RATIO. 3.4.3.2 V_FLT_DEC Switching vertical filter operates field frame (N-1), vertical filter coefficients operate field frame (N). When V_FLT_DEC switched from vice versa, vertical filter coefficients must delayed field frame that they operate same time frame. This necessary because filter coefficients used differently decimation mode non-decimation filter would used decimation mode vice versa. This would most directly affect gain filter that perceived brightness change output video. horizontal coefficients need delayed when switching H_FLT_DEC because horizontal filter horizontal coefficients operate same frame field (N). Even though H_FLT_DEC switched, down sampling (H_PROC_FIRST=1) indicated. Delaying vertical filter coefficients necessary depending application. 3.4.3.3 Pseudo Synchronous Film Mode Conversions This section applies film mode conversion when input frame rate output film rate pull-down, input rate (i.e. 60). these cases zoom update rate restricted every other film frame shown Figure 3-8: 24/24/60 Download Restrictions Figure 3-9: 48/24/60 Download Restrictions. This because output circuit must updated output field frame boundary.
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GF9320 Data Sheet
IN_FILM_RATE=2 OUT_FILM_RATE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR
VIDEO SEQUENCE
VERTICAL PROCESSING:
OE_AB
VIDEO SEQUENCE OE_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE
download shaded regions (OE_AB=1). GF9320 downloaded shaded region, output circuit will updated middle output field/frame will cause field/ frame output invalid.
Figure 3-8: 24/24/60 Download Restrictions
IN_FILM_RATE=1
OUT_FILM_RATE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
OE_AB VIDEO SEQUENCE OE_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
download shaded regions (OE_AB=1). GF9320 downloaded shaded region, output circuit will updated middle output field/frame will cause field/ frame output invalid.
Figure 3-9: 48/24/60 Download Restrictions
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GF9320 Data Sheet
SDRAM Memory Interface
3.5.1 Memory Interface Description
achieve high quality scaling images dimensions, separate processing done horizontal vertical dimensions using dimensional filter banks. Hence, input image transposed before after vertical processing uses SDRAMs achieve real-time transposition digital video images using high quality filters. SDRAM controller within GF9320 acts master controller memory arrays. perform transpose operation memory controller writes entire image from field into image buffer then reads during next field. Further, during film mode processing, controller consecutive image fields together read them next frame single progressive frame. latter technique used processing film material with pull-down. also separate even fields from progressive frame create film material with pull-down. memory organization transposing images high data rates shown Figure 3-10: Memory Interface.
DATA[19:0]
DATA_A[19:0]
DATA_C[19:0]
DATA[19:0]
ADDR[10:0]
ADDR_A[10:0] BA_A CK_A CKEN_A RAS_A CAS_A WE_A CS_A[3:0] DATAEN_AB
ADDR_C[10:0] BA_C CK_C CKEN_C RAS_C CAS_C WE_C CS_C[3:0] DATAEN_CD
ADDR[10:0] CLKEN CS[3:0] DATAEN
MEMORY ARRAY
CLKEN CS[3:0] DATAEN
MEMORY ARRAY
GF9320
DATA[19:0]
DATA_B[19:0]
DATA_D[19:0]
DATA[19:0]
ADDR[10:0]
ADDR_B[10:0] BA_B CK_B CKEN_B RAS_B CAS_B WE_B CS_B[3:0]
DATAEN_AB
ADDR_D[10:0] BA_D CK_D CKEN_D RAS_D CAS_D WE_D CS_D[3:0]
DATAEN_CD
ADDR[10:0] CLKEN CS[3:0] DATAEN
MEMORY ARRAY
CLKEN CS[3:0] DATAEN
MEMORY ARRAY
Figure 3-10: Memory Interface
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GF9320 Data Sheet memory organization consists four arrays memories communicating with GF9320. Each array contain anywhere between five SDRAMs based format conversion mode. Memory array compose left bank while memory array compose right bank. achieve high bandwidth, memory arrays arranged interleaved fashion. That when field written into memory array other field will read memory array sequence read write operations that takes place non-film applications shown Figure 3-11: Timing Diagram Data between GF9320 SDRAMs non-film Modes.
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
MEMORY ARRAY
WRITE FIELD1
READ FIELD1
WRITE FIELD3
READ FIELD3
WRITE FIELD5
MEMORY ARRAY
WRITE FIELD2
READ FIELD2
WRITE FIELD4
READ FIELD4
MEMORY ARRAY
WRITE FIELD1
READ FIELD1
WRITE FIELD3
READ FIELD3
MEMORY ARRAY
WRITE FIELD2
READ FIELD2
WRITE FIELD4
Figure 3-11: Timing Diagram Data between GF9320 SDRAMs nonfilm Modes
data from field written into memory array during Field3. same time data from previous (even) field will read transposed image from memory array horizontal rows data read from memory array will then processed (vertical processing) within GF9320 written into memory array Simultaneously, vertically processed image data from fields back which written into memory array will read out. When image read from memory array went through another image transposition that image back original orientation. Effectively, there field frame delay when processing non-film material. GF9320 experiences significantly more processing time vertical processing section bandwidth limitations SDRAMs. some conversions processing time might exceed available time. This condition circumvented either increasing number memories array increasing processing clock rate. During vertical processing, GF9320 pre-reads (number pixels PIX2READ) into internal FIFO, before beginning every scan line that supply pixels from FIFO into one-dimensional filter uninterrupted way. number pixels pre-read chosen based several parameters that high enough supply data continuously filter enough complete vertical processing available time.
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GF9320 Data Sheet PIX2READ parameter calculated
IN_VLEN_ACT IN_PROGRESSIVE PIX2READ {MAX CEIL ,10), 127} MEM_CONFIG_LEFT
Where IN_VLEN_ACT total number active lines frame, CEIL(x) smallest integer larger than
(a,b) (a,b)
80Mbits 16Mbit SDRAMs required store 2048 2048 bits (maximum image size). illustrated Figure 3-12: Architecture Memory Array with four 1Mx16 4Mx4 SDRAMs, memory array 20-bit data path, supported blocks four 1Mx16 SDRAMs 4Mx4 used parallel, sharing common address control bus. 1Mx16 SDRAMs store upper significant bits luminance Y[10:2] colour difference C[10:2]. 4Mx4 SDRAM stores lower significant bits Y[1:0] C[1:0].
DATA[19:0] DATA[19:4] DQ[15:0] ADDR[10:0] CLKEN DATAEN A[10:0] SDRAM0 1Mx16 DATA[19:4] DQ[15:0] A[10:0] SDRAM1 1Mx16 DATA[19:4] DQ[15:0] A[10:0] SDRAM2 1Mx16 DATA[19:4] DQ[15:0] A[10:0] SDRAM3 1Mx16 DATA[3:0] DQ[15:0] A[10:0] SDRAM(LSB) 4Mx4
CS[3:0]
Figure 3-12: Architecture Memory Array with four 1Mx16 4Mx4 SDRAMs
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GF9320 Data Sheet elements array simultaneously selected command execution activating chip select signals commands directed particular element array activating chip select signal that element deactivating chip select signal others. Figure 3-13: Memory Array Architecture with Four 4MX16 16MX4 SDRAMs shows connections (and slightly different addressing requirements) needed more common SDRAMs within memory array. number memories given format conversion remains same independent memory (16M 64M) being used.
DATA[19:0] DATA[19:4] DQ[15:0] ADDR[10:0] CLKEN DATAEN BA[0] A[10:0] A[11] BA[1] CS[3:0] SDRAM0 4Mx16 DATA[19:4] DQ[15:0] BA[0] A[10:0] A[11] BA[1] SDRAM1 4Mx16 DATA[19:4] DQ[15:0] BA[0] A[10:0] A[11] BA[1] SDRAM2 4Mx16 DATA[19:4] DQ[15:0] BA[0] A[10:0] A[11] BA[1] SDRAM3 4Mx16 DATA[3:0] DQ[3:0] BA[0] A[10:0] A[11] BA[1] SDRAM(LSB) 16Mx4
Figure 3-13: Memory Array Architecture with Four 4MX16 16MX4 SDRAMs
reduce system cost, memory array architecture made scalable. That when transposing smaller image sizes when processing 8-bit images, lesser number SDRAMs memory array required. Table 3-5: Minimum SDRAM Configurations Mode (default mode) shows memory requirements various format conversions.
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GF9320 Data Sheet
Table 3-5: Minimum SDRAM Configurations Mode (default mode) Image Width (max) (Input Image Height, Output Image Height)a
2048 2048 2048 1536 2048 1024 2048
Number SDRAMs required ARRAY 10-bits
(1Mx16) (4Mx4) (1Mx16) (4Mx4) (1Mx16) (4Mx4) (1Mx16) (4Mx4)
Download Parameters
8-bits
(1Mx16) (1Mx16) (1Mx16) (1Mx16)
MDLb
MCLc
MDRd
MCRe
max(a, when else when b.MDL stands parameter MODE_16_LEFT. c.MCL stands parameter MEM_CONFIG_LEFT. d.MDR stands parameter MODE_16_RIGHT. e.MCR stands parameter MEM_CONFIG_RIGHT.
Figure 3-14: Architecture Memory Array with Lesser Number SDRAMs Array shows memory array architecture when number memories reduced SDRAMS SDRAM processing) memory array.
DATA[19:0] DATA[19:4] DQ[15:0] ADDR[10:0] CLKEN DATAEN A[10:0] SDRAM0 1Mx16 DATA[3:0] DQ[15:0] A[10:0] SDRAM(LSB) 4Mx4
DATA[19:0] DATA[19:4] DQ[15:0] ADDR[10:0] CLKEN DATAEN CS[3:0] A[10:0] SDRAM0 1Mx16 DATA[3:0]
CS[3:0]
SDRAMs Array;
SDRAMs Array, proccessing pulled down with resistor ground
Figure 3-14: Architecture Memory Array with Lesser Number SDRAMs Array
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GF9320 Data Sheet
3.5.2 SDRAM Specifications
speed grade SDRAM chosen depending processing clock frequency. example, processing clock running 74.25MHz, SDRAM with speed grade 100MHz should selected.
3.5.3 Special Processing
3.5.3.1 Model further decrease memory requirements expense processing time additional mode available. Table 3-6: Minimum SDRAM Configurations Mode summarizes memory requirements various format conversions this mode.
Table 3-6: Minimum SDRAM Configurations Mode Image Width (max) (Input Image Height, Output Image Height)a
1024 2048 1024 1024
Number SDRAMs required ARRAY 10-bits
(1Mx16) (4Mx4) (1Mx16) (4Mx4)
Download Parameters
8-bits
(1Mx16) (1Mx16)
MDLb
MCLc
MDRd
MCRe
a.max when else when b.MDL stands parameter MODE_16_LEFT. c.MCL stands parameter MEM_CONFIG_LEFT. d.MDR stands parameter MODE_16_RIGHT. e.MCR stands parameter MEM_CONFIG_RIGHT.
3.5.4 Film Processing
During film processing GF9320 uses external signals FILM_FR OUT_FRST encode decode pull-down sequence. timing these signals different modes (film non-film) shown Figure 3-15: 60/60/60 Processing through Figure 3-40: 24p/24p/48p Processing. When input video from film material with pull-down, GF9320 processes image vertically after combining even fields achieve better quality resizing. Duplicate fields input sequence rejected writing into memory. Note that film modes memory switching does occur every field frame boundary. depends input output film formats. example, when input video with pull-down, left array memories switch only after even fields have been together. switching point shown timing diagram DATAEN_AB DATAEN_CD signals that are, respectively, output enable signals left right arrays. GF9320 achieves pull-down output separately reading even fields.
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GF9320 Data Sheet film sequences shown Figure 3-15: 60/60/60 Processing through Figure 340: 24p/24p/48p Processing only film frame sequences that GF9320 generate. Note that through input video sequence through Figure 3-16: 30i/24p/24i Processing Figure 3-34: 48p/24p/24p Processing denotes discarded frame when performing pulldown compensation. Other input output film sequences possible. input control uses rising edge FILM_FR input film sequence film frame reset sent output controller. first V-bit after rising edge FILM_FR marks beginning (starting with film sequences.
IN_FILM_RATE=3 OUT_FILM_RATE=3
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE
DATAEN_CD VIDEO SEQUENCE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE
Figure 3-15: 60/60/60 Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=1 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-16: 30i/24p/24i Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-17: 60p/24p/24p Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-18: 30i/24p/24p Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE **FILM SEQUENCE
Film sequence maintained output.
Figure 3-19: 60p/24p/30i Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_REF=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Film sequence output same input. (OUT_REF
Figure 3-20: 60p/24p/30i (OUT_REF=1) Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE **FILM SEQUENCE
Film sequence maintained output.
Figure 3-21: 30i/24p/30i Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_REF=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
***Film sequence output same input. (OUT_REF=
Figure 3-22: 30i/24p/30i (OUT_REF=1) Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=1 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
DO+DE
O+DE
AO+AE
AO+AE
BO+BE
BO+BE
O+CE
CO+CE
DO+DE
Figure 3-23: 30i/24p/48p Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=1 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-24: 60p/24p/48p Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE
DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-25: 60p/24p/24i Processing
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GF9320 Data Sheet
IN_FILM_RATE=0 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-26: 60p/24p/60p Processing
IN_FILM_RATE=0 IN_PROGRESSIVE=0
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
DO+D
BO+BE BO+BE
Figure 3-27: 30i/24p/60p Processing
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GF9320 Data Sheet
IN_FILM_RATE=1 IN_PROGRESSIVE=0
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
O+CE
O+DE
AO+AE
BO+BE
O+CE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
Figure 3-28: 24i/24p/30i Processing
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
Figure 3-29: 48p/24p/30i Processing
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GF9320 Data Sheet
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
Figure 3-30: 48p/24p/60p Processing
IN_FILM_RATE=1 IN_PROGRESSIVE=0
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE
AO+AE
BO+BE
O+CE
O+DE
AO+AE
DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
O+DE DO+D DO+D AO+AE AO+AE BO+BE BO+BE BO+BE O+CE CO+C O+DE
Figure 3-31: 24i/24p/60p Processing
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GF9320 Data Sheet
IN_FILM_RATE=1 IN_PROGRESSIVE=0
OUT_FILM_RATE=1 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR
VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
AO+AE
BO+BE
O+CE
O+DE
AO+AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
Figure 3-32: 24i/24p/24i Processing
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=1 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
Figure 3-33: 48p/24p/24i Processing
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GF9320 Data Sheet
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-34: 48p/24p/24p Processing
IN_FILM_RATE=1 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
AO+AE
BO+BE
O+CE
O+DE
AO+AE
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
O+DE
AO+AE
BO+BE
Figure 3-35: 24i/24p/24p Processing
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GF9320 Data Sheet
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-36: 24p/24p/30i Processing
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=1 OUT_PROGRESSIVE=0
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE
DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-37: 24p/24p/24i Processing
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GF9320 Data Sheet
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=2 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-38: 24p/24p/24p Processing
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=0 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST VIDEO SEQUENCE FILM SEQUENCE
Figure 3-39: 24p/24p/60p Processing
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GF9320 Data Sheet
IN_FILM_RATE=2 IN_PROGRESSIVE=1
OUT_FILM_RATE=1 OUT_PROGRESSIVE=1
INPUT PROCESSING:
FIELD/FRAME PULSE FILM_FR VIDEO SEQUENCE FILM SEQUENCE
VERTICAL PROCESSING:
DATAEN_AB
VIDEO SEQUENCE DATAEN_CD
OUTPUT PROCESSING:
FIELD/FRAME PULSE OUT_FRST
VIDEO SEQUENCE FILM SEQUENCE
Figure 3-40: 24p/24p/48p Processing
During film processing there possibility that some conversions GF9320 could violate refresh period SDRAM. violation found (IN_REFR_LEFT OUT_REFR_RIGHT '1'), then appropriate (left right) refresh should activated download stream parameters GF9320. Alternatively, Table 3-7: Input Output Formats Requiring Refresh used determine which input output formats require refresh bits active.
Table 3-7: Input Output Formats Requiring Refresh Input Format IN_REFR_LEFT=1
24p/25p 48p/50p 30i/60p with pull-down
Output Format OUT_REFR_RIGHT=1
24p/25p
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GF9320 Data Sheet
3.5.5 Processing Delay
Processing delay video through GF9320 depends conversion. Table 3-8: Processing Delay Various Conversions shows processing delay different film non-film modes.
Table 3-8: Processing Delay Various Conversions Conversion Delay (Input Frames Fields)
[frame field modes 60Hz processing]
Note: other frame rates identical with appropriate time scaling 1/30 seconds fields) 1/30 seconds fields) 1/30 seconds frames) 1/30 seconds frames)
[2:2 modes 30Hz processing]
1/15 seconds fields) 1/15 seconds frames) 1/15 seconds frames) 1/15 seconds frames) 1/15 seconds fields) 1/15 seconds fields)
[3:2 modes 24Hz processing]
1/10-1/12 seconds (5-6 fields) 1/10-1/12 seconds (5-6 fields) 3/40-1/12 seconds (4.5-5 fields) 3/40-1/12 seconds (4.5-5 fields) 3/40-1/12 seconds (4.5-5 fields) 3/40-1/12 seconds (4.5-5 fields) 3/40-1/12 seconds (3.6-4 fields) 3/40-1/12 seconds (3.6-4 fields) 3/40-1/12 seconds (1.8-2 frames) 3/40-1/12 seconds (1.8-2 frames)
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GF9320 Data Sheet
3.5.6 Descriptions
GF9320 uses transpose memory interface signals communicate with external memory (SDRAMs). GF9320 master device interface controls timing address data flow. Each signal interface described follows: 3.5.6.1 Address ADDR_A[10:0], ADDR_B[10:0], ADDR_C[10:0], ADDR_D[10:0] address shared memories array. address BA_A (Bank Select) selects which bank active memory array. BA_A selects bank BA_A high selects bank within memory. During bank activate command cycle, ADDR_A[10:0] defines address when sampled rising clock edge. During read write cycle, ADDR_A[9:0] defines column address when sampled rising clock edge. addition column address ADDR_A10 used invoke auto-precharge operation. Similarly, ADDR_B[10:0], ADDR_C[10:0], ADDR_D[10:0] form address memory arrays respectively. 3.5.6.2 Data DATA_A[19:0], DATA_B[19:0], DATA_C[19:0], DATA_D[19:0] data bi-directional. Valid data driven data GF9320 during write cycle, which accepted back GF9320 during read cycles. These cycles involve transfers bursts data between SDRAM core registers GF9320. Luminance data Y[9:2] available DATA_A/B/C/ D[19:12] while least significant bits Y[1:0] available DATA_A/B/C/D[3:2]. Colour difference data C[9:2] available DATA_A/B/C/D[11:4] while least significant bits C[1:0] available DATA_A/B/C/D[1:0]. 3.5.6.3 Command [RAS_A, CAS_A, WE_A], [RAS_B, CAS_B, WE_B], [RAS_C, CAS_C, WE_C], [RAS_D, CAS_D, WE_D] These signals asserted GF9320 when commands have executed SDRAM memory array Similarly, [RAS_B, CAS_B, WE_B], [RAS_C, CAS_C, WE_C] [RAS_D, CAS_D, WE_D] asserted execute commands memory array respectively. These signals considered valid only respective during active edge clock.
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GF9320 Data Sheet CKEN_A, CKEN_B, CKEN_C, CKEN_D CKEN_A, CKEN_B, CKEN_C CKEN_D used drive memory arrays respectively. CKEN input suspends data (i.e. read data remains valid write data inhibited) during active read write. GF9320 activates CKEN_A CKEN_B signals during field frame write cycle drop pixels. CKEN_C CKEN_D activated during field frame read cycle hold pixel values. These signals considered valid only respective during active edge clock. CS_A[3:0], CS_B[3:0], CS_C[3:0], CS_D[3:0] CS_A[3:0] signals from GF9320 allows selection individual multiple SDRAMs within memory array appropriate SDRAM(s) selected when respective CS_A[3:0] active rising edge clock. CS_B[3:0], CS_C[3:0] CS_D[3:0] select SDRAMs within memory arrays respectively. DATAEN_AB, DATAEN_CD These signals driven GF9320 only during start-up prevent data contention. When sampled high, places data buffers within SDRAM high impedance state. After successful initialization, DATAEN_AB DATAEN_CD stay until next power-up reset. DATAEN_AB shared memories banks while DATAEN_CD shared memories banks CK_A, CK_B, CK_C, CK_D CK_A, CK_B, CK_C CK_D clock signals, which drive SDRAMs clock pins memory array respectively.
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GF9320 Data Sheet
Output Processor
block diagram output processor shown Figure 3-41: Output Processor Block Diagram. output processor consists three major functions: Colour difference over-sample Matrix conversion Output format colour difference over-sample function necessary colour matrix conversion provide 4:4:4 output. colour difference over-sample block also performs colour background insertion horizontal edge shaping. Horizontal edge shaping done eliminate overshoot edges when scaled output does fill entire output raster. That when OUT_HSTART greater that left edge shaping when OUT_HSTOP less than OUT_HLEN_ACT right edge shaping. programmable flat matte colour background inserted into output non-live video. Note that colour background inserted prior matrix conversion. This means that downloaded background colour input colour space coordinates.
YMAT_IN COLOUR DIFFERENCE OVERSAMPLE CBMAT_IN ±9.0 CRMAT_IN ±9.0 MATRIX BLANK OUTPUT FORMAT Y_G_DATA_OUT CB_B_DATA_OUT CR_R_DATA_OUT
R_RAMP_OFF L_RAMP_OFF FILL Y_FROM_FILTER C_FROM_FILTER Y_FROM_MEMORY C_FROM_MEMORY ±9.0 ±9.0
YMAT_OUT CBMAT_OUT ±9.0 CRMAT_OUT ±9.0
H_PROC_FIRST Y_BKGD CB_BKGD CR_BKGD OUT_8_BITS OUT_MODE OUT_TRS_ON OUT_MODE CK_OUT
OUT_MODE 4:4:4 TRIPLE OUTPUT 4:4:4 YCbCr TRIPLE OUTPUT 4:2:2 YCbCr MUXED SINGLE OUPUT 4:2:2 YCbCr MUXED DUAL OUTPUT
NOTE: inputs from serial interface enter from bottom. inputs from output timing circuit enter from top.
Figure 3-41: Output Processor Block Diagram
matrix block performs following operations:
YMAT CBMAT CRMAT YMATOUT 1024
YMAT CBMAT CRMAT PBMATOUT OFFSET 1024
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GF9320 Data Sheet
YMAT CBMAT CRMAT PRMAT OFFSET 1024
where YMATIN, CBMATIN CRMATIN inputs matrix; YMATOUT, CBMATOUT CRMATOUT outputs matrix; matrix coefficients; COFFSET given
OFFSET OUT_MODE otherwise
1024 gain matrix. matrix coefficients provide +6dB range gain adjustments. components input matrix complement format. components output matrix unsigned output mode (OUT_MODE=0) offset binary YCbCr output mode (OUT_MODE=1, matrix coefficients completely programmable downloaded described Serial Interface Control. output format block formats data into one, three channels according OUT_MODE parameter inserts output format TRS. enabled, data clipped 1019 10-bits 8-bits.
Output Timing Control
output timing control block determines output video data timing. This block contains horizontal vertical counters based output format parameters. output timing adjusted relative reference using LINE_ADV H_POS parameters. output reference either input OUT_REF OUT_FRST GF9320 OUT_REF This provides internal external lock capability. LINE_ADV parameter advances output video data LINE_ADV output lines. H_POS parameter delays output video data H_POS samples. range H_POS output line OUT_HLEN_TOT samples. Only limited ranges input output timing relationships available using GF9320. general, there fields frames delay through GF9320. possible GF9320 have output timing relationship such that last active output line occurs after SDRAM field frame switch point.
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GF9320 Data Sheet
Package Dimensions
1.27 33.02 35.00 0.20
0.75 0.15 352)
35.00 0.20
Figure 4-1: Package Dimensions
1.40 30/-0.20
Proprietary Confidential
18090
November 2004
GF9320 Data Sheet
Revision History
Version
134925 133502
Date
November 2004 June 2004 November 2002
Changes Modifications
Corrections address pins: ADDR_A[10:0], ADDR_B[10:0], ADDR_C[10:0], ADDR_D[10:0], BA_A, BA_B, BA_C BA_D. Changed BOUT description. Changed template. OUT_VLIVE issue workaround Change RST, SIF_RST, RAS, descriptions active low. Make same changes throughout -Make 60I->30i changes consistency. Updating GF9320. Remove "Preliminary Confidential" water marks references with document. Correction required both Figure table titled "Output Signal Timing Specification". Correction figure page other improvements. Creating Preliminary Data Sheet.
2002 September 2001 July 2001 June 2001 June 2001
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
OPEN PACKAGES HANDLE EXCEPT STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET product development phase specifications subject change without notice. Gennum reserves right remove product time. Listing product does constitute offer sale.
GENNUM CORPORATION Mailing Address: P.O. 489, Stn. Burlington, Ontario, Canada Tel. (905) 632-2996 Fax. (905) 632-5946 Shipping Address: Fraser Drive, Burlington, Ontario, Canada GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. (03) 3349-5501, Fax. (03) 3349-5505 GENNUM LIMITED Long Garden Walk, Farnham, Surrey, England TEL. (0)1252 (0)1252 Gennum Corporation assumes responsibility circuits described herein makes representations that they free from patent infringement. Copyright June 2001 Gennum Corporation. rights reserved. Printed Canada www.gennum.com
Proprietary Confidential
18090
November 2004

GF9320 Data Sheet Features broadcast quality 8-bit 24-tap poly-ph

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