RDA012M4 GS/s MUXDAC Resolution GS/s Sampling Rate Input Mul

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RDA012M4 GS/s MUXDAC Resolution GS/s Sampling Rate Input Mul

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RDA012M4 DATASHEET DS_0012PB1-2805
RDA012M4
GS/s MUXDAC
Resolution GS/s Sampling Rate Input Multiplexer Master-Slave Operation Synchronous Operation Multiple Devices Differential Analog Output Input code format: Offset Binary Output Swing: with Termination 3.3V NMOS-Compatible Data Inputs Differential Sinusoidal Clock Input LVDS Compatible Clock Output 10-bit static linearity Reference Output/Input Accurate Full-Scale Adjustment. 3.3V -5.2V Power Supply Lead package
Figure Functional Block Diagram
Product Description
RDA012M4 digital-to-analog converter (DAC) with input multiplexer maximum update rate 1.3GS/s. integrated utilizes segmented current source reduce glitch energy achieve high linearity performance. best dynamic performance, outputs internally terminated with resistance, outputs nominal full-scale current 12mA when terminated with external resistors. convenient interface with most CMOS ICs, digital data inputs voltage NMOS compatible.
Ordering information
PART NUMBER RDA012M4-DI RDA012M4-HD EVRDA012M4-HD DESCRIPTION 1.3GS/s DAC, 1.3GS/s DAC, Package RDA012M4-HD Evaluation Board
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RDA012M4 DATASHEET DS_0012PB1-2805
Absolute Maximum Ratings
Supply Voltages
Between GNDs -0.3 +0.3 Between VCCs -0.3 +0.3 VCCs +3.8
Input Voltages
CLKIP, CLKIN
Digital Input Voltages
DI<0:11>
Output Termination Voltages
DOUTP, DOUTN
Temperature
Operating Temperature. +100 Case Temperature. Junction Temperature. +120 Lead, Soldering Seconds) +220 Storage.
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RDA012M4 DATASHEET DS_0012PB1-2805
Electrical Specification
PARAMETER ACCURACY Differential Nonlinearity Integral Nonlinearity DYNAMIC PERFORMANCE Spurious Free Dynamic Range SYMBOL CONDITIONS, NOTE TEST LEVEL ±2.5 UNITS 1200 1260 mVp-p mVp-p -2.0 mVpp mVpp
SFDR1 Fclk 800MHz Fout 267MHz SFDR2 Fclk 1000MHz Fout 333MHz SFDR3 Fclk 1300MHz Fout 400MHz Signal Noise Ratio SNDR Clock Feedthrough ANALOG SIGNAL OUTPUT (OUTP, OUTN) Single Ended, Termination Full-scale Output Range VFSS Ground Single Ended, Termination Full-scale Output Range VFSRS Ground (MIN=000h, MAX=FFFh) Differential with Termination Full-scale output swing VFSD Ground each output Output current IOUT Rise Time TR,OUT 20%-80% with output Fall Time TF,OUT 20%-80% with output Settling Time TSETTL CORE CLOCK INPUT (HCLKIP, HCLKIN) Amplitude VCPP,HCLKI Differential Common Mode Voltage VCM,HCLKI Input Resistance RHCLKI Input Capacitance CHCLKI Maximum Frequency FMAX,HCLKI Minimum Frequency FMIN,HCLKI CLOCK OUPUT (LCLKOP, LCLKON) Amplitude VCPP,LCLKO Differential LVDS Common Mode Voltage VCM,LCLKO Maximum Frequency FMAX,LCLKO Minimum Frequency FMIN,LCLKO DIGITAL INPUTS (DIA<0:11>, DIB<0:11>, DIC<0:11>, DID<0:11>) Input High Voltage Input Voltage Input Resistance RDIN Setup Time tST,DTHCK From data input LCLKO Hold Time tHL,DTHCK From LCLKO data input
-650
1140
-0.8 1300
-1.5
0.25 -0.4
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RDA012M4 DATASHEET DS_0012PB1-2805
Electrical Specification
PARAMETER SYMBOL CONDITIONS, NOTE TEST LEVEL -2.0 Internally generated Internally generated externally driven VREFA, VREFD -1.9 -1.9 -5.4 -5.4 Total dissipation Positive supply Negative supply, analog Negative supply, digital -2.0 -2.0 -5.2 -5.2 3300 2300 -2.1 -2.1 -5.0 -5.0 UNITS
TERMINATION (VTT) HCLKI Termination Voltage REFERENCE (VREFA, VREFD) Analog Reference VREFA Digital Reference VREFD Input Resistance RVREF POWER SUPPLY Positive Supply Negative Supply, Analog VEEA Negative Supply, Digital VEED Power Dissipation Power Dissipation PVCC Power Dissipation PVEEA Power Dissipation PVEED OPERATING RANGE Ambient Temperature Junction Temperature
Test Levels
TEST LEVEL
TEST PROCEDURE 100% production tested Sample tested unless other temperature specified Guaranteed design and/or characterization testing
tests continuous, pulsed. Therefore, (junction temperature) (case temperature) (ambient temperature). This normal operating condition more stressful than pulsed test condition. tests conducted with power VCCMIN VCCMAX.
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RDA012M4 DATASHEET DS_0012PB1-2805
Description
P/I/O Bottom Plate NUM. NAME VEEA VEED VREFA VREFD HCLKIP HCLKIN LCLKOP LCLKON DIA<0:11> DIB<0:11> DIC<0:11> DID<0:11> OUTP OUTN FUNCTION +3.3V Digital Power Supply -5.2V Analog Power Supply -5.2V Digital Power Supply Ground Reference Voltage Digital Circuitry Bias Reference. Bypass Ground HCLKI Clock Termination Voltage Mode Selection: Float Clock Input Clock Output DIA<i> Channel Digital Input. DIB<i> Channel Digital Input. DIC<i> Channel Digital Input. DID<i> Channel Digital Input. Differential Output
Layout (TOP view)
Figure RDA012M4-HD pinout (top view).
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RDA012M4 DATASHEET DS_0012PB1-2805
Layout
Figure RDA012M4 layout.
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RDA012M4 DATASHEET DS_0012PB1-2805
Theory Operation
best dynamic static performance, employs 6-bit segmentation. 3.3V NMOS compatible 12-bit digital data inputs latched master-slave flip-flop immediately after input buffer reduce data skew. four-channel data combined together 48:12 latched again. data bits decoded into thermometer code two-stage decoding block, data bits transported through delay equalizer block. digital data synchronized again second master slave flip-flop reduce switching glitch. decoded data drive identical current switches, data drive current switches. output nodes from current switches connected analog output through R-2R ladder generate binary output. output full-scale voltage follows relationship 0.3xVREF. internal reference circuit with approximately -10dB supply rejection integrated chip application convenience. reference provided monitoring bypass purposes. band-limit noise reference voltage, reference should bypassed GNDA node with capacitance 100pF. VREF also used override internal reference with accurate, temperature-compensated external voltage reference. timing diagram shown figure 1.3GHz external clock (HCLKI) divided resulting internal selection signals low-speed clock (LCLKO) provided drive external digital. four-channel data input latched with internal clock that synchronized with LCLKO. Controlled input data 1.3GS/s order shown.
Figure Input Timing Diagram.
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RDA012M4 DATASHEET DS_0012PB1-2805
Signal Description
HIGH SPEED INPUT CLOCK. RDA012M4 high-speed clock input differential driven from typical circuits. Also differential sinusoidal clock used. HCLKIP HCLKIN inputs, internally terminated with which should connected well decoupled -2.0 volt supply. Since MUXDAC's output phase noise directly related input clock noise jitter, low-jitter clock source ideal. internal clock driver generates very little added jitter (~100fs). 500MHz MUXDAC output demands white noise induced clock jitter less than 250fs 10-bit equivalent, 62dB SNDR. DATA INPUT. data inputs 3.3V NMOS-compatible. data interleaved according significant bit. example, consecutive data pins will occur DIA0, DIB0, DIC0, DID0, DIA1, DIB1, etc. OUTPUT CLOCK. Output clock LCLKOP LCLKON supplied DSP/FPGA/ASIC. They LVDS compliant needs terminated with resistor front receiving buffer receiving pins ASIC/DSP. application convenience, data input's setup hold time specified with respect LCLKO. should noted that LCLKOP LCLKON driven MUXDAC waveforms these signals better defined receiver end; that near ASIC/DSP chip that provides input data MUXDAC. system designer should consider delay associated with signal routing system's timing budget. figure setup hold time LCLK data transition defined MUXDAC side. Data transitions data input have occur during "Valid Data Transition Window." timing margin seen from MUXDAC TP-TS where LCLKO period setup time, assuming that ASIC chip takes LCLKO clock input outputs latched falling edge clock. From ASIC/DSP end, however, timing margin decreased amount equal data delay clock delay between chips, noted lower part diagram. ANALOG OUTPUT. outputs OUTP OUTN should both connected though resistor ground. This will give full-scale amplitude volt (both outputs must terminated), volt differentially. output common mode changed terminating load resistors different voltage. However, device optimized perform best when connected voltage between volt. reliable operation, output termination voltage should exceed volts. REFERENCE. VREFA provided added control fullscale amplitude output. internal reference circuit designed provide -2.0 volts, which change supply voltage and/or operating temperature changes. user prefers accurately control output fullscale signal, external voltage reference with output impedance override internal reference should used. output full-scale voltage follows relationship 0.3xVREF. Note that MUXDAC optimized have best performance with reference voltage volts. output resistance reference node ±10%. VREFD allows adjusting digital circuitry bias point varying input voltage swings. most cases, VREFD should bypassed GND.
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RDA012M4 DATASHEET DS_0012PB1-2805
Typical Operating Circuit
Figure RDA012M4 typical operating circuit using internal voltage reference.
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RDA012M4 DATASHEET DS_0012PB1-2805
Typical Performance
Signal (dB) Fclk (MHz)
Figure Output spectrum Fclk=800MHz, Fout=270MHz
Signal (dB) Fclk (MHz)
Figure Output spectrum Fclk=1000MHz, Fout=340MHz
Signal (dB) Fclk (MHz)
Figure Output spectrum Fclk=1300MHz, Fout=340MHz
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RDA012M4 DATASHEET DS_0012PB1-2805
Package Information
package with heat sink slug package's bottom. leads gull-winged formed trimmed 0.053 inch (1.35 lenght.
Figure RDA012M4-HD package, dimensions shown inches (mm).
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RDA012M4 DATASHEET DS_0012PB1-2805
Figure RDA012M4-HD footprint, dimensions shown inches (mm).
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RDA012M4 GS/s MUXDAC Resolution GS/s Sampling Rate Input Mul

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