DESCRIPTION BH616UV8010 Wide operation voltage 1.65V 3.6V Ul
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Ultra Power/High Speed CMOS SRAM 512K
DESCRIPTION
BH616UV8010
Wide operation voltage 1.65V 3.6V Ultra power consumption 3.0V Operation current 5.0mA 70ns 25OC 1.5mA 1MHz 25OC Standby current 2.5uA 25OC 2.0V Data retention current 2.5uA 25OC High speed access time 70ns 1.8V 85OC Automatic power down when chip deselected Easy expansion with CE1, options Configuration x8/x16 selectable pin. Three state outputs compatible Fully static operation, clock, refreash Data retention supply voltage 1.0V
BH616UV8010 high performance, ultra power CMOS Static Random Access Memory organized 524,288 bits operates wide range 1.65V 3.6V supply voltage. Advanced CMOS technology circuit techniques provide both high speed power features with typical operating current 1.5mA 1MHz 3.6V/25OC maximum access time 70ns 1.8V/85OC. Easy memory expansion provided active chip enable (CE1), active HIGH chip enable (CE2) active output enable (OE) three-state output drivers. BH616UV8010 automatic power down feature, reducing power consumption significantly when chip deselected. BH616UV8010 available DICE form, JEDEC standard 48-pin TSOP-I 48-ball package.
PRODUCT FAMILY
PRODUCT FAMILY OPERATING TEMPERATURE RANGE SPEED (ns)
VCC=1.8~3.6V
POWER CONSUMPTION
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
TYPE
VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V
BH616UV8010DI BH616UV8010TI BH616UV8010AI
+0OC +70OC 1.65V 3.6V
13uA
10uA
10mA
DICE TSOP1-48
15uA
12uA
10mA
BGA-48-0608
CONFIGURATIONS
DQ14 DQ15 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
BLOCK DIAGRAM
BH616UV8010TC BH616UV8010TI
Address Input Buffer
Decoder
1024
Memory Array
1024 8192
8192 DQ15 Data Input Buffer Data Output Buffer Column Decoder Address Input Buffer Control Column Write Driver Sense
DQ10 DQ11 DQ12 DQ13
48-ball view
Brilliance Semiconductor, Inc. reserves right modify document contents without notice.
Detailed product characteristic test report available upon request being accepted.
R0201-BH616UV8010
Revision Jul. 2005
DESCRIPTIONS
BH616UV8010
Function
These address inputs select 524,288
Name
A0-A18 Address Input Chip Enable Input Chip Enable Input
active active HIGH. Both chip enables must active when data read from write device. either chip enable active, device deselected standby power mode. pins will high impedance state when device deselected. write enable input active controls read write operations. With chip selected, when HIGH LOW, output data will present pins; when LOW, data present pins will written into selected memory location. output enable input active LOW. output enable active while chip selected write enable inactive, data will present pins they will enabled. pins will high impendence state when inactive. Lower byte upper byte data input/output control pins.
Write Enable Input
Output Enable Input
Data Byte Control Input DQ0-DQ15 Data Input/Output Ports
bi-directional ports used read data from write data into RAM.
Power Supply
Ground
TRUTH TABLE MODE
Chip De-selected (Power Down)
DQ0~DQ7 DQ8~DQ15 CURRENT
High High High High DOUT High DOUT High High High High DOUT DOUT High ICCSB, ICCSB1 ICCSB, ICCSB1 ICCSB, ICCSB1
Output Disabled
Read
Write
NOTES: means VIH; means VIL; means don't care (Must state)
R0201-BH616UV8010
Revision Jul. 2005
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG IOUT
BH616UV8010
OPERATING RANGE
UNITS
PARAMETER
Terminal Voltage with Respect Temperature Under Bias Storage Temperature Power Dissipation Output Current
RATING
-0.5
RANG
Commercial Industrial
AMBIENT TEMPERATURE
-25OC 85OC
1.65V 3.6V 1.65V 3.6V
4.6V
+125 +150
CAPACITANCE
1.0MHz)
MAX. UNITS
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. -2.0V case pulse width less than
SYMBOL PAMAMETER CONDITIONS
Input Capacitance Input/Output VI/O Capacitance This parameter guaranteed 100% tested.
ELECTRICAL CHARACTERISTICS
PARAMETER NAME PARAMETER
Power Supply
VCC=1.8V VCC=3.6V
TEST CONDITIONS
MIN.
1.65 -0.3(2)
TYP.(1)
MAX.
UNITS
Input Voltage
Input High Voltage VCC, VI/O
VCC=1.8V VCC=3.6V
VCC+0.3(3)
Input Leakage Current
Output Leakage Current
Max, 0.2mA Max, 2.0mA
VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V
ICC1 ICCSB ICCSB1
Output Voltage
-VCC-0.2
Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current
Min, -0.1mA Min, -1.0mA VIH, 0mA, FMAX(4) VIH, 0mA, 1MHz VIH, VIL, CE1VCC-0.2V CE20.2V, VINV CC-0.2V VIN0.2V
-4.5
-2.5
Standby Current CMOS
Typical characteristics TA=25OC. Undershoot: -1.0V case pulse width less than Overshoot: VCC+1.0V case pulse width less than FMAX=1/tRC. ICCSB1(MAX.) 10uA/13uA VCC=1.8V/3.6V TA=0OC 70OC. R0201-BH616UV8010 Revision Jul. 2005
DATA RETENTION CHARACTERISTICS
SYMBOL ICCDR
BH616UV8010
PARAMETER
Data Retention Data Retention Current Chip Deselect Data Retention Time Operation Recovery Time
TEST CONDITIONS
CE1VCC-0.2V CE20.2V, VINVCC-0.2V VIN0.2V CE1VCC-0.2V CE20.2V, VINVCC-0.2V VIN0.2V
VCC=1.0V VCC=2.0V
MIN.
TYP.
-0.5
MAX.
-3.0
UNITS
tCDR
Retention Waveform
TA=25OC. Read Cycle Time. ICCDR(MAX.) 2.5uA /10uA VCC=1.0V/2.0V TA=0OC 70OC.
DATA RETENTION WAVEFORM (CE1 Controlled)
Data Retention Mode
VDR1.0V
tCDR
CE1VCC 0.2V
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode VDR1.0V
tCDR
CE20.2V
TEST CONDITIONS
(Test Load Input/Output Reference) Input Pulse Levels Input Rise Fall Times Input Output Timing Reference Level tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1, tCHZ2, tBDO, tOHZ, tWHZ, Output Load Others 1V/ns 0.5Vcc 5pF+1TTL 30pF+1TTL
SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST STEADY CHANGE FROM CHANGE FROM INPUT PULSES OUTPUTS MUST STEADY WILL CHANGE FROM WILL CHANGE FROM CHANGE STATE UNKNOW CENTER LINE HIGH INPEDANCE "OFF" STATE
Output CL(1)
DON'T CARE CHANGE PERMITTED DOES APPLY
Rise Time: 1V/ns
Fall Time: 1V/ns
Including scope capacitance.
R0201-BH616UV8010
Revision Jul. 2005
ELECTRICAL CHARACTERISTICS READ CYCLE
JEDEC PARAMETER NAME PARANETER NAME
BH616UV8010
CYCLE TIME 70ns DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable Output Valid Chip Select Output Chip Select Output Data Byte Control Output Output Enable Output Chip Select Output High Chip Select Output High Data Byte Control Output High Output Enable Output High Data Hold from Address Change (CE1) (CE2) (LB, (CE1) (CE2) (LB, (CE1) (CE2) (LB, MIN. TYP. -MAX. -UNITS
tAVAX tAVQX tE1LQV tE2LQV tBLQV tGLQV tE1LQX tE2LQX tBLQX tGLQX tE1HQZ tE2HQZ tBHQZ tGHQZ tAVQX
tACS1 tACS2 tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tBDO tOHZ
SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE
(1,2,4)
ADDRESS DOUT
R0201-BH616UV8010
Revision Jul. 2005
READ CYCLE
(1,3,4)
BH616UV8010
tACS1 tCLZ DOUT
tACS2
(5,6)
tCHZ
READ CYCLE
ADDRESS tCLZ1 tCLZ2
tOLZ tACS1 tOHZ tCHZ
(1,5)
tACS2
tCHZ2 tBDO
(2,5)
DOUT
NOTES: high read Cycle. Device continuously selected when CE2= VIH. Address valid prior coincident with transition and/or transition high. VIL. Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested.
R0201-BH616UV8010
Revision Jul. 2005
ELECTRICAL CHARACTERISTICS WRITE CYCLE
JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION Write Cycle Time Address Time Address Valid Write Chip Select Write Data Byte Control Write Write Pulse Width Write Recovery Time Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Disable Output High Write Output Active (CE1, (CE2) (LB,
BH616UV8010
CYCLE TIME 70ns MIN. TYP. -MAX. UNITS
tAVAX tAVWL tAVWH tELWH tBLWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWR1 tWR2 tWHZ tOHZ
SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE ADDRESS
(11)
tWR1
tOHZ DOUT
(4,10)
(11)
tWR2
R0201-BH616UV8010
Revision Jul. 2005
WRITE CYCLE ADDRESS
(11) (1,6)
BH616UV8010
(12)
(11)
tWHZ DOUT
(4,10)
(8,9)
NOTES: must high during address transitions. internal write time memory defined overlap active low. signals must active initiate write signal terminate write going inactive. data input setup hold timing should referenced second transition edge signal that terminates write. measured from earlier going high going write cycle. During this period, pins output state that input signals opposite phase outputs must applied. transition high transition occurs simultaneously with transitions after transition, output remain high impedance state. continuously VIL). DOUT same phase write data this write cycle. DOUT read data next address. high during this period, pins output state. Then data input signals opposite phase outputs must applied them. Transition measured 500mV from steady state with 5pF. parameter guaranteed 100% tested. measured from later going going high write.
R0201-BH616UV8010
Revision Jul. 2005
ORDERING INFORMATION
BH616UV8010
SPEED 70ns
BH616UV8010
MATERIAL Normal Green
GRADE -25oC +85oC PACKAGE TSOP 1-48 BGA-48-0608 D:DICE
Note: Brilliance Semiconductor Inc. (BSI) assumes responsibility application product circuit described herein. does authorize products critical components application which failure product expected result significant injury death, including life-support systems critical medical instruments.
PACKAGE DIMENSIONS
NOTES: CONTROLLING DIMENSIONS MILLIMETERS. PIN#1 MARKING LASER PRINT. SYMBOL NUMBER SOLDER BALLS.
Max.
BALL PITCH 0.75 5.25 3.75
VIEW
mini-BGA
R0201-BH616UV8010
Revision Jul. 2005
PACKAGE DIMENSIONS
BH616UV8010
TSOP1-48 (12mm 20mm)
R0201-BH616UV8010
Revision Jul. 2005
Revision History Revision History Initial Production Version
BH616UV8010
Draft Date July 15,2005 Remark Initial
R0201-BH616UV8010
Revision Jul. 2005
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