Specifically Designed Battery Powered Applications Volts will Operate
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Specifically Designed Battery Powered Applications Volts will Operate from Volts Static Current Drain Volts Maximum Toggle Frequency Flip Flop Volts Drawn Gate Length CMOS Gate Arrays Package Styles Offered Including TQFP Improved Product Testability Using Serial Scan, Boundary Scan, JTAG Second Source Existing ASIC Design Atmel's ATLV Design Translation. Improved Performance Lower Cost
Description
ATLV Series CMOS gate arrays employ µ-drawn, double-level metal, Si-gate, CMOS technology processed Atmel's U.S.-based, advanced manufacturing facility. arrays utilize enhanced channelless architecture which results greater than percent usable gates. Atmel's flexible design system uses industry design standards compatible with popular CAD/CAE software hardware packages. customer start designing with ATLV series today using existing CAD/CAE tools.
ATLV Series Ultra Voltage Gate Arrays ATLV2 ATLV3 ATLV5 ATLV7 ATLV10 ATLV15 ATLV20 ATLV35
ATLV Array Organization
Device Number ATLV2 ATLV3 ATLV5 ATLV7 ATLV10 ATLV15 ATLV20 ATLV35 Gates 2,000 3,000 5,000 7,000 10,000 15,000 22,000 35,000 Routable Gates 1,400 1,600 2,800 4,400 6,600 8,000 12,000 18,000 Count I/O(1) Pins Gate(2) Speed
Notes: Absolute maximum pins maximum count minus Additional power ground pins assumed required support simultaneous switching outputs count increases. Nominal input nand gate with volts, room temperature.
0261B
ATLV Design
Design Systems Supported
Atmel supports major CAE/CAD software systems with complete macro cell libraries (symbols, timing function), well utilities checking netlist accurate pre-route delay simulations. Atmel uses Cadence's Verilog-XL golden simulator. Design systems which supported include Cadence, Viewlogic, Mentor, Synopsys.
Design Options
Schematic Capture
Schematic capture simulation performed customer using Atmel supplied macro cell library. customer also receive complete back annotation delay data post-route simulation.
VHDL/Verilog-HDL
Atmel accept Register Transfer level (RTL) designs VHDL (MIL-STD-454, IEEE 1076) Verilog-HDL format. Atmel fully supports Synopsys VHDL simulation well synthesis. Design VHDL VerilogHDL preferred method performing gate array design.
Design Flow
While Atmel provides four options implementing gate array design, they have same basic flow. Data base acceptance first milestone. This when Atmel receives accepts complete design data base. Preliminary design review where performance design based Cadence simulation. Final design review last review design before making masks. back annotation data incorporated into simulations. After final design review masks released prototypes ceramic packages delivered.
ASIC Design Translation
Atmel successfully translated dozens existing designs from most major ASIC vendors (LSI Logic, Oki, NEC, Fujitsu others) into gate arrays. These designs have been optimized speed, gate count, modified logic memory, replicated pin-for-pin compatible, drop-in replacement.
ATLV Gate Array Design Flow
Customer
Atmel Cell Library Gate Array Design Translation Design Synthesis FPGA/EPLD Conversions -VHDL -Verilog-HDL
Atmel
Data Base Acceptance
Atmel
Simulation Verification
Atmel
Customer
Preliminary Design Review
Atmel
Physical Design, Simulation Verification
Atmel
Customer
Final Design Review
Atmel
Customer
Prototype Delivery
Atmel
FPGA EPLD Conversions
Atmel successfully translated existing FPGA/EPLD designs from most major vendors (Xilinx, Actel, Altera, Atmel) into gate arrays. design optimized speed power consumption, modified logic memory replicated pin-for-pin compatible, drop-in replacement. Atmel frequently combines several devices onto single gate array. transistor level verified through measurements made fabricated test arrays. symbols ATLV cell library compatible with Atmel's (1.0 ATL80 (0.8 cell libraries. Existing designs easily migrated ATLV series. Characterization been performed over commercial temperature volts, ensure that simulation accurately predicts performance finished product. Atmel continually expanding ATLV series cell library with both soft hard macros. Check with your sales representative most recent additions.
ATLV Series Cell Library
Atmel's ATLV series gate arrays cells from accurately modeled highly flexible library. cell library contains over hard-wired data path elements been characterized extensive SPICE modeling
Cell Guide
Buffers Inverters Buffer Buffer Buffer with Enable Buffer with Enable Buffer Buffer Buffer Buffer Buffer Delay Buffer Delay Buffer Delay Buffer AND, NAND, Gates input input input input input NAND Dual 2-input NAND input NAND input NAND input NAND input NAND input NAND Multiplexers Inverting Buffered Inputs Inverting Buffered Inputs with Enable Quad with Enable Quad Inverting Buffered Inputs Inverting Buffered Inputs Buffered Inputs Buffered Inputs with Enable input Dual input input input input input input input input Inverter Dual Inverter Quad Inverter Quad Tri-state Inverter Inverter Dual Inverter Tri-state Inverter Inverter Inverter Inverter Inverter
Cell Guide
AND/OR, OR/AND Gates input INVERT input INVERT input INVERT Exclusive OR/NOR Gates Adder Adder with Buffered Outputs input Carry Lookahead Decoders Decoder Decoder with Enable Flip-flops/Latches Flip-flop Flip-flop with Clear/Preset Flip-flop with Clear Flip-flop with Reset Flip-flop with Flip-flop with Set/Reset Flip-flop Flip-flop with Clear/Preset Flip-flop with Clear Scan Cells Set-scan Register Set-scan Register with Clear Preset Set-scan Register with Reset Options Input, Output, Bidirectional, Tristate Output, Internal Clock Driver Oscillator Output Drive Value Programmable from increments with Slew Rate Control CMOS Operation Testable NAND Gate Input (Bidirectional, Input) Inverting Non-inverting Input Buffers (Bidirectional, Input) Pullup Resistor 310K Pulldown Resistor 3.5K 108.5K Set-scan Register with Set-scan Register with Reset LATCH LATCH with Complementary Outputs LATCH with Inverted Gate Signal QUAD LATBG with Common Gate Signal QUAD Inverting LATCH LATCH with Reset LATCH with LATCH with Reset Decoder with Enable input Exclusive input Exclusive input INVERT input INVERT input INVERT
CMOS Input Interface Characteristics
Interface CMOS Logic High 0.90 Logic Switchpoint Typical
Absolute Maximum Ratings*
Operating Temperature .-40°C +85°C Storage Temperature .-65°C +150°C Voltage with Respect Ground .-2.0 +5.5 Maximum Operating Voltage .5.5
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Notes: Minimum voltage -0.6 which undershoot -2.0 pulses less than Maximum output voltage 0.75V which overshoot +7.0 pulses less than
Volt Characteristics
Applicable over recommended operating range from -40°C +85°C, (unless otherwise noted) Symbol Parameter Input Leakage High Input Leakage pull-up) Output Leakage pull-up) Output Short Circuit Current Buffer)(2) CMOS Input Voltage CMOS Input High Voltage CMOS Switching Threshold Output Voltage Output buffer stages drive capability with stage. Output High Voltage Output buffer stages drive capability with -0.5 stage. Static Current Input Leakage pull-up) VDD=1.5 25°C IOL=as rated VDD=1.5 0.75 Test Condition VIN=VDD, VDD=1.8 VIN=VSS, VDD=1.8 10-5 10-5 Units
VIN=VDD VSS, VDD=3.6 VDD=1.8 VOUT=VDD VDD=1.8 VOUT=VSS
10-5
IOH=as rated VDD=1.5
Note:
This specification Output Buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
Characteristics
Delay
Delay Fanout
Prop Delay (ns)
Prop Delay (ns)
Volts
NAND2 input NAND Temp 25°C
Fanout
Volts
NAND2 input NAND Temp 25°C
Delay Temperature
Current Drain Voltage
Prop Delay (ps)
(nA)
Temperature (°C)
Volts
(Volts)
Temp 25°C
NAND2 input NAND
Buffer Characteristics
Symbol COUT CI/O Parameter Capacitance Input Buffer (Die) Capacitance Output Buffer (Die) Capacitance Bi-Directional Test Condition Units
Buffers
Programmable output drive -4.5 3000 volts protection
ATLV series input/output ring contains buffer circuitry capable sourcing sinking currents responds CMOS logic levels. locations this ring accommodate bidirectional cells.
following design rules, Test Compiler automatically insert scan cells generate test vectors providing greater than fault coverage. This easiest least expensive method designing testability into gate array design.
Advanced Packaging
Atmel supports wide variety standard packages ATLV series, also offers ATLV series gate arrays packages that custom designed maintain performance obtained silicon. Atmel's standard packages have been characterized thermal electrical performance. When standard package can't meet customer's needs, Atmel's package design center develop package precisely application. company delivered custom-designed packages wide variety configurations, including Tape Automated Bonding (TAB) packages. Atmel's domestic packaging facility manufactures commercial, industrial Class
Design Testability
Atmel supports full range Design-for-Test improvement techniques which reduce design prototype debug time, production test time, board system test time. These techniques also improve system level test diagnostic capability. ATLV arrays support Joint Test Action Group (JTAG) boundary scan architecture. required soft hard macros implement IEEE 1149.1 compliant architecture available macro cell library. JTAG allows scan testing with only additional pins required. Atmel also provide automatic high fault coverage test pattern generation (ATPG) Synopsys Test Compiler.
Packaging Options
Package Type PQFP TQFP PLCC CPGA CQFP Count 100, 120, 128, 132, 144, 160, 184, 208, 240, 100, 120, 128, 144, 160, 176, 100, 124, 144, 155, 180, 223, 224, 299, 100, 120, 132, 144, 160, 224, 121, 169,
Cadence, Mentor, Synopsys, Verilog-XL, Viewlogic, Xilinx registered trademarks others.
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