Random Access Time Page Mode Read Time Synchronous Burst Frequency Con

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Random Access Time Page Mode Read Time Synchronous Burst Frequency Con

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1.65V 1.95V Read/Write High Performance
Random Access Time Page Mode Read Time Synchronous Burst Frequency Configurable Burst Operation Sector Erase Architecture Sixteen Word Sectors with Individual Write Lockout Hundred Fifty-four Word Main Sectors with Individual Write Lockout Typical Sector Erase Time: Word Sectors Word Sectors Thirty-two Plane Organization, Permitting Concurrent Read Thirty-one Planes Being Programmed/Erased Suspend/Resume Feature Erase Program Supports Reading Programming Data from Sector Suspending Erase Different Sector Supports Reading Word Suspending Programming Other Word Low-power Operation Active Standby Write Protection Accelerated Program/Erase Operations RESET Input Device Initialization CBGA TSOP Packages Seventeen 128-bit Protection Registers (2,176 Bits) Common Flash Interface (CFI)
128-megabit Burst/Page Mode 1.8-volt Flash Memory AT49SN12804 AT49SV12804
Description
AT49SN/SV12804 1.8-volt 128-megabit Flash memory. memory divided into multiple sectors planes erase operations. AT49SN/SV12804 organized 8,388,608 bits. device read reprogrammed single 1.8V power supply, making ideally suited In-System programming. device configured operate asynchronous/page read (default mode) burst read mode (not available AT49SV12804). burst read mode used achieve faster data rate than possible asynchronous/page read mode. signals both tied burst configuration register configured perform asynchronous reads, device will behave like standard asynchronous Flash memory. page mode, signal tied pulsed latch page address. both cases tied GND. AT49SN/SV12804 divided into thirty-two memory planes. read operation occur thirty-one planes which being programmed erased. This concurrent operation allows improved system performance requiring system wait program erase operation complete before read performed. further increase flexibility device, contains Erase Suspend Program Suspend feature. This feature will erase program hold amount time user read data from program data remaining sectors. There reason suspend erase program operation data read another memory plane. provides data protection faster programming erase times. When input below 0.4V, program erase functions inhibited. When 0.9V above, normal program erase operations performed. With 12.0V, program (Dual-word Program command) erase operations accelerated.
Preliminary
Rev. 3314A-FLASH-4/04
AT49SN/SV12804: Configurations
Name I/O0 I/O15
Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Address Latch Enable Clock Reset Write Protect Write Protection Power Supply Accelerated Program Operations WAIT Output Power Supply
CLK(1) RESET
WAIT(1) VCCQ Note:
These signals available with AT49SV12804. AT49SV12804 only used asynchronous/page mode.
AT49SN12804: CBGA View
AT49SV12804: TSOP View Type
I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCCQ I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0
RESET
WAIT I/O12 VCCQ I/O15 I/O6 I/O4 I/O2 I/O1
I/O14 I/013 I/O11 I/O10 I/O9 I/O0 I/O7 I/O5 I/O3 VCCQ I/O8
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Device Operation
COMMAND SEQUENCES: When device first powered will read mode. Command sequences used place device other operating modes such program erase. command sequences written applying pulse input with high applying low-going pulse input with high. Prior low-going pulse signal, address input latched low-to-high transition signal. pulsed low, address will latched first rising edge Valid data latched rising edge pulse, whichever occurs first. addresses used command sequences affected entering command sequences. BURST CONFIGURATION COMMAND: Program Burst Configuration Register command used program burst configuration register. burst configuration register determines several parameters that control read operation device. determines whether synchronous burst reads enabled asynchronous reads enabled. Since page read operation asynchronous operation, must asynchronous reads enable page read feature. determines whether four-word page eight-word page will used. rest bits burst configuration register used only burst read mode. Bits burst configuration register determine clock latency burst mode. latency two, three, four, five cycles. clock latency versus input clock frequency table shown page "Burst Read Waveform" shown page illustrates clock latency four; data output from device four clock cycles after first valid clock edge following high-to-low edge. configuration register determines polarity WAIT signal. burst configuration register determines number clocks that data will held valid (see Figure Hold Data Clock Cycles Read Waveform shown page clock latency affected value bit. burst configuration register determines when WAIT signal will asserted. When synchronous burst reads enabled, linear burst sequence selected setting selects whether burst starts data output will relative falling edge rising edge clock. Bits burst configuration register determine whether continuous fixed-length burst will used also determine whether four-, eight- sixteen-word length will used fixed-length mode. When four-, eight- sixteen-word burst length selected, used select whether burst accesses wrap within burst length boundary whether they cross word length boundaries perform linear accesses (see Table other bits burst configuration register should programmed shown page default state (after power-up reset) burst configuration register also shown page ASYNCHRONOUS READ: There types asynchronous reads pulsed standard asynchronous reads. pulsed read operation device controlled inputs. outputs high-impedance state whenever high. This dual-line control gives designers flexibility preventing contention. data address location defined captured signal will read when low. address location passes into device when low; address latched low-to-high transition AVD. input levels pins allow data driven device. access time measured from stable address, falling edge falling edge whichever occurs last. During pulsed read, signal static high static low. standard asynchronous reads, signal should tied GND. asynchronous read diagrams shown page PAGE READ: page read operation device controlled inputs. input ignored during page read operation should tied GND. page size four words (default value) eight words depending what value burst configuration register programmed During page read, signal transition then transition high, transition remain low, tied GND. high transition signal occurs, shown Page Read Cycle Waveform
3314A-FLASH-4/04
page address latched low-to-high transition signal. However, signal remains after high-to-low transition signal tied GND, shown Page Read Cycle Waveform then page address (determined eight word page four-word page) cannot change during page read operation. first word access page read same asynchronous read. first word read asynchronous speed Once first word read, toggling (fourword page mode) toggling (eight word page mode) will result subsequent reads within page being output speed pins both tied GND, device will behave like standard asynchronous Flash memory. page read diagrams shown page SYNCHRONOUS READS: Synchronous reads (not available AT49SV12804) used achieve faster data rate that possible asynchronous/page read mode. device configured continuous fixed-length burst access. burst read operation device controlled inputs. initial read location determined pulsed asynchronous read operation; memory location device. burst access, address latched rising edge first clock pulse when rising edge signal, whichever occurs first. input signal controls flow data from device burst operation. After clock latency cycles, data next burst address location read each following clock cycle. Figure Word Boundary
Word Word Word Word
16-word Boundary
CONTINUOUS BURST READ: During continuous burst read, number addresses read from memory. When operating linear burst read mode with burst wrap set, device incur output delay when burst sequence crosses first 16-word boundary memory (see Figure starting address D12, there delay. starting address D15, output delay equal initial clock latency incurred. delay takes place only once, only burst sequence crosses 16-word boundary. indicate that device ready continue burst, device will drive WAIT (B10 during clock cycles which data being presented. Once WAIT driven high (B10 current data will valid. WAIT signal will tri-stated when signal high. "Burst Read Waveform" shown page valid address latched point specified clock latency three, data valid within clock edge low-to-high transition clock point results being read. transition clock point results burst read D15. clock transition point does cause data appear output lines because WAIT signal goes (B10 after clock transition, which signifies that first boundary memory been crossed that data available. After clock latency three, clock transition point does cause burst read data because WAIT signal goes high (B10 after clock transition indicating that data available. Additional clock transitions, like point will continue result burst reads.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
FIXED-LENGTH BURST READS: During fixed-length burst mode read, four, eight sixteen words data burst from device, depending upon configuration. device supports linear burst mode. burst sequence shown page When operating linear burst read mode with burst wrap set, device incur output delay when burst sequence crosses first 16-word boundary memory. starting D12, there delay. starting address D15, output delay equal initial clock latency incurred. delay takes place only once, only burst sequence crosses 16-word boundary. indicate that device ready continue burst, device will drive WAIT (B10 during clock cycles which data being presented. Once WAIT driven high (B10 current data will valid. WAIT signal will tri-stated when signal high. "Four-word Burst Read Waveform" page illustrates fixed-length burst cycle. valid address latched point specified clock latency four, data valid within clock edge low-to-high transition clock point results being read. Similarly, output following next clock cycles. Returning high ends read cycle. There output delay burst access wrap mode BURST SUSPEND: Burst Suspend feature allows system temporarily suspend synchronous burst operation system needs Flash address data other purposes. Burst accesses suspended during initial latency (before data received) after device output data. When burst access suspended, internal array sensing continues previously latched internal data retained. Burst Suspend occurs when asserted, current address been latched (either rising edge valid edge), halted, deasserted. halted when VIL. resume burst access, reasserted restarted. Subsequent edges resume burst sequence where left off. Within device, gates WAIT signal. Therefore, during Burst Suspend WAIT signal reverts high-impedance state when deasserted. "Burst Suspend Waveform" page RESET: RESET input provided ease some system applications. When RESET logic high level, device standard operating mode. level RESET halts present device operation puts outputs device high-impedance state. When high level reasserted RESET pin, device returns read mode. ERASE: Before word reprogrammed must erased. erased state memory bits logical "1". entire memory erased using Chip Erase command individual planes erased using Plane Erase command individual sectors erased using Sector Erase command.
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CHIP ERASE: Chip Erase two-bus cycle operation. automatic erase begins rising edge last pulse. Chip Erase does alter data protected sectors. hardware reset during chip erase will stop erase, data will unknown state. PLANE ERASE: alternative full Chip Erase, device organized into thirty-two planes that individually erased. Plane Erase command two-bus cycle operation. plane whose address valid second rising edge will erased. Plane Erase command does alter data protected sectors. SECTOR ERASE: device organized into multiple sectors that individually erased. Sector Erase command two-bus cycle operation. sector whose address valid second rising edge will erased provided given sector been protected. WORD PROGRAMMING: device programmed word-by-word basis. Programming accomplished internal device command register two-bus cycle operation. programming address data latched second cycle. device will automatically generate required internal programming pulses. Please note that cannot programmed back "1"; only erase operations convert "0"s "1"s. FLEXIBLE SECTOR PROTECTION: AT49SN/SV12804 offers sector protection modes, Softlock Hardlock. Softlock mode optimized sector protection sectors whose content changes frequently. Hardlock protection mode recommended sectors whose content changes infrequently. Once either these modes enabled, contents selected sector read-only cannot erased programmed. Each sector independently programmed either Softlock Hardlock sector protection mode. power-up reset, sectors have their Softlock protection mode enabled. SOFTLOCK UNLOCK: Softlock protection mode disabled issuing twobus cycle Unlock command selected sector. Once sector unlocked, contents erased programmed. enable Softlock protection mode, two-bus cycle Softlock command must issued selected sector. HARDLOCK WRITE PROTECT (WP): Hardlock sector protection mode operates conjunction with Write Protection (WP) pin. Hardlock sector protection mode enabled issuing two-bus cycle Hardlock software command selected sector. state Write Protect affects whether Hardlock protection mode overridden. When Hardlock protection mode enabled, sector cannot unlocked contents sector read-only. When high, Hardlock protection mode overridden sector unlocked Unlock command.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
disable Hardlock sector protection mode, chip must either reset power cycled. Table Hardlock Softlock Protection Configurations Conjunction with
Hardlock Softlock Erase/ Prog Allowed?
Comments sector locked Sector Softlocked. Unlock command unlock sector. Hardlock protection mode enabled. sector cannot unlocked. sector locked. Sector Softlocked. Unlock command unlock sector. Hardlock protection mode overridden sector locked. Hardlock protection mode overridden sector unlocked Unlock command. Erase Program Operations cannot performed.
Figure Sector Locking State Diagram
UNLOCKED LOCKED
[000]
[001]
[011]
Power-Up/Reset Default
Hardlocked
[110]
[111]
Hardlocked disabled
Power-Up/Reset Default
[100]
[101]
Unlock Command Softlock Command Hardlock Command
Note:
notation denotes locking state sector. current locking state sector defined state bits sector-lock status D[1:0].
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SECTOR PROTECTION DETECTION: software method available determine sector protection Softlock Hardlock features enabled. When device software product identification mode read from I/O0 I/O1 address location 00002H within sector will show sector unlocked, softlocked, hardlocked. Table Sector Protection Status
I/O1 I/O0 Sector Protection Status Sector Locked Softlock Enabled Hardlock Enabled Both Hardlock Softlock Enabled
READ STATUS REGISTER: status register indicates status device operations success/failure that operation. Read Status Register command causes subsequent reads output data from status register until another command issued. return reading from memory, issue Read command. status register bits output I/O7 I/O0. upper byte, I/O15 I/O8, outputs when Read Status Register command issued. contents status register [SR7:SR0] latched falling edge (whichever occurs last), which prevents possible errors that might occur status register contents change while being read. must toggled with each subsequent status read, status register will indicate completion Program Erase operation. When Write State Machine (WSM) active, will indicate status WSM; remaining bits status register indicate whether successful performing preferred operation (see Table
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
READ STATUS REGISTER BURST MODE: waveform below shows status register read during program operation. two-bus cycle command program operation given followed read status register command. Following read status register command, signal pulsed latch valid address point With signal pulsed specified clock latency three, status register output valid within from clock edge same status register data output successive clock edges. update status register output, signal needs pulsed next data available after clock latency three. status register output also available after chosen clock latency during erase operation. Figure Read Status Register Burst Mode
ADDRESS
I/O0 I/O15
40H/10H
DATA
WAIT
Note:
WAIT signal burst configuration setting
3314A-FLASH-4/04
Table Status Register Definition
WSMS VPPS Notes WRITE STATE MACHINE STATUS (WSMS) Ready Busy ERASE SUSPEND STATUS (ESS) Erase Suspended Erase Progress/Completed ERASE STATUS (ES) Error Sector Erase Successful Sector Erase PROGRAM STATUS (PRS) Error Programming Successful Programming STATUS (VPPS) Detect, Operation Abort Check Write State Machine first determine Word Program Sector Erase completion, before checking program erase status bits. When Erase Suspend issued, halts execution sets both WSMS bits remains until Erase Resume command issued. When this "1", applied number erase pulses sector still unable verify successful sector erasure. When this "1", attempted failed program word
status does provide continuous indication level. interrogates level only after Program Erase command sequences have been entered informs system been switched also checked before operation verified WSM. When Program Suspend issued, halts execution sets both WSMS bits "1". remains until Program Resume command issued. Program Erase operation attempted locked sectors, this WSM. operation specified aborted device returned read status mode. Indicates program erase status addressed plane.
PROGRAM SUSPEND STATUS (PSS) Program Suspended Program Progress/Completed SECTOR LOCK STATUS Prog/Erase attempted locked sector; Operation aborted. operation locked sectors Plane Status (PLS) Note:
Command Sequence Error indicated when SR1, SR3, set.
Table Status Register Device WSMS Write Status Definition
WSMS (SR7) (SR0) Description addressed plane performing program/erase operation. plane other than currently addressed performing program/erase operation. program/erase operation progress plane. Erase Program suspend bits (SR6, SR2) indicate whether other planes suspended.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
ERASE SUSPEND/ERASE RESUME: Erase Suspend command allows system interrupt sector erase plane erase operation. erase suspend command does work with Chip Erase feature. Using erase suspend command suspend sector erase operation, system program read data from different sector within same plane. Since this device organized into thirty-two planes, there need erase suspend feature while erasing sector when want read data from sector another plane. After Erase Suspend command given, device requires maximum time suspend erase operation. After erase operation been suspended, plane that contains suspended sector enters erase-suspend-read mode. system then read data program data other sector within device. address required during Erase Suspend command. During sector erase suspend, another sector cannot erased. resume sector erase operation, system must write Erase Resume command. Erase Resume command one-bus cycle command, which does require plane address. Read, Read Status Register, Product Entry, Clear Status Register, Program, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector Unlock valid commands during erase suspend. PROGRAM SUSPEND/PROGRAM RESUME: Program Suspend command allows system interrupt programming operation then read data from different word within memory. After Program Suspend command given, device requires maximum suspend programming operation. After programming operation been suspended, system then read from other word within device. address required during program suspend operation. resume programming operation, system must write Program Resume command. program suspend resume one-bus cycle commands. command sequence erase suspend program suspend same, command sequence erase resume program resume same. Read, Read Status Register, Product Entry, Program Resume valid commands during Program Suspend. 128-BIT PROTECTION REGISTERS: AT49SN/SV12804 contains seventeen (PR0 PR16) 128-bit registers that used security purposes system design. Please Protection Register Addressing Table page address locations within each protection register. first protection register (PR0) divided into 64-bit blocks. blocks designated block block data block non-changeable programmed factory with unique number. data block programmed user locked such that data block cannot reprogrammed. other registers (PR1 PR16) have bits words) each that user programmable. program block program PR16 register, two-bus cycle command must used shown Command Definition table page lock block lock PR16, two-bus cycle command must also used shown Command Definition table. lock block PRO, address used second cycle 080h data must zero during second cycle. other data bits during second cycle don't cares. lock PR16, address used second cycle 089h sixteen bits data programmed. these bits programmed zero, appropriate register locked. After being locked, protection register cannot unlocked. determine whether block PR16 locked out, Product Entry command given followed read operation from address address 89H, respectively. (This command shown status protection Command Definition table). block PRO, data zero, block locked. data one, block reprogrammed. PR16, sixteen bits data read out. Each represents protection status particular register. zero, register locked. one, register reprogrammed. read protection register, Product Entry command given followed normal read operation from address within protection register. After determining whether register protected reading protection register, Read command must given return read mode.
3314A-FLASH-4/04
CFI: Common Flash Interface (CFI) published, standardized data structure that read from flash device. allows system software query installed device determine configurations, various electrical timing parameters, functions supported device. used allow system learn interface flash device most optimally. primary benefits using ease upgrading second source availability. command enter Query mode one-bus cycle command which requires writing data address. Query command written when device ready read data also written when part product mode. Once Query mode, system read data addresses given Table page return read mode, read command should issued. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs AT49SN/SV12804 following ways: sense: below 1.2V (typical), device reset program erase functions inhibited. power-on delay: once reached sense level, device will automatically time-out (typical) before programming. Program inhibit: holding low, high high inhibits program cycles. Noise filter: pulses less than (typical) inputs will initiate program cycle. less than VILPP. INPUT LEVELS: While operating with 1.65V 1.95V power supply, address inputs control inputs (OE, driven from 2.5V without adversely affecting operation device. lines driven from VCCQ 0.6V. OUTPUT LEVELS: AT49SN/SV12804, output high levels equal VCCQ 0.1V (not VCC). VCCQ must regulated between 1.8V 2.25V.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Word Program Flowchart
Start
Word Program Procedure
Operation Write Command Program Setup Data None None Comments Data Addr Location program Data Data program Addr Location program Status register data: Toggle update status register Check Ready Busy
Write Word Address
(Setup)
Write
(Confirm)
Write Data, Word Address Read Status Register
Read
Program Suspend Loop
Idle
Suspend?
Full Status Check Desired)
Repeat subsequent Word Program operations. Full status register check done after each program, after sequence program operations. Write after last operation Read state.
Program Complete
Full Status Check Flowchart
Read Status Register
Full Status Check Procedure
Operation Idle Command None None None Comments Check SR3: Error Check SR4: Data Program Error Check SR1: Sector locked; operation aborted
Range Error
Idle Idle
Program Error
Device Protect Error
MUST cleared before Write State Machine allows further program attempts. error detected, clear status register before continuing operations only Clear Status Register command clears status register error bits.
Program Successful
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Program Suspend/Resume Flowchart
Start
Program Suspend/Resume Procedure
Operation Write Command Program Suspend Read Status None Comments Data Addr Sector address Suspend (SA) Data Addr address within Same Plane Status register data: Toggle update status register Addr address Check Ready Busy Check Program suspended Program completed Data Addr address within Suspended Plane Read data from sector memory other than being programmed Data Addr address
Write Address
(Program Suspend)
Write Address (Read Status) within Same Plane Read Status Register
Write Read
Idle
None
Idle
None
Program Completed
Write Suspend Plane
Write
(Read Array)
Read Array
Read Data
Write
(Read Array)
Read Write
None Program Resume
Done Reading
Read Data
Write Address
Suspend Plane placed Read mode:
(Program Resume)
Write
Read Status
Program Resumed
Return Plane Status mode: Data Addr address within Same Plane
Write Address within Same Plane
(Read Status)
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Erase Suspend/Resume Flowchart
Start
Erase Suspend/Resume Procedure
Operation Write Command Erase Suspend Read Status None Comments Data Addr address within Same Plane Data Addr address Status register data: Toggle update status register Addr address within Same Plane Check Ready Busy Check Erase suspended Erase completed Data Addr address Read program data from/to sector other than being erased Data Addr address
Write Address
(Erase Suspend)
Write Address Read Status Register
Write
(Read Status)
Read
Idle
None
Erase Completed
Idle
None
Read Program? Read
Program Loop
Write Read Write Write
Read Program None Program Resume
Done?
(Erase Resume)
Write Address Erase Resumed
Write
(Read Array)
Suspended Plane placed Read mode Program loop:
Read Array Data
Write
Read Status
Write Address within Same Plane
Return Plane Status mode: Data Addr address within Same Plane
(Read Status)
3314A-FLASH-4/04
Sector Erase Flowchart
Start
Sector Erase Procedure
Operation Write Command Sector Erase Setup Erase Confirm None None Comments Data Addr Sector erased (SA) Data Addr Sector erased (SA) Status register data: Toggle update status register data Check WSMS Ready WSMS Busy
Write Sector Address
(Sector Erase)
Write (Erase Confirm) Sector Address Read Status Register
Write
Suspend Erase Loop
Read Idle
Suspend Erase
Full Erase Status Check Desired)
Sector Erase Complete
Repeat subsequent sector erasures. Full status register check done after each sector erase, after sequence sector erasures. Write after last operation enter read mode.
Full Erase Status Check Flowchart
Read Status Register
Full Erase Status Check Procedure
Operation Command None None None None Comments Check SR3: Range Error Check SR4, SR5: Both Command Sequence Error Check SR5: Sector Erase Error Check SR1: Attempted erase locked sector; erase aborted.
SR4,
Range Error Command Sequence Error
Idle Idle Idle
Sector Erase Error
Idle
Sector Locked Error
Sector Erase Successful
SR1, must cleared before Write State Machine allows further erase attempts. Only Clear Status Register command clears SR1, SR3, SR4, SR5. error detected, clear status register before attempting erase retry other error recovery.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Protection Register Programming Flowchart
Start
Protection Register Programming Procedure
Operation Write Command Program Setup Protection Program None None Comments Data Addr First Location Program Data Data Program Addr Location Program Status register data: Toggle update status register data Check WSMS Ready WSMS Busy
Write Address
(Program Setup)
Write
(Confirm Data)
Write Address Data
Read Idle
Read Status Register
Full Status Check Desired)
Program Complete
Program Protection Register operation addresses must within protection register address space. Addresses outside this space will return error. Repeat subsequent programming operations. Full status register check done after each program, after sequence program operations. Write after last operation return Read mode.
Full Status Check Flowchart
Read Status Register Data
Full Status Check Procedure
Operation Command None None None Comments Check SR1, SR3, SR4: 0,1,1 Range Error Check SR1, SR3, SR4: 0,0,1 Programming Error Check SR1, SR3, SR4: Sector locked; operation aborted
SR3,
Idle
Range Error
Idle
SR1,
Program Error
Idle
SR1,
Register Locked; Program Aborted
Program Successful
must cleared before Write State Machine allows further program attempts. Only Clear Status Register command clears SR1, SR3, SR4. error detected, clear status register before attempting program retry other error recovery.
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Command Definition Hex(1)
Command Sequence Read Chip Erase Plane Erase Sector Erase Word Program Dual Word Program
Cycles
Cycle Addr
Cycle Addr Data Addr Addr
(14)
Cycle Addr Data
Data
Addr
(14)
DIN0 Addr1 DIN1
40/10
Addr
Addr0
Addr0
Erase/Program Suspend Erase/Program Resume Product Entry Sector Softlock Sector Hardlock Sector Unlock Read Status Register Clear Status Register Program (Block PR1-PR16 Lock Protection Block Lock Protection PR1-PR16 Status Protection (Block Status Protection PR1-PR16 Program Burst Configuration Register Read Burst Configuration Register Query
Notes:
(13)
SA(3)
DOUT(4) FFFD DIN(11) DOUT(5) DOUT(12) DOUT
Addr(10) Addr(6) PAX005
Addr(6)
DATA FORMAT shown each cycle follows; I/O7 I/O0 (Hex). I/O15 I/O8 don't care. ADDRESS FORMAT shown each cycle follows: (Hex). Address through don't care. plane address (A22 A18). address within plane used. sector address. word address within sector used designate sector address (see pages details). status register bits output I/O7 I/O0. data "0", block locked. data "1", block reprogrammed. "Burst Configuration Register" page Bits burst configuration register determine Addresses select plane. plane address same plane address second cycle. address within user programmable protection register region. This fast programming option enables user program words parallel only when 12V. addresses, Addr0 Addr1, words, DIN0 DIN1, must only differ address This command should used during manufacturing purposes only. Address locations shown next page. represents bits data. programmed "0", appropriate protection register locked. DOUT represents bits data. Each corresponds protection status given register. most significant read corresponds PR16, last significant corresponds PR0. data "0", register locked. data bits "1", register programmed. manufacturer code read from address 0000H, device code read from address 0001H. first cycle address should same word address programmed.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Absolute Maximum Ratings*
Temperature under Bias -55°C +125°C Storage Temperature -65°C +150°C Input Voltages Except (including Pins) with Respect Ground .-0.6V +6.25V Input Voltage with Respect Ground 12.5V Output Voltages with Respect Ground .-0.6V VCCQ 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Protection Register Addressing Table
Address Factory Factory Factory Factory User User User User Block
User
User
User
User
PR16
User
Note:
User
address lines specified above table must when accessing Protection Register, i.e.,
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Burst Configuration Register
B11: 1(1) 0(1) 010(2) 110(1) 1(1)(3) 1(1) 1(1) 1(1) 1(1) 00(1) 1(1) 111(1) Synchronous Burst Reads Enabled Asynchronous Reads Enabled Four-word Page Eight-word Page Clock Latency Clock Latency Three Clock Latency Four Clock Latency Five Clock Latency WAIT Signal Asserted WAIT Signal Asserted High Hold Data Clock Hold Data Clocks WAIT Asserted during Clock Cycle which Data Valid WAIT Asserted Clock Cycle before Data Valid Linear Burst Sequence Burst Starts Data Output Falling Clock Edge Burst Starts Data Output Rising Clock Edge Reserved Future Wrap Burst Within Burst length Don't Wrap Accesses Within Burst Length Four-word Burst Eight-word Burst Sixteen-word Burst Continuous Burst
Notes:
Default State Burst configuration setting (clock latency two), (hold data clock cycles) (WAIT asserted clock cycle before data valid) supported. Data ready when WAIT asserted.
Clock Latency versus Input Clock Frequency
Minimum Clock Latency (Minimum Number Clocks Following Address Latch) Input Clock Frequency
Figure Output Configuration
Data Hold Data Hold I/00 I/015 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT
I/00 I/015
AT49SN/SV12804 [Preliminary]
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AT49SN/SV12804 [Preliminary]
Table Sequence Burst Length
Burst Addressing Sequence (Decimal) 4-word Burst Length Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8-word Burst Length Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 16-word Burst Length Linear 0-1-2.14-15 1-2-3.14-15-0 2-3-4.15-0-1 3-4-5.15-0-1-2 4-5-6.15-0-1-2-3 5-6-7.15-0-1.4 6-7-8.15-0-1.5 7-8-9.15-0-1.6 14-15-0-1.13 15-0-1-2-3.14 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 0-1-2.14-15 1-2-3.15-16 2-3-4.16-17 3-4-5.17-18 4-5-6.18-19 5-6-7.19-20 6-7-8.20-21 7-8-9.21-22 14-15.28-29 15-16.29-30 Continuous Burst Linear 0-1-2-3-4-5-6. 1-2-3-4-5-6-7. 2-3-4-5-6-7-8. 3-4-5-6-7-8-9. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12. 7-8-9-10-11-12-13. 14-15-16-17-18-19-20 15-16-17-18-19-20-21 0-1-2-3-4-5-6. 1-2-3-4-5-6-7. 2-3-4-5-6-7-8. 3-4-5-6-7-8-9. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12. 7-8-9-10-11-12-13. 14-15-16-17-18-19-20 15-16-17-18-19-20-21
Start Addr. (Decimal)
Wrap
Wrap
3314A-FLASH-4/04
Memory Organization AT49SN/SV12804
Plane Plane Size (Bits) Sector Size Words Address Range (A22 00000 00FFF 01000 01FFF 02000 02FFF 03000 03FFF 04000 04FFF 05000 05FFF 06000 06FFF 07000 07FFF 08000 0FFFF 10000 17FFF
SA13 SA14 SA15
30000 37FFF 38000 -3FFFF 40000 47FFF
SA22 SA23
78000 7FFFF 80000 87FFF
SA30 SA31
B8000 BFFFF C0000 C7FFF
SA38 SA39
F8000 FFFFF 100000 107FFF
SA46 SA47
138000 13FFFF 140000 147FFF
SA54 SA55
178000 17FFFF 180000 187FFF
SA62
1B8000 1BFFFF
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Memory Organization AT49SN/SV12804 (Continued)
Plane Plane Size (Bits) Sector SA63 Size Words Address Range (A22 1C0000 1C7FFF
SA70 SA71
1F8000 1FFFFF 200000-207FFF
SA78 SA79
238000 23FFFF 240000 247FFF
SA86 SA87
278000 27FFFF 280000 287FFF
SA94 SA95
2B8000 2BFFFF 2C0000 2C7FFF
SA102 SA103
2F8000 2FFFFF 300000 307FFF
SA110 SA111
338000 33FFFF 340000 347FFF
SA118 SA119
378000 37FFFF 380000 387FFF
SA126 SA127
3B8000 3BFFFF 3C0000 3C7FFF
SA134
3F8000 3FFFFF
3314A-FLASH-4/04
Memory Organization AT49SN/SV12804 (Continued)
Plane Plane Size (Bits) Sector SA135 Size Words Address Range (A22 400000 407FFF
SA142 SA143
438000 43FFFF 440000 447FFF
SA150 SA151
478000 47FFFF 480000 487FFF
SA158 SA159
4B8000 4BFFFF 4C0000 4C7FFF
SA166 SA167
4F8000 4FFFFF 500000 507FFF
SA174 SA175
538000 53FFFF 540000 547FFF
SA182 SA183
578000 57FFFF 580000 587FFF
SA190 SA191
5B8000 5BFFFF 5C0000 5C7FFF
SA198 SA199
5F8000 5FFFFF 600000 607FFF
SA206
638000 63FFFF
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Memory Organization AT49SN/SV12804 (Continued)
Plane Plane Size (Bits) Sector SA207 Size Words Address Range (A22 640000 647FFF
SA214 SA215
678000 67FFFF 680000 687FFF
SA222 SA223
6B8000 6BFFFF 6C0000 6C7FFF
SA230 SA231
6F8000 6FFFFF 700000 707FFF
SA238 SA239
738000 73FFFF 740000 747FFF
SA246 SA247
778000 77FFFF 780000 787FFF
SA254 SA255 SA256
7B8000 7BFFFF 7C0000 7C7FFF 7C8000 7CFFFF
SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
7F0000 7F7FFF 7F8000 7F8FFF 7F9000 7F9FFF 7FA000 7FAFFF 7FB000 7FBFFF 7FC000 7FCFFF 7FD000 7FDFFF 7FE000 7FEFFF 7FF000 7FFFFF
3314A-FLASH-4/04
Operating Range
AT49SN/SV12804-70 Operating Temperature (Case) Power Supply Industrial -40°C 85°C 1.65V 1.95V
Operating Modes
Mode Read Burst Read Program/Erase(3) Standby/Program Inhibit Program Inhibit Output Disable Reset Product Identification Software
Notes:
X(1)
RESET
VPP(4) VIHPP(5) VILPP(6)
DOUT DOUT High
High High
VIL, VIH,
Manufacturer Code(3) Device Code(3)
VIH. Refer programming waveforms. Manufacturer Code: 001FH; Device Code: 00BBH tied VCC. faster program/erase operations, 12.0V 0.5V. VIHPP (min) 0.9V. VILPP (max) 0.4V.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Characteristics
Symbol ISB1
Parameter Input Load Current Output Leakage Current Standby Current CMOS Active Current Read While Erase Current Read While Write Current Input Voltage Input High Voltage Output Voltage
Condition VI/O VCCQ 0.3V MHz; IOUT MHz; IOUT MHz; IOUT
Units
ICCRE ICCRW Note:
VCCQ -100 -400 VCCQ 0.25
Output High Voltage erase mode,
Input Test Waveforms Measurement Level
1.4V DRIVING LEVELS 0.4V 0.9V MEASUREMENT LEVEL
Output Test Load
VCCQ 1.8K OUTPUT 1.3K
Capacitance
MHz, 25°C(1)
COUT Note: Units Conditions VOUT
This parameter characterized 100% tested.
3314A-FLASH-4/04
Asynchronous Read Timing Characteristics
Symbol tACC1 tACC2 tAHAV tAVLP tAVHP tAAV Parameter Access, Data Valid Access, Address Data Valid Access, Data Valid Data Valid Address Hold from Pulse Width High Pulse Width Address Valid High Data Float Output Hold from Address, Whichever Occurred First RESET Output Delay Units
Pulsed Asynchronous Read Cycle Waveform(1)(2)
I/O0-I/O15 tACC2 -A22 tAAV tAHAV tACC2 tAAV tAVHP tAVLP tACC1 RESET tAHAV DATA VALID
Notes:
After high-to-low transition AVD, remain long address stable. static high static low.
Asynchronous Read Cycle Waveform(1)(2)(3)(4)
ADDRESS VALID
tACC2 HIGH OUTPUT VALID
RESET
I/O0 I/O15
Notes:
delayed tACC after address transition without impact tACC. delayed after falling edge without impact tACC after address change without impact tACC. specified from whichever occurs first pF). should tied low.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Asynchronous Read Timing Characteristics
Symbol tACC1 tACC2 tAHAV tAVLP tAVHP tAAV tPAA Parameter Access, Data Valid Access, Address Data Valid Access, Data Valid Data Valid Address Hold from Pulse Width High Pulse Width Address Valid High Data Float RESET Output Delay Page Address Access Time Units
Page Read Cycle Waveform 1(1)
I/O0-I/O15 tACC2 -A22 tAAV tAHAV tACC2 tAAV tAVHP tAVLP tACC1 RESET tAHAV tPAA DATA VALID
Note:
After high-to-low transition AVD, remain long page address stable.
Page Read Cycle Waveform 2(1)
I/O0-I/O15 tACC2 -A22 tPAA tACC2 DATA VALID
RESET
Note:
remain long page address stable.
3314A-FLASH-4/04
Burst Read Timing Characteristics
Symbol tCLK tCKH tCKL tCKRT tCKFT tACK tAVCK tCECK tCKAV tQHCK tAHCK tCKRY tCESAV tAAV tAHAV tCKQV tCEQZ Parameter Period High Time Time Rise Time Fall Time Address Valid Clock Clock Clock Clock High Output Hold from Clock Address Hold from Clock Clock WAIT Delay Setup Address Valid Address Hold From Data Delay High Output High-Z Units
Burst Read Cycle Waveform
tCLK tAHCK tCECK tCESAV tAVCK
tCKH tCKL
tACK
tCKAV tAAV
tAHAV tQHCK
tCKQV
tCEQZ
I/O0-I/O15
A0-A21
tCKRY WAIT tCKRY
Notes:
WAIT signal (dashed line) shown burst configuration register setting WAIT Signal (solid line) shown burst configuration setting After high-to-low transition AVD, remain low.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Burst Read Waveform (Clock Latency
A0-A21
VALID
I/O0-I/O15
WAIT
HIGH
HIGH
Note:
Dashed line reflects setting configuration register. Solid line reflects setting setting configuration register.
Hold Data Clock Cycles Read Waveform (Clock Latency
A0-A21
I/O0-I/O15
WAIT(1)
Note:
Dashed line reflects burst configuration register setting Solid line reflects burst configuration register setting
3314A-FLASH-4/04
Four-word Burst Read Waveform (Clock Latency
A0-A21
VALID
I/O0-I/O15
HIGH
HIGH
WAIT
Note:
WAIT signal shown burst configuration register
Burst Suspend Waveform
tCLK
tCKH tCKL
tAHCK tCECK
tCEAV tAVCK tACK tCKAV tAAV I/O0-I/O15 tAHAV tQHCK tCKQV tCEQZ
A0-A21
WAIT
Notes:
WAIT signal (dashed line) shown burst configuration register setting WAIT Signal (solid line) shown burst configuration setting During Burst Suspend, signal held high.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Word Load Characteristics
Symbol tAAV tAHAV tAVLP tCESAV tWPH tWEAV tCEAV Parameter Address Valid High Address Hold Time from High Pulse Width Data Setup Time Data Hold Time Setup Pulse Width High Pulse Width High Time High Time Units
Word Load Waveforms
Controlled(1)
I/O0-I/O15
DATA VALID
-A22 tAAV tAHAV tAVLP tWEAV
Note:
After high-to-low transition AVD, remain long input does toggle.
Controlled(1)
I/O0-I/O15
DATA VALID
-A22 tAAV tAHAV tAVLP tCESAV tCEAV
Note:
After high-to-low transition AVD, remain long input does toggle.
3314A-FLASH-4/04
Word Load Characteristics
Symbol tWPH Parameter Address Setup Time High Address Hold Time Data Setup Time Data Hold Time Pulse Width High Pulse Width Units
Word Load Waveforms
Controlled(1)
I/O0 I/O15
DATA VALID
Note:
input should toggle.
Controlled(1)
I/O0 I/O15
DATA VALID
Note:
input should toggle.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Program Cycle Characteristics
Symbol tSEC1 tSEC2 tERES Parameter Word Programming Time Sector Erase Cycle Time word sectors) Sector Erase Cycle Time (32K word sectors) Erase Suspend Time Program Suspend Time Delay between Erase Resume Erase Suspend Units
Program Cycle Waveforms
PROGRAM CYCLE
tWPH
ADDRESS
INPUT DATA
I/O0 I/O15
Note
Sector, Plane Chip Erase Cycle Waveforms
tWPH
Note
tSEC1/2
I/O0 I/O15
Note WORD
WORD
Notes:
address used load data. must high only when both low. data 10H. chip erase, address used. plane erase sector erase, address depends what plane sector erased. chip erase, data should 21H, plane erase, data should 22H, sector erase, data should 20H.
3314A-FLASH-4/04
Table Common Flash Interface Definition AT49SN/SV12804
Address AT49SN/SV12804 0051h 0052h 0059h 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h 0019h 00B5h 00C5h 0004h 0000h 0009h 0011h 0004h 0000h 0003h 0003h 0018h 0001h 0000h 0000h 0000h 0003h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0007h 0000h 0020h 0000h block erase chip erase 131,000 word write/typ time block erase/typ block erase chip erase/ chip erase Device size device device Multiple byte write supported Multiple byte write supported regions, bytes, bytes, bytes, bytes, bytes, bytes, bytes, bytes, bytes, bytes, bytes, bytes, write/erase write/erase voltage voltage word write Comments
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Table Common Flash Interface Definition AT49SN/SV12804 (Continued)
Address AT49SN/SV12804 Comments
VENDOR SPECIFIC EXTENDED QUERY 0050h 0052h 0049h 0031h 0030h 00BFh Major version number, ASCII Minor version number, ASCII chip erase supported, erase suspend supported, program suspend supported, simultaneous operations supported, burst mode read supported, page mode read supported, queued erase supported, protection bits supported, 0002h ("0"), bottom ("1"), both bottom ("2") boot block device Undefined bits word linear burst with wrap around, word linear burst with wrap around, word linear burst with wrap around, continuos burst, Undefined bits word page, word page, Undefined bits Location protection register lock byte, section's first byte bytes factory prog section prot register bytes user prog section prot register Number planes planes
000Fh
0003h 0080h 0003h 0007h 0020h
3314A-FLASH-4/04
AT49SN/SV12804 Ordering Information
tACC (ns) (mA) Active Standby 0.01 0.01 Ordering Code AT49SN12804-70CI AT49SV12804-70TI Package 56C3 Operation Range Industrial (-40° 85°C) Industrial (-40° 85°C)
Package Type 56C3 56-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 56-lead, Plastic Thin Small Outline Package (TSOP)
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
AT49SN/SV12804 [Preliminary]
Packaging Information
56C3 CBGA
0.12
Seating Plane
Side View
View
1.375
COMMON DIMENSIONS (Unit Measure SYMBOL 0.21 7.90 8.00 5.25 9.90 10.00 4.50 0.75 0.35 10.10 1.00 8.10 NOTE
2.75
Bottom View
1/9/04 2325 Orchard Parkway Jose, 95131 TITLE 56C3, 56-ball Array), Body, 0.75 Ball Pitch Ceramic Ball Grid Array Package (CBGA) DRAWING 56C3 REV.
3314A-FLASH-4/04
TSOP
Identifier
SEATING PLANE
GAGE PLANE
SYMBOL Notes: This package conforms JEDEC reference MO-142, Variation Dimensions include mold protrusion. Allowable protrusion 0.15 side 0.25 side. Lead coplanarity 0.10 maximum.
COMMON DIMENSIONS (Unit Measure 0.05 0.95 19.80 18.20 13.80 0.50 1.00 20.00 18.40 14.00 0.60 0.25 BASIC 0.10 0.10 0.15 0.50 BASIC 0.20 0.21 1.20 0.15 1.05 20.20 18.60 14.20 0.70 Note Note NOTE
10/23/03 2325 Orchard Parkway Jose, 95131 TITLE 56T, 56-lead Package) Plastic Thin Small Outline Package, Type (TSOP) DRAWING REV.
AT49SN/SV12804 [Preliminary]
3314A-FLASH-4/04
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3314A-FLASH-4/04

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