August 1993 Revised February 2005 74VHC125 Quad Buffer with 3-STA

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August 1993 Revised February 2005 74VHC125 Quad Buffer with 3-STA

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74VHC125 Quad Buffer with 3-STATE Outputs
August 1993 Revised February 2005
74VHC125 Quad Buffer with 3-STATE Outputs
VHC125 contains four independent non-inverting buffers with 3-STATE outputs. advanced high-speed CMOS device fabricated with silicon gate CMOS technology achieves high-speed operation similar equivalent Bipolar Schottky while maintaining CMOS power dissipation. input protection circuit insures that applied input pins without regard supply voltage. This device used interface systems supply systems such battery backup. This circuit prevents device destruction mismatched supply input voltages.
Features
High Speed:
(typ) VNIL
25qC
Lower power dissipation: High noise immunity: VNIH noise: VOLP
(max)
(min)
Power down protection provided inputs
0.8V (max)
function compatible with 74HC125
Ordering Code:
Order Number 74VHC125M 74VHC125MX_NL (Note 74VHC125SJ 74VHC125MTC 74VHC125MTCX_NL (Note 74VHC125N Package Number M14A M14A M14D MTC14 MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages also available Tape Reel. Specify appending suffix letter ordering code. Pb-Free package JEDED J-STD-020B. Note "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available Tape Reel only.
2005 Fairchild Semiconductor Corporation
DS011632
www.fairchildsemi.com
74VHC125
Logic Symbol
IEEE/IEC
Connection Diagram
Descriptions
Names Description Inputs Outputs
Function Table
Inputs
HIGH Voltage Level Voltage Level HIGH Impedance Immaterial
Output
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74VHC125
Absolute Maximum Ratings(Note
Supply Voltage (VCC Input Voltage (VIN) Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) Output Current (IOUT) /GND Current (ICC Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, seconds) 260qC
0.5V 7.0V 0.5V 7.0V 0.5V 0.5V 65qC 150qC
Recommended Operating Conditions (Note
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise Fall Time (tr, 3.3V 0.3V 5.0V 0.5V ns/V ns/V 2.0V 5.5V 5.5V
40qC 85qC
Note Absolute Maximum Ratings values beyond which device damaged have useful life impaired. databook specifications should met, without exception, ensure that system design reliable over power supply, temperature, output/input loading variables. Fairchild does recommend operation outside databook specifications. Note Unused inputs must held HIGH LOW. They float.
Electrical Characteristics
Symbol Parameter HIGH Level Input Voltage Level Input Voltage HIGH Level Output Voltage Level Output Voltage 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 40.0 2.58 3.94 0.36 0.36 1.50 0.50 2.48 3.80 0.44 0.44 VOUT 5.5V 25qC
40qC 85qC
1.50
Units
Conditions
0.50
r0.25 r0.1
r2.5 r1.0
Noise Characteristics
Symbol VOLP (Note VOLV (Note VIHD (Note VILD (Note Parameter Quiet Output Maximum Dynamic Quiet Output Minimum Dynamic Minimum HIGH Level Dynamic Input Voltage Maximum HIGH Level Dynamic Input Voltage 25qC Limits Units Conditions
Note Parameter guaranteed design.
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74VHC125
Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time tPZL tPZH 3-STATE Output Enable Time tPLZ tPHZ tOSLH tOSHL COUT Input Capacitance Output Capacitance Power Dissipation Capacitance
Note Parameter guaranteed design. tOSLH |tPLHmax tPLHmin|; tOSHL |tPHLmax tPHLmin|. Note defined value internal equivalent capacitance which calculated from operating current consumption without load. Average operating current obtained equation: (OPR.) ICC/4 (per bit).
25qC 11.5 11.5 13.2
40qC 85qC
13.0 13.0 15.0 10.0
Units
Conditions (Note Open 5.0V
3-STATE Output Disable Time Output Output Skew
(Note
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74VHC125
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
www.fairchildsemi.com
74VHC125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide Package Number M14D
www.fairchildsemi.com
74VHC125
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
www.fairchildsemi.com
74VHC125 Quad Buffer with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. www.fairchildsemi.com critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com

August 1993 Revised February 2005 74VHC125 Quad Buffer with 3-STA

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