240-Pin Dual Registered DDR2 SDRAM Modules RDIMM SDRAM RoHS Compliant
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HYS72T512022EP-3.7-B HYS72T512022EP-3S-B
240-Pin Dual Registered DDR2 SDRAM Modules RDIMM SDRAM RoHS Compliant
Rev.
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
HYS72T512022EP-3.7-B, HYS72T512022EP-3S-B Revision History: 2007-03, Rev. Page Subjects (major changes since last revision) Adapted internet edition Final Document
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qag_techdoc_rev400 2006-08-07 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Overview
This chapter gives overview 240-Pin Dual Registered DDR2 SDRAM Modules with parity product family describes main characteristics.
Features
Programmable self refresh rate EMRS2 setting Programmable partial array refresh EMRS2 settings enabling EMRS2 setting inputs outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) On-Die Termination (ODT) Serial Presence Detect with E2PROM RDIMM Dimensions (nominal): high, 133.35 wide Based standard reference card layouts Card speed grades faster than DDR2-400 comply with DDR2-400 timing specifications. RoHS compliant products1)
240-Pin PC2-5300 PC2-4200 DDR2 SDRAM memory modules. 512M module organization 256M chip organization Registered DIMM Parity address control modules built with 1Gbit DDR2 SDRAMs P-TFBGA-71 chipsize packages. Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with single power supply Programmable Latencies Burst Length Burst Type Auto Refresh (CBR) Self Refresh
RoHS Compliant Product: Restriction certain hazardous substances (RoHS) electrical electronic equipment defined directive 2002/95/EC issued European Parliament Council January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls polybrominated biphenyl ethers.
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Description
loading system bus, adds cycle SDRAM timing. Decoupling capacitors mounted board. DIMMs feature serial presence detect based serial E2PROM device using 2-pin protocol. first bytes programmed with configuration data second bytes available customer.
Qimonda HYS72T512022EP-[3S/3.7]-B module family Registered DIMM (with parity) modules with height based DDR2 technology. DIMMs available modules 512M organization density, intended mounting into 240-Pin connector sockets. memory array designed with 1-Gbit Double-Data-RateTwo (DDR2) Synchronous DRAMs. control address signals re-driven DIMM using register devices clock distribution. This reduces capacitive
TABLE
Ordering Information RoHS Compliant Products
Product Type1) PC2-4200 HYS72T512022EP-3.7-B PC2-5300 HYS72T512022EP-3S-B PC2-5300P-555-12-K0 Ranks, Mbit
Product Type number with place code, designating silicon revision. Example: HYS72T512022EP-3.7-B, indicating Rev. dies used DDR2 SDRAM components. Qimonda DDR2 module component nomenclature Chapter this data sheet. Compliance Code printed module label describes speed grade, example "PC2-4200R-444-12-F0", where 4200P means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth "444-12" means Column Address Strobe (CAS) latency Column Delay (RCD) latency Precharge (RP) latency using latest JEDEC Revision produced Card
Compliance Code2)
Description
SDRAM Technology Mbit
PC2-4200P-444-12-K0
Ranks,
TABLE
Address Format Table
DIMM Density GByte Module Organization 512M Memory Ranks ECC/ Non-ECC SDRAMs row/bank/column bits 14/3/11 Card
TABLE
Components Modules
Product Type1) HYS72T512022ER DRAM Components1)2) HYB18T2G402BF DRAM Density Gbit DRAM Organisation 256M
Green Product detailed description functionalities DRAM components these modules component data sheet.
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Configuration
Table respectively. numbering depicted Figure
configuration Registered DDR2 SDRAM DIMM listed function Table (240 pins). abbreviations used columns Buffer Type explained Table
TABLE
Configuration RDIMM
Ball Clock Signals CKE0 CKE1 Control Signals Address Signals SSTL SSTL SSTL SSTL Bank Address Greater than 512Mb DDR2 SDRAMS Connected Less than DDR2 SDRAMS Bank Address RESET SSTL SSTL SSTL SSTL SSTL CMOS Register Reset Chip Select Rank Note: 2-Ranks module Connected Note: 1-Rank module Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) SSTL SSTL SSTL SSTL Clock Enables Note: 2-Ranks module Connected Note: 1-Rank module Clock Signal CK0, Complementary Clock Signal Name Type Buffer Type Function
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Ball
Name
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Address 12:0, Address Signal 10/AutoPrecharge
Address Signal Connected Note: parity modules based Mbit component Address Signal Note: Parity module Connected Note: parity module. Less than GBit DRAM die. Address Signal Note: Parity module Connected Note: parity module. Less than GBit DRAM die.
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Ball Data Signals
Name
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38
Data 63:0 Data Input/Output pins
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Ball Check Bits
Name DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data 63:0
Check Bits Check Input Output pins Note: Non-ECC module
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Ball Data Strobe
Name
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 DQS9 DQS9 DQS10 DQS10 DQS11 DQS11 DQS12 DQS12 DQS13 DQS13 DQS14 DQS14 DQS15 DQS15 DQS16 DQS16 DQS17 DQS17
Data Strobes 17:0
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Ball Data Mask EEPROM Parity Power Supplies 170, 175, 181, 191,
Name
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS CMOS CMOS CMOS CMOS CMOS
Function
ERR_OUT PAR_IN
Data Masks Note: based module
Serial Clock Serial Data Serial Address Select
Parity bits
VREF VDDSPD VDDQ
Reference Voltage EEPROM Power Supply Driver Power Supply
172, 178, 184, 187, 189, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234,
Power Supply
Ground Plane
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Ball Other Pins 102, 137, 138, 173, 220,
Name
Type
Buffer Type SSTL SSTL
Function
ODT0 ODT1
connected On-Die Termination Control Note: 2-Ranks module Note: 1-Rank module
TABLE
Abbreviations Buffer Type
Abbreviation SSTL CMOS Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. corresponding operational states, active tristate, allows multiple devices share wire-OR.
TABLE
Abbreviations Type
Abbreviation Description Standard input-only pin. Digital levels. Output. Digital levels. bidirectional input/output signal. Input. Analog levels. Power Ground Usable Connected
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
FIGURE
Configuration RDIMM (240 pins)
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Electrical Characteristics
Absolute Maximum Ratings
TABLE
Absolute Maximum Ratings
This chapter lists electrical characteristics.
Caution needed exceed absolute maximum ratings DRAM device listed Table time.
Symbol
Parameter
Rating Min. Max. +2.3 +2.3 +2.3 +2.3
Unit
Note
Storage Temperature +100 When VDDQ VDDL less than VREF equal less than
Storage Temperature case surface temperature center/top side DRAM.
VDDQ VDDL VIN, VOUT TSTG
Voltage relative Voltage VDDQ relative Voltage VDDL relative Voltage relative
-1.0 -0.5 -0.5 -0.5
1)2) 1)2) 1)2)
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
TABLE
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max.
1)2)3)4)
Unit
Note
TOPER
Operating Temperature
Operating Temperature case surface temperature center side DRAM. operating temperature range temperatures where DRAM specification will supported. During operation, DRAM case temperature must maintained between under other specification parameters. Above Auto-Refresh command interval reduced tREFI= When operating this product TCASE temperature range, High Temperature Self Refresh enabled setting EMR(2) "1". When High Temperature Self Refresh enabled there increase IDD6 approximately
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Operating Conditions
TABLE
Operating Conditions
This chapter contains operating conditions tables.
Parameter
Symbol
Values Min. Max. +100 +105
Unit
Note
Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating storage) Operating Humidity (relative)
TOPR TCASE TSTG PBar HOPR
1)2)3)4)
DRAM Component Case Temperature surface temperature center side DRAMs. Within DRAM Component Case Temperature Range DRAM specifications will supported Above DRAM Case Temperature Auto-Refresh command interval reduced tREFI When operating this product TCASE temperature range, High Temperature Self Refresh enabled setting EMR(2) "1". When High Temperature Self Refresh enabled there increase IDD6 approximately 3000
TABLE
Supply Voltage Levels Operating Conditions
Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage Supply Voltage Input Logic High Input Logic Typ. VDDQ Max. 0.51 VDDQ
Unit
Note
Output Leakage Current Under conditions, VDDQ must less than equal Peak peak noise VREF exceed VREF (DC).VREF also expected track noise VDDQ. Input voltage connector under test VDDQ other pins Current
VDDQ VREF VDDSPD VIH(DC) (DC)
0.49 VDDQ
VREF 0.125
0.30
VDDQ VREF 0.125
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Timing Characteristics
This chapter describes timing characteristics.
3.3.1
Speed Grade Definitions
Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(tCK with tRAS 40ns). Speed Grade Definitions: Table DDR2-667D, Table DDR2-533C
TABLE
Speed Grade Definition Speed Bins DDR2-667D
Speed Grade Sort Name CAS-RCD-RP latencies Parameter Clock Frequency Active Time Cycle Time RAS-CAS-Delay Precharge Time Symbol DDR2-667D 5-5-5 Min. 3.75 Max. 70000 Unit Note
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tRAS tRCD
Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended mode.Timings further guaranteed normal drive strength (EMRS(1) CK/CK input reference level (for timing reference CK/CK) point which cross. DQS, RDQS RDQS, input reference level crosspoint when differential strobe mode Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT. tRAS.MAX calculated from maximum amount time DDR2 device operate without refresh command which equal tREFI.
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TABLE
Speed Grade Definition Speed Bins DDR2-533C
Speed Grade Sort Name CAS-RCD-RP latencies Parameter Clock Frequency Active Time Cycle Time RAS-CAS-Delay Precharge Time Symbol DDR2-533C -3.7 4-4-4 Min. 3.75 3.75 Max. 70000 Unit Note
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tRAS tRCD
Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended modeTimings further guaranteed normal drive strength (EMRS(1) CK/CK input reference level (for timing reference CK/CK) point which cross. DQS, RDQS RDQS, input reference level crosspoint when differential strobe mode. Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT. tRAS.MAX calculated from maximum amount time DDR2 device operate without refresh command which equal tREFI.
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
3.3.2
Component Timing Parameters
TABLE
DRAM Component Timing Parameter Speed Grade DDR2-667
Timing Parameters: Table DDR2-667D, Table DDR2-533C
Parameter
Symbol
DDR2-667 Min. Max. +450 0.52 8000 0.52 +400 0.25
Unit
Note1)2)3)4)5)6)7)
output access time from command delay Average clock high pulse width Average clock period minimum pulse width high pulse width) Average clock pulse width
tCCD tCH.AVG tCK.AVG tCKE
-450 0.48 3000 0.48 tnRP
10)11)
tCK.AVG
tCL.AVG Auto-Precharge write recovery precharge time tDAL Minimum time clocks remain after tDELAY
asynchronously drops input hold time
tCK.AVG
10)11) 13)14)
.AVG
0.35 -400 0.35 0.35 0.25 37.5 (tCH.ABS, tCL.ABS) tAC.MIN
tDH.BASE input pulse width each input tDIPW output access time from tDQSCK input high pulse width tDQSH input pulse width tDQSL DQS-DQ skew associated signals tDQSQ latching rising transition associated clock tDQSS
edges
19)20)15)
tCK.AVG
tCK.AVG tCK.AVG
tCK.AVG
tDS.BASE falling edge hold time from tDSH falling edge setup time tDSS Four Activate Window page size products tFAW Four Activate Window page size products tFAW half pulse width
input setup time
18)19)20)
tCK.AVG tCK.AVG
Address control input hold time tIH.BASE Control address input pulse width each input tIPW Address control input setup time tIS.BASE impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from tLZ.DQS command update delay tMOD Mode register command cycle time tMRD tOIT drive mode output delay DQ/DQS output hold time from
Data-out high-impedance time from
tAC.MAX
9)22) 25)23)
tCK.AVG
24)25) 9)22) 9)22)
tAC.MIN
tAC.MAX tAC.MAX
tQHS
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Parameter
Symbol
DDR2-667 Min. Max.
Unit
Note1)2)3)4)5)6)7)
hold skew factor Read preamble Read postamble Active active command period page size products Active active command period page size products Internal Read Precharge command delay Write preamble Write postamble Write recovery time Internal write read command delay Exit power down read command Exit active power-down mode read command (slow exit, lower power) Exit precharge power-down valid command (other than Deselect) Exit self-refresh non-read command Exit self-refresh read command Write command associated clock edges
tQHS tRPRE tRPST tRRD tRRD tRTP tWPRE tWPST tWTR tXARD tXARDS tXSNR tXSRD
0.35
28)29) 28)30)
tCK.AVG tCK.AVG
tCK.AVG tCK.AVG
31)32)
tRFC
RL-1
details notes relevant Qimonda component data sheet VDDQ 0.1V; Timing that specified illegal after such event, order guarantee proper operation, DRAM must powered down then restarted through specified initialization sequence before normal operation continue. Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended mode. input reference level (for timing reference point which cross. DQS, RDQS RDQS, input reference level crosspoint when differential strobe mode. Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT. units, `tCK.AVG` `nCK`, introduced DDR2-667 DDR2-800. Unit `tCK.AVG` represents actual tCK.AVG input clock under operation. Unit `nCK` represents clock cycle input clock, counting actual clock edges. Note that DDR2-400 DDR2-533, `tCK` used both concepts. Example: [nCK] means; Power Down exit registered Active command registered even tCK.AVG tERR.2PER(Min). When device operated with input clock jitter, this parameter needs derated actual tERR(6-10per) input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tERR(6-10PER).MIN tERR(6- 10PER).MAX then tDQSCK.MIN(DERATED) tDQSCK.MIN tERR(6-10PER).MAX tDQSCK.MAX(DERATED) tDQSCK.MAX tERR(6-10PER).MIN Similarly, tLZ.DQ DDR2-667 derates tLZ.DQ.MIN(DERATED) 1193 tLZ.DQ.MAX(DERATED) (Caution MIN/MAX usage!) Input clock jitter spec parameter. These parameters referred 'input clock jitter spec parameters' these parameters apply DDR2-667 DDR2-800 only. jitter specified random jitter meeting Gaussian distribution. These parameters specified their average values, however understood that relationship between average timing absolute instantaneous timing holds times (min. SPEC values used calculations). tCKE.MIN clocks means must registered three consecutive positive clock edges. must remain valid input level entire time takes achieve clocks registration. Thus, after transition, transition from valid level during time period tIH.
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RU{tRP(ns) tCK(ns)}, where stands round refers parameter stored MRS. tRP, result division already integer, round next highest integer. refers application clock period. Example: DDR2-533 3.75 with programmed clocks. tDAL 3.75 clocks clocks clocks. tDAL.nCK [nCK] tnRP.nCK RU{tRP [ps] tCK.AVG[ps] where value programmed EMR. Input waveform timing with differential data strobe enabled MR[bit10] referenced from differential data strobe crosspoint input signal crossing VIH.DC level falling signal from differential data strobe crosspoint input signal crossing VIL.DC level rising signal applied device under test. DQS, signals must monotonic between VIL.DC.MAX VIH.DC.MIN. Figure tDQSQ: Consists data skew output pattern effects, p-channel n-channel variation output drivers well output slew rate mismatch between associated given cycle. These parameters measured from data strobe signal ((L/U/R)DQS DQS) crossing respective clock signal crossing. spec values affected amount clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), these relative clock signal crossing. That these parameters should whether clock jitter present not. Input waveform timing with differential data strobe enabled MR[bit10] referenced from input signal crossing VIH.AC level differential data strobe crosspoint rising signal, from input signal crossing VIL.AC level differential data strobe crosspoint falling signal applied device under test. DQS, signals must monotonic between Vil(DC)MAX Vih(DC)MIN. Figure violated, data corruption occur data must re-written with valid data before valid READ executed. These parameters measured from data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge respective data strobe signal ((L/U/R)DQS DQS) crossing. minimum absolute half period actual input clock. input parameter input specification parameter. used conjunction with tQHS derive DRAM output timing tQH. value used calculation determined following equation; (tCH.ABS, tCL.ABS), where, tCH.ABS minimum actual instantaneous clock high time; tCL.ABS minimum actual instantaneous clock time. transitions occur same access time valid data transitions. These parameters referenced specific voltage level which specifies when device output longer driving (tHZ), begins driving (tLZ) Input waveform timing referenced from input signal crossing VIL.DC level rising signal VIH.DC falling signal applied device under test. Figure Input waveform timing referenced from input signal crossing VIH.AC level rising signal VIL.AC falling signal applied device under test. Figure These parameters measured from command/address signal (CKE, RAS, CAS, ODT, BA0, etc.) transition edge respective clock signal crossing. spec values affected amount clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), setup hold relative clock signal crossing that latches command/address. That these parameters should whether clock jitter present not. tQHS, where: minimum absolute half period actual input clock; tQHS specification value under column. {The less half-pulse width distortion present, larger value larger valid data will be.} Examples: system provides 1315 into DDR2-667 SDRAM, DRAM provides minimum. system provides 1420 into DDR2-667 SDRAM, DRAM provides 1080 minimum. tQHS accounts for: pulse duration distortion on-chip clock circuits, which represents well actual input transferred output; worst case push-out transition followed worst case pull-in next transition, both which independent each other, data skew, output pattern effects, pchannel n-channel variation output drivers. tRPST point tRPRE begin point referenced specific voltage level specify when device output longer driving (tRPST), begins driving (tRPRE). Figure shows method calculate these points when device longer driving (tRPST), begins driving (tRPRE) measuring signal different voltages. actual voltage measurement points critical long calculation consistent. When device operated with input clock jitter, this parameter needs derated actual tJIT.PER input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tJIT.PER.MIN tJIT.PER.MAX then tRPRE.MIN(DERATED) tRPRE.MIN tJIT.PER.MIN tCK.AVG 2178 tRPRE.MAX(DERATED) tRPRE.MAX tJIT.PER.MAX tCK.AVG 2843 (Caution MIN/MAX usage!). When device operated with input clock jitter, this parameter needs derated actual tJIT.DUTY input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tJIT.DUTY.MIN tJIT.DUTY.MAX then tRPST.MIN(DERATED) tRPST.MIN tJIT.DUTY.MIN tCK.AVG tRPST.MAX(DERATED) tRPST.MAX tJIT.DUTY.MAX tCK.AVG 1592 (Caution MIN/MAX usage!). these parameters, DDR2 SDRAM device characterized verified support tnPARAM RU{tPARAM tCK.AVG}, which clock cycles, assuming input clock jitter specifications satisfied. example, device will support tnRP RU{tRP tCK.AVG}, which clock cycles, input clock jitter specifications met. This means: DDR2-667 5-5-5, which device will support tnRP RU{tRP tCK.AVG} i.e. long input clock jitter specifications met, Precharge command Active command valid even less than input clock jitter. tWTR lease clocks tCK) independent operation frequency.
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
FIGURE
Method calculating transitions endpoint
FIGURE
Differential input waveform timing
FIGURE
Differential input waveform timing
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HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
TABLE
DRAM Component Timing Parameter Speed Grade DDR2-533
Parameter Symbol DDR2-533 Min. output access time from command period high-level width minimum high pulse width low-level width Auto-Precharge write recovery precharge time Minimum time clocks remain after asynchronously drops input hold time (differential data strobe) Max. +500 0.55 0.55 +450 0.25
8)18)
Unit
Note1)2)3)4)5)
6)7)
tCCD tCKE tDAL tDELAY (base)
-500 0.45 0.45
0.35 -450 0.35 0.25 37.5 MIN. (tCL, tCH) tAC.MIN
input hold time (single ended data tDH1 (base) strobe) input pulse width (each input) output access time from input (high) pulse width (write cycle) DQS-DQ skew (for associated signals) Write command latching transition input setup time (differential data strobe)
tDIPW tDQSCK tDQSL,H tDQSQ tDQSS (base)
input setup time (single ended data tDS1 (base) strobe) falling edge hold time from (write cycle) Four Activate Window period Four Activate Window period Clock half period Data-out high-impedance time from Address control input hold time Address control input pulse width (each input) Address control input setup time low-impedance time from low-impedance from Mode register command cycle time drive mode output delay Data output hold time from
tDSH
falling edge setup time (write cycle) tDSS
tFAW tFAW (base) tIPW (base) tLZ(DQ) tLZ(DQS) tMRD tOIT
tAC.MAX
tAC.MIN
tAC.MAX tAC.MAX
-tQHS
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Parameter
Symbol
DDR2-533 Min. Max. 0.60 0.60
Unit
Note1)2)3)4)5)
6)7)
Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh Active/Auto-Refresh command period Precharge-All banks) command period Precharge-All banks) command period Read preamble Read postamble Active bank Active bank command period Active bank Active bank command period Internal Read Precharge command delay Write preamble Write postamble Write recovery time write without AutoPrecharge Internal Write Read command delay Exit power down valid command (other than Deselect) Exit active power-down mode Read command (slow exit, lower power) Exit precharge power-down valid command (other than Deselect) Exit Self-Refresh non-Read command Exit Self-Refresh Read command Write recovery time write with AutoPrecharge
tQHS tREFI tREFI tRFC tRPRE tRPST tRRD tRRD tRTP tWPRE tWPST tWTR tXARD tXARDS tXSNR tXSRD
127.5
14)15) 16)18)
1tCK 1tCK
0.40 0.25 0.40
14)18)
16)22)
tRFC
tWR/tCK
details notes relevant Qimonda component data sheet VDDQ ±0.1 Timing that specified illegal after such event, order guarantee proper operation, DRAM must powered down then restarted through specified initialization sequence before normal operation continue. Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended mode. input reference level (for timing reference point which cross. DQS, RDQS RDQS, input reference level crosspoint when differential strobe mode. Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT. each terms, already integer, round next highest integer. refers application clock period. refers parameter stored clock frequency allowed change during self-refresh mode precharge power-down mode. timing definition, refer Component data sheet. Consists data skew output pattern effects, p-channel n-channel variation output drivers well output Slew Rate mis-match between associated given cycle.
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
(tCL, tCH) refers smaller actual clock time actual clock high time provided device (i.e. this value greater than minimum specification limits tCH). tHZ, tRPST tLZ, tRPRE parameters referenced specific voltage level, which specify when device output longer driving (tHZ, tRPST), begins driving (tLZ, tRPRE). transitions occur same access time windows valid data transitions.These parameters verified design characterization, subject production test. Auto-Refresh command interval reduced when operating DDR2 DRAM temperature range between TCASE TCASE maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. tRRD timing parameter depends page size DRAM organization. Table "Ordering Information RoHS Compliant Products" Page maximum limit tWPST parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) degrades accordingly. Minimum tWTR clocks when operating DDR2-SDRAM frequencies User choose different active power-down modes additional power saving address A12. "standard active powerdown mode" (MR, "0") fast power-down exit timing tXARD used. "low active power-down mode" (MR, ="1") slow power-down exit timing tXARDS satisfied. must programmed fulfill minimum requirement timing parameter, where WRMIN[cycles] tWR(ns)/tCK(ns) rounded next integer value. tDAL (tRP/tCK). each terms, already integer, round next highest integer. refers application clock period. refers parameter stored MRS.
3.3.3
Electrical Characteristics
TABLE
Character. Operating Conditions DDR2-667
Symbol
Parameter Condition
Values Min. Max.
Unit
Note
Power Down Exit Latency units, 'tCK.AVG' 'nCK', introduced DDR2-667 DDR2-800. Unit 'tCK.AVG' represents actual tCK.AVG input clock
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
turn-on delay turn-on turn-on (Power-Down Modes) turn-off delay turn-off turn-off (Power-Down Modes) Power Down Mode Entry Latency
1)2) 1)3)
tAC.MIN tAC.MIN
tAC.MAX tAC.MAX
tAC.MIN tAC.MIN
tAC.MAX tAC.MAX
under operation. Unit 'nCK' represents clock cycle input clock, counting actual clock edges. Note that DDR2-400 DDR2-533, 'tCK' used both concepts. Example: [nCK] means; Power Down exit registered Active command registered even tCK.AVG+ tEPR.2PER(MIN). turn time when device leaves high impedance resistance begins turn turn time when resistance fully Both measured from tAOND, which interpreted differently speed bin. DDR2-667/800, tAOND clock cycles after clock edge that registered first HIGH counting actual input clock edges. turn time min. when device starts turn resistance. turn time when high impedance. Both measured from tAOFD. Both measured from tAOFD, which interpreted differently speed bin. DDR2-667/800,if tCK.AVG assumed, tAOFD= (0.5 after second trailing clock edge counting from clock edge that registered first counting actual input clock edge.
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
TABLE
Character. Operating Conditions DDR2-533
Symbol Parameter Condition Values Min. Max. Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
turn-on delay turn-on turn-on (Power-Down Modes) turn-off delay turn-off turn-off (Power-Down Modes) Power Down Mode Entry Latency Power Down Exit Latency
tAC.MIN tAC.MIN
tAC.MAX tAC.MAX
tAC.MIN tAC.MIN
tAC.MAX tAC.MAX
turn time when device leaves high impedance resistance begins turn turn time when resistance fully Both measured from tAOND, which interpreted differently speed bin. DDR2-400/533, tAOND after clock edge that registered first HIGH turn time min. when device starts turn resistance. turn time when high impedance. Both measured from tAOFD. Both measured from tAOFD, which interpreted differently speed bin. DDR2-400/533, tAOFD 12.5 after clock edge that registered first HIGH
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Specifications Conditions
List tables defining Specifications Conditions. Table "IDD Measurement Conditions" Page Table "Definitions IDD" Page Table "IDD Specification HYS72T512022EP-[3S/3.7]-B" Page
TABLE
Measurement Conditions
Parameter Symbol Note
1)2)3)4)5)
Operating Current IDD0 bank Active Precharge; tCK.MIN, tRC.MIN, tRAS tRAS.MIN, HIGH, HIGH between valid commands. Address control inputs SWITCHING, Databus inputs SWITCHING. Operating Current bank Active Read Precharge; IOUT tCK.MIN, tRC.MIN, tRAS tRAS.MIN, tRCD tRCD.MIN, CLMIN; HIGH, HIGH between valid commands. Address control inputs SWITCHING, Databus inputs SWITCHING.
IDD1
Precharge Standby Current IDD2N banks idle; HIGH; HIGH; tCK.MIN; Other control address inputs SWITCHING, Databus inputs SWITCHING. Precharge Power-Down Current Other control address inputs STABLE, Data inputs FLOATING. Precharge Quiet Standby Current banks idle; HIGH; HIGH; tCK.MIN; Other control address inputs STABLE, Data inputs FLOATING. Active Standby Current Burst Read: banks open; Continuous burst reads; CLMIN; tCK.MIN; tRAS tRAS.MAX, tRP.MIN; HIGH, HIGH between valid commands. Address inputs SWITCHING; Data inputs SWITCHING; IOUT
IDD2P IDD2Q
IDD3N
Active Power-Down Current IDD3P(0) banks open; tCK.MIN, LOW; Other control address inputs STABLE, Data inputs FLOATING. (Fast Power-down Exit); Active Power-Down Current IDD3P(1) banks open; tCK.MIN, LOW; Other control address inputs STABLE, Data inputs FLOATING. HIGH (Slow Power-down Exit); Operating Current Burst Read IDD4R banks open; Continuous burst reads; CLMIN; tCKMIN; tRAS tRASMAX; tRPMIN; HIGH, HIGH between valid commands; Address inputs SWITCHING; Data inputs SWITCHING; IOUT 0mA. Operating Current Burst Write banks open; Continuous burst writes; CLMIN; tCK.MIN; tRAS tRAS.MAX., tRP.MAX; HIGH, HIGH between valid commands. Address inputs SWITCHING; Data inputs SWITCHING; Burst Refresh Current tCK.MIN., Refresh command every tRFC tRFC.MIN interval, HIGH, HIGH between valid commands, Other control address inputs SWITCHING, Data inputs SWITCHING.
IDD4W
IDD5B
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Parameter Distributed Refresh Current tCK.MIN., Refresh command every tRFC tREFI interval, HIGH between valid commands, Other control address inputs SWITCHING, Data inputs SWITCHING.
Symbol Note
1)2)3)4)5)
IDD5D
Self-Refresh Current IDD6 external clock off, Other control address inputs FLOATING, Data inputs FLOATING. IDD6 current values guaranteed TCASE max. Bank Interleave Read Current IDD7 banks being interleaved minimum without violating tRRD using burst length Control address inputs STABLE during DESELECTS. Iout VDDQ specifications tested after device properly initialized parameter specified with disabled. Definitions Table rank modules: active current measurements other rank Precharge Power-Down Mode IDD2P
details notes relevant Qimonda component data sheet IDD1, IDD4R IDD7 current measurements defined with outputs disabled (IOUT mA). achieve this module level output buffers disabled using EMRS(1) (Extended Mode Register Command) setting HIGH.
TABLE
Definitions
Parameter STABLE FLOATING SWITCHING Description
VIL(ac).MAX, HIGH defined VIH(ac).MIN
Inputs stable HIGH level Inputs VREF VDDQ Inputs changing between HIGH every other clock (once cycles) address control signals, inputs changing between HIGH every other data transfer (once cycle) signals including mask strobes
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
TABLE
Specification HYS72T512022EP-[3S/3.7]-B
Product Type Organization HYS72T512022EP-3S-B Ranks HYS72T512022EP-3.7-B Ranks -3.7 2520 2610 2480 2300 1870 1040 2660 3420 3420 4320 4770
3)4) 3)5) 3)6) 3)6)
Units
Note1)
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P_0 (fast) IDD3P_1 (slow) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
2790 2970 1030 2940 2760 2220 1140 3120 3870 3870 4590 1060 4950
Module IDDis calculated basis component IDDand includes currents Registers PLL. disabled. IDD1, IDD4R, IDD7, defined with outputs disabled. other rank IDD2P Precharge Power-Down Current mode Both ranks same IDDcurrent mode Fast: MRS(12)=0 Slow: MRS(12)=1 IDD5D IDD6 values TCase
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Codes
This chapter lists hexadecimal byte values stored EEPROM products described this data sheet. stands serial presence detect. values with table module specific bytes which defined during production. List Code Tables Table "HYS72T512022EP-[3S/3.7]-B" Page
TABLE
HYS72T512022EP-[3S/3.7]-B
Product Type Organization HYS72T512022EP-3S-B GByte Ranks Label Code JEDEC Revision Byte# Description Programmed Bytes EEPROM Total number Bytes EEPROM Memory Type (DDR2) Number Addresses Number Column Addresses DIMM Rank Stacking Information Data Width used Interface Voltage Level PC2-5300P-555 Rev. HYS72T512022EP-3.7-B GByte Ranks PC2-4200P-444 Rev.
CLMAX (Byte [ns] SDRAM CLMAX (Byte [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate Type Primary SDRAM Width Error Checking SDRAM Width used Burst Length Supported Number Banks SDRAM Device Supported Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Product Type Organization
HYS72T512022EP-3S-B GByte Ranks
HYS72T512022EP-3.7-B GByte Ranks PC2-4200P-444 Rev.
Label Code JEDEC Revision Byte# Description Component Attributes
PC2-5300P-555 Rev.
CLMAX (Byte [ns] SDRAM CLMAX [ns] CLMAX (Byte [ns] SDRAM CLMAX [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density Rank
tAS.MIN tCS.MIN [ns] tAH.MIN tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
Relock Time
TCASE.MAX Delta T4R4W Delta
Psi(T-A) DRAM (DT0) (DT2N, UDIMM) (DT2Q, RDIMM) (DT2P) (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow)
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Product Type Organization
HYS72T512022EP-3S-B GByte Ranks
HYS72T512022EP-3.7-B GByte Ranks PC2-4200P-444 Rev.
Label Code JEDEC Revision Byte# Description (DT4R) T4R4W Sign (DT4R4W) (DT5B) (DT7) Psi(ca) Psi(ca) TPLL (DTPLL) TREG (DTREG) Toggle Rate Revision Checksum Bytes 0-62 Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Module Manufacturer Location Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char
PC2-5300P-555 Rev.
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Product Type Organization
HYS72T512022EP-3S-B GByte Ranks
HYS72T512022EP-3.7-B GByte Ranks PC2-4200P-444 Rev.
Label Code JEDEC Revision Byte# Description Product Type, Char Product Type, Char Product Type, Char Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank customer
PC2-5300P-555 Rev.
used
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Package Outlines
FIGURE
Package Outline Card L-DIM-240-70
This chapter contains package outlines products.
Notes Drawing according 8015 Dimensions General tolerances 0.15
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Product Type Nomenclature
nomenclature uses simple coding combined with some propriatory coding. Table provides examples module component product type number well field number. detailed field description together with possible values coding explanation listed modules Table components Table
TABLE
Nomenclature Fields Examples
Example Field Number Micro-DIMM DDR2 DRAM 64/128
512/1G
TABLE
DDR2 DIMM Nomenclature
Field Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density [Mbit]; Module Density1) Values Card Generation Number Module Ranks Product Variations Package, Lead-Free Status Module Type Coding Constant Non-ECC DDR2 MByte MByte GByte GByte GByte Look table Look table Look table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Field
Description Speed Grade
Values -2.5F -2.5 -3.7
Coding PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
Revision
Multiplying "Memory Density I/O" with "Module Data Width" dividing Non-ECC modules gives overall module memory density MBytes listed column "Coding".
TABLE
DDR2 DRAM Nomenclature
Field Description Qimonda Component Prefix Interface Voltage DRAM Technology Component Density [Mbit] Values Number I/Os Product Variations Revision Package, Lead-Free Status Speed Grade -25F -2.5 -3.7 Coding Constant SSTL_18 DDR2 Mbit Mbit Gbit Gbit Look table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP-[3S/3.7]-B Registerd DDR2 SDRAM Module
Table Contents
3.3.1 3.3.2 3.3.3 Overview Features Description Configuration Electrical Characteristics Absolute Maximum Ratings Operating Conditions Timing Characteristics Speed Grade Definitions Component Timing Parameters Electrical Characteristics Specifications Conditions
Codes Package Outlines Product Type Nomenclature Table Contents
Rev. 1.0, 2007-03 03292007-RHOW-C5L6
Edition 2007-03 Published Qimonda Gustav-Heinemann-Ring D-81739 Germany Qimonda 2007. Rights Reserved. Legal Disclaimer information given this Internet Data Sheet shall event regarded guarantee conditions characteristics ("Beschaffenheitsgarantie"). With respect examples hints given herein, typical values stated herein and/or information regarding application device, Qimonda hereby disclaims warranties liabilities kind, including without limitation warranties non-infringement intellectual property rights third party. Information further information technology, delivery terms conditions prices please contact your nearest Qimonda Office. Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Qimonda Office. Qimonda Components only used life-support devices systems with express written approval Qimonda, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered. www.qimonda.com
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