240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHs Comp
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HYS72T32000HP-[3S/3.7]-A HYS72T64001HP-[3S/3.7]-A HYS72T64020HP-[3S/3.7]-A
240-Pin Registered DDR2 SDRAM Modules DDR2 SDRAM RDIMM SDRAM RoHs Compilant
Rev. 1.01
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
HYS72T32000HP-[3S/3.7]-A, HYS72T64001HP-[3S/3.7]-A, HYS72T64020HP-[3S/3.7]-A Revision History: 2006-09, Rev. 1.01 Page Subjects (major changes since last revision) Qimonda update Adapted internet edition Modified Timing Parameters
Previous Revision: 2006-03, Rev.
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qag_techdoc_rev400 2006-07-21 03292006-ZZHP-PR83
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
Overview
This chapter gives overview 240-pin Registered DDR2 SDRAM Modules with parity product family describes main characteristics.
Features
Programmable Latencies Burst Length Burst Type Auto Refresh (CBR) Self Refresh Average Refresh Period lower than between Programmable self refresh rate EMRS2 setting inputs outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) On-Die Termination (ODT) Serial Presence Detect with E2PROM Based standard reference layouts Cards "F", RDIMM with parity Dimensions (nominal): 30.00 high, 133.35 wide RoHS compliant products1)
240-pin PC2-5300 PC2-4200 DDR2 SDRAM memory modules. rank rank module organization chip organization 256M, MByte modules built with 256-Mbit DDR2 SDRAMs P-TFBGA-60 chipsize packages. Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with single power supply speed grades faster than DDR2-400 comply with DDR2-400 timing specifications well. Registered DIMM with Parity address control
TABLE
Performance table
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Precharge Time Min. Active Time Min. Cycle Time PC2-5300 5-5-5 Unit
fCK5 fCK4 fCK3 tRCD tRAS
RoHS Compliant Product: Restriction certain hazardous substances (RoHS) electrical electronic equipment defined directive 2002/95/EC issued European Parliament Council January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls polybrominated biphenyl ethers.
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TABLE
Performance table -3.7
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Precharge Time Min. Active Time Min. Cycle Time -3.7 PC2-4200 4-4-4 Unit
fCK5 fCK4 fCK3 tRCD tRAS
TABLE
Performance table
Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Precharge Time Min. Active Time Min. Cycle Time PC2-3200 3-3-3 Units
fCK5 fCK4 fCK3 tRCD tRAS
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Description
devices clock distribution. This reduces capacitive loading system bus, adds cycle SDRAM timing. Decoupling capacitors mounted board. DIMMs feature serial presence detect based serial device using 2-pin protocol. first bytes programmed with configuration data second bytes available customer.
QIMONDA HYS72T[32/64]xxxHP-[3S/3.7]-A module family Registered DIMM (RDIMM with parity) with 30.00 height based DDR2 technology. DIMMs available modules (256 Mbyte) (512 MByte) organization density, intended mounting into 240-Pin connector sockets. memory array designed with 256-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. control address signals re-driven DIMM using register
TABLE
Ordering Information RoHS Compliant Products
Product Type1) PC2-5300 HYS72T32000HP-3S-A HYS72T64001HP-3S-A HYS72T64020HP-3S-A PC2-4200 HYS72T32000HP-3.7-A HYS72T64001HP-3.7-A HYS72T64020HP-3.7-A 256MB PC2-4200P-444-12-F0 512MB PC2-4200P-444-12-H0 512MB PC2-4200P-444-12-G0 Rank, Rank, Rank, Mbit Mbit Mbit 256MB PC2-5300P-555-12-F0 512MB PC2-5300P-555-12-H0 512MB PC2-5300P-555-12-G0 Rank, Rank, Rank, Mbit Mbit Mbit Compliance Code2) Description SDRAM Technology
Product Types with place code, designating silicon revision. Example: HYS72T64020HP-3.7-A, indicating Rev. dies used DDR2 SDRAM components. QIMONDA DDR2 module component nomenclature Chapter this data sheet. Compliance Code printed module label describes speed grade, example "PC2-4200P-444-12-G0", where 4200P means Very Profile Registered DIMM modules with 4.26 GB/sec Module Bandwidth "444-12" means Column Address Strobe (CAS) latency Column Delay (RCD) latency Precharge (RP) latency using latest JEDEC Revision produced Card
TABLE
Address Format
DIMM Density Module Organization Memory Ranks ECC/ Non-ECC SDRAMs row/bank/columns bits 13/2/10 13/2/11 13/2/10 Card
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TABLE
Components Modules
Product Type1) HYS72T32000HP HYS72T64001HP HYS72T64020HP DRAM Components1) HYB18T256800AF HYB18T256400AF HYB18T256800AF DRAM Density Mbit Mbit 256Mbit DRAM Organization Note2)
Green Product detailed description available functions DRAM components these modules component data sheet.
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Configuration
Configuration
Table respectively. numbering depicted Figure
This chapter contains configuration block diagrams.
configuration Registered DDR2 SDRAM DIMM listed function Table (240 pins). abbreviations used columns Buffer Type explained Table
TABLE
Configuration RDIMM
Ball Clock Signals CKE0 CKE1 Control Signals Address Signals SSTL SSTL SSTL SSTL Bank Address Connected Bank Address RESET SSTL SSTL SSTL SSTL SSTL CMOS Register Reset Chip Select Rank Note: 2-Ranks module Connected Note: 1-Rank module Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) SSTL SSTL SSTL SSTL Clock Enables Note: 2-Ranks module Connected Note: 1-Rank module Clock Signal CK0, Complementary Clock Signal Name Type Buffer Type Function
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Ball
Name
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Address 12:0, Address Signal 10/AutoPrecharge
Address Signal Connected Address Signal Connected Address Signal Connected
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Ball Data Signals
Name
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38
Data 63:0
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Ball Check Bits
Name DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data 63:0
Check Bits
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Ball Data Strobe
Name
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 DQS9 DQS9 DQS10 DQS10 DQS11 DQS11 DQS12 DQS12 DQS13 DQS13 DQS14 DQS14 DQS15 DQS15 DQS16 DQS16 DQS17 DQS17
Data Strobes 17:0
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Ball Data Mask EEPROM Parity Power Supplies 170, 175,, 181, 191, 172, 178, 184,, 187, 189,
Name
Type
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS CMOS CMOS CMOS CMOS CMOS
Function
ERR_OUT PAR_IN
Data Masks Note: based module
Serial Clock Serial Data Serial Address Select
Parity bits
VREF VDDSPD VDDQ
Reference Voltage EEPROM Power Supply Driver Power Supply
Power Supply
100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234,
Ground Plane
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Ball Other Pins
Name
Type
Buffer Type
Function
102, 137, 138, 173, 220, ODT0 ODT1
connected
SSTL SSTL
On-Die Termination Control Note: 2-Ranks module Note: 1-Rank modules
TABLE
Abbreviations Buffer Type
Abbreviation SSTL CMOS Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. corresponding operational states, active tristate, allows multiple devices share wire-OR.
TABLE
Abbreviations Type
Abbreviation Description Standard input-only pin. Digital levels. Output. Digital levels. bidirectional input/output signal. Input. Analog levels. Power Ground Usable Connected
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FIGURE
Configuration RDIMM (240 pins)
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Electrical Characteristics
Absolute Maximum Ratings
TABLE
Absolute Maximum Ratings
This chapter lists electrical characteristics.
Caution needed exceed absolute maximum ratings DRAM device listed Table time.
Symbol
Parameter
Rating Min. Max. +2.3 +2.3 +2.3 +2.3
Unit
Note
Storage Temperature +100 When VDDQ VDDL less than VREF equal less than
Storage Temperature case surface temperature center/top side DRAM.
VDDQ VDDL VIN, VOUT TSTG
Voltage relative Voltage VDDQ relative Voltage VDDL relative Voltage relative
-1.0 -0.5 -0.5 -0.5
1)2) 1)2) 1)2)
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
TABLE
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max.
1)2)3)4)
Unit
Note
TOPER
Operating Temperature
Operating Temperature case surface temperature center side DRAM. operating temperature range temperatures where DRAM specification will supported. During operation, DRAM case temperature must maintained between under other specification parameters. Above Auto-Refresh command interval reduced tREFI= When operating this product TCASE temperature range, High Temperature Self Refresh enabled setting EMR(2) "1". When High Temperature Self Refresh enabled there increase IDD6 approximately
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Operating Conditions
TABLE
Operating Conditions
This chapter describes characteristics.
Parameter
Symbol
Values Min. Max. +100 +105
Unit
Note
Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating storage) Operating Humidity (relative)
TOPR TCASE TSTG
PBar
1)2)3)4)
HOPR
DRAM Component Case Temperature surface temperature center side DRAMs. Within DRAM Component Case Temperature Range DRAM specifications will supported Above DRAM Case Temperature Auto-Refresh command interval reduced tREFI When operating this product TCASE temperature range, High Temperature Self Refresh enabled setting EMR(2) "1". When High Temperature Self Refresh enabled there increase IDD6 approximately 50%. 3000
TABLE
Supply Voltage Levels Operating Conditions
Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage Supply Voltage Input Logic High Input Logic Typ. VDDQ Max. 0.51 VDDQ
Unit
Note
Output Leakage Current Under conditions, VDDQ must less than equal Peak peak noise VREF exceed VREF (DC).VREF also expected track noise VDDQ. Input voltage connector under test VDDQ other pins Current
VDDQ VREF VDDSPD VIH(DC) (DC)
0.49 VDDQ
VREF 0.125
0.30
VDDQ VREF 0.125
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Characteristics
This chapter describes characteristics.
3.3.1
Speed Grades Definitions
TABLE
Speed Grade Definition Speed Bins DDR2-667D
This chapter contains Speed Grade Definition tables.
Speed Grade Sort Name CAS-RCD-RP latencies Parameter Clock Frequency Active Time Cycle Time RAS-CAS-Delay Precharge Time Symbol
DDR2-667D 5-5-5 Min. 3.75 Max. 70000
Unit
Notes
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tRAS tRCD
Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended mode.Timings further guaranteed normal drive strength (EMRS(1) CK/CK input reference level (for timing reference CK/CK) point which cross. DQS, RDQS RDQS, input reference level crosspoint when differential strobe mode Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT. tRAS.MAX calculated from maximum amount time DDR2 device operate without refresh command which equal tREFI.
TABLE
Speed Grade Definition Speed Bins DDR2-533C
Speed Grade Sort Name CAS-RCD-RP latencies Parameter Clock Frequency Active Time Cycle Time Symbol DDR2-533C -3.7 4-4-4 Min. 3.75 3.75 Max. 70000 Unit Note
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4)
tRAS
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Speed Grade Sort Name CAS-RCD-RP latencies Parameter RAS-CAS-Delay Precharge Time Symbol
DDR2-533C -3.7 4-4-4 Min. Max.
Unit
Note
1)2)3)4) 1)2)3)4)
tRCD
Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended mode.Timings further guaranteed normal drive strength (EMRS(1) CK/CK input reference level (for timing reference CK/CK) point which cross. DQS, RDQS RDQS, input reference level crosspoint when differential strobe mode. Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT. tRAS.MAX calculated from maximum amount time DDR2 device operate without refresh command which equal tREFI.
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3.3.2
Timing Parameters
TABLE
Timing Parameter Speed Grade DDR2-667
This chapter contains Timing Parameters.
Parameter
Symbol
DDR2-667 Min. Max. +450 +400 0.52 0.52 8000
Unit
Note1)2)3)4)5)6)7)
output access time from tDQSCK Average clock high pulse width tCH.AVG Average clock pulse width tCL.AVG Average clock period tCK.AVG tDS.BASE input setup time input hold time tDH.BASE Control address input pulse width each input tIPW input pulse width each input tDIPW Data-out high-impedance time from DQS/DQS low-impedance time from tLZ.DQS impedance time from CK/CK tLZ.DQ DQS-DQ skew associated signals tDQSQ half pulse width
output access time from hold skew factor DQ/DQS output hold time from Write command associated clock edges
-450 -400 0.48 0.48 3000 0.35
10)11) 10)11)
tCK.AVG tCK.AVG
12)13)14) 1)1)15)
tCK.AVG tCK.AVG
1)16) 1)1) 1)1)
tAC.MIN tAC.MIN
Min(tCH.ABS, tCL.ABS)
tAC.MAX tAC.MAX tAC.MAX
0.25 70000
tQHS
tQHS
RL-1 0.25 0.35 0.35 0.35
latching rising transition associated clock tDQSS edges input high pulse width input pulse width falling edge setup time falling edge hold time from Write postamble Write preamble Address control input setup time Address control input hold time Read preamble Read postamble Active precharge command Active active command period page size products Active active command period page size products
tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG
tDQSH tDQSL tDSS tDSH tWPST tWPRE tLS.BASE tLH.BASE tRPRE tRPST tRAS tRRD tRRD
22)23) 1)24) 25)26) 1)27)
tCK.AVG tCK.AVG
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Parameter
Symbol
DDR2-667 Min. Max.
Unit
Note1)2)3)4)5)6)7)
Four Activate Window page size products tFAW Four Activate Window page size products tFAW
37.5 tnRP
tCCD Write recovery time Auto-Precharge write recovery precharge time tDAL Internal write read command delay tWTR Internal Read Precharge command delay tRTP Exit self-refresh non-read command tXSNR Exit self-refresh read command tXSRD Exit precharge power-down valid
command delay command (other than Deselect) Exit power down read command Exit active power-down mode read command (slow exit, lower power) minimum pulse width high pulse width) turn-on delay turn-on turn-on (Power down mode) turn-off delay turn-off turn-off (Power down mode) power down entry latency power down exit latency Mode register command cycle time command update delay drive mode output delay Minimum time clocks remain after asynchronously drops
29)30) 1)31)
tRFC
tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tMRD tMOD tOIT tDELAY
tAC.MIN tAC.MIN
tAC.MAX tCK.AVG tAC.MAX
1)33)
tAC.MIN tAC.MIN
tAC.MAX tCK.AVG tAC.MAX
34)35)
.AVG
details notes relevant QIMONDA component data sheet VDDQ 0.1V; notes 1)1)1)1) Timing that specified illegal after such event, order guarantee proper operation, DRAM must powered down then restarted through specified initialization sequence before normal operation continue. Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended mode. input reference level (for timing reference point which cross. DQS, RDQS RDQS, input reference level crosspoint when differential strobe mode. Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT.
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units, `tCK.AVG` `nCK`, introduced DDR2-667 DDR2-800. Unit `tCK.AVG` represents actual tCK.AVG input clock under operation. Unit `nCK` represents clock cycle input clock, counting actual clock edges. Note that DDR2-400 DDR2-533, `tCK` used both concepts. Example: [nCK] means; Power Down exit registered Active command registered even tCK.AVG tERR.2PER(Min). When device operated with input clock jitter, this parameter needs derated actual tERR(6-10per) input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tERR(6-10PER).MIN tERR(6- 10PER).MAX then tDQSCK.MIN(DERATED) tDQSCK.MIN tERR(6-10PER).MAX tDQSCK.MAX(DERATED) tDQSCK.MAX tERR(6-10PER).MIN Similarly, tLZ.DQ DDR2-667 derates tLZ.DQ.MIN(DERATED) 1193 tLZ.DQ.MAX(DERATED) (Caution MIN/MAX usage!) Input clock jitter spec parameter. These parameters referred 'input clock jitter spec parameters' these parameters apply DDR2-667 DDR2-800 only. jitter specified random jitter meeting Gaussian distribution. These parameters specified their average values, however understood that relationship between average timing absolute instantaneous timing holds times (min. SPEC values used calculations). Input waveform timing with differential data strobe enabled MR[bit10] referenced from input signal crossing VIH.AC level differential data strobe crosspoint rising signal, from input signal crossing VIL.AC level differential data strobe crosspoint falling signal applied device under test. DQS, signals must monotonic between Vil(DC)MAX Vih(DC)MIN. Figure violated, data corruption occur data must re-written with valid data before valid READ executed. These parameters measured from data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge respective data strobe signal ((L/U/R)DQS DQS) crossing. Input waveform timing with differential data strobe enabled MR[bit10] referenced from differential data strobe crosspoint input signal crossing VIH.DC level falling signal from differential data strobe crosspoint input signal crossing VIL.DC level rising signal applied device under test. DQS, signals must monotonic between VIL.DC.MAX VIH.DC.MIN. Figure transitions occur same access time valid data transitions. These parameters referenced specific voltage level which specifies when device output longer driving (tHZ), begins driving (tLZ) tDQSQ: Consists data skew output pattern effects, p-channel n-channel variation output drivers well output slew rate mismatch between associated given cycle. minimum absolute half period actual input clock. input parameter input specification parameter. used conjunction with tQHS derive DRAM output timing tQH. value used calculation determined following equation; (tCH.ABS, tCL.ABS), where, tCH.ABS minimum actual instantaneous clock high time; tCL.ABS minimum actual instantaneous clock time. tQHS accounts for: pulse duration distortion on-chip clock circuits, which represents well actual input transferred output; worst case push-out transition followed worst case pull-in next transition, both which independent each other, data skew, output pattern effects, pchannel n-channel variation output drivers. tQHS, where: minimum absolute half period actual input clock; tQHS specification value under column. {The less half-pulse width distortion present, larger value larger valid data will be.} Examples: system provides 1315 into DDR2-667 SDRAM, DRAM provides minimum. system provides 1420 into DDR2-667 SDRAM, DRAM provides 1080 minimum. These parameters measured from data strobe signal ((L/U/R)DQS DQS) crossing respective clock signal crossing. spec values affected amount clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), these relative clock signal crossing. That these parameters should whether clock jitter present not. Input waveform timing referenced from input signal crossing VIH.AC level rising signal VIL.AC falling signal applied device under test. Figure These parameters measured from command/address signal (CKE, RAS, CAS, ODT, BA0, etc.) transition edge respective clock signal crossing. spec values affected amount clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), setup hold relative clock signal crossing that latches command/address. That these parameters should whether clock jitter present not. Input waveform timing referenced from input signal crossing VIL.DC level rising signal VIH.DC falling signal applied device under test. Figure tRPST point tRPRE begin point referenced specific voltage level specify when device output longer driving (tRPST), begins driving (tRPRE). Figure shows method calculate these points when device longer driving (tRPST), begins driving (tRPRE) measuring signal different voltages. actual voltage measurement points critical long calculation consistent. When device operated with input clock jitter, this parameter needs derated actual tJIT.PER input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tJIT.PER.MIN tJIT.PER.MAX then tRPRE.MIN(DERATED) tRPRE.MIN tJIT.PER.MIN tCK.AVG 2178 tRPRE.MAX(DERATED) tRPRE.MAX tJIT.PER.MAX tCK.AVG 2843 (Caution MIN/MAX usage!).
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When device operated with input clock jitter, this parameter needs derated actual tJIT.DUTY input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tJIT.DUTY.MIN tJIT.DUTY.MAX then tRPST.MIN(DERATED) tRPST.MIN tJIT.DUTY.MIN tCK.AVG tRPST.MAX(DERATED) tRPST.MAX tJIT.DUTY.MAX tCK.AVG 1592 (Caution MIN/MAX usage!). these parameters, DDR2 SDRAM device characterized verified support tnPARAM RU{tPARAM tCK.AVG}, which clock cycles, assuming input clock jitter specifications satisfied. example, device will support tnRP RU{tRP tCK.AVG}, which clock cycles, input clock jitter specifications met. This means: DDR2-667 5-5-5, which device will support tnRP RU{tRP tCK.AVG} i.e. long input clock jitter specifications met, Precharge command Active command valid even less than input clock jitter. RU{tRP(ns) tCK(ns)}, where stands round refers parameter stored MRS. tRP, result division already integer, round next highest integer. refers application clock period. Example: DDR2-533 3.75 with programmed clocks. tDAL 3.75 clocks clocks clocks. tDAL.nCK [nCK] tnRP.nCK RU{tRP [ps] tCK.AVG[ps] where value programmed EMR. tWTR lease clocks tCK) independent operation frequency. tCKE.MIN clocks means must registered three consecutive positive clock edges. must remain valid input level entire time takes achieve clocks registration. Thus, after transition, transition from valid level during time period tIH. turn time when device leaves high impedance resistance begins turn turn time when resistance fully Both measured from tAOND. turn time when device starts turn resistance. turn time when high impedance. Both measured from tAOFD. When device operated with input clock jitter, this parameter needs derated {-tJIT.DUTY.MAX tERR(6-10PER).MAX} {-tJIT.DUTY.MIN tERR(6-10PER).MIN actual input clock. (output deratings relative SDRAM input clock.) example, measured jitter into DDR2-667 SDRAM tERR(6-10PER).MIN tERR(6- 10PER).MAX tJIT.DUTY.MIN tJIT.DUTY.MAX then tAOF.MIN(DERATED) tAOF.MIN tJIT.DUTY.MAX tERR(6-10PER).MAX} tAOF.MAX(DERATED) tAOF.MAX tJIT.DUTY.MIN tERR(6-10PER).MIN} 1050 {106 1428 (Caution MIN/MAX usage!)
FIGURE
Method calculating transitions endpoint
tRPST point
tRPRE begin point
tHZ,tRPST point 2*T1-T2
tLZ,tRPRE begin point 2*T1-T2
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FIGURE
Differential input waveform timing
VDDQ VIH(ac) VIH(dc)
VREF(dc)
VIL(dc) VIL(ac)
FIGURE
Differential input waveform timing
VDDQ VIH(ac) VIH(dc) VREF(dc) VIL(dc) VIL(ac)
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TABLE
Timing Parameter Speed Grade DDR2-533
Parameter Symbol DDR2-533 Min. output access time from command period high-level width minimum high pulse width low-level width Auto-Precharge write recovery precharge time Minimum time clocks remain after asynchronously drops input hold time (differential data strobe) Max. +500 0.55 0.55 +450 0.25 Unit Note1)2)3)4)5)
6)7)
tCCD tCKE tDAL tDELAY tDH(base)
-500 0.45 0.45
8)21)
0.35 -450 0.35 0.25 37.5 MIN. (tCL, tCH) tAC.MIN
input hold time (single ended data tDH1(base) strobe) input pulse width (each input) output access time from input (high) pulse width (write cycle) DQS-DQ skew (for associated signals) Write command latching transition input setup time (differential data strobe)
tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS(base)
input setup time (single ended data tDS1(base) strobe) falling edge hold time from (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from Address control input hold time Address control input pulse width (each input) Address control input setup time low-impedance time from low-impedance from Mode register command cycle time drive mode output delay Data output hold time from
tDSH
falling edge setup time (write cycle) tDSS
tFAW tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT
tAC.MAX
tAC.MIN
tAC.MAX tAC.MAX
-tQHS
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Parameter
Symbol
DDR2-533 Min. Max. 0.60 0.60
Unit
Note1)2)3)4)5)
6)7)
Data hold skew factor Average periodic refresh Interval Auto-Refresh Active/Auto-Refresh command period Auto-Refresh Active/Auto-Refresh command period Auto-Refresh Active/Auto-Refresh command period Auto-Refresh Active/Auto-Refresh command period Precharge-All banks) command period Precharge-All banks) command period Read preamble Read postamble Active bank Active bank command period Internal Read Precharge command delay Write preamble Write postamble Write recovery time write without AutoPrecharge Write recovery time write with AutoPrecharge Internal Write Read command delay Exit power down valid command (other than Deselect) Exit active power-down mode Read command (slow exit, lower power) Exit precharge power-down valid command (other than Deselect) Exit Self-Refresh non-Read command Exit Self-Refresh Read command
tQHS tREFI tRFC tRFC tRFC tRFC tRPRE tRPST tRRD tRTP tWPRE tWPST
127.5 197.5
14)15) 16)21)
1tCK
1tCK 0.40 0.25 0.40
14)21) 16)23)
tWR/tCK
tWTR tXARD tXARDS tXSNR tXSRD
tRFC
details notes relevant QIMONDA component data sheet VDDQ ±0.1 notes 5)6)7)8) Timing that specified illegal after such event, order guarantee proper operation, DRAM must powered down then restarted through specified initialization sequence before normal operation continue. Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended mode. input reference level (for timing reference point which cross. DQS, RDQS/ RDQS, input reference level crosspoint when differential strobe mode. Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT.
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each terms, already integer, round next highest integer. refers application clock period. refers parameter stored clock frequency allowed change during self-refresh mode precharge power-down mode. timing definition, refer Component data sheet. Consists data skew output pattern effects, p-channel n-channel variation output drivers well output Slew Rate mis-match between associated given cycle. (tCL, tCH) refers smaller actual clock time actual clock high time provided device (i.e. this value greater than minimum specification limits tCH). tHZ, tRPST tLZ, tRPRE parameters referenced specific voltage level, which specify when device output longer driving (tHZ, tRPST), begins driving (tLZ, tRPRE). transitions occur same access time windows valid data transitions.These parameters verified design characterization, subject production test. Auto-Refresh command interval reduced when operating DDR2 DRAM temperature range between TCASE TCASE maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. tRRD timing parameter depends page size DRAM organization. See. maximum limit tWPST parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) degrades accordingly. must programmed fulfill minimum requirement timing parameter, where WRMIN[cycles] tWR(ns)/tCK(ns) rounded next integer value. tDAL (tRP/tCK). each terms, already integer, round next highest integer. refers application clock period. refers parameter stored MRS. Minimum tWTR clocks when operating DDR2-SDRAM frequencies User choose different active power-down modes additional power saving address A12. "standard active powerdown mode" (MR, "0") fast power-down exit timing tXARD used. "low active power-down mode" (MR, ="1") slow power-down exit timing tXARDS satisfied.
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TABLE
Timing Parameter Speed Grade DDR2-400
Parameter Symbol DDR2-400 Min. output access time from command period high-level width minimum high pulse width low-level width Auto-Precharge write recovery precharge time Minimum time clocks remain after asynchronously drops input hold time (differential data strobe) Max. +600 0.55 0.55 +500 0.25 Unit Note1)2)3)4)5)
6)7)
tCCD tCKE tDAL tDELAY tDH(base)
-600 0.45 0.45
8)25)
0.35 -500 0.35 0.25 37.5 MIN. (tCL, tCH) tAC.MIN
input hold time (single ended data tDH1(base) strobe) input pulse width (each input) output access time from input (high) pulse width (write cycle) DQS-DQ skew (for associated signals) input setup time (differential data strobe) input setup time (single ended data strobe) falling edge hold time from (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from Address control input hold time Address control input pulse width (each input) Address control input setup time low-impedance time from low-impedance from Mode register command cycle time drive mode output delay Data output hold time from
tDIPW tDQSCK tDQSL,H tDQSQ
Write command latching transition tDQSS
tDS(base) tDS1(base) tDSH
falling edge setup time (write cycle) tDSS
tFAW tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT
tAC.MAX
tAC.MIN
tAC.MAX tAC.MAX
-tQHS
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Parameter
Symbol
DDR2-400 Min. Max. 0.60 0.60
Unit
Note1)2)3)4)5)
6)7)
Data hold skew factor Average periodic refresh Interval Auto-Refresh Active/Auto-Refresh command period Auto-Refresh Active/Auto-Refresh command period Auto-Refresh Active/Auto-Refresh command period Auto-Refresh Active/Auto-Refresh command period Precharge-All banks) command period Precharge-All banks) command period Read preamble Read postamble Active bank Active bank command period Internal Read Precharge command delay Write preamble Write postamble Write recovery time write without AutoPrecharge Write recovery time write with AutoPrecharge Internal Write Read command delay Exit power down valid command (other than Deselect) Exit active power-down mode Read command (slow exit, lower power) Exit precharge power-down valid command (other than Deselect) Exit Self-Refresh non-Read command Exit Self-Refresh Read command
tQHS tREFI tRFC tRFC tRFC tRFC tRPRE tRPST tRRD tRTP tWPRE tWPST
127.5 197.5
14)15) 16)21)
1tCK 1tCK
0.40 0.25 0.40
14)21) 16)23)
tWR/tCK
tWTR tXARD tXARDS tXSNR tXSRD
tRFC
details notes relevant QIMONDA component data sheet VDDQ ±0.1 notes 5)6)7)8) Timing that specified illegal after such event, order guarantee proper operation, DRAM must powered down then restarted through specified initialization sequence before normal operation continue. Timings guaranteed with CK/CK differential Slew Rate V/ns. signals timings guaranteed with differential Slew Rate V/ns differential strobe mode Slew Rate V/ns single ended mode. input reference level (for timing reference point which cross. DQS, RDQS/ RDQS, input reference level crosspoint when differential strobe mode. Inputs recognized valid until VREF stabilizes. During period before VREF stabilizes, VDDQ recognized low. output timing reference voltage level VTT.
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
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each terms, already integer, round next highest integer. refers application clock period. refers parameter stored clock frequency allowed change during self-refresh mode precharge power-down mode. timing definition, refer Component data sheet. Consists data skew output pattern effects, p-channel n-channel variation output drivers well output Slew Rate mis-match between associated given cycle. (tCL, tCH) refers smaller actual clock time actual clock high time provided device (i.e. this value greater than minimum specification limits tCH). tHZ, tRPST tLZ, tRPRE parameters referenced specific voltage level, which specify when device output longer driving (tHZ, tRPST), begins driving (tLZ, tRPRE). transitions occur same access time windows valid data transitions.These parameters verified design characterization, subject production test. Auto-Refresh command interval reduced when operating DDR2 DRAM temperature range between TCASE TCASE maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. maximum eight Auto-Refresh commands posted given DDR2 SDRAM device. tRRD timing parameter depends page size DRAM organization. maximum limit tWPST parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) degrades accordingly. must programmed fulfill minimum requirement timing parameter, where WRMIN[cycles] tWR(ns)/tCK(ns) rounded next integer value. tDAL (tRP/tCK). each terms, already integer, round next highest integer. refers application clock period. refers parameter stored MRS. Minimum tWTR clocks when operating DDR2-SDRAM frequencies User choose different active power-down modes additional power saving address A12. "standard active powerdown mode" (MR, "0") fast power-down exit timing tXARD used. "low active power-down mode" (MR, ="1") slow power-down exit timing tXARDS satisfied.
3.3.3
Electrical Characteristics
TABLE
Characteristics Operating Conditions DDR2-667
This chapter contains electrical characteristics tables.
Symbol
Parameter Condition
Values Min. Max.
Unit
Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
turn-on delay turn-on turn-on (Power-Down Modes) turn-off delay turn-off turn-off (Power-Down Modes) Power Down Mode Entry Latency Power Down Exit Latency
tAC.MIN tAC.MIN
tAC.MAX tAC.MAX
tAC.MIN tAC.MIN
tAC.MAX tAC.MAX
turn time min. when device leaves high impedance resistance begins turn turn time when resistance fully Both measure from tAOND. turn time min. when device starts turn resistance. turn time when high impedance. Both measured from tAOFD.
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TABLE
Characteristics Operating Conditions DDR2-533 DDR2-400
Symbol Parameter Condition Values Min. Max. Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
turn-on delay turn-on turn-on (Power-Down Modes) turn-off delay turn-off turn-off (Power-Down Modes) Power Down Mode Entry Latency Power Down Exit Latency
tAC.MIN tAC.MIN
tAC.MAX tAC.MAX
tAC.MIN tAC.MIN
tAC.MAX tAC.MAX
turn time min. when device leaves high impedance resistance begins turn turn time when resistance fully Both measure from tAOND. turn time min. when device starts turn resistance. turn time when high impedance. Both measured from tAOFD.
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Currents Specifications Conditions
TABLE
Measurement Conditions
This chapter describes Specifications Conditions.
Parameter
Symbol
Note1)2)
3)4)5)6)
Operating Current IDD0 bank Active Precharge; tCK.MIN, tRC.MIN, tRAS tRAS.MIN, HIGH, HIGH between valid commands. Address control inputs SWITCHING, Databus inputs SWITCHING. Operating Current bank Active Read Precharge; IOUT tCK.MIN, tRC.MIN, tRAS tRAS.MIN, tRCD tRCD.MIN, CLMIN; HIGH, HIGH between valid commands. Address control inputs SWITCHING, Databus inputs SWITCHING.
IDD1
Precharge Standby Current IDD2N banks idle; HIGH; HIGH; tCK.MIN; Other control address inputs SWITCHING, Data inputs SWITCHING. Precharge Power-Down Current Other control address inputs STABLE, Data inputs FLOATING. Precharge Quiet Standby Current banks idle; HIGH; HIGH; tCK.MIN; Other control address inputs STABLE, Data inputs FLOATING. Active Standby Current Burst Read: banks open; Continuous burst reads; CLMIN; tCK.MIN; tRAS tRAS.MAX, tRP.MIN; HIGH, HIGH between valid commands. Address inputs SWITCHING; Data inputs SWITCHING; IOUT
IDD2P IDD2Q
IDD3N
Active Power-Down Current IDD3P(0) banks open; tCK.MIN, LOW; Other control address inputs STABLE, Data inputs FLOATING. (Fast Power-down Exit); Active Power-Down Current IDD3P(1) banks open; tCK.MIN, LOW; Other control address inputs STABLE, Data inputs FLOATING. HIGH (Slow Power-down Exit); Operating Current Burst Write: banks open; Continuous burst writes; CLMIN; tCK.MIN; tRAS tRAS.MAX., tRP.MAX; HIGH, HIGH between valid commands. Address inputs SWITCHING; Data inputs SWITCHING; Burst Refresh Current tCK.MIN., Refresh command every tRFC tRFC.MIN interval, HIGH, HIGH between valid commands, Other control address inputs SWITCHING, Data inputs SWITCHING. Distributed Refresh Current tCK.MIN., Refresh command every tRFC tREFI interval, HIGH between valid commands, Other control address inputs SWITCHING, Data inputs SWITCHING.
IDD4W
IDD5B
IDD5D
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Parameter
Symbol
Note1)2)
3)4)5)6)
Self-Refresh Current IDD6 external clock off, Other control address inputs FLOATING, Data inputs FLOATING. IDD6 current values guaranteed TCASE max. Bank Interleave Read Current IDD7 banks being interleaved minimum without violating tRRD using burst length Control address inputs STABLE during DESELECTS. Iout VDDQ specifications tested after device properly initialized parameter specified with disabled. Definitions Table IDD1, IDD4R IDD7 current measurements defined with outputs disabled (IOUT mA). achieve this module level output
buffers disabled using EMRS(1) (Extended Mode Register Command) setting HIGH. rank modules: active current measurements other rank Precharge Power-Down Mode IDD2P details notes relevant QIMONDA component data sheet
TABLE
Definitions
Parameter STABLE FLOATING SWITCHING Description
VIL(ac).MAX, HIGH defined VIH(ac).MIN
inputs stable HIGH level inputs VREF VDDQ inputs changing between HIGH every other clock (once cycles) address control signals, inputs changing between HIGH every other data transfer (once cycle) signals including mask strobes
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TABLE
Specification
HYS72T32000HP-3.7-A HYS72T64001HP-3.7-A HYS72T32000HP-3S-A HYS72T64001HP-3S-A HYS72T64020HP-3S-A Product Type HYS72T64020HP-3.7-A Unit Note1)
Organization
MByte Rank
MByte Rank Max. 1710 1870 1410 1140 1410 2580 2670 2310 3080
MByte Rank Max. 1070 1200 1200 1420 1470 1290
MByte Rank -3.7 Max. 1100 1100
MByte Rank -3.7 Max. 1490 1580 1130 1130 1760 2030 2030
MByte Rank -3.7 Max. 1000 1130 1130
3)4) 3)4)
Symbol
Max. 1020 1380 1420 1240 1630
1670 1550 2930 1580 Module calculated basis component includes currents Registers PLL. disabled. IDD1, IDD4R IDD7
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P.MRS=0 IDD3P.MRS=1 IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
defined with outputs disabled. other rank IDD2P Precharge Power-Down Standby Current mode. Both ranks same mode. Values TCASE
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3.4.1
Currents Test Conditions
TABLE
Measurement Test Conditions DDR2-667
testing parameters, following timing parameters used:
Parameter
Symbol
DDR2-667D
Unit
Latency Clock Cycle Time Active Read Write delay Active Active Auto-Refresh command period Active bank Active bank command delay Active Precharge Command Precharge Command Period Average periodic Refresh interval
CL(IDD)
3.75 70000
tCK(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tRAS.MIN(IDD) tRAS.MAX(IDD) tRP(IDD) tREFI
TABLE
Measurement Test Conditions DDR2-533
Parameter Symbol -3.7 DDR2-533C Latency Clock Cycle Time Active Read Write delay Active Active Auto-Refresh command period Active bank Active bank command delay Active Precharge Command Precharge Command Period Average periodic Refresh interval CL(IDD) 3.75 70000 Unit
tCK(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tRAS.MIN(IDD) tRAS.MAX(IDD) tRP(IDD) tREFI
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3.4.2
Termination (ODT) Current
function adds additional current consumption DDR2 SDRAM when enabled EMRS(1). Depending address bits A[6,2] EMRS(1) "weak" "strong" termination selected. current consumption terminated input pin, depends input tri-state driving long enabled during given period time.
TABLE
current terminated
Parameter Enabled current HIGH; Data inputs FLOATING Active current HIGH; worst case Data inputs STABLE SWITCHING. Symbol Min. Typ. Max. 3.75 22.5 Unit mA/DQ mA/DQ mA/DQ mA/DQ mA/DQ EMRS(1) State
IODTO
11.25 mA/DQ
IODTT
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Codes
This chapter lists hexadecimal byte values stored EEPROM products described this data sheet. stands serial presence detect. values with table module specific bytes which defined during production. List Code Tables Table "SPD Codes PC2-5300" Page Table "SPD Codes PC2-4200" Page
TABLE
Codes PC2-5300
HYS72T32000HP-3S-A HYS72T64000HP-3S-A Product Type HYS72T64020HP-3S-A 512MB Ranks PC2-5300P-555 Rev.
Organization
256MB Rank
512MB Rank PC2-5300P-555 Rev.
Label Code JEDEC Revision Byte# Description Programmed Bytes EEPROM Total number Bytes EEPROM Memory Type (DDR2) Number Addresses Number Column Addresses DIMM Rank Stacking Information Data Width used Interface Voltage Level
PC2-5300P-555 Rev.
CLMAX (Byte [ns] SDRAM CLMAX (Byte [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate Type Primary SDRAM Width Error Checking SDRAM Width
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HYS72T32000HP-3S-A
HYS72T64000HP-3S-A
Product Type
Organization
256MB Rank
512MB Rank PC2-5300P-555 Rev.
512MB Ranks PC2-5300P-555 Rev.
Label Code JEDEC Revision Byte# Description used Burst Length Supported Number Banks SDRAM Device Supported Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
PC2-5300P-555 Rev.
CLMAX (Byte [ns] SDRAM CLMAX [ns] CLMAX (Byte [ns] SDRAM CLMAX [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density Rank
tAS.MIN tCS.MIN [ns] tAH.MIN tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRFC Extension tRC.MIN [ns]
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HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
HYS72T32000HP-3S-A
HYS72T64000HP-3S-A
Product Type
Organization
256MB Rank
512MB Rank PC2-5300P-555 Rev.
512MB Ranks PC2-5300P-555 Rev.
Label Code JEDEC Revision Byte# Description
PC2-5300P-555 Rev.
tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
Relock Time
TCASE.MAX Delta T4R4W Delta
Psi(T-A) DRAM (DT0) (DT2N, UDIMM) (DT2Q, RDIMM) (DT2P) (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) (DT4R) T4R4W Sign (DT4R4W) (DT5B) (DT7) Psi(ca) Psi(ca) TPLL (DTPLL) TREG (DTREG) Toggle Rate Revision Checksum Bytes 0-62 Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code
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HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
HYS72T32000HP-3S-A
HYS72T64000HP-3S-A
Product Type
Organization
256MB Rank
512MB Rank PC2-5300P-555 Rev.
512MB Ranks PC2-5300P-555 Rev.
Label Code JEDEC Revision Byte# Description Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Module Manufacturer Location Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-5300P-555 Rev.
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
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HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
HYS72T32000HP-3S-A
HYS72T64000HP-3S-A
Product Type
Organization
256MB Rank
512MB Rank PC2-5300P-555 Rev.
512MB Ranks PC2-5300P-555 Rev.
Label Code JEDEC Revision Byte# Description Blank customer
PC2-5300P-555 Rev.
used
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TABLE
Codes PC2-4200
HYS72T32000HP-3.7-A HYS72T64000HP-3.7-A Product Type HYS72T64020HP-3.7-A 512MB Ranks PC2-4200P-444 Rev.
Organization
256MB Rank
512MB Rank PC2-4200P-444 Rev.
Label Code JEDEC Revision Byte# Description Programmed Bytes EEPROM Total number Bytes EEPROM Memory Type (DDR2) Number Addresses Number Column Addresses DIMM Rank Stacking Information Data Width used Interface Voltage Level
PC2-4200P-444 Rev.
CLMAX (Byte [ns] SDRAM CLMAX (Byte [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate Type Primary SDRAM Width Error Checking SDRAM Width used Burst Length Supported Number Banks SDRAM Device Supported Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
CLMAX (Byte [ns]
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HYS72T32000HP-3.7-A
HYS72T64000HP-3.7-A
Product Type
Organization
256MB Rank
512MB Rank PC2-4200P-444 Rev.
512MB Ranks PC2-4200P-444 Rev.
Label Code JEDEC Revision Byte# Description
PC2-4200P-444 Rev.
SDRAM CLMAX [ns] CLMAX (Byte [ns] SDRAM CLMAX [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density Rank
tAS.MIN tCS.MIN [ns] tAH.MIN tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
Relock Time
TCASE.MAX Delta T4R4W Delta
Psi(T-A) DRAM (DT0) (DT2N, UDIMM) (DT2Q, RDIMM)
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T64020HP-3.7-A
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
HYS72T32000HP-3.7-A
HYS72T64000HP-3.7-A
Product Type
Organization
256MB Rank
512MB Rank PC2-4200P-444 Rev.
512MB Ranks PC2-4200P-444 Rev.
Label Code JEDEC Revision Byte# Description (DT2P) (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) (DT4R) T4R4W Sign (DT4R4W) (DT5B) (DT7) Psi(ca) Psi(ca) TPLL (DTPLL) TREG (DTREG) Toggle Rate Revision Checksum Bytes 0-62 Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Manufacturer's JEDEC Code Module Manufacturer Location Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char
PC2-4200P-444 Rev.
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T64020HP-3.7-A
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
HYS72T32000HP-3.7-A
HYS72T64000HP-3.7-A
Product Type
Organization
256MB Rank
512MB Rank PC2-4200P-444 Rev.
512MB Ranks PC2-4200P-444 Rev.
Label Code JEDEC Revision Byte# Description Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Product Type, Char Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank customer
PC2-4200P-444 Rev.
used
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T64020HP-3.7-A
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
Package Outlines
FIGURE
Package Outline Card L-DIM-240-11
This chapter contains package outlines products.
Notes General tolerances 0.15 Drawing according 8015
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
FIGURE
Package Outline Card L-DIM-240-12
Notes General tolerances 0.15 Drawing according 8015
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
FIGURE
Package Outline Card L-DIM-240-13
Notes General tolerances 0.15 Drawing according 8015
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
Product Type Nomenclature
Qimonda's nomenclature uses simple coding combined with some propriatory coding. Table provides examples module component product type number well field number. detailed field description together with possible values coding explanation listed modules Table components Table
TABLE
Nomenclature Fields Examples
Example Field Number Micro-DIMM DDR2 DRAM 64/128 512/
TABLE
DDR2 DIMM Nomenclature
Field Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density [Mbit]; Module Density1) Values Card Generation Number Module Ranks Product Variations Package, Lead-Free Status Module Type Coding Constant Non-ECC DDR2 MByte MByte GByte GByte GByte Look table Look table Look table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
Field
Description Speed Grade
Values -2.5F -2.5 -3.7
Coding PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
Revision
Multiplying "Memory Density I/O" with "Module Data Width" dividing Non-ECC modules gives overall module memory density MBytes listed column "Coding".
TABLE
DDR2 DRAM Nomenclature
Field Description Qimonda Component Prefix Interface Voltage DRAM Technology Component Density [Mbit] Values Number I/Os Product Variations Revision Package, Lead-Free Status Speed Grade -25F -2.5 -3.7 Coding Constant SSTL_18 DDR2 Mbit Mbit Gbit Gbit Look table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Performance table Performance table -3.7 Performance table Ordering Information RoHS Compliant Products. Address Format Components Modules Configuration RDIMM Abbreviations Buffer Type Abbreviations Type Absolute Maximum Ratings DRAM Component Operating Temperature Range Operating Conditions Supply Voltage Levels Operating Conditions Speed Grade Definition Speed Bins DDR2-667D. Speed Grade Definition Speed Bins DDR2-533C. Timing Parameter Speed Grade DDR2-667 Timing Parameter Speed Grade DDR2-533 Timing Parameter Speed Grade DDR2-400 Characteristics Operating Conditions DDR2-667. Characteristics Operating Conditions DDR2-533 DDR2-400 Measurement Conditions Definitions Specification Measurement Test Conditions DDR2-667 Measurement Test Conditions DDR2-533 current terminated Codes PC2-5300 Codes PC2-4200 Nomenclature Fields Examples DDR2 DIMM Nomenclature DDR2 DRAM Nomenclature
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
List Figures
Figure Figure Figure Figure Figure Figure Figure Configuration RDIMM (240 pins) Method calculating transitions endpoint Differential input waveform timing Differential input waveform timing Package Outline Card L-DIM-240-11 Package Outline Card L-DIM-240-12 Package Outline Card L-DIM-240-13
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
HYS72T[32/64]xxxHP-[3S/3.7]-A Registered DDR2 SDRAM Modules
Table Contents
3.3.1 3.3.2 3.3.3 3.4.1 3.4.2 Overview Features Description Configuration Configuration Electrical Characteristics Absolute Maximum Ratings Operating Conditions Characteristics Speed Grades Definitions Timing Parameters Electrical Characteristics Currents Specifications Conditions Currents Test Conditions Termination (ODT) Current
Codes Package Outlines Product Type Nomenclature List Tables List Figures Table Contents
Rev. 1.01, 2006-09 03292006-ZZHP-PR83
Edition 2006-09 Published Qimonda Gustav-Heinemann-Ring D-81739 Germany Qimonda 2006. Rights Reserved. Legal Disclaimer information given this Internet Data Sheet shall event regarded guarantee conditions characteristics ("Beschaffenheitsgarantie"). With respect examples hints given herein, typical values stated herein and/or information regarding application device, Qimonda hereby disclaims warranties liabilities kind, including without limitation warranties non-infringement intellectual property rights third party. Information further information technology, delivery terms conditions prices please contact your nearest Qimonda Office. Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Qimonda Office. Qimonda Components only used life-support devices systems with express written approval Qimonda, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered. www.qimonda.com
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