Dual power asynchronous stereo audio Codec with integrated power ampli
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STw5098
Dual power asynchronous stereo audio Codec with integrated power amplifiers
Dual audio resolution, 8kHz 96kHz independent rate Dual digital interfaces dual master Sustain complex voice audio flow with without mixing I2C/SPI compatible control Asynchronous sampling DAC: they require oversampled clock information audio data sampling frequency (fs). Jitter tolerant Wide master clock range: from 4MHz 32MHz Stereo headphones drivers, handsfree loudspeaker driver, line drivers Mixable analog line inputs Voice filters: 8/16kHz with voice channel filters Automatic gain control microphone linein inputs Frequency programmable clock outputs Multibit modulators with data weighted averaging functions bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter dynamic compression dynamic range ADC, 0.001% with full scale output 2.7V dynamic range DAC, 0.02% performance 2.7V over load
LFBGA 6x6x1.4 (112 pins) VFBGA 5x5x1 (112 pins)
STw5098
Description
STw5098 dual power asynchronous stereo audio CODEC device with headphones amplifiers high quality audio listening recording. I2S/PCM digital interfaces available, master example Bluetooth Application Processor, enabling concurrent audio voice flow between Network user. STw5098 control registers accessible through selectable I2C-bus compatible compatible interface.
Applications
Digital cellular telephones with application processor such gaming Bluetooth concurrent application
April 2007
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www.st.com
Contents
STw5098
Contents
Overview Pinout Block diagram Functional description
4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 Naming convention Power supply Device programming Power Master clock Data rates Clock generators master mode function Audio digital interfaces Analog inputs Analog output drivers Analog mixers paths paths Analog-only operations Automatic Gain Control (AGC) Interrupt request: pins Headset plug-in push-button detection Microphone biasing circuits
Control registers
Summary Supply power control Gains control Analog functions
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STw5098
Contents
5.10
Digital audio interfaces master mode clock generators Digital audio interfaces Digital filters, software reset master clock control Interrupt control control interface mode
Control interface master clock
Control interface mode Control interface mode Master clock timing
Audio interfaces Timing specifications Operative ranges
Absolute maximum ratings Operative supply voltage Power dissipation Typical power dissipation entity
Electrical characteristics
10.1 10.2 10.3 10.4 10.5 10.6 10.7 Digital interfaces AMCK with sinusoid input Analog interfaces Headset plug-in push-button detector Microphone bias Power supply rejection ratio gain limiter
Analog input/output operative ranges
11.1 11.2 11.3 11.4 Analog levels Microphone input levels Line output levels Power output levels
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Contents
STw5098
11.5
Power output levels
Stereo audio specifications Stereo audio specifications mixing (sidetone) specifications Stereo analog-only path specifications (TX) (RX) specifications with voice filters selected Typical performance plots Package mechanical data
18.1 18.2 LFBGA 6x6x1.4 VFBGA 5x5x1.0
Application schematics Ordering information Revision history
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STw5098
List tables
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table STw5098 description Control register summary description description description description description description description CR10 CR11 description CR12 CR13 description CR14 description CR15 description CR16 description CR17 description CR18 description CR19 description CR21-20 CR24-23 description. CR22 CR25 description CR26 description CR27 description CR28 description CR29 description CR30 description CR31 description CR32 description CR33 description description description Control interface timing with format Control interface signal timing with format AMCK timing Audio interface signal timings Absolute maximum ratings Operative supply voltage Power dissipation Typical power dissipation, master clock Typical power dissipation with master clock AMCK Digital interfaces specifications. AMCK with sinusoid input specifications Analog interface specifications Headset plug-in push-button detector specifications Microphone bias specifications Power supply rejection ratio specifications gain limiter Reference full scale analog levels Microphone input levels, absolute levels pins connected preamplifiers Microphone input levels, absolute levels pins connected line-in amplifiers
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List tables Table Table Table Table Table Table Table Table Table Table Table Table
STw5098
Absolute levels OLP/OLN, ORP/ORN Absolute levels Absolute levels 1EARP-1EARN 2LSP 2LSN. Stereo audio specifications Stereo audio specifications mixing (sidetone) specifications Stereo analog-only path specifications (TX) (RX) specifications with voice filters selected. Dimensions LFBGA 6x6x1.4 4R11x11. Dimensions VFBGA 5x5x1.0 balls pitch Order codes Document revision history
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STw5098
List figures
List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure assignment STw5098 block diagram Power block diagram: example shown entity Plug-in push-button detection application note Control interface format Control interface: format timing Control interface format Control interface: format timing Audio interfaces formats: delayed, left right justified Audio interfaces formats: DSP, Audio interface timings: master mode Audio interface timing: slave mode A.C. testing input-output waveform. Bass treble control, de-emphasis filter Dynamic compressor transfer function audio path measured filter response band audio path measured filter response digital audio filter characteristics band digital audio filter characteristics audio path measured filter response audio in-band measured filter response. voice path measured filter response. voice path measured in-band filter response voice (RX) digital filter characteristics voice (RX) in-band digital filter characteristics path FFT. versus input-level path FFT. versus input-level Analog path Analog path versus input-level. LFBGA 6x6x1.4 4R11x11 drawing VFBGA 5x5x1.0 drawing STw5098 application schematics
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Overview
STw5098
Overview
Dual audio resolution, 8kHz 96kHz independent rate Dual I2S/PCM digital interfaces dual master Sustain complex voice audio flow with without mixing I2C/SPI compatible independent control interfaces Asynchronous sampling that require oversampled clock information audio data sampling frequency (fs). Jitter tolerant Wide master clock range from 4MHz 32MHz stereo headphones drivers, hand free loudspeaker driver, line drivers Mixable analog line inputs Voice filters: 8/16kHz with voice channel filters Automatic gain control microphone line-in inputs Four programmable master/slave serial audio data interfaces: I2S, SPI, compatible other formats Frequency programmable clock outputs Multibit modulators with data weighted averaging Four functions bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter dynamic compression dynamic range ADC, 0.001% with full scale with full scale output 2.7V dynamic range DAC, 0.02% performance 2.7V over load
Analog inputs
Selectable stereo differential single-ended microphone amplifier inputs with 51dB range programmable gain microphone biasing output Microphone plug-in push-button detection input Selectable stereo differential single-ended line inputs with 38dB range programmable gain
Analog output drivers
Stereo headphones outputs. driving capability: 40mW (0.1% THD) over with 40dB range programmable gain Common mode voltage headphones driver (phantom ground) Balanced loudspeaker output with driving capability 500mW (VCCLS>3.5V; THD) over with 30dB range programmable gain Balanced earphone output with driving capability 125mW Transient suppression filter during power power down Balanced/unbalanced stereo line outputs with driving capability
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STw5098
Pinout
Figure
Pinout
assignment
1SCLK
1AD_OCK
2SDA/SDIN
1DA_OCK
1AD_CK
2AS/CSB
2AD_DATA
2AD_SYNC
1DA_SYNC
1DA_DATA
2HDET 2SCLK 2AD_OCK 1CMOD 2DA_OCK 2DA_CK AMCK 2DA_SYNC 2DA_DATA
VCCA 1HDET VCCA 2CMOD 1SDA/SDIN 2AD_CK
1AD_DATA
1AD_SYNC
2IRQ
2MBIAS
1MBIAS
2AUX1L 1AUX1L 1MICLN VCCIO 1DA_CK 1AS/CSB 1IRQ VCCA 1AUX1R 2AUX1R
2AUX3L 1AUX3L 1MICLP 2MICLN 2CAPLINEIN 1MICRN 2AUX3R 2MICRN
2CAPMIC 1CAPMIC GNDA 2MICLP 1CAPLINEIN 1MICRP 1AUX3R 2MICRP
1AUX2LN 2AUX2LN 1LINEINL 2LINEINL GNDA 1AUX2RP 1AUX2RN 2AUX2RN
1AUX2LP 2AUX2LP 2OLN GNDCM 1EARPS 1EARP VCCP 1HPR 2ORN 2LINEINR 2AUX2RP
1OLN 1OLP 2OLP 2HPL 1VCMHP 1CAPEAR 1EARN VCCLS 2ORP 1ORN 1LINEINR
GNDCM VCCP 1HPL 2VCMHPS VCCLS
GNDP
GNDP
1EARNS
VCCLS
1ORP
GNDP
VCCP GNDP 1VCMHPS 2VCMHP 2LSPS 2LSP 2CAPLS 2LSN 2LSNS VCCP 2HPR
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Pinout
STw5098
Table
Position
STw5098 description
Type DIOD name 1SCLK 1AD_OCK 2SDA/SDIN 1DA_OCK 1AD_CK 2AS/CSB 2AD_DATA 2AD_SYNC 1DA_SYNC 1DA_DATA 2HDET 2SCLK 2AD_OCK 1CMOD 2DA_OCK 2DA_CK AMCK Description Ground digital section Control interface serial clock input Oversampled clock from clock generator Control interface serial data input-output mode (SDA), control interface serial data input mode (SDIN). Oversampled clock from clock generator Serial data clock stereo converter Control interface address select mode (AS). Interface enable signal mode (CSB). Serial data stereo converter Frame sync stereo converter Frame sync stereo converter Serial data stereo converter Headset detection input (microphone plug-in push-button detection) Control interface serial clock input Oversampled clock from clock generator Control interface type selector I2C-bus mode mode Oversampled clock from clock generator Serial data clock stereo converter Master clock input. Accepted range MHz. AMCK digital square wave AMCK analog sinewave (Section 10.2 page Power supply digital section. Operating range: from 1.71 Frame sync stereo converter Serial data stereo converter Ground digital section Power supply analog section. Standard operating range: from 2.7V 3.3V voltage (LV) range: from 2.4V 2.7V Headset detection input (microphone plug-in push-button detection) Power supply analog section. Standard operating range: from 2.7V 3.3V voltage (LV) range: from 2.4V 2.7V Control interface type selector I2C-bus mode mode.
2DA_SYNC 2DA_DATA VCCA
1HDET
VCCA 2CMOD
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STw5098 Table
Position
Pinout STw5098 description
Type DIOD name 1SDA/SDIN 2AD_CK 1AD_DATA 1AD_SYNC 2IRQ 2MBIAS 1MBIAS 2AUX1L 1AUX1L 1MICLN VCCIO 1DA_CK 1AS/CSB 1IRQ VCCA 1AUX1R 2AUX1R 2AUX3L 1AUX3L 1MICLP 2MICLN 2CAPLINEIN 1MICRN 2AUX3R 2MICRN 2CAPMIC 1CAPMIC GNDA 2MICLP Description Control interface serial data input-output mode (SDA). Control interface serial data input mode (SDIN). Serial data clock stereo converter Serial data stereo converter Frame sync stereo converter Programmable interrupt output. Active signal. Microphone biasing pin. Fixed voltage reference Microphone biasing pin. Fixed voltage reference Left right channel single ended pins microphone line input Left right channel single ended pins microphone line input Left right channel differential pins microphone input Power supply digital section. Operating range: from 1.71V 2.7V Power supply digital buffers. Operating ranges: from 1.2V 1.8V from 1.71V Serial data clock stereo converter Control interface address select mode (AS) Interface enable signal mode (CSB) Programmable interrupt output. Active signal. Power supply analog section. Standard operating range: from 2.7V 3.3V voltage (LV) range: from 2.4V 2.7V Left right channel single ended pins microphone line input Left right channel single ended pins microphone line input Left right channel single ended pins microphone line input Left right channel single ended pins microphone line input Left right channel differential pins microphone input Left right channel differential pins microphone input capacitor must connected between CAPLINEIN ground Left right channel differential pins microphone input Left right channel single ended pins microphone line input Left right channel differential pins microphone input capacitor must connected between CAPMIC ground. capacitor must connected between CAPMIC ground Ground analog section Left right channel differential pins microphone input
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Pinout Table
Position
STw5098 STw5098 description
Type name 1CAPLINEIN 1MICRP 1AUX3R 2MICRP 1AUX2LN 2AUX2LN 1LINEINL 2LINEINL GNDA 1AUX2RP 1AUX2RN 2AUX2RN 1AUX2LP 2AUX2LP 2OLN Description capacitor must connected between CAPLINEIN ground Left right channel differential pins microphone input Left right channel single ended pins microphone line input Left right channel differential pins microphone input Left right channel differential pins microphone line input Left right channel differential pins microphone line input Left right channel single ended pins line input Left right channel single ended pins line input Ground analog section Left right channel differential pins microphone line input. Left right channel differential pins microphone line input Left right channel differential pins microphone line input Left right channel differential pins microphone line input Left right channel differential pins microphone line input Audio differential line amplifier left right channels. This outputs drive resistive load. used single ended output. Ground analog reference. GNDCM connected GNDA EARPS, EARNS (sense) pins must connected application board EARP, EARN pins respectively. connection must close possible pins. Analog differential loudspeaker amplifier output left channel right channel both. This output drive 50nF (with series resistor) directly earpiece transductor from deliver from 500mW 125mW. Power supply left right output drivers (headphones line-out). Operating range: from VCCA 3.3V Audio single ended headphones amplifier outputs left right channels. outputs drive 50nF (with series resistor) directly earpiece transductor Audio differential line amplifier left right channels. This outputs drive resistive load. used single ended output. Left right channel single ended pins line input Left right channel differential pins microphone line input Audio differential line amplifier left right channels. This outputs drive resistive load. used single ended output.
GNDCM
1EARPS
1EARP
VCCP
1HPR
2ORN 2LINEINR 2AUX2RP 1OLN
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STw5098 Table
Position
Pinout STw5098 description
Type name 1OLP Description Audio differential line amplifier left right channels. This outputs drive resistive load. used single ended output. Audio differential line amplifier left right channels. This outputs drive resistive load. used single ended output. Audio single ended headphones amplifier outputs left right channels. outputs drive 50nF (with series resistor) directly earpiece transductor Common mode voltage headphones output. negative pins headphones left right speakers connected this avoid decoupling capacitors. capacitor connected between this node ground Analog differential loudspeaker amplifier output Left channel Right channel both. This output drive 50nF (with series resistor) directly earpiece transductor from deliver from 500mW 125mW. Power supply mono differential output driver. Operating range: from VCCA 5.5V Audio differential line amplifier left right channels. This outputs drive resistive load. used single ended output. Audio differential line amplifier left right channels. This outputs drive resistive load. used single ended output. Left right channel single ended pins line input Ground analog reference. GNDCM connected GNDA Power supply pins left right output drivers (headphones line-out). Operating range: from VCCA 3.3V Audio single ended headphones amplifier outputs left right channels. outputs drive 50nF (with series resistor) directly earpiece transductor VCMHPS (sense) must connected application board VCMHP pin. connection must close possible pins. Power supply mono differential output driver. Operating range: from VCCA 5.5V Ground left, right mono-differential output drivers. GNDP GNDA must connected together. Ground left, right mono-differential output drivers. GNDP GNDA must connected together.
2OLP
2HPL
1VCMHP 1CAPEAR
1EARN
VCCLS
2ORP
1ORN 1LINEINR GNDCM
VCCP
1HPL
2VCMHPS
VCCLS GNDP GNDP
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Pinout Table
Position
STw5098 STw5098 description
Type name 1EARNS Description EARPS, EARNS (sense) pins must connected application board EARP, EARN pins respectively. connection must close possible pins. Power supply pins mono differential output driver. Operating range: from VCCA 5.5V Audio differential line amplifier left right channels. This outputs drive resistive load. used single ended output. Ground left, right mono-differential output drivers. GNDP GNDA must connected together. Power supply left right output drivers (headphones line-out). Operating range: from VCCA 3.3V Ground left, right mono-differential output drivers. GNDP GNDA must connected together. VCMHPS (sense) must connected application board VCMHP pin. connection must close possible pins. Common mode voltage headphones output. negative pins headphones left right speakers connected this avoid decoupling capacitors. LSPS, LSNS (sense) pins must connected application board LSP, pins respectively. connection must close possible pins. Analog differential loudspeaker amplifier output Left channel Right channel both. This output drive 50nF (with series resistor) directly earpiece transductor deliver 500mW. capacitor connected between this node ground Analog differential loudspeaker amplifier output Left channel Right channel both. This output drive 50nF (with series resistor) directly earpiece transductor deliver 500mW. LSPS, LSNS (sense) pins must connected application board LSP, pins respectively. connection must close possible pins. Power supply left right output drivers (headphones line-out). Operating range: from VCCA 3.3V Audio single ended headphones amplifier outputs left right channels. outputs drive 50nF (with series resistor) directly earpiece transductor
VCCLS
1ORP
GNDP
VCCP
GNDP
1VCMHPS
2VCMHP
2LSPS
2LSP
2CAPLS
2LSN
2LSNS
VCCP
2HPR
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STw5098
Pinout
Type definitions
DIOD Analog input Analog output Analog input output Digital input Digital output Digital input output Digital input output open drain Power supply ground
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ADLIN1
ADMIC1
MIXLIN1
MIXMIC1
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GNDA VCCIO VCCA 1IRQ 2IRQ 1HDET 2HDET 1SDA/SDIN 1SCLK 1AS/CSB 2AS/CSB 2CMOD 1CMOD 2SCLK 2SDA/SDIN 2MICLP LINSEL2 2MICLN Stereo Diff. 2MICRP 2MICRN 2AUX1L 2AUX1R 2AUX2PL (from DSP) MICSEL2 Stereo Diff. MICLG2 MICRG2 0÷39 Step PreAmps Stereo Sing.E. 2AUX2NL 2AUX2PR 2AUX2NR 2AUX3L 2AUX3R 2LINEINR Stereo Sing.E. 2LINEINL Comm. Mode 2CAPMIC 2CAPLINEIN Control LINLG2 LINRG2 -20:+18 Step Headset Detection (from DSP) Stereo Path Power-On Reset Registers Control Logic Stereo Sing.E. Stereo Path Amps LINEIN AUX1 AUX2 AUX3 MUTE MICLA2 MICRA2 -12÷0 Step
ADLIN2
Figure
VCCP
VCCLS
GNDP
GNDCM
1MICLP
1MICLN
LINSEL1
(from DSP)
1MICRP
Stereo Diff.
LINLG1 LINRG1 -20:+18 Step
Block diagram
1MICRN
1AUX1L
1AUX1R
Stereo Sing.E.
LINEIN AUX1 AUX2 AUX3 MUTE
Amps
1AUX2PL
1AUX2NL
1AUX2PR
Stereo Diff.
MICSEL1
(from DSP)
AUX2NR
MICLG1 MICRG1 0÷39 Step
1AUX3L
1AUX3R
Stereo Sing.E.
MICLA1 MICRA1 -12÷0 Step
PreAmps
1LINEINR
1LINEINL
Stereo Sing.E.
AUX1 AUX2 AUX3 MUTE
AUX1 AUX2 AUX3 MUTE
1CAPMIC
1CAPLINEIN
Comm. Mode
STw5098
ADMIC2
Block diagram
STw5098 block diagram
1MBIAS
Mic. Bias
2.1V Reference
2.1V Reference
Mic. Bias
2MBIAS
LOG: -18:0 Step Oscillator
LOG: -18:0 Step Left LineOut MICLO2 Bandgap Right LineOut CurrentBias 2ORP 2ORN 2OLP 2OLN
1OLP
1OLN
Left LineOut
MICLO1
1ORP
1ORN
Right LineOut
MIXLIN2
MIXMIC2
1HPL
Left Driver
-40:0 Step Transient Suppr. Filter
-40:0 Step Transient Suppr. Filter
Left Driver HPLG2 Voltage Reference
Driver
2HPL
HPLG1
1VCMHP
Driver
Voltage Reference
2VCMHP 2VCMHPS -40:0 Step Transient Suppr. Filter Right Driver HPRG2 2LSPS 2LSP Mono Driver 2CAPLS 2LSN 2LSNS 2HPR
1VCMHPS
1HPR
Right Driver
-40:0 Step Transient Suppr. Filter
HPRG1
1EARPS
1EARP
1CAPEAR
Mono Driver
1EARN
LSG1 -24:6 Step Transient Suppr. Filter
LSSEL1 (L+R)/2
Stereo
Stereo
LSSEL2 (L+R)/2
LSG2 -24:6 Step Transient Suppr. Filter
1EARNS
1AD_DATA Digital AD-PLL AD_SYNC1 AD_SYNC2 Digital AD-PLL
Sample Rate Converter
Sample Rate Converter
2AD_DATA
1AD_CK MIXDAC1 ADCHSW
Audio AD-I/F
DSP1
DSP2
MIXDAC2 ADCHSW ADMONO
Audio AD-I/F
2AD_CK 2AD_SYNC
1AD_SYNC
ADMONO
1AD_OCK
Gen/ Master Mode
Analog Filter
(Mic&Lin)
Analog Filter
Filter Digital Audio/Voice Gain
Filter Audio/Voice Digital Gain
(Mic&Lin)
Gen/ Master Mode
2AD_OCK
MCK1
AMCK
Mixing Gain
Stereo
Stereo
MCK2 Mixing Gain
(Audio Only)
(Audio Only)
Mixing Gain (sidetone)
Mixing Gain (sidetone)
AMCK Modulator
Bass Treble
Bass Treble Modulator Filter Digital Audio/Voice Gain
(Audio only)
AMCK
(Audio only)
1DA_OCK Filter Digital Gain Audio/Voice
2DA_OCK Dyn.Comp. Gen/ Master Mode
Gen/ Master Mode
Dyn.Comp.
DACHSW Digital DA-PLL DA_SYNC1
1DA_SYNC
DAMONO
Sample Rate Converter
DA_SYNC2
Digital DA-PLL
DACHSW DAMONO Audio DA-I/F 2DA_SYNC 2DA_CK 2DA_DATA
Sample Rate Converter
1DA_CK
Audio DA-I/F
1DA_DATA
STw5098
STw5098
Functional description
Functional description
Naming convention
STw5098 composed identical entities, with their respective control registers. Regarding labelling, name preceded refers entity name preceded refers entity (ie.g. 1SCLK, 2SCLK). following sections, distinction made between entities when relevant. Consequently, prefixes entities respectively omitted. same naming convention applies control registers (CRxxx).
Power supply
STw5098 have different supply voltages different blocks, optimize performance, power consumption connectivity. Section page voltage definition. correct sequence apply supply voltage first (and unset last) digital supply (VCCIO). other supply voltages order disconnected individually, needed. Disconnection does cause harm device extra current pulled from supply during this operation. Moreover voltage conflict detected, like VCCA (not allowed), simply blocks connected VCCA power down extra current pulled from supply. When VCCIO (digital supply) set, digital output pins high impedance state, while digital inputs disconnected avoid power consumption input voltage value between VCCIO. Before disconnected device reset (SWRES CR30). When analog supply (VCCA) set, analog inputs high impedance state. sets control registers powered pins (digital supply) these pins disconnected information stored control registers lost. When digital supply voltage set, power-on-reset (POR) circuit sets registers content default value then generates signals writing bits PORMSK POREV CR31 CR32 respectively both entities. supplies must during operation.
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Functional description
STw5098
Device programming
STw5098 programmed writing Control Registers with compatible control interface (both slave). interface always active, there need have master clock running program device registers. control interfaces each entity operated independently either modes. choice between interfaces each entity done their input pins 1CMOD 2CMOD (CMOD): CMOD connected GND: compatible mode selected device address selected with pin:
chip address 00110101(35hex) reading, 00110100 (34hex) writing chip address 00110111(37hex) reading, 00110110 (36hex) writing
AS/CSB connected GND: AS/CSB connected VCCIO:
When this mode selected control registers accessed through pins: SCLK (clock) (serial data out/in, open drain) CMOD connected VCCIO: compatible mode selected When this mode selected control registers accessed through: AS/CSB (chip select, active low) SCLK (clock) SDIN (serial data AD_OCK DA_OCK (serial data out, selected)
Device Programming: I2C. Control Interface timing shown Section page interface internal counter that keeps current address control register read written. each write access interface address counter loaded with data register address field. value address counter increased after each data byte read write. possible access interface modes: single-byte mode which address data single register specified, multi-byte mode which address first register written read specified following bytes exchanged data successive registers starting from specified multi-byte mode internal address counter restart from register after last register 36). Using multi-byte mode possible write read registers with single access device bus. This applies both entities device. Device Programming: SPI. Control Interface timing shown section Section page Bits SPIOSEL (SPI Output Select) CR33 control selection serial data (none, AD_OCK, DA_OCK IRQ), while SPIOHIZ=1 CR33 selects high impedance state serial data when idle. first sent SDIN, after AS/CSB falling edge, sets interface writing (SDIN=1) reading (SDIN=0), then 7-bit Control Register address follows. interface writing then last bits SDIN written control register. interface reading then after address STw5098 sends bits data selected with bits SPIOSEL CR33, while bits present SDIN ignored. SPIOSEL=00 selected) reading access interface still useful clear event bits CR32.
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STw5098
Functional description
Power
STw5098 internal blocks individually switched according user needs. general power-up present CR0. output drivers should always powered after general power following drawing select needed block desired function. fast-settling function activated quickly charge external capacitors when device switched (CAPLS, CAPLINEIN CAPMIC). Figure Power block diagram: example shown entity
ENANA ENMICL ENHSD MBIAS POWERUP
ENMICR
ENADCL
STw5098
ENLINL
ENADCR
ENADCKGEN
ENLINR ADMAST ENADOCK
ENLOL
AUDIO
DAMAST ENDAOCK ENHPL ENMIXL
ENLS ENMIXL
ENDACL
ENDACKGEN
ENHPR
ENDACR
ENPLL
ENLOR ENOSC=0
ENAMCK
ENOSC=1 ENHPVCM
ENOSC
Master clock
Master clock applied both entities. master clock (AMCK) accepts frequency from MHz. 4-32 range divided sub-ranges that have programmed bits CKRANGE CR30. jitter spectral properties this clock have direct impact performance because used directly integer division drive continuous-time sampled-time interfaces.
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Functional description
STw5098
Note that AMCK clock does need have relation other digital analog input output. AMCK either square wave sinewave, AMCKSIN CR30 selects proper input mode. When sinewave used input, AMCK must decoupled with capacitor. Specification sinusoid input found Section 10.2 page AMCK clock needed when only analog functions used. this purpose internal oscillator with external components used operate device (see Section 4.14 page 25).
Data rates
STw5098 supports data rate ranges: kHz. range selected with bits DA96K AD96K CR29 paths respectively.
Note:
When AD96K=1 required have DA96K=1.
rates fully independent paths. Moreover rates have specified device they change fly, within range, while data flowing. audio data interfaces (for D/A) independently operate master slave modes.
Clock generators master mode function
STw5098 provides internal clock generators that drive, needed, audio interfaces (master mode), and/or independent master clocks. AMCK clock input frequency internally raised each entity obtain clock (MCK) range MHz. ratio MCK/AMCK defined CR30 (see MCKCOEFF Section page 20). used obtain, fractional division, oversampled clock (OCK), word clock (SYNC) clock (CK), that will therefore have edges aligned with (the period have jitter period). frequency OCK, SYNC with DAOCKF CR21/20 interface, ADOCKF CR24/23 interface. ratio between SYNC clocks selected with DAOCK512 CR22 interface ADOCK512 CR25 interface. ratio between SYNC clocks depends selected interface format (see Audio digital interfaces paragraph below). Note that format only slave. ADOCK DAOCK output clocks activated bits ENADOCK ENDAOCK respectively, while master mode generation activated with bits: first ADMAST (DAMAST) sets ADSYNC ADCK (DASYNC DACK) pins outputs, then ADMASTGEN (DAMASTGEN) generates SYNC clocks. logical value SYNC pins before data generation depends interface selected format. description CR20 CR25 further details.
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STw5098
Functional description
Audio digital interfaces
Four separate audio data interfaces provided paths have maximum flexibility communicating with other devices. interfaces have different rates work different formats modes (i.e interface slave while 44.1 master). pins used interfaces are: AD_SYNC, AD_CK AD_DATA paths word clock, clock data, respectively, DA_SYNC, DA_CK DA_DATA paths word clock, clock data, respectively. Data exchanged with first left channel data first formats. Data word-length selected with bits DAWL CR26 ADWL CR27. AD_DATA pin, outside selected time slot, impedance condition selected ADHIZ CR28 data formats except right aligned format. following paragraphs SYNC, DATA will used when distinction between relevant. When Master Mode selected (bits DAMAST ADMAST CR22 CR25 respectively) SYNC clocks generated internally. addition, oversampled clock generated each interface (AD_OCK DA_OCK). clock available Slave Mode also, needed. interfaces also used single bidirectional interface when they configured with same format (Delayed, DSP, etc.) AD_SYNC connected DA_SYNC DA_CK AD_CK. Master Mode still available selecting ADMAST DAMAST (not both). interfaces features controlled with control registers CR26, CR27 CR28. Supported operating formats:
Delayed format (I2S compatible) (DAFORM ADFORM =000): Audio Interface compatible (Figure page 54). number periods within SYNC period relevant, long enough periods used transfer data maximum frequency limit specified clock exceeded. either continuous clock sequence bursts. master mode there periods SYNC period (that means periods channel) when word length bit, while there periods SYNC period periods channel) when word length 18bit higher. Bits ADSYNCP, DASYNCP ADCKP, DACKP affect interface format inverting polarity SYNC pins respectively. Left aligned format (DAFORM ADFORM =001): this format equivalent delayed format without clock delay beginning each frame (Figure page 54). Right aligned format (DAFORM ADFORM =010): this format equivalent delayed format, except that audio data right aligned that number periods fixed each SYNC period (Figure page 54). format (DAFORM ADFORM =011) this format audio interface starting from frame sync pulse SYNC receives (DA) sends (AD) left right data after other (Figure page 55). number periods within SYNC period relevant, long enough periods used transfer data maximum frequency limit specified clock exceeded. either continuous clock sequence bursts. Master Mode there periods SYNC period when word length bit, while there periods SYNC period when word length 18bit higher. (ADCKP DACKP)
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Functional description
STw5098
affects interface format inverting polarity pin. SYNCP (ADSYNCP DASYNCP) switches between delayed (SYNCP=0) delayed (SYNCP=1) formats. format suited interface with multi-channel serial port.
format (DAFORM ADFORM =100) this format left right data received with separate data burst. Every burst identified with level SYNC signal (Figure page 55). There timing difference between left right data burst: channels identified startup order: first burst after path path power-up identifies left channel data, second Right channel data, then left right data repeat after other. must have periods channel case data word periods channel case data word. interface configured single-channel (mono) interface with SPIM (ADSPIM DASPIM). mono interface always exchanges left channel sample. SPI-format only slave: Master Mode selected SYNC pins (ADCKP DACKP) affects interface format inverting polarity pin. format (DAFORM ADFORM =111): this format monophonic, only receive (DA) transmit (AD) single channel data (Figure page 55). mainly used when voice filters selected. audio filters used then same sample sent from DA-PCM interface both channel path, left channel sample from path sent AD-PCM interface. path right channel sent interface then following must set: ADRTOL=1 (CR27) ENADCR=0 (CR1). Master Mode number periods SYNC period between (see DAPCMF CR22 ADPCMF CR25 Section page details). (ADCKP DACKP) affects interface format inverting polarity pin. SYNCP (ADSYNCP DASYNCP) switches between delayed (SYNCP=0) delayed (SYNCP=1) formats.
Analog inputs
Each entity STw5098 stereo Microphone preamplifier stereo Line amplifier, with inputs selectable among (for Microphone preamplifiers only), LINEIN (for Line amplifiers only) different inputs (for Microphone Line amplifiers). inputs used simultaneously Line amplifiers Microphone preamplifiers. following description entity, similar other entity.
Microphone preamplifier: very noise input, specifically designed amplitude signals. this reason preamplifier high input gain keeping constant input impedance whole gain range. However also used line preamplifier because accept high dynamic input signal Vpp). There separate gain attenuation stages order improve ratio when preamplifier output range below full scale (volume control).The gain attenuation controls separate left right channel (CR3 respectively). Preamplifier input selected with bits MICSEL CR18, disconnected when MICMUTE=1. single ended input selected then preamplifier uses selected positive input connects negative input (for both left right channels) CAPMIC pin, which connected through capacitor noise ground (typically same reference ground input).
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STw5098
Functional description Each stereo Microphone preamplifier powered with bits ENMICL ENMICR CR1.
Line amplifier: each line amplifier designed high level input signal. input gain range Line amplifier input selected with bits LINSEL CR18, disconnected when LINMUTE=1. single ended input selected then amplifier uses selected positive input connects negative input (for both left right channels) CAPLINEIN pin, which connected through capacitor noise ground (typically same reference ground input). stereo Line amplifier powered with bits ENLINL ENLINR CR1.
4.10
Analog output drivers
Each entity STw5098 provides different analog signal outputs common mode reference output. description here below entity. VCCP VCCL common both entities.
Line drivers: stereo differential output, used single-ended output just using positive negative pin. drive resistive load. load connected between positive negative pins between ground through decoupling capacitor. output gain regulated with bits CR7, range simultaneously left right channels. When used single ended output effective gain lower. muted with MUTELO CR19. input signal this stereo output come from analog mixer directly from preamplifiers. output Common Mode Voltage level controlled with bits VCML CR19. supply voltage line drivers VCCP line drivers powered with bits ENLOL ENLOR CR1. output pins high impedance state with 180k pull-down resistor when line drivers powered down. Headphones drivers: stereo single ended output. drive resistive load deliver output gain regulated with HPLG HPRG bits respectively, with range muted with MUTEHP CR19. input signal this stereo output comes from analog mixer.The output common mode voltage controlled with bits VCML CR19. supply voltage headphones drivers VCCP headphones drivers powered with bits ENHPL ENHPR CR2.The output pins high impedance state when headphones drivers powered down. Common mode voltage driver: single ended output with output voltage value selectable with bits VCML CR19, from 1.65 steps output voltage should value closest VCCP/2 optimize output drivers performance. common mode voltage driver designed connected common stereo headphones, that decoupling capacitors needed outputs. supply voltage common mode voltage driver VCCP common mode voltage driver powered with ENHPVCM CR2.The output high impedance state when common mode voltage driver powered down.
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Functional description
STw5098
Loudspeaker driver (one entity only): monophonic differential output. drive resistive load deliver load. output gain regulated with bits CR7, range input signal loudspeaker driver comes from analog mixers: bits LSSEL CR29 select left channel, right channel, (L+R)/2 (mono) mute. output common mode voltage obtained with internal voltage divider from VCCLS connected CAPLS pin. supply voltage loudspeaker driver VCCLS. loudspeaker driver powered with ENLS CR2.The output high impedance state when loudspeaker driver powered down.
Note:
Together with driver, only second power output allowed among: (1EARP 1EARN) Headphones (1HPL 1HPR) Headphones (2HPL 2HPR) Earphone driver (one entity only): monophonic differential output. drive resistive load deliver load. output gain regulated with EARG bits CR7, range input signal loudspeaker driver comes from analog mixers: bits EARSEL CR29 select left channel, right channel, (L+R)/2 (mono) mute. output Common Mode Voltage obtained with internal voltage divider from VCCLS connected CAPEAR pin. supply voltage loudspeaker driver VCCLS. loudspeaker driver powered with ENEAR CR2.The output high impedance state when loudspeaker driver powered down. Note direct connection VCCLS battery: voltage batteries handheld devices during charging usually below making VCCLS supply suitable direct connection battery. this case STw5098 delivering maximum power load ambient temperature above then simultaneous charging battery overheat device. basic protection scheme implemented STw5098 (activated with LSLIM CR19): limits maximum gain loudspeaker when VCCLS above removes limit VCCLS below loudspeaker gain left unchanged below with bits LSG. This event (VCCLS generate, enabled (bit VLSMSK CR31), signal.
Note:
4.11
Analog mixers
STw5098 send output drivers stereo audio signals from different sources each entity: path (bit MIXDAC CR17), Microphone Preamplifiers (bit MIXMIC CR17) Line Amplifiers (bit MIXLIN CR17). analog mixers have gain control inputs, therefore user should reduce levels input signals within analog signal range. stereo analog mixers powered with bits ENMIXL ENMIXR CR2.
4.12
paths
each entity path converts audio signals from Microphone Preamplifiers (selected with ADMIC CR17) Line Amplifiers (bit ADLIN CR17) inputs digital domain. both inputs selected then converted. After conversion audio data resampled with sample rate converter then processed with internal DSP. different filters selectable (bit ADVOICE CR29): stereo Audio
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STw5098
Functional description Filter, with offset removal image filtering; standard mono voice-channel filter (uses left channel input feeds both channel output). path includes digital gain control (ADCLG, ADCRG CR12 CR13 respectively) range maximum gain from Preamplifier interface then When Audio filter selected both paths then audio data summed data sent Audio Interface (see DA2ADG CR15). Left right channels independently switched save power, needed (bits ENADCL ENADCR CR1)
4.13
paths
each entity path converts digital data from digital audio interface analog domain feeds analog mixer. Incoming audio data processed with where different filters selectable (bit DAVOICE CR29): Audio filter, stereo, with image filtering, bass treble controls (bits BASS TREBLE CR14), de-emphasis filter; standard voice channel filter, mono (uses left channel input feeds both channel output). dynamic compression function available both audio voice filters (bit DYNC CR14). path includes digital gain control (DACLG, DACRG CR10 CR11 respectively) range mixing (sidetone) enabled: CR16 details. Left right channel independently switched save power, needed (bits ENDACL ENDACR CR1).
4.14
Analog-only operations
Each entity from STw5098 operate without AMCK master clock analog-only functions used. possible Microphone Line preamplifiers signals listen through headphones, loudspeaker send them line-out. analog-only operation enabled with ENOSC CR0. When ENOSC=1 paths cannot used. Analog Mode, each entities handle different stereo audio signals, used front external voice codec that does include microphone preamplifiers power drivers: signal sent through Microphone preamplifiers directly line drivers (Transmit path), while Receive signal sent through Line amplifiers selected power drivers.
4.15
Automatic Gain Control (AGC)
STw5098 provides digital Automatic Gain Control path each entity. circuit control input gain preamplifier, Line amplifier both (bits ENAGCMIC ENAGCLIN CR35). When input selected, center gain value used input fixed with bits MICLG, MICRG, LINLG LINRG (like normal operation), then circuit adds gains value range -10.5 +10.5 (or, extended with AGCRANGE CR35, dB), order obtain average level digital interface output range (selected with bits AGCLEV CR35). added gain acts directly input gain, avoid input saturation improve ratio, cannot exceed input gain range. When Line-In inputs selected simultaneously control performed two, preserving balance fixed with input gains. Different values Attack Decay constants selected, depending kind signal control (i.e. voice, music).
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Functional description
STw5098
Attack Decay time constants related data rate (see bits AGCATT AGCDEL CR34).
4.16
Interrupt request: pins
each entity STw5098, interrupt request feature signal control device occurrence particular events each entity. control registers used choose behavior pin: first Status/Event Register (CR32), where bits represent status internal function (i.e. voltage above below threshold) event (i.e. voltage changed crossing threshold); second Mask Register (CR31) where mask then corresponding Status/Event Register affect status. each entity, always active low. power interrupt request generated Power-On-Reset circuit that sets bits PORMSK CR31 POREV CR32. After this event PORMSK should cleared user IRQCMOS CR33 should according application (open drain CMOS). When event occurs control interface selected with serial output still possible identify event (and relative status) that generated interrupt request. This done setting mask/enable bits CR31) time (with successive writings) reading status. simple example this headset plug-in detection: first HSDETMSK=1 CR31 (with other bits there interrupt request then HSDETMSK=0 HSDETEN=1, read HSDET status pin. Then read CR32 clear content (even data sent out).
4.17
Headset plug-in push-button detection
Each entity STw5098 detect plug-in microphone connector press/release event call/answer push-button. application example found below, while specifications found Section 10.4 page Figure Plug-in push-button detection application note
HDET 200nF VCCA 1.5k Call/Answer Button 10µF 200nF CAPMIC AUX1L AUX1R
STw5095
From driver Generic Connector
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STw5098
Functional description
4.18
Microphone biasing circuits
Microphone Biasing Circuits drive mono stereo microphones switch them when needed order save current used microphone biasing network each entity. bits control behavior microphone bias circuit: MBIAS CR17 enables circuit (fixed voltage MBIAS pin), while MBIASPD CR17 affects behavior MBIAS when function enabled. particular when MBIASPD=1 MBIAS pulled down, otherwise left tristate mode. specification microphone biasing circuits found Section 10.6 page
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Control registers
STw5098
Table
(hex) (00h) (01h) (02h) (03h) (04h) (05h) (06h) (07h) (08h) (09h) CR10 (0Ah) CR11 (0Bh) CR12 (0Ch) CR13 (0Dh) CR14 (0Eh) CR15 (0Fh) CR16 (10h) CR17 (11h)
Control registers
Summary
Control register summary
Description Supply power control Power control Power control gain left gain right Line gain left Line gain right gain gain gain gain digital gain left digital gain right digital gain left digital gain right Bass/treble/deemphasis mixing gain mix/sidetone gain Mixer switches bias
POWER
Def.
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1001 0000 1001 0000 0011 0000 0011 0000 0011 0000 0000 0000 0000 0000 1000 0000 1000 0000 0000 0000 0000
ENANA
ENAMCK
ENOSC
ENPLL
ENHSD
A24V
D12V
ENADCL
ENADCR
ENDACL
ENDACR
ENMICL
ENMICR
ENLINL
ENLINR
ENLOL
ENLOR
ENHPL
ENHPR
ENHPVC
1ENEAR 2ENLS
ENMIXL
ENMIXR
MICLA(2:0)
MICLG(4:0)
MICRA(2:0)
MICRG(4:0)
LINLG(4:0)
LINRG(4:0)
LOG(2:0)
1EARG(3:0) 2LSG(3:0)
HPLG(4:0)
HPRG(4:0)
DACLG(5:0)
DACRG(5:0)
ADCLG(5:0)
ADCRG(5:0)
DYNC
TREBLE(2:0)
BASS(3:0)
DA2ADG(4:0)
AD2DAG(5:0)
0000 0000
MBIAS
BIASPD
ADMIC
ADLIN
MIXMIC
MIXLIN
MIXDAC
MICLO
0000 0000
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STw5098 Table
(hex) CR18 (12h) CR19 (13h) CR20 (14h) CR21 (15h) CR22 (16h) CR23 (17h) CR24 (18h) CR25 (19h) CR26 (1Ah) CR27 (1Bh) CR28 (1Ch) CR29 (1Dh) CR30 (1Eh) CR31 (1Fh) CR32 (20h) CR33 (21h) CR34 (22h) CR35 (23h) CR36 (24h)
Control registers Control register summary
Description Def.
0010 0100 0101 1000 0000 0000 0000 0000 CK512 0000 0000 0000 0000 0000 0000 CK512 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Input switches Drivers control DAOCK frequency DAOCK frequency clock generator control ADOCK frequency ADOCK frequency Clock generator control data control data control DAC&ADC data control Digital filters control Soft reset AMCK range Interrupt mask Interrupt status Misc. control attack/decay coeff. control RESERVED
IN2VCM
LINMUTE
LINSEL(1:0)
MICMUTE
MICSEL(1:0)
VCML(1:0)
MUTELO
MUTEHP
1EARLIM 2LSLIM
1EARSEL(1:0) 2LSSEL(1:0)
DAOCKF(7:0)
DAOCKF(15:8)
DAMAST
MASTGEN
AOCK
DAPCMF(1:0)
ADOCKF(7:0)
ADOCKF(15:8)
ADMAST
MASTGEN
DOCK
ADPCMF(1:0)
DAFORM(2:0)
DASPIM
DAWL(2:0)
ADRTOL
ADFORM2:0)
ADSPIM
ADWL(2:0)
KINV
DACKP
DASYNCP
DAMONO
ADCKP
SYNCP
ADMONO
ADHIZ
DAVOICE
DA96K
RXNH
ADVOICE
AD96K
ADNH
TXNH
SWRES
AMCKSIN
CKRANGE(2:0)
VLSHEN
PUSH
HSDETEN
VLSHMSK
PUSH BMSK
HSDET
OVFMSK
PORMSK
VLSH
PUSHB
HSDET
VLSHEV
PUSHBEV HSDETEV
OVFEV
POREV
SPIOHIZ
SPIOSEL(1:0)
IRQCMOS
OVFDA
OVFAD
AGCATT(3:0)
AGCDEC(3:0)
0000 0000
GCLIN
ENAG CMIC
RANGE
AGCLEV(3:0)
0000 0000 0000 0000
Note: reserved, write zero
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Control registers Caution:
STw5098
following Section Control registers, reference each entity omitted. Each entity STw5098 same register set.
(hex) (00h) (01h) (02h)
Supply power control
Description Supply power control Power control Power control
POWER
Def.
0000 0000 0000 0000 0000 0000
ENANA
ENAMCK
ENOSC
ENPLL
ENHSD
A24V
D12V
ENADCL
ENADCR
ENDACL
ENDACR
ENMICL
ENMICR
ENLINL
ENLINR
ENLOL
ENLOR
ENHPL
ENHPR
PVCM
ENLS
ENMIXL
ENMIXR
Table
Bits
description
Name Val. description enabled analog digital blocks power device power down analog blocks enabled analog blocks power down AMCK clock input enabled AMCK clock input disabled Internal oscillator enabled. analog blocks oscillator clock internal oscillator power down enabled power down headset plug-in detector enabled headset plug-in detector disabled Analog supply pins voltage range 2.4V<VCCA<2.7V Analog supply pins voltage range 2.7V<VCCA<3.3V Digital voltage range 1.2V<VCCIO<1.8V Digital voltage range 1.71V<VCCIO<VCC Def.
POWERUP ENANA ENAMCK
ENOSC
ENPLL ENHSD A24V D12V
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STw5098 Table
Bits
Control registers description
Name Value description left channel converter enabled left channel converter power down right channel converter enabled right channel converter power down left channel converter enabled left channel converter power down right channel converter enabled right channel converter power down left channel microphone preamplifier enabled left channel microphone preamplifier power down right channel microphone preamplifier enabled right channel microphone preamplifier power down left channel line-in preamplifier enabled left channel line-in preamplifier power down right channel line-in preamplifier enabled right channel line-in preamplifier power down Def.
ENADCL ENADCR ENDACL ENDACR ENMICL ENMICR ENLINL ENLINR
Table
description
Name Value Description left channel line driver enabled left channel line driver power down (default) right channel line driver enabled right channel line driver power down (default) left channel headphones driver enabled left channel headphones driver power down (default) right channel headphones driver enabled right channel headphones driver power down (default) headphones reference voltage generator enabled headphones reference voltage generator power down (def) earphone amplifier enabled earphone amplifier power down (default) loudspeaker amplifier enabled loudspeaker amplifier power down (default) left channel analog output mixer enabled left channel analog output mixer power down (default) right channel analog output mixer enabled right channel analog output mixer power down (default) Def.
ENLOL ENLOR ENHPL ENHPR ENHPVCM 1ENEAR
2ENLS ENMIXL ENMIXR
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Control registers
STw5098
(hex) (03h) (04h) (05h) (06h) (07h) (08h) (09h) CR10 (0Ah) CR11 (0Bh) CR12 (0Ch) CR13 (0Dh)
Gains
Description gain left gain right Line gain left Line gain right gain gain gain gain digital gain left digital gain right digital gain left digital gain right
Def.
0000 0000 0000 0000 0000 1001 0000 1001 0000 0011 0000 0011 0000 0011 0000 0000 0000 0000 0000 1000 0000 1000
MICLA(2:0)
MICLG(4:0)
MICRA(2:0)
MICRG(4:0)
LINLG(4:0)
LINRG(4:0)
LOG(2:0)
LSG(3:0)
HPLG(4:0)
HPRG(4:0)
DACLG(5:0)
DACRG(5:0)
ADCLG(5:0)
ADCRG(5:0)
Table
Bits
description
Name Name Value description Left (CR3) right (CR4) channels microphone attenuation gain (default) -1.5 gain -3.0 gain .step -9.0 gain -12.0 gain Left (CR3) right (CR4) channels microphone gain gain (default) gain gain .step 39.0 gain Def.
MICLA(2:0) MICRA(2:0)
00000 00001 00010 11010
MICLG(4:0) MICRG(4:0)
00000
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STw5098 Table
Bits
Control registers description
Name Name
Value
description Left (CR5) right (CR6) channels line gain 18.0 gain 16.0 gain 14.0 gain .step gain (default) .step -20.0 gain
Def.
LINLG(4:0) LINRG(4:0)
00000 00001 00010 01001 10011
01001
Table
Bits
description
Name Value description Left right channel line drivers gain Gain differential output Equivalent single-ended gain 18.0 gain (default) -24.0 gain (default) -15.0 gain -21.0 gain -12.0 gain -18.0 gain .step .step gain -6.0 gain earphone gain/ loudspeaker gain gain gain gain gain (default) .step -24.0 gain Def.
LOG(2:0)
0000 0001 0010 0011 1111
1EARG(3:0)
2LSG(3:0)
0011
Table
Bits
description Name Name Value description Left (CR8) right (CR9) channels headphones driver gain gain -2.0 gain -4.0 gain -6.0 gain (default) .step -40.0 gain Def.
HPLG(4:0) HPRG(4:0)
00000 00001 00010 00011 10100
00011
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Control registers Table
Bits
STw5098
CR10 CR11 description
Value CR10 CR11 description Left (CR10) right (CR11) channels digital gain gain (default) -1.0 gain -2.0 gain -3.0 gain -4.0 gain -5.0 gain -6.0 gain -7.0 gain -8.0 gain -9.0 gain -10.0 gain -11.0 gain -12.0 gain -13.0 gain -14.0 gain -15.0 gain -16.0 gain -17.0 gain -18.0 gain -20.0 gain -22.0 gain -24.0 gain -26.0 gain -28.0 gain -30.0 gain -32.0 gain -34.0 gain -36.0 gain -38.0 gain -41.0 gain -44.0 gain -47.0 gain -50.0 gain -53.0 gain -56.0 gain -59.0 gain -65.0 gain gain Def.
Name CR10 Name CR11
DACLG(5:0) DACRG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101
000000
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STw5098 Table
Bits
Control registers CR12 CR13 description
Value CR12 CR13 description Left (CR12) right (CR13) channels digital gain gain gain gain gain gain gain gain gain gain (default) -1.0 gain -2.0 gain -3.0 gain -4.0 gain -5.0 gain -6.0 gain -7.0 gain -8.0 gain -9.0 gain -10.0 gain -11.0 gain -12.0 gain -14.0 gain -16.0 gain -18.0 gain -20.0 gain -22.0 gain -24.0 gain -26.0 gain -28.0 gain -30.0 gain -33.0 gain -36.0 gain -39.0 gain -42.0 gain -45.0 gain -48.0 gain -51.0 gain -57.0 gain gain Def.
Name CR12 Name CR13
ADCLG(5:0) ACDRG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110
001000
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Control registers
STw5098
(hex) CR14 (0Eh) CR15 (0Fh) CR16 (10h)
control
Description Bass/treble/deemphasis mixing gain mix/sidetone gain Def.
0000 0000 0000 0000
DYNC
TREBLE(2:0)
BASS(3:0)
DA2ADG(4:0)
AD2DAG(5:0)
0000 0000
Table
Bits
CR14 description
Name Value 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 CR14 description Audio dynamic compression path enabled Audio dynamic compression path disabled Treble control path +6.0 treble gain +4.0 treble gain +2.0 treble gain treble gain -2.0 treble gain -4.0 treble gain -6.0 treble gain De-emphasis filter enabled Bass control path +12.5 bass gain +10.0 bass gain +7.5 bass gain +5.0 bass gain +2.5 bass gain bass gain -2.5 bass gain -5.0 bass gain -7.5 bass gain -10.0 bass gain -12.5 bass gain Def.
DYNC
TREBLE(2:0)
BASS(3:0)
0000
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STw5098 Table
Bits
Control registers CR15 description
Name Value CR15 description mixing (Audio filter path selected) mixing disabled (default) +2.0 gain gain -2.0 gain -4.0 gain -6.0 gain -8.0 gain -10.0 gain -12.0 gain -14.0 gain -16.0 gain -18.0 gain -20.0 gain -22.0 gain -24.0 gain -26.0 gain -28.0 gain -30.0 gain -32.0 gain -34.0 gain -36.0 gain -38.0 gain -40.0 gain Def.
DA2ADG(4:0)*
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110
00000
When Voice filter path selected this function disabled Note: mixing performed data rate, rates different then asynchronous sampling artifacts occur.
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Control registers Table
Bits
STw5098
CR16 description
Name Value CR16 description mixing (sidetone) mixing disabled (default) -1.0 gain -2.0 gain -3.0 gain -4.0 gain -5.0 gain -6.0 gain -7.0 gain -8.0 gain -9.0 gain -10.0 gain -11.0 gain -12.0 gain -13.0 gain -14.0 gain -15.0 gain -16.0 gain -17.0 gain -18.0 gain -19.0 gain -20.0 gain -21.0 gain -22.0 gain -23.0 gain -24.0 gain -25.0 gain -26.0 gain -27.0 gain -28.0 gain -29.0 gain -30.0 gain -31.0 gain -32.0 gain -33.0 gain -34.0 gain -35.0 gain -36.0 gain -37.0 gain -38.0 gain -39.0 gain -40.0 gain -41.0 gain -42.0 gain Def.
AD2DAG(5:0)
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010
000000
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STw5098
Control registers
(hex) CR17 (11h) CR18 (12h) CR19 (13h)
Analog functions
Description Mixer switches Bias Input switches Drivers control Def.
0000 0000 0010 0100 0101 1000
MBIAS
MBIASPD
ADMIC
ADLIN
MIXMIC
MIXLIN
MIXDAC
MICLO
IN2VCM
LINMUTE
LINSEL(1:0)
MICMUTE
MICSEL(1:0)
VCML(1:0)
MUTELO
MUTEHP
LSLIM
LSSEL(1:0)
Table
Bits
CR17 description
Name Value CR17 description Microphone Bias enabled (2.1V MBIAS pin) Microphone Bias disabled MBIAS pulled down when microphone bias disabled MBIAS high impedance state when microphone Bias disabled Microphone preamplifiers connected path Microphone preamplifiers connected path Line preamplifiers connected path Line preamplifiers connected path Microphone preamplifiers connected mixers Microphone preamplifiers connected mixers Line preamplifiers connected mixers Line preamplifiers connected mixers Stereo path connected mixers Stereo path connected mixers Microphone preamplifiers connected line drivers Mixers connected line drivers Def.
MBIAS
MBIASPD
ADMIC ADLIN MIXMIC MIXLIN MIXDAC MICLO
Table
Bits
CR18 description
Name Value CR18 description Unused analog input pins biased common mode voltage Unused analog input pins high impedance state Line preamplifiers muted Line preamplifiers muted Input pins connected line preamplifiers LINMUTE=0) LINEIN (LINEINL, LINEINR) AUX1 (AUX1L, AUX1R) AUX2 (AUX2LP-AUX2LN, AUX2RP-AUX2RN) AUX3 (AUX3L, AUX3R) Def.
IN2VCM LINMUTE
LINSEL(1:0)
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Control registers Table
Bits
STw5098
CR18 description
Name Value CR18 description Microphone preamplifiers muted Microphone preamplifiers muted Input pins connected microphone preamplifiers MICMUTE=0) (MICLP-MICLN, MICRP-MICRN) AUX1 (AUX1L, AUX1R) AUX2 (AUX2LP-AUX2LN, AUX2RP-AUX2RN) AUX3 (AUX3L, AUX3R) Def.
MICMUTE
MICSEL(1:0)
Table
Bits
CR19 description
Name Value CR19 Description Common mode voltage level line headphones drivers 1.20 1.35 (default) 1.50 1.65 Line drivers muted Line drivers muted Headphones drivers (HP) muted Headphones drivers (HP) muted EAR/LS driver gain limited when VCCLS above 4.2V EAR/LS driver (LS) gain limited Mute Right Left Mono driver Loudspeaker driver (LS) muted Right channel mixer only connected loudspeaker driver Left channel mixer only connected loudspeaker driver (Left Right)/2 channel mixers connected loudspeaker Def.
VCML(1:0)
MUTELO MUTEHP 1EARLIM
2LSLIM 1EARSEL(1:0) 2LSSEL(1:0)
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STw5098
Control registers
(hex) CR20 (14h) CR21 (15h) CR22 (16h) CR23 (17h) CR24 (18h) CR25 (19h)
Digital audio interfaces master mode clock generators
Description DAOCK frequency DAOCK frequency clock generator control ADOCK frequency ADOCK frequency clock generator control
ADMAST DAMAST
Def.
0000 0000 0000 0000
DAOCKF(7:0)
DAOCKF(15:8)
MASTGEN
CK512
DAPCMF(1:0)
0000 0000 0000 0000 0000 0000
ADOCKF(7:0)
ADOCKF(15:8)
MASTGEN
DOCK
CK512
ADPCMF(1:0)
0000 0000
Table
Bits
CR21-20 CR24-23 description
Value CR21-20 CR24-23 Description following formulas used obtain value desired respectively clock generator
round
Name CR21-20 Name CR24-23
Def.
AMCK MCKCOEFF AMCK MCKCOEFF
15-0
DAOCKF(15:0) ADOCKF(15:0)
round
0000h
Data rate (DA_SYNC AD_SYNC frequency master mode) OCK: Oversampled clock frequency (DA_OCK AD_OCK) AMCK: Input master clock frequency MCKCOEFF: CR30 definition OSR: CR22 CR25
Note: CR21-20 CR24-23 meaningful master mode only.
Table
Bits
CR22 CR25 description
Value CR22 CR25 description (AD) Audio interface master mode (low impedance output) (AD) Audio interface slave mode (high impedance input) (AD) Master generator enabled (AD) Master generator disabled DA_OCK (AD_OCK) output clock enabled DA_OCK (AD_OCK) output clock disabled Def.
Name CR22 (Name CR25) DAMAST (ADMAST) DAMASTGEN (ADMASTGEN) ENDAOCK (ENADOCK)
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Control registers Table
Bits
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CR22 CR25 description
Value CR22 CR25 description Definition DA_OSR (AD_OSR) DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) ratio master mode da_ock/da_sync (ad_ock/ad_sync) ratio master mode DA_CK/DA_SYNC (AD_CK/AD_SYNC) Ratio master mode when CR26 DAWL=000 (CR27 ADWL=000) when CR26 DAWL000 (CR27 ADWL000) when CR22 DAOCK512=0 (CR25 ADOCK512=0) when CR22 DAOCK512=1 (CR25 ADOCK512=1) Def.
Name CR22 (Name CR25)
DAOCK512 (ADOCK512)
DAPCMF(1:0) (ADPCMF(1:0))
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Control registers
(hex) CR26 (1Ah) CR27 (1Bh) CR28 (1Ch)
Digital audio interfaces
Description data control data control DAC&ADC data control Def.
0000 0000 0000 0000 0000 0000
DAFORM(2:0)
DASPIM
DAWL(2:0)
ADRTOL
ADFORM2:0)
ADSPIM
ADWL(2:0)
AMCKINV
DACKP
DASYNCP
DAMONO
ADCKP
SYNCP
ADMONO
ADHIZ
Table
Bits
CR26 description
Name Value CR26 Description audio interface format selection Delayed format (I2S compatible) Left aligned format Right aligned format format format format (uses left channel) interface mode receives word both channels interface mode receives words (alternated, left channel first) interface word length Def.
DAFORM(2:0)
DASPIM
DAWL(2:0)
Table
Bits
CR27 description
Name Value CR27 description right channel sent (must ENADCR=0 CR1) Normal operation audio interface format selection Delayed format (I2S compatible) Left aligned format Right aligned format format format format (sends left channel) Def.
ADRTOL
ADFORM(2:0)
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Control registers Table
Bits
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CR27 description (continued)
Name Value CR27 description interface mode sends channel (left) interface mode sends channels (alternated, left first) interface word length Def.
ADSPIM
ADWL(2:0)
Table
Bits
CR28 description
Name Value AMCK inverted AMCK inverted clock (DA_CK) polarity inverted clock (DA_CK) polarity inverted formats interface delayed format Delayed format Delayed, left-aligned, right-aligned formats interface sync (DA_SYNC) polarity inverted sync (DA_SYNC) polarity inverted Mono mode: (L+R)/2 from Audio Interface used both channels Stereo mode clock (AD_CK) polarity inverted clock (AD_CK) polarity inverted formats interface delayed format Delayed format Delayed, left-aligned, right-aligned formats interface sync (DA_SYNC) polarity inverted sync (DA_SYNC) polarity inverted Mono mode: (L+R)/2 from sent both channels Audio interface Stereo mode data (AD_DATA) high impedance state when data available data (AD_DATA) forced when data available CR28 description Def.
AMCKINV DACKP
DASYNCP
DAMONO
ADCKP
ADSYNCP
ADMONO
ADHIZ
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Control registers
(hex) CR29 (1Dh) CR30 (1Eh)
Digital filters, software reset master clock control
Description Digital filters control Soft reset AMCK range Def.
0000 0000 0000 0000
DAVOICE
DA96K
RXNH
ADVOICE
AD96K
ADNH
TXNH
SWRES
AMCKSIN
CKRANGE(2:0)
Table
Bits
CR29 description
Name Value CR29 description path voice filter enabled (single channel, left used) path voice filters enabled path data rate range path data rate range path high pass voice filter disabled path high pass voice filter enabled (300Hz 8kHz rate) path voice filter enabled (single channel, left used) path audio filters enabled path data rate range path data rate range path audio filter disabled path audio filter enabled path high pass voice filter disabled path high pass voice filter enabled (300Hz 8kHz rate) Def.
DAVOICE DA96K RXNH ADVOICE AD96K ADNH TXNH
Table
Bits
CR30 description
Name Value CR30 description Software reset: registers content reset default value Control Register content left unchanged Signal AMCK sinusoid Signal AMCK square wave AMCK range 12.0 12.0 16.0 16.0 24.0 24.0 32.0 MCKCOEFF Def.
SWRES AMCKSIN
CKRANGE(2:0)
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Control registers
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(hex) CR31 (1Fh) CR32 (20h) CR33 (21h)
Interrupt control control interface mode
Description Interrupt mask Interrupt status Misc. control
PUSH
PUSH BMSK
HSDET
Def.
0000 0000 0000 0000 0000 0000
VLSHEN
HSDETEN VLSHMSK
OVFMSK
PORMSK
VLSH
PUSHB
HSDET
VLSHEV
PUSHBEV HSDETEV
OVFEV
POREV
SPIOHIZ
SPIOSEL(1:0)
IRQCMOS
OVFDA
OVFAD
Table
Bits
CR31 description
Name Value CR31description VLSH status seen output VLSH status masked PUSHB status seen output PUSHB status masked HSDET status seen output HSDET status masked VLSH event seen output VLSH event masked PUSHB event seen output PUSHB event masked HSDET event seen output HSDET event masked event seen output event masked event seen output event masked Def.
VLSHEN PUSHBEN HSDETEN VLSHMSK PUSHBMSK HSDETMSK OVFMSK PORMSK
Note:
Value
when (CR31 CR32) when (CR31 CR32)
Table
Bits
CR32 description
Name Read only VCCLS above VCCLS below Headset Button pressed Headset Button released Headset Connector inserted Headset Connector inserted CR32 description Def.
VLSH* PUSHB* HSDET*
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STw5098 Table
Bits
Control registers CR32 description (continued)
Name Read only CR32 description VLSH changed VLSH changed Headset Button Status changed Headset Button Status changed Headset Connector Status changed Headset Connector Status changed Audio Data overflow occurred Audio Data overflow occurred Device reset power-on-reset Device reset power-on-reset Def.
VLSHEV PUSHBEV HSDETEV OVFEV POREV
Note: content bits CR32 cleared after reading, while left unchanged accessed writing. *Bits represent status when Control register read, when event occurred.
Table
Bits
CR33 description
Name Val. CR33 description control interface high impedance state when inactive control interface zero when inactive selection control interface output. Control registers cannot read mode output sent output sent DA_OCK output sent AD_OCK interrupt request CMOS (active low) interrupt request pull down overflow (saturation) occurred path overflow occurred channel overflow (saturation) occurred path overflow occurred channel Def.
SPIOHIZ
SPIOSEL(1:0)
IRQCMOS OVFDA OVFAD
Note: content bits CR33 cleared after reading, while left unchanged accessed writing.
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Control registers
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5.10
(hex) CR34 (22h) CR35 (23h)
Description attack/decay coeff. control
Def. 0000 0000 0000 0000
AGCATT(3:0)
AGCDEC(3:0)
ENAG CLIN
ENAG CMIC
RANGE
AGCLEV(3:0)
Table
Bits
description
Name Value description attack time constant; FS=AD data rate 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Audio filter path 4096 2048 1365 1024 Voice filter path 8192 4096 2731 2048 1365 1024 Def.
AGCATT(3:0)
0000
decay time constant; FS=AD data rate 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Audio filter path 65536 32768 21845 16384 10923 8192 5461 4096 2731 2048 1365 1024 Voice filter path 131072 65536 43691 32768 21845 16384 10923 8192 5461 4096 2731 2048 1365 1024
AGCDEC(3:0)
0000
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STw5098 Table
Bits
Control registers description
Name Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 CR35 description control path acts Line Gain control path does Line Gain control path acts Gain control path does Gain action range -21.0 +21.0 action range -10.5 +10.5 requested output level -30.0 gain -30.0 gain -27.0 gain -24.0 gain -21.0 gain -18.0 gain -15.0 gain -12.0 gain -9.0 gain -6.0 gain Def.
ENAGCLIN ENAGCMIC AGCRANGE
AGCLEV(3:0)
0000
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Control interface master clock
STw5098
Control interface master clock
Unless specified, following description applies both entities.
Figure
WRITE SINGLE BYTE
Control interface mode
Control interface format
DEVICE ADDRESS ADDRESS START
DATA STOP
WRITE MULTI BYTE
DEVICE ADDRESS ADDRESS DATA DATA START data bytes STOP
CURRENT ADDR READ SINGLE BYTE CURRENT ADDR READ MULTI BYTE
DEVICE ADDRESS Current DATA START STOP DEVICE ADDRESS Current DATA Curr REG+m DATA data bytes START STOP
RANDOM ADDR READ SINGLE BYTE RANDOM ADDR READ MULTI BYTE
DEVICE ADDRESS ADDRESS DEVICE ADDRESS DATA START START STOP DEVICE ADDRESS ADDRESS DEVICE ADDRESS DATA DATA START START data bytes STOP
Note:
Figure
CMOD tied
Control interface: format timing
tBUF
(STA)
tLOW
(DAT)
tHIGH
(DAT)
(STA)
(STA)
(STO)
SCLK
STOP START START repeated
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STw5098 Table
Symbol fSCL tHIGH tLOW tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF
Control interface master clock Control interface timing with format
Parameter Clock frequency Clock pulse width high Clock pulse width SCLK rise time SCLK fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time free time 1300 1300 1000 Test conditions Min. Typ. Max. Unit
Control interface mode
Figure
SCLK
Control interface format(a)
SDIN
Address
Data
SPIOHIZ=1
Data
CMOD tied VCCIO; position selected with bits SPIOSEL CR33.
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Control interface master clock Figure Control interface: format timing
tHICS tSCSF tPSCK tLSCK SCLK tSDI tHDI tHSCK tHCS
STw5098
tSCSR
SDIN
tDDOF SPIOHIZ=1 SPIOHIZ=0
tDDO
tDDOL
Table
Symbol tHICS tSCSR tSCSF tHCS tSDI tHDI tDDOF tDDO tDDOL tPSCK tHSCK tLSCK
Control interface signal timing with format
Parameter pulse width high Setup time rising edge SCLK rising edge Setup time falling edge SCLK rising edge Hold time rising edge from SCLK rising edge Setup time SDIN SCLK rising edge Hold time SDIN from SCLK rising edge first Delay time from SCLK falling edge Delay time from SCLK falling edge Delay time from rising edge Period pulse width high pulse width Measured from Measured from Test conditions Min. Typ. Max. Unit
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Control interface master clock
Table
Symbol tCKDC
Master clock timing
AMCK timing
Parameter AMCK duty cycle AMCK range MHz-8 MHz-32 Min. Typ. Max. Unit
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Audio interfaces
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Audio interfaces
Information included following section valid both entities.
Figure
Audio interfaces formats: delayed, left right justified
format (delayed) with default polarity settings, ADHIZ=0
DA_SYNC/ AD_SYNC DA_CK/ AD_CK AD_CK/DA_CK DA_DATA n-bit word Left data n-bit word Left data
AD_CK/DA_CK
n-bit word Right data n-bit word Right data
AD_DATA
Left justified format with default polarity settings, ADHIZ=0
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA n-bit word Left data n-bit word Left data n-bit word Right data n-bit word Right data
AD_DATA
Right justified format with default polarity settings
AD_CK/DA_CK DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA n-bit word Left data
n-bit word Left data
AD_CK/DA_CK
n-bit word Right data n-bit word Right data
AD_DATA
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STw5098 Figure Audio interfaces formats: DSP,
format delayed non-delayed (default AD_CK/DA_CK polarity, ADHIZ=0)
Audio interfaces
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
SYNCP=0 SYNCP=1
n-bit word Left data n-bit word Right data n-bit word Left data n-bit word Right data
AD_DATA
format (slave only) (default AD_CK/DA_CK polarity, ADHIZ=1 Stereo Mono)
DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA
n-bit word Left/Mono data n-bit word Left/Mono data High impedance n-bit word Right/Mono data n-bit word Right/Mono data
AD_DATA
format (default AD_CK/DA_CK polarity, ADHIZ=1)
DA_SYNC/ AD_SYNC
SYNCP=0 SYNCP=1
DA_CK/ AD_CK DA_DATA
n-bit word Mono data n-bit word Mono data High impedance
AD_DATA
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Audio interfaces Figure Audio interface timings: master mode
DA_SYNC/ AD_SYNC tDSY
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DA_CK/ AD_CK
CKP=0
CKP=1 tSDDA tHDDA
DA_DATA tDAD AD_DATA format only ADHIZ=1 ADHIZ=0 tDAD AD_DATA other formats ADHIZ=1 ADHIZ=0 ADHIZ=1 ADHIZ=0 tDAD tDADZ ADHIZ=1 ADHIZ=0
Figure Audio interface timing: slave mode
DA_SYNC/ AD_SYNC tHSY tSSY
DA_CK/ AD_CK
CKP=0 tHCK CKP=1 tSDDA tHDDA tPCK tLCK
DA_DATA tDADST ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 tDAD ADHIZ=1 ADHIZ=0 tDAD tDADZ ADHIZ=1 ADHIZ=0
AD_DATA format
AD_DATA other formats
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STw5098 Table
Symbol
Audio interfaces Audio interface signal timings
Parameter Test conditions Min. Typ. Max. Unit
tDSY
Delay AD_SYNC/DA_SYNC Master Mode edge from AD_CK/DA_CK active edge Setup time DA_DATA DA_CK active edge Hold time DA_DATA from DA_CK active edge Delay AD_DATA edge from AD_CK active edge Delay first AD_DATA AD_SYNC active edge comes edge from AD_SYNC after AD_CK active edge active edge Delay AD_DATA high impedance from AD_SYNC inactive edge Setup time AD_SYNC/DA_SYNC AD_CK/DA_CK active edge format
tSDDA tHDDA tDAD
tDADST
tDADZ
tSSY
Slave Mode
tHSY
Hold time AD_SYNC/DA_SYNC from Slave Mode AD_CK/DA_CK active edge Period AD_CK/DA_CK AD_CK/DA_CK pulse width high AD_CK/DA_CK pulse width Slave Mode Measured from Measured from
tPCK tHCK tLCK
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Timing specifications
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Timing specifications
Information included this section valid both entities. Unless otherwise specified, VCCIO 1.71V 2.7V, Tamb -30°C 85°C, capacitive load typical characteristics specified VCCIO Tamb signals referenced GND, Note below figure timing definitions. Figure A.C. testing input-output waveform
Input/output TEST POINTS
Testing: inputs driven logic logic `0'. Timing measurements made logic logic `0'.
Note:
signal valid above below invalid between VIH. purpose this specification following conditions apply (see Figure above): input signal defined VCCIO, VCCIO, 10ns, 10ns. Delay times measured from inputs signal valid output signal valid. Setup times measured from data input valid clock input invalid. Hold times measured from clock signal valid data input invalid. timing specifications subject change.
Note:
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Operative ranges
Table
Operative ranges
Absolute maximum ratings
Absolute maximum ratings
Parameter Value -0.5 -0.5 -0.5 GND-0.5 VCCA+0.5 GND-0.5 VCCIO+0.5 Human body model(2) Charge device model(3) -500 +500 Unit
VCCIO VCCA VCCP VCCLS Voltage analog inputs (VCCA 3.3V) Maximum power delivered load from LSP/N Peak current HPR,HPL Current VCCP, VCCLS, GNDP Current digital output Voltage digital input (VCCIO 2.7V); limited 50mA Storage temperature range Operating temperature range(1)
Electrostatic discharge voltage (Vesd)
some operating conditions temperature limited loudspeaker driver description from Section 4.10 details. tests have been performed compliance with JESD22-A114-B S5.1-2001.HBM tests have been performed compliance with ANSI-ESDSTM5.3.1-1999
Table
Symbol VCCA VCCIO VCCP VCCLS
Operative supply voltage
Operative supply voltage
Parameter Digital supply Analog supply Note: VCCA Digital supply Stereo power drivers supply Mono power driver supply Single supply voltage range VCC=VCCA=VCCIO=VCCP=VCCLS A24V=1 (bit CR0) A24V=0 (bit CR0) A24V=1 (bit CR0) D12V=0 (bit CR0) D12V=1 (bit CR0) Condition Min. 1.71 1.71 VCCA VCCA Max. Unit
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Operative ranges
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Power dissipation
Unless otherwise specified, VCCP VCCLS VCCA 2.7V 3.3V, VCCIO 1.71V 2.7V, Tamb -30°C 85°C, analog outputs loaded; typical characteristics specified VCCIO 1.8V, VCCP VCCLS VCCA 2.7V, Tamb 25°C.
Table
Symbol POFF PDAAD
Power dissipation
Parameter Power Down Dissipation Stereo power Stereo power Stereo ADC+DAC power Stereo Analog Path power Test conditions Master Clock AMCK=13MHz Min. Typ. 52.6 46.6 93.8 27.6 Max. Unit
Typical power dissipation entity
Tamb 25°C; Analog Supply: VCCP VCCLS VCCA 2.7V; digital supply: VCCIO 1.8V. Full scale signal every path, load analog outputs.
master clock
Table
Typical power dissipation, master clock
Function CR0-CR2 setting CR0=0x00 CR1=0x00 CR2=0x00 CR0=0xD0 CR1=0x0C CR2=0xC0 CR0=0xD0; CR1=0x0C; CR2=0xC3 MICLO=1 MICSEL=2 MIXMIC=1 MICSEL=2 Other settings Supply Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Current 0.02 0.20 Power 0.05 0.36 0.41 11.6 11.6 14.6 14.6
Power Down
Stereo analog path (Mic-LO) Stereo analog path (Mic-Mixer-LO)
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Operative ranges
Master clock AMCK
Table
Typical power dissipation with master clock AMCK
Function CR0-CR2 setting CR0=0x00 CR1=0x00 CR2=0x00 CR0=0xE8 CR1=0xCC CR2=0x00 CR0=0xE8 CR1=0x30 CR2=0x33 CR0=0xE8 CR1=0x0C CR2=0xC0 CR0=0xE8 CR1=0xFC CR2=0x33 CR0=0xE8 CR1=0xFF CR2=0xF3 CR0=0xE8 CR1=0xA8 CR2=0x06 MICSEL=1 ADMIC=1 Other settings Supply Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: Analog: Digital: Total: VCCA,VCCP: VCCLS: Digital Total: Current 0.02 2.20 13.5 15.2 Power 0.05 3.96 4.01 21.3 26.3 16.5 23.3 13.0 13.8 36.5 10.4 46.9 41.0 10.4 51.4 18.4 28.4
Power Down
Stereo
Stereo
MIXDAC=1
Stereo analog path (Mic-LO) Stereo Stereo Stereo Stereo Stereo analog path
MICLO=1 MICSEL=2 MICSEL=2 ADMIC=1 MIXDAC=1 LINSEL=2; MICSEL=2 ADLIN=1;MIXDAC=1 MICLO=1 MICSEL=2; LSMODE=2 ADMIC=1 MIXDAC=1 ADVOICE=1 DAVOICE=1
Voice TX+RX
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Electrical characteristics
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Electrical characteristics
Unless otherwise specified, VCCIO 1.71V 2.7V, Tamb -30°C 85°C; typical characteristic specified VCCIO 2.0V, Tamb 25°C; signals referenced GND.
10.1
Table
Symbol
Digital interfaces
Digital interfaces specifications
Parameter Input voltage Input high voltage Output voltage Output high voltage Input current Input high current Output current high impedance (Tristate) Test conditions digital inputs digital inputs, digital outputs digital outputs 10µA 10µA VCCIO-0.1 VCCIO-0.4 Min. Typ. Max. Unit
digital input, digital input, VCCIO Tristate outputs
Note:
Figure A.C. testing input-output waveform page
10.2
Table
Symbol CAMCK VAMCK
AMCK with sinusoid input
AMCK with sinusoid input specifications
Parameter Minimum External Capacitance AMCK sinusoidal voltage swing Test conditions AMCKSIN=1, CR30 AMCKSIN=1, CR30 Min. VCCIO Typ. Max. Unit
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Electrical characteristics
10.3
Table
Symbol IMIC RMIC RLIN RLHP RLEAR RLLS CLHP CLEAR CLLS VOFFLS VOFFEAR
Analog interfaces
Information below each entity. Analog interface specifications
Parameter input leakage input resistance Line input resistance Headphones (HP) drivers load resistance Earphone (EAR) drivers load resistance Loudspeaker (LS) drivers load resistance Headphones (HP) drivers load capacitance Earphone (EAR) drivers load capacitance Loudspeaker (LS) drivers load capacitance Differential offset voltage 2LSP, 2LSN Differential offset voltage 1EARP, 1EARN Line (OL) diff./singleended driver load resistance HPL, GNDP VCMHP EARP 1EARN 2LSP 2LSN HPL, GNDP VCMHP EARP 1EARN 2LSP 2LSN OLP/ORP OLN/ORN OLP/ORP (decoupled) Test conditions GND< VMIC< VCCA Min. -100 14.4 16/32 Typ. Max. +100 Unit
RLOL
with series resistor
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Electrical characteristics
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10.4
Table
Symbol HDVL HDVH PBVL PBVH
Headset plug-in push-button detector
Information below each entity. Headset plug-in push-button detector specifications
Parameter Plug-in detected Plug-in undetected Plug-in detector hysteresis Push-button pressed Push-button released Push-button de-bounce time Voltage HDET Voltage HDET Test conditions Voltage HDET Voltage HDET VCCA-0.5 Min. Typ. Max. VCCA-1 Unit
10.5
Table
Symbol VMBIAS IMBIAS RMBIAS CMBIAS PSRMB4 PSRMB20
Microphone bias
Information below each entity. Microphone bias specifications
Parameter MBIAS output voltage MBIAS output current MBIAS output load MBIAS output capacitance MBIAS power supply rejection f<4kHz f<20kHz From MBIAS ground Test conditions Min. 1.95 Typ. Max. 2.25 Unit
10.6
Table
Symbol PSRL20 PSRL200 PSRPH PSRPOS PSRPOD PSRAM PSRAL
Power supply rejection ratio
Power supply rejection ratio specifications
Parameter PSRR VCCLS Test conditions Each output (LSP, LSN) f<20kHz f<200kHz Headphones f<20kHz Line single ended f<20kHz Line differential f<20kHz input f<20kHz Line f<20kHz Min. Typ. Max. Unit
PSRR VCCP
PSRR VCCA
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Electrical characteristics
10.7
Table
Symbol VLSLIMH VLSLIML VLSLIMD
gain limiter
Information below each entity. gain limiter
Parameter High voltage VCCLS (VLSH=1) voltage VCCLS (VLSH=0) VCCLS Hysteresis Test conditions VCCLS raising VCCLS falling Min. Typ. Max. Unit
Note: CR32 VLSH definition. Loudspeaker driver description Section 4.10 details.
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Analog input/output operative ranges
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Analog input/output operative ranges
Information included this section applies both entities.
11.1
Table
Symbol
Analog levels
Reference full scale analog levels
Parameter 0dBFS level 0dBFS level voltage mode Test conditions 2.7V VCCA 3.3V 2.4V VCCA 2.7V Min. Typ. 3.18 Max. Unit dBVpp dBVpp
11.2
Table
Symbol
Microphone input levels
Analog supply range: VCCA Microphone input levels, absolute levels pins connected preamplifiers
Parameter Overload level, single ended Overload level, single ended, versus gain Overload level, differential Test conditions gain Min. Typ. (MIC_Gain) 1.41 (MIC_Gain) Max. Unit mVRMS dBFS dBFS mVRMS dBFS dBFS
gain
gain
Overload level, differential, gain versus gain
Note: When VCCA voltage values reduced 2dB.
Table
Symbol
Microphone input levels, absolute levels pins connected line-in amplifiers
Parameter Overload level, single ended Overload level (single ended) versus line gain Test conditions Line gain from 20dB Min. Typ. (Line_In_Gain) 1.41 Max. Unit mVRMS dBFS dBFS mVRMS dBFS
Line gain
Overload level (differential) Line gain from 20dB
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STw5098 Table
Symbol
Analog input/output operative ranges Microphone input levels, absolute levels pins connected line-in amplifiers
Parameter Test conditions Min. Typ. (Line_In_Gain) Max. Unit dBFS
Overload level (differential) Line gain versus line gain
Note: When VCCA values reduced
11.3
Table
Symbol
Line output levels
Analog supply range: VCCA Absolute levels OLP/OLN, ORP/ORN
Parameter Output level, single ended Test conditions gain Full scale digital input gain Full scale digital input Min. Typ. 1.41 Max. Unit mVRMS dBFS mVRMS dBFS
Output level, differential
Note: When VCCA values reduced
11.4
Table
Symbol
Power output levels
Analog supply range: VCCA Absolute levels
Parameter Test conditions -6dB gain Full scale digital input load VCCP Min. Typ. Max. Unit mVRMS dBFS
Output level
output power(1)
some operating conditions maximum output power limited. "Section 9.1: Absolute maximum ratings" "loudspeaker driver" description from Section 4.10: Analog output drivers details. Note: When VCCA values reduced
11.5
Power output levels
Analog supply range: VCCA
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Analog input/output operative ranges Table
Symbol
STw5098
Absolute levels 1EARP-1EARN 2LSP 2LSN
Parameter Test conditions gain Full scale digital input load VCCLS load VCCLS Min. Typ. 1.41 Max. Unit VRMS dBFS
Output level
output power output power(1)
some operating conditions maximum output power limited. "Section 9.1: Absolute maximum ratings" "loudspeaker driver" description from Section 4.10: Analog output drivers details. Note: When VCCA values reduced
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Stereo audio specifications
Stereo audio specifications
Information included this section applies both entities. Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8 Tamb=25° C;13 AMCK
Table
Symbol ADDRM ADDRLI
Stereo audio specifications
Parameter Resolution 20Hz 20kHz, A-weighted Measured -60dBFS input, 21dB gain Line-In, gain level input, 21dB gain A-weighted Unweighted kHz) A-weighted Input referred noise input gain input 21dB gain input 39dB gain Line input gain Line input 18dB gain level input, 21dB gain Measurement bandwidth 20Hz 20kHz, 48kHz. Combined digital analog filter characteristics Combined digital analog filter characteristics AD96K=0 Combined digital analog filter characteristics AD96K=0 Combined digital analog filter characteristics AD96K=0 Measurement bandwidth 3.45Fs. Combined digital analog filter characteristics, AD96K=0 Audio filters, 96kHz Audio filters, 48kHz Audio filters, 8kHz 0.55Fs 0.001 0.003 Test conditions Min. Typ. Max. Unit Bits
Dynamic range
ADSNA ADSN
Signal noise ratio
ADTHD
Total harmonic distortion Deviation from linear phase
ADfPB
Passband Passband ripple
0.45Fs
ADfSB
Stopband Stopband Attenuation
0.11
ADtgd
Group delay Interchannel isolation Interchannel gain mismatch Gain error
Note: When VCCA values reduced
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Stereo audio specifications
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Stereo audio specifications
Information included this section applies both entities. Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz AMCK
Table
Symbol
Stereo audio specifications
Parameter Resolution 20Hz 20kHz, A-weighted. Measured -60dBFS Differential line Single-ended line HPL/HPR VCMHP LSP-LSN Test conditions Min. Typ. Max. Unit Bits
DADR
Dynamic range
DASNA DASN
2Vpp output HPL, gain -6dB, load Signal noise ratio A-weighted Unweighted kHz) Total harmonic distortion Worst case load Total harmonic distortion Deviation from linear phase 2Vpp output HPL, gain -6dB, load 2Vpp output, HPL, gain -6dB, load Measurement bandwidth 20Hz 20kHz, 48kHz. Combined digital analog filter characteristics Combined digital analog filter characteristics, DA96K=0 Combined digital analog filter characteristics, DA96K=0 Combined digital analog filter characteristics, DA96K=0 Measurement bandwidth 3.45Fs. Combined digital analog filter characteristics, DA96K=0 0.55Fs
0.02 0.04
DATHDL
DATHD
0.004
DAfPB
Passband Passband ripple
0.45Fs
DAfSB
Stopband
Stopband attenuation Transient suppression filter cut-off frequency band noise
Measurement bandwidth kHz. Zero input signal
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STw5098 Table
Symbol
mixing (sidetone) specifications Stereo audio specifications (continued)
Parameter Test conditions Audio filters, 96kHz Audio filters, 48kHz Audio filters, 8kHz 2Vpp output HPR, unloaded HPR, with VCMHP Min. Typ. 0.09 FS=48 Line HPL/R Max. Unit
DAtgd
Group delay
Interchannel isolation Interchannel gain mismatch Gain error Startup time from power
Note: When VCCA values reduced
mixing (sidetone) specifications
Information included this section applies both entities. Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz AMCK.
Table
Symbol STDEL
mixing (sidetone) specifications
Parameter mixing (sidetone) delay Test conditions Valid audio voice filters Min. Typ. Max. Unit
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Stereo analog-only path specifications
STw5098
Stereo analog-only path specifications
Information included this section applies both entities. Measured differential line-out, ENOSC=1, master clock. Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25°
Table
Symbol
Stereo analog-only path specifications
Parameter Test conditions 20Hz 20kHz, A-weighted. Measured -60dBFS input, 21dB gain Line-In, gain level line-in input, gain, A-weighted Unweighted kHz) 1kHz 0dBFS input, 21dB gain Line-in input, gain 0.003 0.004 0.01 0.02 Min. Typ. Max. Unit
AADRM AADRLI
Dynamic range
AASNA AASN
Signal noise ratio
AATHD
Total harmonic distortion
Note: When 2.4V<VCCA<2.7V, values reduced 2dB.
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STw5098
(TX) (RX) specifications with voice filters selected
(TX) (RX) specifications with voice filters selected
Information included this section applies both entities. Typical measures VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25° C;13MHz AMCK
Table
Symbol
(TX) (RX) specifications with voice filters selected
Parameter Test conditions 300Hz 3.4kHz; 1kHz -60dBFS Path, input, 21dB gain Path, Output, gain 300Hz 3.4kHz; 1kHz 0dBFS Path, input, 21dB gain Path, outputs, gain 1kHz 0dBFS Path, input, 21dB gain Path, outputs, gain f=60Hz f=100Hz f=200Hz f=300Hz f=400Hz-3000Hz f=3400Hz f=4000H f=4600Hzz f=8000Hz f=60Hz f=100Hz f=200Hz f=300Hz f=400Hz-3000Hz f=3400Hz f=4000Hz f=5000Hz Measurement bandwidth 4kHz 100kHz. Zero input signal path path Min. Typ. Max. Unit
TXDR RXDR TXSN RXSN
Dynamic range
<0.001 0.005 0.32 0.28
Signal noise ratio
gain mask
-1.5 -0.5 -1.5
gain mask
-1.5 -0.5 -1.5
band noise Group delay
Note: When 2.4V<VCCA<2.7V, values reduced
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Typical performance plots
STw5098
Typical performance plots
Figure Dynamic compressor transfer function
Output Amplitude [FS] Frequency [Hz] 0.75 0.25 -0.25 -0.5 -0.75 -0.75-0.5-0.25 0.25 0.75 Input Amplitude [FS] Audio signal transfer function when Dynamic Compressor active.
Figure Bass treble control, de-emphasis filter
Gain Fs=44.1 [dB]
Bass treble gains independently selectable combination. de-emphasis filter (thick line, alternative treble control) compensates pre-emphasis used some audio CDs. Gain error 0.1dB. Filter characteristics Fs=44.1kHz plotted
Figure audio path measured filter response
Gain [dB] Frequency [Hz] 100k
Figure band audio path measured filter response
-0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
Frequency [Hz]
sample rate. Full path Frequency response kHz.
Sample Rate. band Frequency response
Figure digital audio filter characteristics
Gain [dB] Frequency [Hz] 100k
Figure band digital audio filter characteristics
-0.1 -0.2 -0.3 -0.4 -0.5 Frequency [Hz] Sample Rate band Frequency response
DA96K=0; Sample Rate Frequency response 166kHz (3.45 48kHz sampling rate)
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Gain [dB]
STw5098 Figure audio path measured filter response
Gain [dB] Frequency [Hz] 100k Gain [dB]
Typical performance plots Figure audio in-band measured filter response
Frequency [Hz]
plot extended down show high pass filter implemented sample rate, audio filter selected signal from input
sample rate, audio filter selected signal from input.
Figure voice path measured filter response
Gain [dB] Frequency [Hz]
Figure voice path measured inband filter response
-0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
1500 2500 Frequency [Hz]
3500
Sample rate, voice filter selected. Signal from input
sample rate, voice filter selected signal from input.
Figure voice (RX) digital filter characteristics
Gain [dB] Frequency [Hz]
Figure voice (RX) in-band digital filter characteristics
-0.1 -0.2 -0.3 -0.4 -0.5
Gain [dB]
1500 2500 Frequency [Hz]
3500
sample rate, voice filter
sample rate, voice filter
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Typical performance plots Figure path
Amplitude [dBFS] [dB] -100 -120 Frequency [Hz]
STw5098 Figure versus input-level
Input Level [dBFS]
master clock. Differential input preamplifier, gain. sampling rate. Both channels active
master clock Differential input Line-In Amplifier, gain. Sampling Rate A-Weighted, Both channels active
Figure path
Amplitude [dBFS]
Figure versus input-level
[dB]
-100 -120 Frequency [Hz]
Input Level [dBFS]
master clock. sampling rate Differential output line-out, load. Both channels active
master clock. Sampling Rate Differential output Line-Out, load.
A-Weighted, Both channels active
Figure Analog path
Amplitude [dBFS]
Figure Analog path versus input-level
[dB]
-100 -120 Frequency [Hz]
Input Level [dBFS]
Differential input Preamplifier, gain. Direct Line-Out connection (MICLO=1) Differential output Line-Out, load. Both channels active
Differential input Line-In Amplifier, gain. Line-In DA-Mixer Line-Out connection. Differential output Line-Out, load. A-weighted, both channels active
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STw5098
Package mechanical data
Package mechanical data
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have Lead-free second level interconnect. category second Level Interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com.
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Package mechanical data
STw5098
18.1
LFBGA 6x6x1.4
Table
Reference Min. 5.85 0.25 5.85 0.30 6.00 5.00 6.00 5.00 0.50 0.50 0.08 0.15 0.05 6.15 5.90 0.15 0.985 0.20 0.80 0.35 6.15 Typ. Max. 1.40 0.16 0.93 0.16 0.77 0.25 5.90 0.21 0.985 0.20 0.785 0.30 6.00 5.00 6.00 5.00 0.50 0.50 0.08 0.15 0.05 6.10 Min. Typ. Max. 1.26 0.26 1.04 0.24 0.80 0.35 6.10
Dimensions LFBGA 6x6x1.4 4R11x11.
Databook (mm) Drawing (mm) Notes
Note
Note
Note Note
Note:
LFBGA stands Profile Fine Pitch Ball Grid Array. profile: total profile height (DIm measured from seating plane component. maximum total package height calculated follows: A2Typ A1Typ tolerancevalues Fine pitch: e<1.0 pitch typical ball diameter before mounting 0.30 tolerance position that controls location pattern balls with respect datum each ball there cylindrical tolerance zone perpendicular datum located true position with respect datum defined axis perpendicular datum each ball must within this tolerance zone. tolerance position that controls location balls within matrix with respect each other. each ball there cylindrical tolerance zone perpendicular datum located true position defined axis perpendicular datum each ball must within this tolerance zone. Each tolerance zone array contained entirely respective zone above. axis each ball must simultaneously both tolerance zones. terminal corner must identified surface using corner chamfer, metallized markings, other feature package body integral heatslug. distinguishing feature allowable bottom surface package identify terminal corner. Exact shape each corner optional.
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STw5098 Figure LFBGA 6x6x1.4 4R11x11 drawing
Package mechanical data
(112 BALLS)
BOTTOM VIEW
CORNER INDEX AREA (SEE NOTE
SEATING PLANE
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Package mechanical data
STw5098
18.2
VFBGA 5x5x1.0
Table
Reference Min. 4.95 0.22 4.95 0.26 5.00 4.00 5.00 4.00 0.40 0.50 0.08 0.13 0.04 5.05 4.95 0.125 0.765 0.18 0.60 0.30 5.05 Typ. Max. 1.00 0.125 0.71 0.14 0.57 0.22 4.95 0.165 0.765 0.18 0.585 0.26 5.00 4.00 5.00 4.00 0.40 0.50 0.08 0.13 0.04 5.05 Min. Typ. Max. 0.99 0.205 0.82 0.22 0.60 0.30 5.05
Dimensions VFBGA 5x5x1.0 balls pitch
Databook (mm) Drawing (mm) Notes
Note
Note
Note
Note Note
Note:
VFBGA stands Very thin Profile Fine Pitch Ball Grid Array. maximum total package height calculated following methodology: A2Typ A1Typ tolerancevalues Very thin profile: 0.80mm 1.00mm Max/Fine pitch: e<1.0 typical ball diameter before mounting 0.25 VFBGA with 0.40mm ball pitch registered into JEDEC publications. tolerance position that controls location pattern balls with respect datum each ball there cylindrical tolerance zone perpendicular datum located true position with respect datum defined axis perpendicular datum each ball must within this tolerance zone. tolerance position that controls location balls within matrix with respect each other. each ball there cylindrical tolerance zone perpendicular datum located true position defined axis perpendicular datum each ball must within this tolerance zone. Each tolerance zone array contained entirely respective zone above. axis each ball must simultaneously both tolerance zones. terminal corner must identified surface using corner chamfer, metallized markings, other feature package body integral heatslug. distinguishing feature allowable bottom surface package identify terminal corner. Exact shape each corner optional.
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STw5098 Figure VFBGA 5x5x1.0 drawing
Package mechanical data
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Application schematics
STw5098
Application schematics
Figure STw5098 application schematics.
82/85
VBAT
AUDIO_APP_I2S_AD_DATA AUDIO_TO_BT_PCM_DATA AUDIO_TO_MODEM_N AUDIO_TO_MODEM_P AUDIO_IRQ AUDIO_FM_ANTENNA AUDIO_TO_TVOUT_R AUDIO_TO_TVOUT_L
STw5098
VBAT
AUDIO_2V8
AUDIO_2V8
AUDIO_1V8
AUDIO_1V8
AUDIO_I2C_SCLK
AUDIO_I2C_SDA
AUDIO_CLK
AUDIO_PWR_AMPLIFIER_STANDBY
AUDIO_1V8
AUDIO_APP_I2S_AD_DA_SYNC
AUDIO_1V8
AUDIO_APP_I2S_AD_DA_CLK
AUDIO_APP_I2S_DA_DATA
AUDIO_FROM_BT_PCM_DATA
R802 10kohm R800 10kohm
AUDIO_BT_PCM_FS
1CMOD 1SCLK 1SDA_SDIN 1AS_CSB 1AD_SYNC 1DA_CK 1AD_CK 1DA_DATA 1AD_DATA 2CMOD 2IRQ 2SCLK 2SDA_SDIN 2AS_CSB 2AD_CK 2AD_DATA 2DA_DATA 2AD_SYNC 2DA_SYNC 2DA_CK 2DA_OCK 2AD_OCK 1DA_SYNC 1DA_OCK 1AD_OCK 1IRQ
AUDIO_PCM_CLK
AUDIO_IRQ TP809 TP806 AUDIO_BT_PCM_FS AUDIO_PCM_CLK AUDIO_FROM_BT_PCM_DATA
AUDIO_FROM_MODEM_P
AUDIO_I2C_SCLK AUDIO_I2C_SDA
AUDIO_FROM_MODEM_N
AUDIO_FM_LEFT
AUDIO_TO_BT_PCM_DATA
AUDIO_FM_RIGHT
AUDIO_APP_I2S_AD_DA_SYNC AUDIO_APP_I2S_AD_DA_CLK AUDIO_APP_I2S_DA_DATA
AUDIO_APP_I2S_AD_DATA AUDIO_CLK
AUDIO_1V8
0402 C801
VCC2 VCC1 VCCIO GND2 C808 GND1 100nF
AMCK
Figure STw5098 application schematics
C815
470nF C807
AUDIO_HANDSET_MIC_P
220ohm R815
1MBIAS 2MBIAS 1HDET 2HDET 1MICLP 2MICLP 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF C834 C831 C830 C829 C828 C824 C823 C822 C819 C817 C814 1MICLN 2MICLN 1MICRP 2MICRP 1MICRN 2MICRN 1CAPMIC 2CAPMIC 1AUX1L 1AUX1R 1AUX2LN 2AUX2LN 1AUX2RP 2AUX2RP 1AUX3L 2AUX3L 1AUX3R 2AUX3R 1LINEINL 2LINEINL 1CAPLINEIN VCCA2 VCCA1 VCCA3 100nF C832 GNDA1 GNDA2 2CAPLINEIN 2LINEINR 100nF C836 1LINEINR 2AUX2RN 1AUX2RN 1AUX2LP 2AUX2LP 2AUX1R 2AUX1L C827 33uF
33uF 220ohm R816
Microphone
M800
0406
C811
R808 2.7kohm C809
AUDIO_HANDSET_MIC_N
R811 2.7kohm C821 680nF 680nF C820 R810 1.2kohm
R807 1.2kohm 680nF
0406 0406
100nF 100nF 100nF 100nF 100nF C806 C810 C805 C804 C803 C802
100nF
C800
680nF
AUDIO_FM_LEFT AUDIO_FM_RIGHT
AUDIO_FROM_MODEM_P AUDIO_FROM_MODEM_N
0406
0406
100nF C812
100nF
0406
AUDIO_2V8 0603 2.2nF C813
0406
HP800 2LSP 2LSPS 2LSN 2LSNS 2CAPLS 2HPL 2VCMHP 2VCMHPS 2HPR 2OLP 2OLN 2ORP 2ORN GNDP3 GNDP1 GNDP2 GNDP4 GNDCM1 GNDCM2 VCCP1 VCCP2 1ORN VCCLS2 VCCLS1 VCCLS3 VCCP3 VCCP4
1LSP 1LSPS 1LSN 1LSNS
Mono speaker
10uF
Jack audio
D801
J800 C833
AUDIO_FM_ANTENNA
AUDIO_EARKIT_LEFT_SPEAKER
I_O1
JACK_CUI
TRANSIL ST000000145 I_O5
100nF C838 100nF C816
1CAPLS 1HPL 1VCMHP 1VCMHPS 1HPR 1OLP 1OLN 1ORP
I_O2 I_O3
100nF C826
AUDIO_EARKIT_RIGHT_SPEAKER
GND1 GND2
AUDIO_TO_TVOUT_L
ST000000144 AUDIO_TO_MODEM_P AUDIO_TO_MODEM_N
AUDIO_TO_TVOUT_R
C839
100nF
22uF 0805
C818
AUDIO_2V8
AUDIO_JACK_DETECT
22pF C841
MN800 STW5098 ST000000131
VBAT
22pF C844
R812 22kohm
22uF 0805 C837
100nF
22pF C845
C835
VBAT
VCC1
VCC2
C846 0402
HP801 100nF 22kohm R813 IN1M VOUT1P
C139
100nF
22kohm R814
IN1P IN2P IN2M
MN801 TS4984
VOUT1M VOUT2P VOUT2M
LOUDSPEAKER
C825
BYPASS1 ST000000133 BYPASS2 HP802
C840 0402
STDBY GND1 GND2
LOUDSPEAKER
AUDIO_PWR_AMPLIFIER_STANDBY
Application schematics
22pF C842
22pF C843 R809 22kohm
83/85
Ordering information
STw5098
Ordering information
Table Order codes
Package LFBGA 6x6x1.4, pitch, pins LFBGA 6x6x1.4, pitch, pins VFBGA 5x5x1.0, pitch, pins VFBGA 5x5x1.0, pitch, pins Tray Tape reel Tray Tape reel Packing
Part Number STw5098 STw5098T STw5098BBLR/LF STw5098BBLT/LF
Revision history
Table
Date 24-Apr-2007
Document revision history
Revision Initial release. Changes
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STw5098
Please Read Carefully:
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