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AKD4682-A AK4682 Evaluation Board Rev.0 FEATURE AKD4682-A ev


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[AKD4682-A]
AKD4682-A
AK4682 Evaluation Board Rev.0
FEATURE AKD4682-A evaluation board AK4682, single chip 24bit CODEC that channels four channels DAC. This board interfaces with AKM's evaluation boards converter converter makes easy evaluate AK4682. Also this board digital audio interface then achieves interface with digital audio systems connector. Ordering guide
AKD4682-A AK4682 Evaluation Board wire flat cable connection with printer port (IBM-AT compatible machine), control software AK4682, driver control software Windows 2000/XP packed with this. Control software does work Windows Windows 2000/XP needs installation driver. Windows 95/98/ME does need installation driver.
FUNCTION On-board clock generators (AK4114 Compatible with types digital audio interface (S/PDIF) input/output 10pin headers interfacing with external data source (x2) connectors clock input with external clock source 10pin headers register control
Regulator Regulator +3.3V
LOUT1/ROUT1
AK4114 (DIR) PORT 10pin Header
LOUT2/ROUT2
AK4682
LOUT3/ROUT3
Control Data 10pin Header PORT 10pin Header AK4114 (DIT)
LINA/RINA
(Note) Each AK4114 integrates DIR, X'tal oscillator. Figure AKD4682-A Block Diagram Circuit diagram layout attached this manual.)
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[AKD4682-A]
EVALUATION BOARD MANUAL
Operating sequence power supply lines.
Name Jack AVDD1 Color Jack Orange Voltage Used AVDD1 DVDD1 AK4682 Comment attention Default
+4.5+5.5V
AVDD2
Orange
+4.5+5.5V
AVDD2 DVDD2 AK4682
D3.3V
Orange
+3.0+3.6V
Power supply logic
TVDD (4682) PVDD AVSS1 AVSS2 DGND
Orange
+2.7+5.5V
TVDD AK4682 TVDD AK4114 PVDD AK4682 Regulator Analog Ground Analog Ground Digital Ground
Should always connected when JP25 (AVDD1_SEL) AVDD1 side. open when JP25 (AVDD1_SEL) side. Should always connected when JP26 (AVDD2_SEL) AVDD2 side. open when JP26 (AVDD2_SEL) AVDD1 side. Should always connected when JP45 (D3.3V_SEL) D3.3V side. open when JP45 (D3.3V_SEL) side. Should always connected when JP32 (TVDD_SEL) TVDD side. open when JP32 (TVDD_SEL) side. Should always connected
Open
Open
Open
Open
Black Black Black
+9+12V
Should always connected Should always connected Should always connected Table Power supply lines
Each supply line should distributed from power supply unit. evaluation mode jumper pins. (Refer following item.) Connect cables. (Refer following item.) Power AK4682 should reset once bringing (SW1) upon power-up. control software registers. (Refer following item.)
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[AKD4682-A]
Evaluation modes with external Connection connector digital (S/PDIF) input, connector (PORTA_RX0) available. analog output, connector (LOUT1) JP28 (ROUT1) available. Setting jumper Setting interface signal PORTA: AK4114 (U7) follows. (Default input PORTA SDTIA1.) Jumper Default JP10
XTIA
JP13
SDTIA1_SEL
JP14
SDTIA2_SEL
JP16
MCLKA_SEL
JP17
BICKA
JP18
LRCKA
Open
MCKO1
Short
Short
Table Setting interface signal PORTA: AK4114 (U7) (1/3) Setting toggle switch Switch Default
Table Setting interface signal PORTA: AK4114 (U7) (2/3) Setting switch Switch Default DIF0 DIF1 DIF2 OCKS0 OCKS1
Table Setting interface signal PORTA: AK4114 (U7) (3/3) with external Connection connector analog input, connector (LINA)/J6 (RINA), (LINB)/J9 (RINB) available. Setting jumpers without inputs open. digital (S/PDIF) output, connector (PORTB_TX1) available. Setting jumper Setting analog inputs. Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6 JP39 (LIN1)/ JP33 (RIN1) LINA/RINA Open Open Open Open Open JP40 (LIN2)/ JP34 (RIN2) Open LINA/RINA Open Open Open Open JP41 (LIN3)/ JP35 (RIN3) Open Open LINA/RINA Open Open Open JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINA/RINA Open Open JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINA/RINA Open JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINA/RINA (Default)
Table Setting inputs through LINA/RINA
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[AKD4682-A]
Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6
JP39 (LIN1)/ JP33 (RIN1) LINB/RINB Open Open Open Open Open
JP40 (LIN2)/ JP34 (RIN2) Open LINB/RINB Open Open Open Open
JP41 (LIN3)/ JP35 (RIN3) Open Open LINB/RINB Open Open Open
JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINB/RINB Open Open
JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINB/RINB Open
JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINB/RINB
Table Setting inputs through LINB/RINB Setting interface signal PORTB: AK4114 (U10) follows. (12.288MHz) used Clock (256fs) Jumper Default JP20
EXA50
JP27
MCLKB_SEL1
JP28
BICKB_SEL
JP29
LRCKB_SEL
JP46
MCLKB_SEL2
Open
Open
BICK
LRCK
MCKO1
Table Setting interface signal PORTB: AK4114 (U10) (1/3) Setting toggle switch Switch Default
Table Setting PORTB: AK4114 (U10) (2/3) Setting switch Switch Default DIF0 DIF1 OCKS0 OCKS1
Table Setting interface signal PORTB: AK4114 (U7) (3/3) Analog input analog output (Through: Analog input Analog output) Connection connector analog input, connector (LINA)/J6 (RINA), (LINB)/J9 (RINB) available. Setting jumpers without inputs open. analog output, connector (LOUT1)/J28 (ROUT1), (LOUT2)/J18 (ROUT2), (LOUT3)/J27 (ROUT3) available. Setting jumper Setting analog inputs. Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6 JP39 (LIN1)/ JP33 (RIN1) LINA/RINA Open Open Open Open Open JP40 (LIN2)/ JP34 (RIN2) Open LINA/RINA Open Open Open Open JP41 (LIN3)/ JP35 (RIN3) Open Open LINA/RINA Open Open Open JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINA/RINA Open Open JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINA/RINA Open JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINA/RINA (Default)
Table Setting inputs through LINA/RINA <KM086400> -42007/02
[AKD4682-A]
Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6
JP39 (LIN1)/ JP33 (RIN1) LINB/RINB Open Open Open Open Open
JP40 (LIN2)/ JP34 (RIN2) Open LINB/RINB Open Open Open Open
JP41 (LIN3)/ JP35 (RIN3) Open Open LINB/RINB Open Open Open
JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINB/RINB Open Open
JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINB/RINB Open
JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINB/RINB
Table Setting inputs through LINB/RINB Setting toggle switch Switch Default
Table Setting interface signal PORTB: AK4114 (U7, U10) Analog input analog output with external (Analog input Analog output) Connection connector analog input, connector (LINA)/J6 (RINA), (LINB)/J9 (RINB) available. Setting jumpers unused inputs open. analog output, connector (LOUT1)/J28 (ROUT1), (LOUT2)/J18 (ROUT2), (LOUT3)/J27 (ROUT3) available. available clock. X'tal 11.2896MHz evaluation board. Change X'tal depends Setting jumper Setting analog inputs. Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6 JP39 (LIN1)/ JP33 (RIN1) LINA/RINA Open Open Open Open Open JP40 (LIN2)/ JP34 (RIN2) Open LINA/RINA Open Open Open Open JP41 (LIN3)/ JP35 (RIN3) Open Open LINA/RINA Open Open Open JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINA/RINA Open Open JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINA/RINA Open JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINA/RINA (Default)
Table Setting inputs through LINA/RINA Inputs
LIN1/ RIN1 LIN2/ RIN2 LIN3/ RIN3 LIN4/ RIN4 LIN5/ RIN5 LIN6/ RIN6 JP39 (LIN1)/ JP33 (RIN1) LINB/RINB Open Open Open Open Open JP40 (LIN2)/ JP34 (RIN2) Open LINB/RINB Open Open Open Open JP41 (LIN3)/ JP35 (RIN3) Open Open LINB/RINB Open Open Open JP42 (LIN4)/ JP36 (RIN4) Open Open Open LINB/RINB Open Open JP43 (LIN5)/ JP37 (RIN5) Open Open Open Open LINB/RINB Open JP44 (LIN6)/ JP38 (RIN6) Open Open Open Open Open LINB/RINB
Table Setting inputs through LINB/RINB
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[AKD4682-A]
Setting interface signal PORTA: AK4114 (U7) follows. (Default input PORTA SDTIA1.) JP10 JP13 JP14 JP16 Jumper
XTIA SDTIA1_SEL SDTIA2_SEL
JP17
BICKA
JP18
LRCKA
MCLKA_SEL
Default
Open
MCKO1
Short
Short
Table Setting interface signal PORTA: AK4114 (U7) (1/5) Setting interface signal PORTB: AK4114 (U10) follows. JP20 JP27 JP28 JP29 Jumper
EXA50 MCLKB_SEL1 BICKB_SEL
JP46
MCLKB_SEL2
LRCKB_SEL
Default
Open
Open
BICKA
LRCKA
MCLKA
Table Setting interface signal PORTB: AK4114 (U10) (2/5) Setting toggle switch Switch Default
Table Setting interface signal PORTB: AK4114 (U7, U10) (3/5) Setting switch Switch Default DIF0 DIF1 DIF2 OCKS0 OCKS1
Table Setting interface signal PORTA: AK4114 (U7) (4/5) Switch Default DIF0 DIF1 OCKS0 OCKS1
Table Setting interface signal PORTB: AK4114 (U7) (5/5)
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[AKD4682-A]
Register control
AKD4682-A controlled printer port (parallel port) IBM-AT compatible Connect PORT2 (uP-I/F) 10-line flat cable packed with this. Take care direction connector. There mark connector. Connect mark 10-pin connector pin#6 PORT2. (Figure
PORT2 UP-I/F
Connect
(ACK)
10-wire flat cable 10-pin connector
10-pin header
AKD4682-A
Figure PORT2 layout Control software packed with this evaluation board. Software operation procedure included evaluation board manual.
Set-up switch (SW2)
Name DIF0 DIF1 DIF2 Content Setting AK4114 Audio Interface Format (Refer Table 20.) Default
Selection AK4114 Clock Mode (Clock Source) (Refer Table 21.) OCKS0 Selection AK4114 Master Clock Output frequency (Refer Table 22.) OCKS1 Table modes AK4114 (U7) AK4682 (U1) DIF1 DIF0 DAUX SDTO
Mode
DIF2
24bit, Left justified 16bit, Right justified 24bit, Left justified 18bit, Right justified 24bit, Left justified 20bit, Right justified 24bit, Left justified 24bit, Right justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, 24bit, Left justified 24bit, Left justified 24bit, 24bit, Table AK4114 Audio Interface Format X'tal Clock source SDTO ON(Note) X'tal DAUX Table AK4114 Clock Mode (Clock Source)
LRCK
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs
<Default>
Mode
<Default>
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[AKD4682-A]
OCKS1
OCKS0 MCKO1 MCKO2 X'tal (max) 256fs 256fs 256fs 256fs 128fs 256fs 512fs 256fs 512fs 128fs 64fs 128fs Table AK4114 Master Clock Output Frequency
<Default>
Toggle switch
[SW1] PDN: Switch power down reset AK4682 (U1). Keep during operation AK4682 (U1). Power down reset AK4682 will done setting once, after power [SW3] AK4114 (U7)-PDN: Switch power down reset AK4114 (U7). Keep during operation AK4114 (U7). Power down reset AK4114 (U7) will done setting once, after power [SW5] AK4114 (U10)-PDN: Switch power down reset AK4114 (U10). Keep during operation AK4114 (U10). Power down reset AK4114 (U10) will done setting once, after power indication [LED1] ERF: output AK4114 (U7): INT0. turns when output AK4114 (U7): INT0 "H". [LED2] ERF: output AK4114 (U10): INT0. turns when output AK4114 (U10): INT0 "H".
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[AKD4682-A]
Jumper pins
Jumper JP39 (LIN1) JP40 (LIN2) JP41 (LIN3) JP42 (LIN4) JP43 (LIN5) JP44 (LIN6) JP33 (RIN1) JP34 (RIN2) JP35 (RIN3) JP36 (RIN4) JP37 (RIN5) JP38 (RIN6) JP10 (XTIA) JP13 (SDTIA1_SEL) JP14 (SDTIA2_SEL) JP16 (MCLKA_SEL) JP17 (BICKA) JP18 (LRCKA) JP27 (MCLKB_SEL1) JP28 (BICKB_SEL) JP29 (LRCKB_SEL) JP46 (MCLKB_SEL2) JP25 (AVDD1_SEL) JP26 (AVDD2_SEL) JP32 (TVDD_SEL) JP45 (D3.3V_SEL) JP19 (EXA50) JP20 (EXB50) Evaluation Mode Open Open Open Open Open Open Open Open Open Open Open Open Open MCKO1 Short Short Open Open Open Open LINA Open Open Open Open Open RINA Open Open Open Open Open Open Open Open Open Open BICK LRCK MCKO1 LINA Open Open Open Open Open RINA Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open Open MCKO1 Short Short MCLKA BICK LRCK MCKO1
Open Open (Default)
Open Open
Open Open
Open Open
control software registers
After reset, setting example files available follows CD-ROM registers each evaluation modes.
Evaluation Mode
ADC/DAC: ak4682_dac_mode1.akr
Evaluation Mode
ADC/DAC: ak4682_adc_mode2.akr
Evaluation Mode
ADC/DAC: ak4682_analog_through _mode3.akr
Evaluation Mode
ADC/DAC: ak4682_loopback_mode4.akr
<KM086400>
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[AKD4682-A]
Analog Input Circuit
JP39
LINA LINB
LIN1
LIN1
2.2u
LINA
MR-552LS
JP40
LINA LINB
LIN2
LIN2
AVSS1
JP41
LINA LINB
C109
LIN3
LIN3
LINB
2.2u
JP42
LINA LINB AVSS1
MR-552LS
LIN4
LIN4
JP43
LINA LINB
LIN5
LIN5
JP44
LINA LINB
LIN6
LIN6
JP33
RINA RINB
RIN1
RIN1
2.2u
RINA
MR-552LS
JP34
RINA RINB
RIN2
RIN2
AVSS1
JP35
RINA RINB
C108
RIN3
RIN3
RINB
2.2u
JP36
RINA RINB AVSS1
MR-552LS
RIN4
RIN4
JP37
RINA RINB RINA RINB
RIN5
RIN5
JP38
RIN6
RIN6
Figure Analog Input Circuit analog input, connector: (LINA), (RINA), (LINB), (RINB) available use. Analog inputs single-ended input ranges each channel nominally Vpp@5V.
<KM086400>
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[AKD4682-A]
Analog Output Circuit
C112
LOUT1 ROUT1
C113
LOUT1
ROUT1
PVSS
4.7n PVSS
MR-552LS
PVSS
4.7n PVSS
MR-552LS
LOUT2 ROUT2
LOUT2
PVSS
4.7n PVSS
MR-552LS
PVSS
ROUT2
4.7n PVSS
MR-552LS
C110
LOUT3 ROUT3
C111
LOUT3
ROUT3
PVSS
4.7n PVSS
MR-552LS
PVSS
4.7n PVSS
MR-552LS
Figure Analog Output Circuit analog output, connector: (LOUT1), (ROUT1), (LOUT2), (ROUT2), J17(LOUT3), J27(ROUT3) available use. Analog outputs single-ended output ranges each channel nominally 5.6Vpp@5V. Output range: AOUT proportional AVDD2 (AOUT=2 AVDD2/5 =5.6Vpp).
Digital Input Circuit (External PORTA)
PORTA_RX0
MR-552LS
0.1u
DGND DGND Figure Digital Input Circuit (External DIR)
digital input, connector: (PORTA-RX0) available.
Digital Output Circuit (External PORTB)
PORTB_TX1
DA02
MR-552LS
DGND1
DGND1 Figure Digital Output Circuit (External DIT)
digital output, connector: (PORTB-TX1) available.
<KM086400>
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[AKD4682-A]
Control Software Manual Set-up evaluation board control software
AKD4682-A according previous term. Connect IBM-AT compatible with AKD4682-A 10-line type flat cable (packed with AKD4682-A). Take care direction 10pin header. (Please install driver CD-ROM when this control software used Windows 2000/XP. Please refer "Installation Manual Control Software Driver device control software". case Windows95/98/ME, this installation needed. This control software does operate Windows NT.) Insert CD-ROM labeled "AKD4682-A Evaluation Kit" into CD-ROM drive. Access CD-ROM drive, double-click icon "akd4682-a.exe", control program. akd4682-a.exe: AK4682-A control program Then evaluate according follows.
Operation flow
Keep following flow. control program according explanation above. Click "Port Reset" button.
Explanation each buttons
[Port Reset]: [Write default]: [All Write]: [Function1]: [Function2]: [Function3]: [Function4]: [Function5]: [SAVE]: [OPEN]: [Write]: interface board (AKDUSBIF-A). Initialize registers. Write registers data that currently displayed. Dialog write data keyboard operation. Dialog write data keyboard operation. sequence register setting executed. sequence that created [Function3] assigned buttons executed. register setting that created [SAVE] function main window assigned buttons executed. Save current register setting. Write saved values register. Dialog write data mouse operation.
Indication data
Input data indicated register map. letter indicates blue indicates "0". Blank part that defined datasheet.
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[AKD4682-A]
Explanation each dialog [Write Dialog]: Dialog write data mouse operation
There dialogs corresponding each register. Click [Write] button corresponding each register dialog. check check box, data becomes "1". not, "0". When writing input data register, click [OK] button. not, click [Cancel] button.
[Function1 Dialog]: Dialog write data keyboard operation
Address Box: Input registers address figures hexadecimal. Data Box: Input registers data figures hexadecimal. When writing input data register, click [OK] button. not, click [Cancel] button.
[Function2 Dialog]: Dialog evaluate
This dialog corresponding address: 08H, 09H, 0AH, 0BH, 0CH, AK4682. Address Box: Input registers address figures hexadecimal. Start Data Box: Input starts data figures hexadecimal. Data Box: Input data figures hexadecimal. Interval Box: Data written register this interval. Step Box: Data changes this step. Mode Select Box: With checking this check box, data reaches data, returns start data. [Example] Start Data Data Data flow: Without checking this check box, data reaches data, does return start data. [Example] Start Data Data Data flow: When writing input data register, click [OK] button. not, click [Cancel] button.
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[AKD4682-A]
[Save] [Open] 4-1. [Save]
Save current register setting data file. extension file name "akr". (Operation flow) Click [Save] Button. file name push [Save] Button. extension file name "akr".
4-2. [Open]
register setting data saved file [Save] written register. file type same [Save]. (Operation flow) Click [Open] Button. Select file (*.akr) Click [Open] Button.
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[AKD4682-A]
[Function3 Dialog]
sequence register setting executed. Click [F3] Button. control sequence. address, Data Interval time. "-1" address step where sequence should paused. Click [Start] button. Then this sequence executed. sequence paused step Interval="-1". Click [START] button, sequence restarts from paused step. This sequence saved opened [Save] [Open] button [Function3] window. extension file name "aks".
Figure Window [F3]
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[AKD4682-A]
[Function4 Dialog]
sequence that created [Function3] assigned buttons executed. When [F4] button clicked, window shown Figure opens.
Figure [F4] window
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[AKD4682-A]
6-1. [OPEN] buttons left side [START] buttons
Click [OPEN] button select sequence file (*.aks). sequence file name displayed shown Figure
Figure [F4] window(2) Click [START] button, then sequence executed.
6-2. [SAVE] [OPEN] buttons right side
[SAVE]: sequence file names assign saved. file name *.ak4. [OPEN]: sequence file names assign that saved *.ak4 loaded.
6-3. Note
[Function4] doesn't support pause function sequence function. files need same folder used [SAVE] [OPEN] function right side. When sequence changed [Function3], file should loaded again order reflect change.
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[AKD4682-A]
[Function5 Dialog]
register setting that created [SAVE] function main window assigned buttons executed. When [F5] button clicked, following window shown Figure opens.
Figure [F5] window
7-1. [OPEN] buttons left side [WRITE] button
Click [OPEN] button select register setting file (*.akr). Click [WRITE] button, then register setting executed.
7-2. [SAVE] [OPEN] buttons right side
[SAVE]: register setting file names assign saved. file name *.ak5. [OPEN]: register setting file names assign that saved *.ak5 loaded.
7-3. Note
files need same folder used [SAVE] [OPEN] function right side. When register setting changed [Save] Button main window, file should loaded again order reflect change.
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[AKD4682-A]
Measure Result
part [Measurement condition] Measurement unit Audio Precision MCLK 256fs (fs=48kHz) BICK 64fs 48kHz 20Hz20kHz (fs=48kHz) 24bit Power Supply AVDD1=AVDD2=DVDD1=DVDD2=5V, TVDD=3V, PVDD Interface External (fs=48kHz,) Temperature Room Temp fs=48kHz (ADC) Parameter S/(N+D) Input signal 1kHz, -0.5dB 1kHz, -60dB 1kHz, -60dB signal signal Measurement filter 20kLPF 20kLPF 20kLPF, A-weighted 20kLPF 20kLPF, A-weighted Results 90.7 93.5 96.1 93.5 96.1 [dB] 90.9 93.6 96.1 93.6 96.1
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[AKD4682-A]
part [Measurement condition] Measurement unit Audio Precision MCLK 256fs (fs=48kHz, 96kHz), 128fs (fs=192kHz) BICK 64fs 48kHz, 96kHz, 192kHz 20Hz20kHz (fs=48kHz), 20Hz40kHz (fs=96kHz), 20Hz40kHz (fs=192kHz) Resolution 24bit Power Supply AVDD1=AVDD2=DVDD1=DVDD2=5V, TVDD=3V, PVDD Interface External (48kHz, 96kHz, 192kHz) Temperature Room Temp fs=48kHz Parameter S/(N+D) fs=96kHz Parameter S/(N+D) fs=192kHz Parameter S/(N+D) Input signal 1kHz, 1kHz, -60dB 1kHz, -60dB data data Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted Results [dB] 87.1 96.4 101.4 96.5 101.4 86.7 96.2 101.2 96.3 101.2 Input signal 1kHz, 1kHz, -60dB 1kHz, -60dB data data Measurement filter 40kLPF 40kLPF 22kLPF, A-weighted 40kLPF 22kLPF, A-weighted Results [dB] 87.2 96.6 101.4 96.6 101.4 86.8 96.3 101.2 96.3 101.2 Input signal 1kHz, 1kHz, -60dB 1kHz, -60dB data data Measurement filter 20kLPF 20kLPF 22kLPF, A-weighted 20kLPF 22kLPF, A-weighted Results 87.9 98.7 101.4 98.7 101.4 [dB] 87.4 98.4 101.2 98.4 101.2
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[AKD4682-A]
part (ADC fs=48kHz)
AK4682 fs=48kHz -1.0dB input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz,Input Level=-1.0dBFS)
AK4682 fs=48kHz -60dB input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz,Input Level=-60dBFS)
<KM086400>
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[AKD4682-A]
(ADC fs=48kHz)
AK4682 fs=48kHz signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(noise floor)
AK4682 THD+N Input Level fs=48kHz
-100 -105 -110 -115 -120 -120 -110 -100
Figure Input Level (Input Frequency =1kHz)
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[AKD4682-A]
(ADC fs=48kHz)
AK4682 THD+N Input Frequency fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120
Figure Input Frequency (Input Level=-1.0dBFS)
AK4682 Linearity fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -140
-130
-120
-110
-100
Figure Linearity (Input Frequency =1kHz)
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[AKD4682-A]
(ADC fs=48kHz)
AK4682 Frequency Respons fs=48kHz
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9
Figure Frequency Response (Input Level=-1.0dBFS)
AK4682 Crosstalk fs=48kHz AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150
Figure Crosstalk (Input Level=-1.0dBFS)
<KM086400>
2007/02
[AKD4682-A]
part (DAC fs=48kHz)
AK4682 fs=48kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Out Band Noise) fs=48kHz signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160 100k
Figure FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on)
<KM086400>
2007/02
ASAHI KASEI (DAC fs=48kHz)
AK4682 fs=48kHz -60dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
[AKD4682-A]
Figure FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 fs=48kHz signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(noise floor)
<KM086400>
2007/02
ASAHI KASEI (DAC fs=48kHz)
AK4682 FFT(Out Band Noise) fs=48kHz signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
[AKD4682-A]
100k
Figure FFT(out-of-band noise)
AK4682 THD+N Input Level fs=48kHz
-82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -120 -110 -100 dBFS
Figure THD+N Input Level (Input Frequency =1kHz)
<KM086400>
2007/02
ASAHI KASEI (DAC fs=48kHz)
AK4682 THD+N Input Frequency fs=48kHz
-72.5 -77.5 -82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110
[AKD4682-A]
Figure THD+N Input Frequency (Input Level=0dBFS)
AK4682 Linearity fs=48kHz
-100 -110 -120 -130 -140 -140
-130
-120
-110
-100
dBFS
Figure Linearity (Input Frequency =1kHz)
<KM086400>
2007/02
ASAHI KASEI (DAC fs=48kHz)
AK4682 Frequency Response fs=48kHz
+0.8 +0.6 +0.4 +0.2 -0.2 -0.4 -0.6 -0.8
[AKD4682-A]
Figure Frequency Response (Input Level=0dBFS)
AK4682 Crosstalk fs=48kHz
-92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130
Figure Cross-talk (Input Level=0dBFS)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=96kHz)
AK4682 fs=96kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Notch) fs=96kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=96kHz)
AK4682 fs=96kHz -60dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 fs=96kHz signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(noise floor)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=96kHz)
AK4682 THD+N Input Level fs=96kHz
-82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100 dBFS
FigureFigure THD+N Input Level (Input Frequency =1kHz)
AK4682 THD+N Input Frequency fs=96kHz
-72.5 -77.5 -82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110
Figure THD+N (Input Level=0dBFS)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=96kHz)
AK4682 Linearity fs=96kHz
-100 -110 -120 -130 -140 -140
-130
-120
-110
-100
dBFS
Figure Linearity (Input Frequency =1kHz)
AK4682 Frequency Response fs=96kHz
+0.8 +0.6 +0.4 +0.2 -0.2 -0.4 -0.6 -0.8
Figure Frequency Response (Input Level=0dBFS)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=96kHz)
AK4682 Crosstalk fs=96kHz
-92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130
Figure Cross-talk (Input Level=0dBFS)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=192kHz)
AK4682 fs=192kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz, Input Level=0dBFS)
AK4682 FFT(Notch) fs=192kHz 0dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz, Input Level=0dBFS,Notch=on,40kHzLPF)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=192kHz)
AK4682 fs=192kHz -60dBFS input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(Input Frequency =1kHz, Input Level=-60dBFS)
AK4682 fs=192kHz signal input AVDD1=AVDD2=DVDD1=DVDD2=5.0V, TVDD=3.3V, PVDD=9.0V
-100 -110 -120 -130 -140 -150 -160
Figure FFT(noise floor)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=192kHz)
AK4682 THD+N Input Level fs=192kHz
-82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100 dBFS
Figure THD+N Input Level (Input Frequency =1kHz)
AK4682 THD+N Input Frequency fs=192kHz
-72.5 -77.5 -82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110
Figure THD+N Input Frequency (Input Level=0dBFS)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=192kHz)
AK4682 Linearity fs=192kHz
-100 -110 -120 -130 -140 -140
-130
-120
-110
-100
dBFS
Figure Linearity Input Frequency =1kHz)
AK4682 Frequency Response fs=192kHz
+0.75 +0.5 +0.25 -0.25 -0.5 -0.75 -1.25 -1.5 -1.75 -2.25 -2.5 -2.75
Figure Frequency Response (Input Level=0dBFS)
<KM086400>
2007/02
[AKD4682-A]
(DAC fs=192kHz)
AK4682 Crosstalk fs=192kHz
-82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120
Figure Cross-talk (Input Level=0dBFS
<KM086400>
2007/02
[AKD4682-A]
Revision History
Date Manual Board (YY/MM/DD) Revision Revision 07/02/19 KM086400 Reason First Edition Contents
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
<KM086400>
2007/02
DVDD1
LIN6
LIN5
LIN4
RIN6
RIN5
RIN4
48pin_4
RIN3
(short)
(short)
(short)
(short)
(short)
(short)
(short)
(short)
LIN3
AVSS1
48pin_3
DVDD1
LIN6
LIN5
LIN4
RIN6
RIN5
RIN4
DVSS1 MCLKB (short) 4682_TVDD
0.1u
DVSS1
RIN3
LIN3
RIN2
(short)
RIN2
DVSS1
MCLKB
LIN2
(short)
LIN2
0.1u
LRCKB
(short)
BICKB
(short)
SDTOB
(short)
LRCKA
(short)
LRCKA
VCOM3
BICKA
(short)
BICKA
VCOM36
MCLKA
(short)
MCLKA
AVSS2
SDTIA1
(short)
SDTIA1
AVDD2
SDTIA2
(short)
SDTIA2 ROUT1 ROUT2 DVDD2 DVSS2 LOUT1 LOUT2 LOUT3 PVDD PVSS
ROUT3
48pin_1
0.1u
0.1u
DVSS2
PVSS
48pin_2
(short)
(short) DVDD2
DVSS2
(short) PVDD1
PVSS
LOUT1
LOUT2
ROUT1
ROUT2
LOUT3
0.1u
0.1u
TVDD
LRCKB
RIN1
(short)
RIN1
BICKB
LIN1
(short)
LIN1
SDTOB
AK4682
AVDD1
AVDD1
0.1u
+10u
AVSS1
AVSS1
AVSS1
0.1u
AVSS1
AVSS2 AVSS2
AVDD2
ROUT3
Title Size Date:
Document Number
AKD4682-A
AK4682
Sheet
Monday, November 2006
JP39
LINA LINB
LINA
LIN1
LIN1
2.2u
MR-552LS
JP40
LINA LINB
LIN2
LIN2
AVSS1
JP41
LINA LINB
C109
LIN3
LIN3
LINB
2.2u
JP42
MR-552LS
LINA LINB AVSS1
LIN4
LIN4
JP43
LINA LINB
LIN5
LIN5
JP44
LINA LINB
LIN6
LIN6
JP33
RINA RINB
RINA
RIN1
RIN1
2.2u
MR-552LS
JP34
RINA RINB
RIN2
RIN2
AVSS1
JP35
RINA RINB
C108
RIN3
RIN3
RINB
2.2u
JP36
MR-552LS
RINA RINB AVSS1
RIN4
RIN4
JP37
RINA RINB
RIN5
RIN5
JP38
RINA RINB
RIN6
RIN6
Title Size Date:
Document Number
AKD4682-A
LIN/RIN
Monday, September 2006
Sheet
D3.3V
D3.3V
74LS07
D3.3V
74LS07
PORT2
A1-10PA-2.54DSA
SDA(ACK)
(short)
D3.3V
DGND
uP-I/F
D3.3V
74HC14
1S1588
D3.3V
D3.3V
74HC14
ATE1D-2M3 DGND
0.1u
Title Size Date:
Document Number
AKD4682-A
INPUT/OUTPUT
Sheet
Monday, November 2006
C112
LOUT1
MR-552LS
LOUT1 ROUT1
C113
ROUT1
MR-552LS
PVSS
4.7n PVSS
PVSS
4.7n PVSS
LOUT2
MR-552LS
LOUT2 ROUT2
ROUT2
MR-552LS
PVSS
4.7n PVSS
PVSS
4.7n PVSS
C110
LOUT3
MR-552LS
LOUT3 ROUT3
C111
ROUT3
MR-552LS
4.7n PVSS
PVSS
4.7n PVSS
PVSS
Title Size Date:
Document Number
AKD4682-A
LOUT/ROUT
Monday, September 2006
Sheet
DGND
PORTA_RX0
D3.3V
0.1u
D3.3V
MR-552LS
DGND
HSU119
0.1u
DGND
D3.3V
0.47u
U14B 74HC14
U14A 74HC14
DGND
D3.3V
D3.3V
PORT A_DIR/4682
DIF0 DIF1 DIF2 OCKS0 OCKS1
D3.3V D3.3V
INT0
74HC04 PORTA_OCKS0 LED1
D3.3V
0.1u
ATE1D-2M3 PORTA
AVSS
TEST1
VCOM
AVDD
INT1
D3.3V
IPS0
DGND
OCKS0
D3.3V
DIF0 OCKS1
PORTA_OCKS1
PORTA_CM0 PORTA_OCKS0 PORTA_OCKS1
TEST2
DGND
DIF1
PORTA_CM0
DGND
DIF2
AK4114
JP10 XTIA
11.2896MHz
IPS1
DGND
P/SN DAUX
DGND
SDTOB MCLKA
XTL0
MCKO2
BICKA LRCKA
XTL1
BICK
MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK
SDTO
JP13 SDTIA1_SEL
JP14 SDTIA2_SEL
SDTIA1
DGND
0.1u
0.1u
SDTIA2
JP16 MCLKA_SEL
4114_TVDD
DGND
D3.3V
MCKO2 MCKO1 DGND JP17 BICKA JP18 LRCKA
DGND
MCLKA BICKA LRCKA SDTOB
SDTIA1 SDTIA2
D3.3V
74VHC04
PORT
PORT4
A1-10PA-2.54DSA
DGND
JP19 EXA50
DGND
Title Size Date:
Document Number
AKD4682-A
PORT
DGND
Monday, November 2006
Sheet
DGND1
D3.3V
PORTB_RX0
0.1u
D3.3V
MR-552LS
DGND1
HSU119
0.1u
DVDD2 D3.3V
DGND1
0.47u
U14C 74HC14
DGND1
D3.3V
D3.3V
U14D 74HC14
PORT B_DIT
AVSS
TEST1
VCOM
AVDD
INT1
DIF0 DIF1 OCKS0 OCKS1
0.1u D3.3V
INT0
74HC04 PORTB_OCKS0
ATE1D-2M3 PORTB
LED2
D3.3V
IPS0
DGND
OCKS0
PORTB_CM0 PORTB_OCKS0 PORTB_OCKS1
DIF0
OCKS1
PORTB_OCKS1
TEST2
DGND1
DIF1
PORTB_CM0
DGND1
DIF2
AK4114
JP27 MCLKA MCLKB_SEL1
12.288MHz
IPS1
DGND1
P/SN DAUX
DGND1
SDTOB
XTL0
MCKO2
MCLKB
XTL1
BICK
BICKB LRCKB
MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK
SDTO
0.1u
0.1u
PORT5 JP46
4114_TVDD
DGND1
DGND1
D3.3V
MCKO2 MCKO1 DGND1
MCLKA MCLKB_SEL2
A1-10PA-2.54DSA
MCLK BICKB LRCKB SDTOB
DGND1
PORTB_TX1
DA02
MR-552LS
DGND1
JP28
D3.3V
PORT
BICKA BICKB_SEL JP29
74VHC04
DGND1
JP20 EXA50
DGND1
LRCKA LRCKB_SEL Title Size Date:
Document Number
AKD4682-A
PORT
DGND1
Monday, November 2006
Sheet
TM_AVDD1
TM_PVDD
JP25
(short)
AVDD1
AVDD1_SEL
NJM78M05FA
(short) AVDD1
AVSS1
PVDD1 (short)
PVDD T-45(R)
AVDD1 T-45(O)
AVDD2 T-45(O)
TVDD T-45(O)
D3.3V T-45(O)
DVSS1
0.1u AVSS2 AVSS2
0.1u AVSS2
AVSS2 TM_PVDD TM_AVDD2 TM_D3.3V TM_AVDD1 TM_TVDD
DGND T-45(B) AVSS1 T-45(B) AVSS2 T-45(B)
DVDD1 (short) TM_AVDD2
AVSS2
(short)
JP26
(short) AVDD2
AVSS2
AVDD2
AVDD2_SEL
DGND AVSS1
AVSS2
(short)
DVSS2
DVDD2
TA48M033F
(open)
(short) TM_TVDD
DGND 0.1u
DVSS2
0.1u
(open)
(short)
JP32
TVDD
TVDD_SEL
DVSS1 DGND1 DVSS1
DVSS1 4682_TVDD 4114_TVDD (short) TM_D3.3V
PVSS
AVSS2
(short)
C114
JP45
DGND D3.3V
D3.3V D3.3V
D3.3V
D3.3V_SEL
(short)
D3.3V
D3.3V
74LS07
74HC04 74HC04 74HC04 74HC04
74VHC04 74VHC04 74VHC04 74VHC04
74HC14 74HC14 74HC14 74HC14 C100 C101
74LS07
74HC14(U4), 74LS07(U3)
D3.3V D3.3V
74HC04(U8), 74VHC04(U9), 74HC14(U14)
74LS07
U14F 74HC14 U14E 74HC14
0.1u
0.1u
0.1u
0.1u
0.1u
DGND
74LS07
Title Size Date:
DGND
DGND
DGND
DGND
DGND
Document Number
AKD4682-A
Power Supply
Sheet
Monday, November 2006

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