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AKD4682-A

AK4682 Evaluation Board Rev.0

ASAHI KASEI
AKD4682-A
AK4682 Evaluation Board Rev.0
AKD4682-A -- AK4682 Evaluation Board 10 wire flat cable for connection with printer port of PC (IBM-AT compatible machine), control software for AK4682, driver for control software on Windows 2000 / XP are packed with this. Control software does not work on Windows NT Windows 2000 / XP needs an installation of driver. Windows 95 / 98 / ME does not need an installation of driver.
FUNCTION On-board clock generators (AK4114 x2) Compatible with 2 types of digital audio interface - RCA (S / PDIF) input / output - 10pin headers for interfacing with external data source (x2) RCA connectors for clock input with external clock source 10pin headers for register control
GND +9V Regulator Regulator +5V +3.3V EXA
LOUT1 / ROUT1
AK4114 (DIR) PORT A 10pin Header
RCA IN
LOUT2 / ROUT2
AK4682
LOUT3 / ROUT3
Control Data 10pin Header PORT B 10pin Header AK4114 (DIT)
RCA OUT
LINA / RINA
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AKD4682-A
EVALUATION BOARD MANUAL
Operating sequence 1. Set up power supply lines.
Name of Jack AVDD1 Color of Jack Orange Voltage Used for AVDD1 and DVDD1 of AK4682 Comment and attention Default
+4.5+5.5V
AVDD2
Orange
+4.5+5.5V
AVDD2 and DVDD2 of AK4682
D3.3V
Orange
+3.0+3.6V
Power supply of logic
TVDD (4682) PVDD AVSS1 AVSS2 DGND
Orange
+2.7+5.5V
TVDD of AK4682 TVDD of AK4114 PVDD of AK4682 Regulator Analog Ground Analog Ground Digital Ground
Red Black Black Black
+9+12V 0V 0V 0V
+9V 0V 0V 0V
Should be always connected Should be always connected Should be always connected Table 1. Power supply lines
Each supply line should be distributed from the power supply unit. 2. Set up evaluation mode and jumper pins. (Refer to the following item.) 3. Connect cables. (Refer to the following item.) 4. Power on. The AK4682 should be reset once bringing PDN (SW1) "L" upon power-up. 5. Set up control software registers. (Refer to the following item.)
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AKD4682-A
BICKA
LRCKA
MCKO1
Short
Table 2. Setting of interface signal of PORTA: AK4114 (U7) (1 / 3) 3. Setting of toggle switch Switch Default SW3 H
Table 3. Setting of interface signal of PORTA: AK4114 (U7) (2 / 3) 4. Setting of DIP switch Switch Default SW2 DIF0 H DIF1 L DIF2 H CM0 L OCKS0 L OCKS1 L
LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6 JP39 (LIN1) / JP33 (RIN1) LINA / RINA Open Open Open Open Open JP40 (LIN2) / JP34 (RIN2) Open LINA / RINA Open Open Open Open JP41 (LIN3) / JP35 (RIN3) Open Open LINA / RINA Open Open Open JP42 (LIN4) / JP36 (RIN4) Open Open Open LINA / RINA Open Open JP43 (LIN5) / JP37 (RIN5) Open Open Open Open LINA / RINA Open JP44 (LIN6) / JP38 (RIN6) Open Open Open Open Open LINA / RINA (Default)
Table 5. Setting of inputs through LINA / RINA
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AKD4682-A
Inputs
LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6
JP39 (LIN1) / JP33 (RIN1) LINB / RINB Open Open Open Open Open
JP40 (LIN2) / JP34 (RIN2) Open LINB / RINB Open Open Open Open
JP41 (LIN3) / JP35 (RIN3) Open Open LINB / RINB Open Open Open
JP42 (LIN4) / JP36 (RIN4) Open Open Open LINB / RINB Open Open
JP43 (LIN5) / JP37 (RIN5) Open Open Open Open LINB / RINB Open
JP44 (LIN6) / JP38 (RIN6) Open Open Open Open Open LINB / RINB
Table 6. Setting of inputs through LINB / RINB Setting of interface signal of PORTB: AK4114 (U10) is as follows. X3 (12.288MHz) is used as Clock (256fs) . Jumper Default JP20
EXA50
MCKO1
Table 7. Setting of interface signal of PORTB: AK4114 (U10) (1 / 3) 3. Setting of toggle switch Switch Default SW5 H
Table 8. Setting of PORTB: AK4114 (U10) (2 / 3) 4. Setting of DIP switch Switch Default SW4 DIF0 H DIF1 L CM0 H OCKS0 L OCKS1 L MSB L
Table 9. Setting of interface signal of PORTB: AK4114 (U7) (3 / 3) (3) Analog input to analog output (Through: Analog input Analog output) 1. Connection of connector For analog input, RCA connector J3 (LINA) / J6 (RINA), J7 (LINB) / J9 (RINB) are available. Setting of jumpers without inputs are open. For analog output, RCA connector J15 (LOUT1) / J28 (ROUT1), J16 (LOUT2) / J18 (ROUT2), J17 (LOUT3) / J27 (ROUT3) are available. 2. Setting of jumper pin Setting of analog inputs. Inputs
LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6 JP39 (LIN1) / JP33 (RIN1) LINA / RINA Open Open Open Open Open JP40 (LIN2) / JP34 (RIN2) Open LINA / RINA Open Open Open Open JP41 (LIN3) / JP35 (RIN3) Open Open LINA / RINA Open Open Open JP42 (LIN4) / JP36 (RIN4) Open Open Open LINA / RINA Open Open JP43 (LIN5) / JP37 (RIN5) Open Open Open Open LINA / RINA Open JP44 (LIN6) / JP38 (RIN6) Open Open Open Open Open LINA / RINA (Default)
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AKD4682-A
Inputs
LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6
JP39 (LIN1) / JP33 (RIN1) LINB / RINB Open Open Open Open Open
JP40 (LIN2) / JP34 (RIN2) Open LINB / RINB Open Open Open Open
JP41 (LIN3) / JP35 (RIN3) Open Open LINB / RINB Open Open Open
JP42 (LIN4) / JP36 (RIN4) Open Open Open LINB / RINB Open Open
JP43 (LIN5) / JP37 (RIN5) Open Open Open Open LINB / RINB Open
JP44 (LIN6) / JP38 (RIN6) Open Open Open Open Open LINB / RINB
Table 11. Setting of inputs through LINB / RINB 3. Setting of toggle switch Switch Default SW3 L SW5 H
LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6 JP39 (LIN1) / JP33 (RIN1) LINA / RINA Open Open Open Open Open JP40 (LIN2) / JP34 (RIN2) Open LINA / RINA Open Open Open Open JP41 (LIN3) / JP35 (RIN3) Open Open LINA / RINA Open Open Open JP42 (LIN4) / JP36 (RIN4) Open Open Open LINA / RINA Open Open JP43 (LIN5) / JP37 (RIN5) Open Open Open Open LINA / RINA Open JP44 (LIN6) / JP38 (RIN6) Open Open Open Open Open LINA / RINA (Default)
Table 13. Setting of inputs through LINA / RINA Inputs
LIN1 / RIN1 LIN2 / RIN2 LIN3 / RIN3 LIN4 / RIN4 LIN5 / RIN5 LIN6 / RIN6 JP39 (LIN1) / JP33 (RIN1) LINB / RINB Open Open Open Open Open JP40 (LIN2) / JP34 (RIN2) Open LINB / RINB Open Open Open Open JP41 (LIN3) / JP35 (RIN3) Open Open LINB / RINB Open Open Open JP42 (LIN4) / JP36 (RIN4) Open Open Open LINB / RINB Open Open JP43 (LIN5) / JP37 (RIN5) Open Open Open Open LINB / RINB Open JP44 (LIN6) / JP38 (RIN6) Open Open Open Open Open LINB / RINB
Table 14. Setting of inputs through LINB / RINB
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AKD4682-A
Setting of interface signal of PORTA: AK4114 (U7) is as follows. (Default input of PORTA is SDTIA1.) JP10 JP13 JP14 JP16 Jumper
BICKA
LRCKA
Default
MCKO1
Short
Table 15. Setting of interface signal of PORTA: AK4114 (U7) (1 / 5) Setting of interface signal of PORTB: AK4114 (U10) is as follows. JP20 JP27 JP28 JP29 Jumper
Default
BICKA
LRCKA
MCLKA
Table 16. Setting of interface signal of PORTB: AK4114 (U10) (2 / 5) 3. Setting of toggle switch Switch Default SW3 H SW5 H
Table 17. Setting of interface signal of PORTB: AK4114 (U7, U10) (3 / 5) 4. Setting of DIP switch Switch Default SW2 DIF0 H DIF1 L DIF2 H CM0 H OCKS0 L OCKS1 L
Table 18. Setting of interface signal of PORTA: AK4114 (U7) (4 / 5) Switch Default SW4 DIF0 H DIF1 L CM0 H OCKS0 L OCKS1 L MSB L
Table 19. Setting of interface signal of PORTB: AK4114 (U7) (5 / 5)
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AKD4682-A
Register control
AKD4682-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2 (uP-I / F) to PC by 10-line flat cable packed with this. Take care of the direction of connector. There is a mark at connector. Connect the mark of 10-pin connector to pin#6 of PORT2. (Figure 2.)
PORT2 1 UP-I / F 10
Connect PC
SCL SDA SDA (ACK)
RED 10-wire flat cable 10-pin connector
5 6 10-pin header
AKD4682-A
Figure 2. PORT2 pin layout Control software is packed with this evaluation board. Software operation procedure is included in evaluation board manual.
Set-up DIP switch (SW2)
No. 1 2 3 4 6 7 Name DIF0 DIF1 DIF2 CM0 Content Setting of AK4114 Audio Interface Format (Refer Table 20.) Default ON OFF ON OFF OFF OFF
Selection of AK4114 Clock Mode (Clock Source) (Refer Table 21.) OCKS0 Selection of AK4114 Master Clock Output frequency (Refer Table 22.) OCKS1 Table 20. Set up modes of AK4114 (U7) and AK4682 (U1) DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DAUX SDTO
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs I / O O O O O O O I I
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AKD4682-A
Toggle switch
SW1 PDN: Switch for power down reset of AK4682 (U1). Keep "H" during operation of AK4682 (U1). Power down reset of AK4682 will be done by setting SW1 to "L" once, after power on. SW3 AK4114 (U7)-PDN: Switch for power down reset of AK4114 (U7). Keep "H" during operation of AK4114 (U7). Power down reset of AK4114 (U7) will be done by setting SW1 to "L" once, after power on. SW5 AK4114 (U10)-PDN: Switch for power down reset of AK4114 (U10). Keep "H" during operation of AK4114 (U10). Power down reset of AK4114 (U10) will be done by setting SW1 to "L" once, after power on. LED indication LED1 ERF: LED for output of AK4114 (U7): INT0. It turns on when output of AK4114 (U7): INT0 is "H". LED2 ERF: LED for output of AK4114 (U10): INT0. It turns on when output of AK4114 (U10): INT0 is "H".
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AKD4682-A
Set up Jumper pins
REG REG REG REG
Open Open (Default)
REG REG REG REG
Open Open
REG REG REG REG
Open Open
REG REG REG REG
Open Open
Set up control software registers
After the reset, setting example files are available as follows in CD-ROM to set registers in each evaluation modes.
Evaluation Mode 1
Evaluation Mode 2
Evaluation Mode 3
Evaluation Mode 4
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AKD4682-A
Analog Input Circuit
C20 JP39 +
LINA LINB
MR-552LS
LINA LINB
AVSS1
LINA LINB
LINA LINB AVSS1
MR-552LS
LINA LINB
C25 JP33 +
RINA RINB
MR-552LS
RINA RINB
AVSS1
RINA RINB
RINA RINB AVSS1
MR-552LS
RINA RINB RINA RINB
Figure 3. Analog Input Circuit For analog input, RCA connector: J3 (LINA), J6 (RINA), J7 (LINB), J9 (RINB) are available to use. Analog inputs are single-ended and input ranges of each channel are nominally 5.6 Vpp@5V.
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AKD4682-A
Analog Output Circuit
LOUT1 ROUT1
+ C113
LOUT1
ROUT1
10k PVSS
4.7n PVSS
MR-552LS
10k PVSS
4.7n PVSS
MR-552LS
LOUT2 ROUT2
LOUT2
10k PVSS
4.7n PVSS
MR-552LS
10k PVSS
ROUT2
4.7n PVSS
MR-552LS
LOUT3 ROUT3
+ C111
LOUT3
ROUT3
10k PVSS
4.7n PVSS
MR-552LS
10k PVSS
4.7n PVSS
MR-552LS
Digital Input Circuit (External DIR : PORTA)
MR-552LS
DGND DGND Figure 5. Digital Input Circuit (External DIR)
For digital input, RCA connector: J22 (PORTA-RX0) is available.
Digital Output Circuit (External DIT : PORTB)
T3 DA02
R85 8 R84
MR-552LS
DGND1
DGND1 Figure 6. Digital Output Circuit (External DIT)
For digital output, RCA connector: J26 (PORTB-TX1) is available.
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AKD4682-A
Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4682-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4682-A by 10-line type flat cable (packed with AKD4682-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000 / XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95 / 98 / ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4682-A Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive, and double-click the icon of "akd4682-a.exe", and set up the control program. akd4682-a.exe: AK4682-A control program 5. Then evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button.
Explanation of each buttons
1. Port Reset: 2. Write default: 3. All Write: 4. Function1: 5. Function2: 6. Function3: 7. Function4: 8. Function5: 9. SAVE: 10. OPEN: 11. Write: Set up the USB interface board (AKDUSBIF-A). Initialize the registers. Write all registers data that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on Function3 can be assigned to buttons and executed. The register setting that is created by SAVE function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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AKD4682-A
Explanation of each dialog 1. Write Dialog: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the Write button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". When writing the input data to register, click OK button. If not, click Cancel button.
2. Function1 Dialog: Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal. Data Box: Input registers data in 2 figures of hexadecimal. When writing the input data to register, click OK button. If not, click Cancel button.
3. Function2 Dialog: Dialog to evaluate ATT
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AKD4682-A
4. Save and Open 4-1. Save
Save the current register setting data to the file. The extension of file name is "akr". (Operation flow) (1) Click Save Button. (2) Set the file name and push Save Button. The extension of file name is "akr".
4-2. Open
The register setting data saved to the file by Save is written to register. The file type is the same as Save. (Operation flow) (1) Click Open Button. (2) Select the file (.akr) and Click Open Button.
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AKD4682-A
5. Function3 Dialog
Figure 7. Window of F3
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AKD4682-A
6. Function4 Dialog
The sequence that is created on Function3 can be assigned to buttons and executed. When F4 button is clicked, the window as shown in Figure 8 opens.
Figure 8. F4 window
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AKD4682-A
6-1. OPEN buttons on left side and START buttons
(1) Click OPEN button and select the sequence file (.aks). The sequence file name is displayed as shown in Figure 9.
Figure 9. F4 window(2) (2) Click START button, then the sequence is executed.
6-2. SAVE and OPEN buttons on right side
SAVE: The sequence file names can assign be saved. The file name is .ak4. OPEN: The sequence file names assign that are saved in .ak4 are loaded.
6-3. Note
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AKD4682-A
7. Function5 Dialog
The register setting that is created by SAVE function on main window can be assigned to buttons and executed. When F5 button is clicked, the following window as shown in Figure 10 opens.
Figure 10. F5 window
7-1. OPEN buttons on left side and WRITE button
(1) Click OPEN button and select the register setting file (.akr). (2) Click WRITE button, then the register setting is executed.
7-2. SAVE and OPEN buttons on right side
SAVE: The register setting file names assign can be saved. The file name is .ak5. OPEN: The register setting file names assign that are saved in .ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by SAVE and OPEN function on right side. (2) When the register setting is changed by Save Button in main window, the file should be loaded again in order to reflect the change.
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AKD4682-A
Measure Result
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AKD4682-A
ASAHI KASEI
AKD4682-A
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
ASAHI KASEI
AKD4682-A
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 13. FFT(noise floor)
-45 -50 -55 -60 -65 -70 -75 d B F S -80 -85 -90 -95 -100 -105 -110 -115 -120 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 +0
ASAHI KASEI
AKD4682-A
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B F S -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
+0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
-70 dBr
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AKD4682-A
-0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 d B F S -0.9 -1 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
-70 -75 -80 -85 -90 -95 -100 -105 d B -110 -115 -120 -125 -130 -135 -140 -145 -150 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
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AKD4682-A
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k Hz 2k 5k 10k 20k 50k 100k
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k
AKD4682-A
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 22. FFT(noise floor)
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k Hz 2k 5k 10k 20k
AKD4682-A
Figure 23. FFT(out-of-band noise)
-82.5 -85 -87.5 -90 -92.5 -95 d B r A -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -120 -110 -100 -90 -80 -70 -60 dBFS -50 -40 -30 -20 -10 +0
-70 -72.5 -75 -77.5 -80 -82.5 -85 d B r A -87.5 -90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 20 50 100 200 500 Hz 1k 2k 5k
AKD4682-A
-70 dBFS
+1 +0.8 +0.6 +0.4 +0.2 d B r A +0 -0.2 -0.4 -0.6 -0.8
AKD4682-A
500 Hz
-92.5 -95 -97.5 -100 -102.5 -105 -107.5 d B -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
ASAHI KASEI
AKD4682-A
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
ASAHI KASEI
AKD4682-A
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
Figure 32. FFT(noise floor)
ASAHI KASEI
AKD4682-A
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B r A -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0
-70 -72.5 -75 -77.5 -80 -82.5 -85 d B r A -87.5 -90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
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AKD4682-A
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
-70 dBFS
+1 +0.8 +0.6 +0.4 +0.2 d B r A +0 -0.2 -0.4 -0.6 -0.8
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AKD4682-A
-90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 d B -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 40 50 100 200 500 1k Hz 2k 5k 10k 20k 40k
ASAHI KASEI
AKD4682-A
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
ASAHI KASEI
AKD4682-A
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
Figure 41. FFT(noise floor)
ASAHI KASEI
AKD4682-A
-80 -82.5 -85 -87.5 -90 -92.5 -95 d B r A -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0
-70 -72.5 -75 -77.5 -80 -82.5 -85 d B r A -87.5 -90 -92.5 -95 -97.5 -100 -102.5 -105 -107.5 -110 90 200 500 1k Hz 2k 5k 10k 20k 40k
ASAHI KASEI
AKD4682-A
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -140
-70 dBFS
+1 +0.75 +0.5 +0.25 -0 -0.25 -0.5 d B r A -0.75 -1 -1.25 -1.5 -1.75 -2 -2.25 -2.5 -2.75 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
ASAHI KASEI
AKD4682-A
-80 -82.5 -85 -87.5 -90 -92.5 -95 -97.5 d B -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 90 200 500 1k 2k Hz 5k 10k 20k 50k 80k
ASAHI KASEI
AKD4682-A
Revision History
Date Manual Board (YY / MM / DD) Revision Revision 07 / 02 / 19 KM086400 0 Reason First Edition Contents
IMPORTANT NOTICE · These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. · AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. · Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. · AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. · It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
DVDD1
R12 (short)
R11 (short)
R10 (short)
R9 (short)
R8 (short)
R7 (short)
R6 (short)
R5 (short)
AVSS1
U1 CN1 + C16 C17
DVDD1
1 DVSS1
R4 (short)
DVSS1
MCLKB
R3 (short)
LRCKB
R14 (short)
BICKB
R15 (short)
SDTOB
R16 (short) PDN
LRCKA
R18 (short)
LRCKA
VCOM3
C94 C95
BICKA
R19 (short)
BICKA
VCOM36
MCLKA
R20 (short)
MCLKA
AVSS2
C87 C91
SDTIA1
R21 (short)
SDTIA1
AVDD2
SDTIA2
R22 (short)
SDTIA2 ROUT1 ROUT2 DVDD2 DVSS2 LOUT1 LOUT2 LOUT3 PVDD PVSS MSB SDA SCL
ROUT3
DVSS2
R23 (short)
R24 (short) DVDD2
DVSS2
R25 (short) PVDD1
LOUT1
LOUT2
ROUT1
ROUT2
LOUT3
LRCKB
R2 (short)
BICKB
R1 (short)
SDTOB
AK4682
AVDD1
+10u C96
AVSS1
C92 C93 AVSS1
AVSS1
AVSS2 AVSS2
AVDD2
ROUT3
Title Size A2 Date:
Document Number
AKD4682-A
AK4682
Sheet 1 of 1
Monday, November 20, 2006
C20 JP39
LINA LINB
MR-552LS
LINA LINB
AVSS1
LINA LINB
C109 +
MR-552LS
LINA LINB AVSS1
LINA LINB
C25 JP33
RINA RINB
MR-552LS
RINA RINB
AVSS1
RINA RINB
C108 +
MR-552LS
RINA RINB AVSS1
RINA RINB
Title Size A3 Date:
Document Number
AKD4682-A
LIN / RIN
Monday, September 11, 2006
Sheet
D3.3V
R35 R38 D3.3V
U3B 4 74LS07
D3.3V
U3A 2 74LS07
PORT2
A1-10PA-2.54DSA
SCL SDA SDA(ACK)
(short)
R66 R48 D3.3V
10k 10k
D3.3V
U4A 2 74HC14
D1 1S1588
D3.3V
U4B 4 74HC14
R51 PDN 100
ATE1D-2M3 PDN DGND
Title Size A3 Date:
Document Number
AKD4682-A
INPUT / OUTPUT
Sheet
Monday, November 20, 2006
LOUT1
R54 + C37
MR-552LS
LOUT1 ROUT1
+ C113
ROUT1
MR-552LS
10k PVSS
4.7n PVSS
10k PVSS
4.7n PVSS
LOUT2
R56 + C38
MR-552LS
LOUT2 ROUT2
ROUT2
MR-552LS
10k PVSS
4.7n PVSS
10k PVSS
4.7n PVSS
LOUT3
R58 + C40
MR-552LS
LOUT3 ROUT3
+ C111
ROUT3
MR-552LS
4.7n PVSS
10k PVSS
4.7n PVSS
Title Size A3 Date:
Document Number
AKD4682-A
LOUT / ROUT
Monday, September 11, 2006
Sheet
C45 10u
D3.3V
C47 0.1u
D3.3V
MR-552LS
75 DGND
D2 HSU119
D3.3V
C48 0.47u
R76 18k
U14B 4 74HC14
U14A 2 74HC14
D3.3V
C49 SW3
DIF0 DIF1 DIF2 CM0 OCKS0 OCKS1
D3.3V D3.3V
D3.3V
ATE1D-2M3 DIR PORTA
TEST1
D3.3V
OCKS0
D3.3V
TEST2
5 DIF1 CM0 32
AK4114
C50 5p
JP10 XTIA
X2 11.2896MHz
C51 5p
SDTOB MCLKA
MCKO2
BICKA LRCKA
VIN MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK TX0 TX1
DIR GND DIR GND
SDTIA1
C52 0.1u
C53 0.1u
SDTIA2
C55 10u
D3.3V
MCKO2 MCKO1 DGND JP17 BICKA JP18 LRCKA
MCLKA BICKA LRCKA SDTOB
10 GND 9 8 SDTIA1 7 SDTIA2 6
EXA J29
D3.3V
U9A 2 74VHC04 EXA
PORT A
PORT4
A1-10PA-2.54DSA
JP19 EXA50
R87 50
Title Size A3 Date:
Document Number
AKD4682-A
PORT A
Monday, November 20, 2006
Sheet
DGND1
C57 10u D3.3V
C58 0.1u
D3.3V
MR-552LS
75 DGND1
D3 HSU119
DVDD2 D3.3V
DGND1
C59 0.47u
R82 18k
U14C 5 74HC14
DGND1
D3.3V
U14D 9 74HC14
TEST1
DIF0 DIF1 CM0 OCKS0 OCKS1 MSB
0.1u D3.3V
ATE1D-2M3 DIT PORTB
R83 1k
D3.3V
OCKS0
OCKS1
TEST2
DGND1
5 DIF1 CM0 32
DGND1
AK4114
C61 5p
X3 12.288MHz
C62 5p
DGND1
SDTOB
MCKO2
MCLKB
BICKB LRCKB
VIN MCKO1 COUT UOUT DVDD BOUT VOUT TVDD DVSS DVSS LRCK TX0 TX1
C63 0.1u
C64 0.1u
PORT5 JP46
C66 10u
DGND1
D3.3V R85
MCKO2 MCKO1 DGND1
A1-10PA-2.54DSA
MCLK BICKB LRCKB SDTOB
DGND1
T3 DA02
MR-552LS
DGND1
240 EXB J30
D3.3V
PORT B
74VHC04
DGND1
JP20 EXA50
R86 50
DGND1
Document Number
AKD4682-A
PORT B
DGND1
Monday, November 20, 2006
Sheet
(short)
AVDD1 REG
T4 NJM78M05FA L4
R98 (short) AVDD1
47u AVSS1
PVDD1 (short)
PVDD T-45(R)
AVDD1 T-45(O)
AVDD2 T-45(O)
TVDD T-45(O)
D3.3V T-45(O)
DVSS1
0.1u AVSS2 AVSS2
0.1u AVSS2
DGND T-45(B) AVSS1 T-45(B) AVSS2 T-45(B)
AVSS2
(short)
R95 (short) AVDD2
47u AVSS2
AVDD2 R91 REG
DGND AVSS1
AVSS2
(short) R97
DVSS2
R90 DVDD2
T5 TA48M033F
(open)
C80 + C81
DGND 0.1u 47u
DVSS2
R96 (open)
(short)
TVDD REG
DVSS1 DGND1 DVSS1
AVSS2
(short)
47u DGND D3.3V
D3.3V D3.3V
D3.3V R92 REG
(short)
D3.3V
U3C 6 74LS07
U8C 6 74HC04 U8D 8 74HC04 U8E 10 74HC04 U8F 12 74HC04
U9C 6 74VHC04 U9D 8 74VHC04 U9E 10 74VHC04 U9F 12 74VHC04
U4F 12 74HC14 U4E 10 74HC14 C88 U4D 8 74HC14 U4C 6 74HC14 C89 C90 C100 C101
U3D 8 74LS07
for 74HC14(U4), 74LS07(U3)
D3.3V D3.3V
74HC04(U8), 74VHC04(U9), 74HC14(U14)
U3E 10 74LS07
U14F 12 74HC14 U14E 10 74HC14
U3F 12 74LS07
Title Size A3 Date:
Document Number
AKD4682-A
Power Supply
Sheet
Monday, November 20, 2006