AKD4345-A AK4345 Evaluation Board Rev.2 GENERAL DESCRIPTION

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AKD4345-A AK4345 Evaluation Board Rev.2 GENERAL DESCRIPTION

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[AKD4345-A]
AKD4345-A
AK4345 Evaluation Board Rev.2
GENERAL DESCRIPTION AKD4345-A evaluation board AK4345, 24bit 96kHz with portable home audio systems. AKD4345-A interface with AKM's converter evaluation boards interface with digital audio systems optical connector. Therefore, easy evaluate AK4345. Ordering guide
AKD4345-A -AK4345 Evaluation Board
FUNCTION Compatible with types input data interface Direct interface with AKM's converter evaluation boards 10-pin header On-board AK4112B DIR, which accepts optical Inputs Optical output internal connector external clock input connector output
DGND
AGND
Digital MCLK
74LVC541 AK4112B (DIR)
AK4345
Digital Analog LOUT
Clock Divider Generator 10pin Header Data
Figure AKD4345-A Block Diagram
ROUT
Circuit diagram layout attached this manual.
<KM087802>
2007/07
[AKD4345-A]
Operation sequence
power supply lines. [VDD] (Red) 3.6V (typ. 3.3V, AK4345) [VCC] (Red) 3.6V (typ. 3.3V, AK4112B, 74LVC541 logic) [AGND] (Black) [DGND] (Black) Each supply line should distributed from power supply unit. Set-up evaluation modes, jumper pins switches (See followings.) Power When AK4112B used, AK4112B AK4345 should reset once bringing upon power-up. When AK4112B used, keep "L", AK4345 should reset once bringing upon power-up.
Evaluation mode
part evaluation using optical S/PDIF input <Default> PORT1 (RX1: OPT) (RX1: BNC). AK4112B (DIR) generates MCLK, BICK, LRCK SDTI1 from received data through Optical connector (TORX141) connector. This evaluation mode should used evaluation using test disk. Nothing should connected PORT3 (DSP). selection should done JP14 (RX1)
MCLK BICK SDTI1 LRCK JP12
part evaluation using 10-pin connector AKM's evaluation board PORT3 (DSP). able evaluate AK4345, connecting 10-pin connector AKM's evaluation board PORT3 (DSP) 10-line flat cable. MCLK, BICK, LRCK SDTI1 sent from converter evaluation board AKD4345 through PORT3 (DSP) 10-line flat cable.
MCLK BICK SDTI1 LRCK JP12
part evaluation using PORT3 (DSP), supplying interface signals from external equipments case using PORT3 (DSP), supplying signals (MCLK, BICK, LRCK, SDTI1) that needed AK4345 from external equipments, following.
MCLK BICK SDTI1 LRCK JP12
case using PORT3 (DSP), supplying SDTI2 from external equipments, setting SDTI2 should done (SDTI2). <KM087802> -22007/07
[AKD4345-A]
Other Jumper pins
JP15 (VDD): OPEN: Separated SHORT: Common. (The connector "VCC" open.) <Default> opening connector "VCC", shorting JP15 (VDD) supplying 3.3V connector "VDD", connector "VDD" supply 3.3V circuits JP16 (GND): Analog ground Digital ground OPEN: Separated SHORT: Common. (The connector "DGND" open.) <Default> JP10 (BCFS): Select BICK AK4345 BICK=128fs case MCLK=256fs/384fs/512fs/768fs. BICK=64fs case MCLK=192fs. BICK=64fs case <Default BICK=32fs case MCLK=192fs. BICK=128fs case MCLK=1024fs/1536fs. BICK=32fs case BICK=64fs case MCLK=1024fs/1536fs. BICK=32fs case MCLK=1024fs/1536fs. JP11 (DIV), [JP9] (CLK), [JP13] (LRFS) When using (EXT), these jumper pins should according Table (CDTO SDTI2): Select signal CDTO SDTI2 CDTO: Select CDTO<Default> SDTI2: Select SDTI2 (SDTI2): Select input SDTI2 PORT3: Input signal from PORT3 GND: Input Data <Default> (When (CDTO SDTI2): setting CDTO, GND)
<KM087802>
2007/07
[AKD4345-A]
Example External Clock setting
Refer following setting when MCLK, BICK LRCK supplied AK4345 from (EXT). Mode 8kHz Half 24kHz MCLK JP11 (DIV) (CLK) 512fs 4.096MHz 768fs 6.144MHz 1024fs 8.192MHz 1536fs 12.288MHz 512fs 12.288MHz 768fs 18.432MHz 1024fs 24.576MHz 1536fs 36.864MHz 256fs 2.048MHz 384fs 3.072MHz OPEN 512fs 4.096MHz 768fs 6.144MHz 256fs 8.192MHz 384fs 12.288MHz OPEN 512fs 16.384MHz 768fs 24.576MHz 256fs 11.2896MHz 384fs 16.9344MHz OPEN 512fs 22.5792MHz 768fs 33.8688MHz 256fs 12.288MHz 384fs 18.432MHz OPEN 512fs 24.576MHz 768fs 36.864MHz 128fs 6.144MHz OPEN 192fs 9.216MHz OPEN 256fs 12.288MHz 384fs 18.432MHz OPEN 128fs 12.288MHz OPEN 192fs 18.432MHz OPEN 256fs 24.576MHz 384fs 36.864MHz OPEN Table Clock Setting JP13 (LRFS)
8kHz
32kHz Normal 44.1kHz
Default
48kHz
48kHz Double 96kHz
<KM087802>
2007/07
[AKD4345-A]
Switch
[SW3]: Setting audio data format AK4112B (ON="H", OFF="L") Mode SW3-3 SW3-2 SW3-1 SDTI Format DIF2 DIF1 DIF0 16bit, justified 24bit, justified 24bit, justified 24bit, Compatible Table SW3: Audio Data Format AK4112B
Default
Note. AK4112B does support 16bit, Compatible.
<KM087802>
2007/07
[AKD4345-A]
function toggle
[SW1] (AK4345-PDN): Resets AK4345. Keep during normal operation. AK4345 should reset once bringing upon power-up. [SW2] (AK4112B-PDN): Resets AK4112B. Keep during normal operation. AK4112B should reset once bringing upon power-up.
Analog Output Circuit
AK4345 outputs analog audio signals through
AK4345-LOUT BNC-R-PC
LOUT
C100
AK4345-ROUT
BNC-R-PC
ROUT
C101
Figure LOUT/ROUT Output circuit
AKEMD assumes responsibility trouble when using above circuit examples.
Serial control
AKD4345-A controlled printer port (parallel port) IBM-AT compatible Connect PORT4 (uP-I/F) 10-line flat cable packed with AKD4345-A. Take care direction connector. There mark pin#1. layout PORT4 shown Figure
PORT4
Figure PORT4 layout
<KM087802>
CDTO
CCLK
CDTI
2007/07
[AKD4345-A]
Control Software Manual Set-up evaluation board control software
AKD4345-A according Operating Sequence located page Connect IBM-AT compatible with AKD4345-A 10-line type flat cable (packed with AKD4345-A). Take care direction 10pin header. (Please install driver CD-ROM when this control software used Windows 2000/XP. Please refer "Installation Manual Control Software Driver device control software". case Windows95/98/ME, this installation needed. This control software does operate Windows NT.) Insert CD-ROM labeled "AKD4345-A Evaluation Kit" into CD-ROM drive. Access CD-ROM drive double-click icon "akd4345-a.exe" control program. Please evaluate according following.
Operation flow
Keep following flow. control program according explanation above. Click "Port Reset" button.
Explanation each buttons
[Port Reset]: [Write default]: [All Write]: [Function1]: [Function2]: [Function3]: [Function4]: [Function5]: [SAVE]: [OPEN]: [Write]: interface board (AKDUSBIF-A) Initialize register AK4345. Write registers that currently displayed. Dialog write data keyboard operation. Dialog write data keyboard operation. sequence register setting executed. sequence that created [Function3] assigned buttons executed. register setting that created [SAVE] function main window assigned buttons executed. Save current register setting. Write saved values register. Dialog write data mouse operation.
Indication data
Input data indicated register map. letter indicates blue indicates "0". Blank part that defined datasheet.
<KM087802>
2007/07
[AKD4345-A]
Explanation each dialog [Write Dialog]: Dialog write data mouse operation
There dialogs corresponding each register. Click [Write] button corresponding each register dialog. check check box, data becomes "1". not, "0". want write input data AK4345, click [OK] button. not, click [Cancel] button.
[Function1 Dialog] Dialog write data keyboard operation
Address Box: Input registers address figures hexadecimal. Data Box: Input registers data figures hexadecimal. want write input data AK4345, click [OK] button. not, click [Cancel] button.
[Function2 Dialog] Dialog evaluate
Address Box: Start Data Box: Data Box: Interval Box: Step Box: Input registers address figures hexadecimal. Input starts data figures hexadecimal. Input data figures hexadecimal. Data written AK4345 this interval. Data changes this step.
Mode Select Box: check this check box, data reaches data, returns start data. [Example] Start Data Data Data flow: check this check box, data reaches data, does return start data. [Example] Start Data Data Data flow: want write input data AK4345, click [OK] button. not, click [Cancel] button.
<KM087802>
2007/07
[AKD4345-A]
[Save] [Open] 4-1. [Save]
Save current register setting data. extension file name "akr".
(Operation flow)
Click [Save] Button. file name push [Save] Button. extension file name "akr". 4-2. [Open] register setting data saved [Save] written AK4345. file type same [Save].
(Operation flow)
Click [Open] Button. Select file (*.akr) Click [Open] Button.
<KM087802>
2007/07
[AKD4345-A]
[Function3 Dialog]
sequence register setting executed. Click [F3] Button. control sequence. address, Data Interval time. "-1" address step where sequence should paused. Click [Start] button. Then this sequence executed. sequence paused step Interval="-1". Click [START] button, sequence restarts from paused step. This sequence saved opened [Save] [Open] button Function3 window. extension file name "aks".
Figure Window [F3]
<KM087802>
2007/07
[AKD4345-A]
[Function4 Dialog]
sequence that created [Function3] assigned buttons executed. When [F4] button clicked,
window shown Figure opens.
Figure [F4] window
<KM087802>
2007/07
[AKD4345-A]
6-1. [OPEN] buttons left side [START] buttons
Click [OPEN] button select sequence file (*.aks). sequence file name displayed shown Figure.
Figure [F4] window(2) Click [START] button, then sequence executed.
6-2. [SAVE] [OPEN] buttons right side
[SAVE]: sequence file names assign saved. file name *.ak4. [OPEN]: sequence file names assign that saved *.ak4 loaded.
6-3. Note
This function doesn't support pause function sequence function. files need same folder used [SAVE] [OPEN] function right side. When sequence changed [Function3], file should loaded again order reflect change.
<KM087802>
2007/07
[AKD4345-A]
[Function5 Dialog] register setting that created [SAVE] function main window assigned buttons executed. When [F5] button clicked, following window shown Figure opens.
Figure [F5] window
7-1. [OPEN] buttons left side [WRITE] button
Click [OPEN] button select register setting file (*.akr).
Click [WRITE] button, then register setting executed.
7-2. [SAVE] [OPEN] buttons right side
[SAVE] register setting file names assign saved. file name *.ak5. [OPEN] register setting file names assign that saved *.ak5 loaded.
7-3. Note
files need same folder used [SAVE] [OPEN] function right side. When register setting changed [Save] Button main window, file should loaded again order reflect change.
<KM087802>
2007/07
[AKD4345-A]
MEASUREMENT RESULTS
[Measurement condition] Measurement unit MCLK BICK Power Supply Interface Temperature [Measurement Results] Parameter Analog Output Characteristics S/(N+D) (fs=44.1kHz, fin=1KHz, 0dBFS) (fs=96kHz, fin=1KHz, 0dBFS) D-Range (fs=44.1kHz, fin=1KHz, -60dBFS, A-weighted) (fs=96kHz, fin=1KHz, -60dBFS, A-weighted) (fs=44.1kHz, no-input, A-weighted) (fs=96kHz, no-input, A-weighted) Interchannel Isolation (fin=1KHz, 0dBFS/no-input) 99.7/99.7 99.0/99.1 115.7/115.7 Results -90.6/-90.6 -87.7/-87.7 99.4/99.4 98.9/98.9 Unit
Audio Precision, System Cascade 512fs (fs=44.1KHz) /256fs (fs=96KHz) 64fs 44.1kHz 96kHz 20Hz~20KHz (fs=44.1kHz) 20Hz~40KHz (fs=96kHz) 24bit 3.3V PSIA Room
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=44.1kHz]
-100 -140
THD+N Input Level fs=44.1kHz, fin=1kHz
06/18/07 09:30:43
-130
-120
-110
-100
dBFS
Figure THD+N Input Level (fin=1KHz)
-100
THD+N Input Freqency fs=44.1kHz, fin=0dBFs
06/18/07 09:28:48
Figure THD+N Input Frequency (Input Level=0dBFS)
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=44.1kHz]
-100 -110 -120 -130 -140 -140
Linearity fs=44.1kHz, fin=1kHz
06/18/07 09:35:13
-130
-120
-110
-100
dBFS
Figure Linearity (fin=1KHz)
+0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 +0.1 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9
Freqency Response fs=44.1kHz, fin=0dBFs
06/18/07 09:49:36
Figure Frequency Response (Input Level=0dBFS)
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=44.1kHz]
Crosstalk fs=44.1kHz
06/18/07 09:56:53
-100
-106
-112
-118
-124
-130
Figure Crosstalk (fin=1KHz, Input Level=0dBFS/no-input)
-100 -110 -120 -130 -140 -150 -160
fs=44.1kHz, fin=0dBFs,1kHz
06/18/07 10:07:31
Figure Plot (fin=1KHz, Input Level=0dBFS)
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=44.1kHz]
-100 -110 -120 -130 -140 -150 -160
fs=44.1kHz, fin=-60dBFs,1kHz
06/18/07 10:08:53
Figure Plot (fin=1KHz, Input Level=-60dBFS)
-100 -110 -120 -130 -140 -150 -160
Noise floor fs=44.1kHz
06/18/07 10:09:30
Figure Plot (no-input)
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=96kHz]
-100 -110 -120 -130 -140 -150 -160 100k
Out-of-band Noise fs=44.1kHz
06/18/07 10:32:35
Figure Plot (out-of-band-noise)
-72.5 -77.5 -82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120 -140 -130 -120 -110 -100
THD+N Input Level fs=96KHz, fin=1KHz
dBFS
Figure THD+N Input Level (fin=1KHz)
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=96kHz] THD+N Input Frequency fs=96KHz, Input Level=0dBFS
-72.5 -77.5 -82.5 -87.5 -92.5 -97.5 -100 -102.5 -105 -107.5 -110 -112.5 -115 -117.5 -120
Figure THD+N Input Frequency (Input Level=0dBFS)
-100 -110 -120 -130 -140 -140
Linearity fs=96kHz
06/18/07 10:46:53
-130
-120
-110
-100
dBFS
Figure Linearity (fin=1KHz)
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=96kHz]
+0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 +0.1 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 2.5k 7.5k 12.5k 17.5k 22.5k 27.5k 32.5k 37.5k
Frequency response fs=96kHz
06/18/07 10:49:42
Figure Frequency Response (Input Level=0dBFS)
-100 -105 -110 -115 -120 -125 -130
Crosstalk fs=96kHz
06/18/07 10:52:01
Figure Crosstalk (fin=1KHz, Input Level=0dBFS/no-input)
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=96kHz]
-100 -110 -120 -130 -140 -150 -160
fs=96kHz, fin=0dBFs,1kHz
06/18/07 10:24:00
Figure Plot (fin=1KHz, Input Level= 0dBFS)
-100 -110 -120 -130 -140 -150 -160
fs=96kHz, fin=-60dBFs,1kHz
06/18/07 10:28:58
Figure Plot (fin=1KHz, Input Level= -60dBFS)
<KM087802>
2007/07
[AKD4345-A]
[DAC Plot: fs=96kHz]
-100 -110 -120 -130 -140 -150 -160
Noise floor fs=96kHz
06/18/07 10:29:37
Figure Plot (no-input)
-100 -110 -120 -130 -140 -150 -160
Out-of-band Noise fs=96kHz
06/18/07 10:30:24
100k
Figure Plot (out-of-band-noise)
<KM087802>
2007/07
[AKD4345-A]
Revision History Date (yy/mm/dd) 07/03/15 07/04/17 Manual Revision KM087800 KM087801 Board Revision Reason First Edition Circuit Change Change Circuit Change Contents
07/07/02
KM087802
Change (AK4345): 28pin 16pin TSSOP Remove jumper pins: (TX), (TEST1). resistance: R100 (300) TEST1 open. Remove description: (TX), (TEST1). Capacitor between VCOM VSS: Change: 10uF 4.7uF capacitor C100: between (LOUT) GND. capacitor C101: between (ROUT) GND. measurement results
IMPORTANT NOTICE These products their specifications subject change without notice. When consider application these products, please make inquiries sales office Asahi Kasei Corporation (AKEMD) authorized distributors current status products. AKEMD assumes liability infringement patent, intellectual property, other rights application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. AKEMD products neither intended authorized critical componentsNote1) safety, life support, other hazard related device systemNote2), AKEMD assumes responsibility such use, except approved with express written consent Representative Director AKEMD. used here: Note1) critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. Note2) hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. responsibility buyer distributor AKEMD products, distributes, disposes otherwise places product with third party, notify such third party advance above content conditions, buyer distributor agrees assume responsibility liability hold AKEMD harmless from claims arising from said product absence such notification.
<KM087802>
2007/07
R100
AK4345-MCLK
MCLK
AK4345-TX
AK4345-BICK
BICK
CDTO/SDTI2
CDTO JP2(3x1) CDTO/SDTI2 SDTI2
AK4345-CDTO
AK4345-SDTI1
SDTI1
AK4345-SDTI2
0.1u AK4345-LRCK
LRCK
AK4345-PDN
VCOM
AK4345-CSN
LOUT
AK4345-CCLK
CCLK
ROUT
AK4345-CDTI
CDTI
TEST1
AK4345
4.7u
AK4345-LOUT
AK4345-ROUT
Title
Size
Date:
AKD4345-A AK4345 Tuesday, June 2007
Document Number Sheet
0.1u
DVDD
CM0/CDTO
DVSS
CM1/CDTI
HC-49/U 11.2896MHz
MCKO2
AK4112B-PDN
0.1u
AK4112B-RX1
AK4112B-DIF0
AK4112B-DIF1
AK4112B-DIF2
0.1u
TVDD OCKS1/CCLK
V/TX
OCKS0/CSN
MCKO1
AK4112B-MCKO1
DAUX
BICK
AK4112B-BICK
AVDD
SDTO
AK4112B-SDTO
AVSS
LRCK
AK4112B-LRCK
AK4112B-ERF
RX2/DIF0
FS96
RX3/DIF1
RX4/DIF2
AUTO
AK4112B
Title Size
Document Number
Date:
AKD4345-A AK4112B
Sheet
Thursday, 2007
0.1u
EXT-MCLK AK4112B-MCKO1 EXT-BICK AK4112B-BICK AK4112B-SDTO EXT-LRCK AK4112B-LRCK
PORT3-MCLK JP4(3x1) MCLK PORT3-BICK JP5(3x1) BICK PORT3-SDTI1 JP6(2x1) SDTI1 PORT3-LRCK (3x1) LRCK 74LVC541A-PDN
AK4345-MCLK
AK4345-BICK
AK4345-SDTI1
AK4345-LRCK
AK4345-PDN
PORT3-SDTI2
PORT3
(3x1) SDTI2
AK4345-SDTI2
74LVC541A
Title Size Document Number
Date:
AKD4345-A 74LVC541A
Sheet
Thursday, 2007
EXT-MCLK
74AC74
BNC-R-PC
74AC74
JP11 (3x2)
(3x2)
JP10 (4x2)
JP12 (2x1)
74AC163
74HC4040
EXT-BICK
BCFS
JP13 (3x2)
EXT-LRCK
LRFS
74HC14
LOAD
74HC14
74HC14
74HC14
74HC14
74HC14
Title Size Document Number
AKD4345-A
External Master Clock Divider
Sheet
Date:
Thursday, 2007
PORT1 TORX141 HSU119
AK4345-LOUT
BNC-R-PC
LOUT
RX1(OPT)
0.1u JP14 (3x1) AK4112B-RX1
C100
74LVC541A-PDN
74HC14 0.1u
74HC14 BNC-R-PC
ATE1D-2M3 AK4345-PDN
RX1(BNC)
0.1u
BNC-R-PC
ROUT
AK4345-ROUT PORT2 TOTX141
HSU119
TX(OPT)
AK4345-TX 0.1u
C101
AK4112B-PDN
74HC14 0.1u
74HC14
ATE1D-2M3 AK4112B-PDN
DSS103 DIF0 DIF1 DIF2
PORT3-MCLK PORT3-BICK PORT3-LRCK PORT3-SDTI1 PORT3-SDTI2 PORT3 A1-10PA-2.54DSA MCLK BICK LRCK SDTI1 SDTI2
AK4112B-MODE AK4112B-DIF0 AK4112B-DIF1 AK4112B-DIF2 74HCT04 AK4112B-ERF
LED1 SML-210VT
AK4112B-ERF
74HCT04
74HCT157
74HCT04
74HC14
74HCT04
74HC14
74HCT04
100K
AK4345-CSN AK4345-CCLK AK4345-CDTI AK4345-CDTO
74HCT04
PORT4 A1-10PA-2.54DSA CCLK CDTI CDTO uP-I/F (short)
Title Size
AKD4345-A
Document Number
Date:
Input Output Digital Analog Sheet
Tuesday, June 2007
T_45(RED)
T_45(RED)
AGND DGND T_45(BLACK)T_45(BLACK)
VDDi
VCCi
AGND
DGND
VDDi
VCCi
(short)
(short) JP15 (2x1) (short) 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 74HC14 74HCT04 74AC74 74HC4040 74AC163 74HC14
(short)
JP16 AGND (2x1) DGND
Title Size Document Number
Date:
AKD4345-A Power Supply
Sheet
Thursday, 2007

AKD4345-A AK4345 Evaluation Board Rev.2 GENERAL DESCRIPTION

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