AK5386 Single-ended 24-Bit 192kHz GENERAL DESCRIPTION AK5386
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[AK5386]
AK5386
Single-ended 24-Bit 192kHz
GENERAL DESCRIPTION AK5386 stereo Converter with wide sampling rate 8kHz 216kHz suitable consumer professional audio system. AK5386 achieves high accuracy cost using Enhanced dual techniques. AK5386 requires external components because analog inputs single-ended. audio interface formats (MSB justified, I2S) correspond various systems like Recorder, Receiver, Sound card Music Instrument recording. FEATURES Single-ended Input Digital DC-Offset cancel S/(N+D): 96dB 110dB S/N: 110dB Linear Phase Digital Anti-Alias Filtering Passband: 21.768kHz fs=48kHz) Passband Ripple: ±0.005dB Stopband Attenuation: 80dB Master Clock: 512fs/768fs (Normal Speed) 256fs/384fs (Double Speed) 128fs/192fs (Quad Speed) Sampling Frequency: Normal Speed: 8kHz 54kHz (512fs) 8kHz 48kHz (768fs) Double Speed: 54kHz 108kHz (256fs) 48kHz 96kHz (384fs) 216kHz (128fs) Quad Speed: 108kHz 96kHz 192kHz (192fs) Master Slave Mode Audio Interface: 24bit justified selectable Input level: CMOS Power Supply: Analog: 5.5V Digital: 3.6V (Normal Speed) 3.6V (Double Speed, Quad Speed) 85°C Small 16pin TSSOP Package AK5357/58/59/81 Pin-compatible
MS0579-E-00
2006/12
[AK5386]
AGND
DGND
MCLK
Clock Divider AINL Modulator Modulator Voltage Reference Decimation Filter Decimation Filter Serial Interface
LRCK SCLK
AINR
SDTO
VCOM
CKS2 CKS1
CKS0
Block Diagram
Compatibility with AK5357, AK5358, AK5359, AK5381 AK5386
AK5357 4kHz 96kHz 88dB 102dB
256/512/384/768fs
S/(N+D) MCLK 48kHz Level Mode VA(Analog Supply) (Digital Supply) Disable Operating Temperature
AK5358 8kHz 96kHz 92dB 102dB
256/512/384/768fs
AK5381 4kHz 96kHz 96dB 106dB
256/512/384/768fs
AK5359 8kHz 216kHz 94dB 102dB
256/512/384/768fs
AK5386 8kHz 216kHz 96dB 110dB 512/768fs Available 5.5V 3.6V 3.6V fs=96k, 192kHz Available -40+85°C
2.2V 5.5V 5.5V Available -20+85°C -40+85°C
2.2V 5.5V 5.5V Available -20+85°C
2.4V 5.5V 5.5V 5.5V@ fs=96kHz Available -20+85°C -40+85°C -40+85°C
Available 5.5V 5.5V Available -20+85°C -40+85°C
MS0579-E-00
2006/12
[AK5386]
Ordering Guide
AK5386VT AKD5386 16pin TSSOP (0.65mm pitch) +85°C Evaluation Board AK5386
Layout
AINR AINL CKS1 VCOM AGND DGND
View
CKS0 CKS2 SCLK MCLK LRCK SDTO
FUNCTION
Name AINR AINL CKS1 Function
Analog Input Analog Input Mode Select Common Voltage Output Pin, VA/2 VCOM Bias voltage input. AGND Analog Ground Analog Power Supply Pin, Digital Power Supply Pin, 3.3V DGND Digital Ground Audio Serial Data Output SDTO Output Power-down mode. Output Channel Clock LRCK Output Master Mode Power-down mode. MCLK Master Clock Input Audio Serial Data Clock SCLK Output Master Mode Power-down mode. Power Down Reset Mode "H": Power "L": Power down Reset AK5386 must reset once upon power-up. Audio Interface Format "H": 24bit Compatible, "L": 24bit justified CKS2 Mode Select CKS0 Mode Select Note: allow digital input pins except analog input pins (AINL AINR pins) float.
MS0579-E-00
2006/12
[AK5386]
Handling Unused
unused input pins should processed appropriately below. Classification Analog Name AINL AINR Setting This should open. This should open.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND=0V; Note Parameter Symbol Power Supplies: Analog -0.3 (Note Digital -0.3 Input Current, Except Supplies Analog Input Voltage (AINL, AINR, CKS1 pins) VINA -0.3 Digital Input Voltage (Note VIND -0.3 Ambient Temperature (powered applied) Storage Temperature Tstg Note voltages with respect ground. Note AGND DGND must connected same analog ground plane. Note DIF, PDN, SCLK, MCLK, LRCK, CKS0 CKS2 pins
VA+0.3 VD+0.3
Units
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND=0V; Note Parameter Symbol Power Supplies Analog (Note Digital: Normal Speed Double/Quad Speed Note power sequence between critical. Units
WARNING: assumes responsibility usage beyond conditions this datasheet.
MS0579-E-00
2006/12
[AK5386]
ANALOG CHARACTERISTICS (Ta=25°C; VA=5.0V, VD=3.3V; AGND=DGND=0V; fs=48kHz, 96kHz, 192kHz; SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz 20kHz fs=48kHz, 40Hz 40kHz fs=96kHz, 40Hz 40kHz fs=192kHz; unless otherwise specified) Parameter Units Analog Input Characteristics: Resolution Bits Input Voltage (Note S/(N+D) fs=48kHz -1dBFS BW=20kHz -60dBFS fs=96kHz -1dBFS BW=40kHz -60dBFS fs=192kHz -1dBFS BW=40kHz -60dBFS (-60dBFS with A-weighted) (A-weighted) Input Resistance Interchannel Isolation Interchannel Gain Mismatch Gain Drift ppm/°C Power Supply Rejection (Note Power Supplies
Power Supply Current Normal Operation (PDN "H") (fs=48kHz) (fs=96kHz) (fs=192kHz) Power down mode (PDN "L") (Note VA+VD Note This value full scale (0dB) input voltage. Input voltage proportional voltage. (Vpp). Note applied with 1kHz, 50mVpp. Note digital input pins held DGND.
MS0579-E-00
2006/12
[AK5386]
FILTER CHARACTERISTICS (fs=48kHz) (Ta=-40 85°C; VA=4.5 5.5V; VD=2.7 3.6V) Parameter Symbol Digital Filter (Decimation LPF): Passband (Note ±0.02dB 221. -0.1dB 22.3 -0.2dB 23.5 -3.0dB Stopband 26.5 Passband Ripple Stopband Attenuation Group Delay Distortion Group Delay (Note 29.4 Digital Filter (HPF): Frequency Response (Note -3dB -0.1dB FILTER CHARACTERISTICS (fs=96kHz) (Ta=-40 85°C; VA=4.5 5.5V; VD=3.0 3.6V) Parameter Symbol Digital Filter (Decimation LPF): Passband (Note ±0.02dB 44.3 -0.1dB 44.6 -0.2dB 47.0 -3.0dB Stopband 53.0 Passband Ripple Stopband Attenuation Group Delay Distortion Group Delay (Note 29.4 Digital Filter (HPF): Frequency Response (Note -3dB 13.0 -0.1dB
21.768 ±0.005
Units 1/fs
43.536 ±0.005
Units 1/fs
MS0579-E-00
2006/12
[AK5386]
FILTER CHARACTERISTICS (fs=192kHz) (Ta=-40 85°C; VA=4.5 5.5V; VD=3.0 3.6V) Parameter Symbol Units Digital Filter (Decimation LPF): Passband (Note ±0.1dB 43.8 52.9 -0.2dB 90.1 -3.0dB Stopband Passband Ripple ±0.005 Stopband Attenuation Group Delay Distortion Group Delay (Note 16.5 1/fs Digital Filter (HPF): Frequency Response (Note -3dB 26.0 -0.1dB Note passband stopband frequencies scale with example, (±0.02dB) fs=48kHz 0.4535 reference frequency these response 1kHz. Note calculated delay time induced digital filtering. This time from input analog signal setting 24bit data both channels output register ADC.
CHARACTERISTICS (Ta=-40 85°C; VA=4.5 5.5V; VD=2.7 3.6V Normal Speed, VD=3.0 3.6V Double/Quad Speed) Parameter Symbol High-Level Input Voltage 70%VD Low-Level Input Voltage 30%VD High-Level Output Voltage (Iout=-1mA) VD-0.5 Low-Level Output Voltage (Iout=1mA) Input Leakage Current
Units
MS0579-E-00
2006/12
[AK5386]
SWITCHING CHARACTERISTICS (Normal Speed) (Ta=-40 85°C; VA=4. 5.5V; VD=2.7 3.6V; CL=20pF) Parameter Symbol Master Clock Timing Frequency: 512fs fCLK 4.096 768fs fCLK 6.144 Pulse Width tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Frequency: 512fs 768fs Duty Cycle Slave mode Master mode
27.648 36.864
Units
Audio Interface Timing Slave mode SCLK Period SCLK Pulse Width Pulse Width High LRCK Edge SCLK (Note SCLK LRCK Edge (Note LRCK SDTO (MSB) (Except mode) SCLK SDTO Master mode SCLK Frequency SCLK Duty SCLK LRCK SCLK SDTO Reset Timing Pulse Width (Note SDTO valid Slave Mode (Note SDTO valid Master Mode (Note
tSCK tSCKL tSCKH tLRSH tSHLR tLRS tSSD fSCK dSCK tMSLR tSSD tPDV tPDV
1/128fs
64fs 4132 4129
1/fs 1/fs
MS0579-E-00
2006/12
[AK5386]
SWITCHING CHARACTERISTICS (Double Quad Speed) (Ta=-40 85°C; VA=4. 5.5V; VD=3.0 3.6V; CL=20pF) Parameter Symbol Master Clock Timing Frequency: 128fs, 256fs fCLK 13.824 192fs, 384fs fCLK 18.432 Pulse Width tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Frequency: Double Speed:256fs 384fs Quad Speed: 128fs 192fs Duty Cycle Slave mode Master mode
27.648 36.864
Units
Audio Interface Timing Slave mode SCLK Period: Double Speed Quad Speed SCLK Pulse Width Pulse Width High LRCK Edge SCLK (Note SCLK LRCK Edge (Note LRCK SDTO (MSB) (Except mode) SCLK SDTO Master mode SCLK Frequency SCLK Duty SCLK LRCK SCLK SDTO
tSCK tSCK tSCKL tSCKH tLRSH tSHLR tLRS tSSD fSCK dSCK tMSLR tSSD
1/128fs 1/64fs
64fs 4132 4129
1/fs 1/fs
Reset Timing Pulse Width (Note tPDV SDTO valid Slave Mode (Note tPDV SDTO valid Master Mode (Note Note SCLK rising edge must occur same time LRCK edge. Note AK5386 reset bringing Note This cycle number LRCK rising edges from "H".
MS0579-E-00
2006/12
[AK5386]
Timing Diagram
1/fCLK MCLK tCLKH 1/fs LRCK tSCK SCLK tSCKH tSCKL
Clock Timing
tCLKL
LRCK tSHLR tLRSH SCLK tLRS tSSD
SDTO
50%VD
Audio Interface Timing (Slave mode)
MS0579-E-00
2006/12
[AK5386]
LRCK
50%VD
tMSLR
dSCK 50%VD
SCLK
tSSD
SDTO
50%VD
Audio Interface Timing (Master mode)
tPDV
SDTO
50%VD
Power Down Reset Timing
MS0579-E-00
2006/12
[AK5386]
OPERATION OVERVIEW System Clock
MCLK, SCLK LRCK (fs) clocks required slave mode. LRCK clock input must synchronized with MCLK, however phase critical. Table shows relationship typical sampling frequency system clock frequency. MCLK frequency, SCLK frequency, OFF) master/slave selected CKS2-0 pins shown Table When MCLK 192fs, 384fs 768fs, sampling frequency does support variable pitch. external clocks (MCLK, SCLK LRCK) must present unless "L". these clocks provided, AK5386 draw excess current internal dynamically refreshed logic. external clocks present, place AK5386 power-down mode (PDN "L"). master mode, master clock (MCLK) must provided unless "L".
32kHz 44.1kHz 48kHz 96kHz 192kHz
128fs 24.576MHz
MCLK 192fs 256fs 384fs 24.576MHz 36.864MHz 36.864MHz Table System Clock Example Sampling Frequency 8kHz 54kHz Normal Speed 8kHz 48kHz 54kHz 108kHz Double Speed 48kHz 96kHz 108kHz 216kHz Quad Speed 96kHz 192kHz Table Sampling Frequency Range Mode
512fs 16.384MHz 22.5792MHz 24.576MHz
768fs 24.576MHz 33.8688MHz 36.864MHz
MCLK 512fs 768fs 256fs 384fs 128fs 192fs
CKS2
CKS1
CKS0
MCLK 128/192fs (Quad Speed) Slave 256/384fs (Double Speed) 512/768fs (Normal Speed) 128/192fs (Quad Speed) Slave 256/384fs (Double Speed) 512/768fs (Normal Speed) Master 256fs (Double Speed) Master 512fs (Normal Speed) Master 128fs (Quad Speed) Master 192fs (Quad Speed) Master 384fs (Double Speed) Master 768fs (Normal Speed) Table Mode Select
Master/Slave
SCLK 48fs 32fs (Note 48fs 32fs (Note 64fs 64fs 64fs 64fs 64fs 64fs
Note SDTO outputs 16bit data SCLK=32fs.
MS0579-E-00
2006/12
[AK5386]
Audio Interface Format
kinds data formats chosen with (Table both modes, serial data first, complement format. SDTO clocked falling edge SCLK. audio interface supports both master slave modes. master mode, SCLK LRCK output with SCLK frequency fixed 64fs LRCK frequency fixed 1fs. Mode SDTO LRCK SCLK 24bit, justified 48fs 32fs 24bit, Compatible 48fs 32fs Table Audio Interface Format Figure Figure Figure
LRCK
SCLK(64fs) SDTO(o)
23:MSB, 0:LSB Data Data
Figure Mode Timing
LRCK
SCLK(64fs) SDTO(o)
23:MSB, 0:LSB Data Data
Figure Mode Timing
Digital High Pass Filter
digital high pass filter offset cancellation. cut-off frequency 1.0Hz (@fs=48kHz) scales with sampling rate (fs). controlled CKS2-0 pins (Table setting (ON/OFF) changed operating, click noise occurs changing offset. recommended that setting changed "L".
MS0579-E-00
2006/12
[AK5386]
Power down
AK5386 placed power-down mode bringing digital filter also reset same time. This reset should always done after power-up. power-down mode, VCOM AGND level. analog initialization cycle starts after exiting power-down mode. Therefore, output data SDTO becomes available after 4129 cycles LRCK clock master mode 4132 cycles LRCK clock slave mode. During initialization, digital data outputs both channels forced complement "0". outputs settle data corresponding input signals after initialization (Settling approximately takes group delay time).
Internal State (Analog) (Digital) Clock
MCLK,LRCK,SCLK
Normal Operation
Power-down
Initialize
Normal Operation
Idle Noise
"0"data
"0"data
Idle Noise
Notes: 4132/fs slave mode 4129/fs master mode. Digital output corresponding analog input group delay (GD). outputs data power-down state. When external clocks (MCLK, SCLK LRCK) stopped, AK5386 should power-down state. Figure Power-down/up sequence example
System Reset
AK5386 should reset once bringing after power-up. slave mode, internal timing starts clocking rising edge (falling edge mode LRCK after exiting from reset power down state MCLK. AK5386 power down state until LRCK input. master mode, internal timing starts when MCLK input.
MS0579-E-00
2006/12
[AK5386]
SYSTEM DESIGN
Figure shows system connection diagram. evaluation board available which demonstrates application circuits, optimum layout, power supply arrangements measurement results.
AINR AINL CKS1 2.2u VCOM AGND
CKS0 CKS2 Mode Control
AK5386
SCLK MCLK LRCK SDTO
Reset
Analog Digital 3.3V
0.1u
Audio Controller
0.1u
DGND
Analog Ground
System Ground
Notes: AGND DGND AK5386 should distributed separately from ground external digital devices (MPU, etc.). digital input pins should left floating. CKS1 should connected AGND. Figure Typical Connection Diagram
Digital Ground
Analog Ground
AINR AINL CKS1 VCOM AGND DGND
CKS0 CKS2
System Controller
AK5386
SCLK MCLK LRCK SDTO
Figure Ground Layout Note: AGND DGND must connected same analog ground plane.
MS0579-E-00
2006/12
[AK5386]
Grounding Power Supply Decoupling AK5386 requires careful attention power supply grounding arrangements. minimize coupling from digital noise, decoupling capacitors should connected respectively. supplied from analog supply system, supplied from digital supply system. power sequence critical between AGND DGND AK5386 must connected analog ground plane. System analog ground digital ground should connected together near where supplies brought onto printed circuit board. Decoupling capacitors should near AK5386 possible, with small value ceramic capacitor being nearest. Voltage Reference voltage input sets analog input range. VCOM 50%VA normally connected AGND with 0.1µF ceramic capacitor. capacitor 2.2µF attached VCOM eliminates effects high frequency noise. load current drawn from these pins. signals, especially clocks, should kept away from VCOM pins order avoid unwanted coupling into AK5386. Analog Inputs inputs single-ended internally biased common voltage (50%VA) with (typ, @fs=48kHz, 96kHz, 192kHz) resistance. input signal range scales with supply voltage nominally 0.6xVA (typ). output data format complement. internal removes offset. AK5386 samples analog inputs 128fs fs=48kHz), 64fs fs=96kHz) 32fs(@ fs=192kHz). digital filter rejects noise above stop band except multiples 64fs 32fs. AK5386 includes anti-aliasing filter filter) attenuate noise around 128fs, 64fs 32fs.
MS0579-E-00
2006/12
[AK5386]
PACKAGE
16pin TSSOP (Unit:
1.10max
6.4±0.2 0.17±0.05 0.1±0.1 Detail 0.5±0.2 0.10 010°
Epoxy Solder free) plate 2006/12
0.22±0.1
0.65
Seating Plane
Material Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment:
MS0579-E-00
[AK5386]
MARKING
5386VT XXYYY
indication Date Code: XXYYY digits) Lot# YYY: Date Code Marketing Code: 5386VT
Revision History
Date (YY/MM/DD) 06/12/13 Revision Reason First Edition Page Contents
IMPORTANT NOTICE These products their specifications subject change without notice. considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, ices systems containing them, require export license other icial approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representativ Director AKM. used here: hazard related system designed intended life support maintenance applications medicine, aerospace, nuclear energy, other fields, which failure unction perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance abov content conditions, buyer distributor agrees assume responsibility liability hold harmless claims arising from said product absence such notification. MS0579-E-00 2006/12
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