Character Controller Driver Logic voltage: 2.7V~5.5V High voltage

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Character Controller Driver Logic voltage: 2.7V~5.5V High voltage

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HT16514
Character Controller Driver
Logic voltage: 2.7V~5.5V High voltage: (max.) Provides driving segment cursor display Display contents: columns rows (16) cursors columns rows (20) cursors columns rows (24) cursors Supports display output (80-segment 24-grid) Parallel data input/output (switchable bit)
units)
Alphanumeric symbolic display through built-in
display chip dot), total characters,
serial data input/output
Built-in oscillation circuit 144-pin LQFP package
plus user-defined characters
Customized acceptable
Applications
Consumer products panel function control Industrial measuring instrument panel function Other similar application panel function control
control
General Description
HT16514 Vacuum Fluorescent Display, controller/driver with matrix display. consists segment output lines grid output lines. display HT16514 character generator which stores characters. HT16514 serial/parallel interface. This controller/driver ideal peripheral device.
Ordering Information
Part Number HT16514-001 HT16514-002 Package Information 144-pin plastic LQFP (Fine pitch) standard (ROM code: 001) 144-pin plastic LQFP (Fine pitch) standard (ROM code: 002)
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Block Diagram
Assignment
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Description
Name Description Logic System (Microprocessor Interface) When parallel mode selected, this utilized select register, either Instruction Register Data Register. (Instruction Register) (Data Register) When serial mode selected, this performs strobe input. Data input when this signal goes During next rising edge this signal, command processing performed. When parallel mode selected (E), this write enable. Writes data falling edge. When parallel mode selected (RD), this read enable. When this data output data Bus. When Serial mode selected, this shift clock input, data will written rising edge. When this device active. Connected external resistor generate oscillation frequency. Oscillator signal output When parallel mode selected this data mode select write, read). When parallel mode selected (WR), this write enable pin. Data will written rising edge signal. When serial mode selected, connect this Read Write chosen instruction. When serial mode selected, this used pin. When parallel mode selected, this needs connected
(RD),
OSCI OSCO XOUT
(WR)
DB0~DB7
When parallel mode selected, these pins used pins. Data stored sequentially, first which sent HT16514 MSB. bits mode selected, only DB4~DB7 used. Initialize internal register commands. segments digits fixed PGND. duty ratio. Duty ratio will determine number grid. relationship between duty ratio these pins shown Table 1-1. Select interface mode (parallel mode serial mode) Serial mode Parallel mode parallel mode, instruction will determine length word. Select interface mode (i80 type mode type mode) type mode type mode Select number display line when power reset resetting. Select line (N=0), display line select flag Function command. Select line (N=1) segment outputs assignment. selection table listed Table Table open: Normal operation mode Test mode testing only, leave this open.
RESET DS0,
RL1, TESTI TESTO
Logic System External Extension Driver) Serial data output extension digit driver. Shift clock pulse extension digit driver. Active during rising edge
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Name Output Pins G1~G24 S1~S80 Power System LGND PGND Pins logic circuit LGND ground logic circuit Power supply pins driver circuit PGND ground driver circuit High-voltage output, grid output pins. High-voltage output, segment output pins. Description Clear signal extension digit driver, active low. digit data stored latch register extension driver output when this signal this signal extension driver outputs Latch enable signal extension digit driver.
Table 1-1. Duty Ratio Setting Note: Duty Ratio 1/16 grid 1/24 grid 1/20 grid 1/40 grid 40)*
When setting 1/40 duty mode, external extension grid driver.
Table 1-2. Segment Setting: Line Display (N=1) Table Table Table Table Table
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Table 1-3. Number Segment Pins Name PGND XOUT OSCO OSCI RESET TESTI (WR) (RD), TESTO LGND PGND Name Name Name
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Table 1-4. Number Segment Pins Name PGND XOUT OSCI RESET TESTI (WR) (RD), TESTO LGND PGND Name Name Name
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Table 1-5. Number Segment Pins Name PGND XOUT OSCO OSCI RESET TESTI (WR) (RD), TESTO LGND PGND Name Name Name
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Table 1-6. Number Segment Pins Name PGND XOUT OSCO OSCI RESET TESTI (WR) (RD), TESTO LGND PGND Name Name Name
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Table 1-7. Segment Setting: Line Display (N=0) care care Table Table Table
Table 1-8. Number Segment Pins Name PGND XOUT OSCO OSCI RESET TESTI (WR) (RD), TESTO LGND PGND Name Name Name
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Table 1-9. Number Segment Pins Name PGND XOUT OSCO OSCI RESET TESTI (WR) (RD), TESTO LGND PGND Name Name Name
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HT16514 Connect Below Figure
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Approximate Internal Connections
Absolute Maximum Ratings
Logic Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Driver Output Voltage.VSS-0.3V Driver Output Current (Total) .500 (Est.) Operating Temperature .-40°C 85°C Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability. Driver Supply Voltage .VSS-0.3V VSS+80V Output Voltage.VSS-0.3V VDD+0.3V Driver Output Current .±50mA Storage Temperature .-55°C 125°C
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D.C. Characteristics
Symbol ILOH ILOL VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH21 VOH22 VOH2G VOL2 Hi-level Output Voltage Parameter Logic Supply Voltage Supply Voltage Operating Current Operating Current VH=50V, VSS=VLGND=VPGND=0V, Ta=-40°C~85°C Test Conditions Conditions Min. 0.7VDD 0.8VDD Typ. Max. 1000 0.3VDD 0.2VDD VSS+0.5 Unit
2.7V~5.5V load, Non-access 2.7V~5.5V load Logic except DB0~DB7, VIN/OUT=VDD
Hi-level Leakage Current 2.7V~5.5V
Hi-level Leakage Current 2.7V~5.5V Logic VIN/OUT=VSS Hi-level Input Current Pull-up Current Input Voltage Input Voltage Input Voltage Input Voltage Hi-level Output Voltage 2.7V~5.5V TEST, VIN=VDD 2.7V~5.5V DB0~DB7, 2.7V~5.5V Except SCK, RESET, (WR) Except E,SCK, RESET, (WR) SCK, RESET, (WR) SCK, RESET, (WR)
DB0~DB7, SI,SO, SDO, SLK, VDD-0.5 IOL1= -0.1mA DB0~DB7, SI,SO, SDO, SLK, IOL1= 0.1mA S1~S80, IOH2= -0.5mA
Low-level Output Voltage 2.7V~5.5V
2.7V~5.5V S1~S80, IOH2= -1mA G1~G24, IOH2= -15mA
Low-level Output Voltage 2.7V~5.5V S1~S80, G1~G24, IOL2=
A.C. Characteristics
Symbol fOSC Parameter Oscillation Frequency Oscillation Frequency Rise Time Test Conditions
VH=50V, VSS=VLGND=VPGND=0V, Ta=-40°C~85°C Min. Typ. Max. 0.25 Unit
Conditions
2.7V~5.5V ROSC=56kW 2.7V~5.5V OSCI external clock 2.7V~5.5V 50pF, S1~S80 2.7V~5.5V CL=50pF, G1~G24 2.7V~5.5V 50pF, S1~S80, G1~G24
Fall Time
Switching Timing
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Timing Conditions M68-Type Parallel Mode, Write Symbol Parameter Test Conditions 4.5V~5.5V Enable Cycle Time 2.7V~4.5V 4.5V~5.5V Enable Pulse Width High 2.7V~4.5V 4.5V~5.5V Enable Pulse Width 2.7V~4.5V ((RS), (CS)) Setup Time ((RS), Hold Time (CS) Hold Time 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V Write Data Setup Time 2.7V~4.5V 4.5V~5.5V Write Data Hold Time 2.7V~4.5V 4.5V~5.5V Reset Pulse Width 2.7V~4.5V Conditions Min. 1000 Typ. Max. Ta=25°C Unit Ta=25°C Test Conditions 4.5V~5.5V Enable Cycle Time 2.7V~4.5V 4.5V~5.5V Enable Pulse Width High 2.7V~4.5V 4.5V~5.5V Enable Pulse Width 2.7V~4.5V ((RS), (CS)) Setup Time ((RS), Hold Time (CS) Hold Time 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V Read Data Setup Time 2.7V~4.5V 4.5V~5.5V Read Data Hold Time 2.7V~4.5V Conditions Min. 1000 Typ. Max. Unit
tCYCLE
PWEH
PWEL
Data
Data
tWRE
M68-Type Parallel Mode, Read Symbol Parameter
tCYCLE
PWEH
PWEL
Data
tDHr
Data
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Parallel Mode (M68 Input)
Parallel Mode (M68 Output)
Note:
input signal rising time falling time (tf, specified 15ns less. timing specified using reference. PWEH specified overlap between being
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Timing Conditions i80-Type, Parallel Mode Symbol Parameter Test Conditions 4.5V~5.5V Hold Time 2.7V~4.5V tCH8 4.5V~5.5V Hold Time 2.7V~4.5V tRS8 4.5V~5.5V Setup Time 2.7V~4.5V tCYC8 4.5V~5.5V System Cycle Time 2.7V~4.5V tCCLW Control Pulse Width (WR) 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V Data Setup Time 2.7V~4.5V tDH8 4.5V~5.5V Data Hold Time 2.7V~4.5V tACC8 4.5V~5.5V Access Time 2.7V~4.5V tOH8 4.5V~5.5V Output Disable Time 2.7V~4.5V tWRE 4.5V~5.5V Reset Pulse Width 2.7V~4.5V DB0~DB7, CL=100pF DB0~DB7, CL=100pF DB0~DB7 DB0~DB7 Conditions Min. Typ. Max. Ta=25°C Unit
tRH8
tCCLR
Control Pulse Width (RD)
tCCHW
Control Pulse Width (WR)
tCCHR
Control Pulse Width (RD)
tDS8
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Parallel Mode (i80)
Note:
input signal rising time falling time (tf, specified 15ns less. timing specified using reference. tCCLW tCCLR specified overlap between level.
Timing Conditions Serial Mode Symbol tCYK tWHK tWLK tHSTBK tDKSTB tWSTB tWAIT tODO Parameter Shift Clock Cycle Test Conditions 4.5V~5.5V 2.7V~4.5V Conditions Min. 1000 Typ. Max.
Ta=25°C Unit
High-level Shift Clock Pulse 4.5V~5.5V Width 2.7V~4.5V Low-level Shift Clock Pulse 4.5V~5.5V Width 2.7V~4.5V Shift Clock Hold Time 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V Data Data Data
Data Setup Time
Data Hold Time
Hold Time
Pulse Width
Wait Time
Output Data Delay Time
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Symbol tODH tWRE Parameter Output Data Hold Time Test Conditions 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V Conditions Data Min. Typ. Max. Unit
Reset Pulse Width
Serial Mode (Input)
Serial Mode (Output)
Measurement Point
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Timing Condition interface: M68, Serial Power Reset Symbol tRES ttrDD tOFF Parameter Resetting Time Rising Time Width
Ta=25°C Min. Typ. Max. Unit
Test Conditions 2.7V~4.5V 2.7V~4.5V 2.7V~4.5V
Conditions
RESET Timing Symbol tRSTD tOFF tRST Parameter Delay Time After Reset Time RST/Pulse Width Test Conditions Conditions Min. Typ. Max. Unit
Power Supply Connection Sequence
Connect PGND LGND externally have
equal potential voltage
avoid faulty connection, turn driver power
supply (VH) after turning logic power supply (VDD). Then turn logic power supply (VDD) after turning driver power supply (VH).
power connection sequence recommended
Holtek followed, possibility that internal logic transistors damaged.
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Functional Description
Interface HT16514 have 8-bit parallel interface serial interface. These modes selected pin.
Serial mode Parallel mode
Interface Table (RD), (RD) (WR) Note (WR) Note Note DB0~DB7 Note DB0~DB7
Note: Keep this Registers (IR, HT16514 8-bit registers, namely, instruction register (IR) data register (DR). register stores instruction code such display clear cursor shift. also contains address information display data (DDRAM) character generator (CGRAM). only written from MPU. temporarily stores data written into read from DDRAM CGRAM. Data written into from automatically written into DDRAM CGRAM internal operation. also used data storage when reading data from DDRAM CGRAM. When address information written into data read then stored into from DDRAM CGRAM internal operation. Data transfer between completed when reads After read, data DDRAM CGRAM next address sent next read from MPU. These registers selected register selector (RS) signal, (Refer Interface table). Registers (IR, Table Common Register Selection Write data during internal operation (display clear, etc.) Read data busy flag (DB7) address counter (DB6~DB0) Write data (DR®DDRAM, CGRAM) Read data (DDRAM, CGRAM®DR)
Busy Flag (Read Flag) Busy flag data (DB7) always output Address Counter (AC) Address counter (AC) assigns address both DDRAM CGRAM. When instruction address written into address information sent from Selection either DDRAM CGRAM also determined concurrently instruction. After writing into read from) DDRAM CGRAM, automatically incremented decremented cursor position then output DB0~DB6 when RS=0 (Refer Registers (IR, Table).
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Display Data (DDRAM) Display data (DDRAM) stores display data represented 8-bit character codes. extended capacity bits characters. area DDRAM that used display used general data RAM. Refer DDRAM address table relationships between DDRAM address positions VFD. DDRAM address (ADD) address counter (AC) hexadecimal. DDRAM Address Table High Order Bits Hexadecimal Example: DDRAM address
1-line display (N=0)
Order Bits
Hexadecimal
Display Position (Digit) DDRAM Address (Hexadecimal) When there fewer than display characters, display begins head position. example, using only HT16514, characters displayed. When display shift operation performed, DDRAMaddress shifts shown following table. Example: 1-line 24-character Display Table Display Position (Digit) DDRAM Address (Hexadecimal) Shift Left
Shift Right
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2-line display (N=1)
Display Position (Digit) DDRAM Address (Hexadecimal)
When number display character less than lines, lines displayed from head. first line address second line start address consecutive. example, using only HT16514, characters lines displayed. When display shift operation performed, DDRAM address shifts shown following table. Example: 2-line 24-character Display Table Display Position (Digit) DDRAM Address (Hexadecimal)
Shift Left
Shift Right
line display
DDRAM stores character code each character being displayed VFD. Valid DDRAMaddresses 67H. DDRAMnot used display characters used general purpose RAM. tables below show relationship between DDRAMaddress character position display shift shown following table. Example: 2-line 40-character Display Table Display Position (Digit) DDRAM Address (Hexadecimal)
Shift Left
Shift Right
HT16514 Display
Extension Driver Display
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Character Generator (CGROM)
CGROM generating character patterns dots from 8-bit character codes, generates type character patterns. character codes shown following page. Character codes allocated CGRAM
Character Code Table (ROM Code: 001) Rev. 1.00 October 2006
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Character Code Table (ROM Code: 002)
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Character Generator (CGRAM) CGRAM stores pixel information (1=pixel 0=pixel off) eight user-define characters. Valid CGRAM addresses 3FH. CGRAM used defined characters used general purpose RAM. Character codes 00H~07H 08H~0FH) assigned user-defined characters (see section character font tables). table below shows relationship between character codes, CGRAM addresses, CGRAM data each user-defined character. Relationship between CGRAM address character code (DDRAM) (with cursor) character patterns (CGRAM)
itio itio
itio
Note:
means care Character code bits correspond CGRAM address bits bits: types) CGRAM address bits designate character pattern line position. line cursor position display formed logical with cursor. Maintain line data, corresponding cursor display position cursor display. line data will light line regardless cursor presence. Character pattern position corresponds CGRAM data bits (bit being left). CGRAM character patterns selected when character code bits However, since character code effect, display example above selected either character code 08H. CGRAM data corresponds display selection selection.
Timing Generation Circuit Timing generation circuit generates timing signals operation internal circuit such DDRAM, CGRAM CGROM. reads timing display internal operation timing access generated separately avoid interfering with each other. Therefore, when writing data DDRAM, example, there will undesirable interference, such flickering, areas other than display area.
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Driver Circuit driver circuit consists grid signal drivers segment signal drivers. When character font number digits selected hardware (DS0, DS1) power required grid signal drivers automatically output drive waveforms, while other grid signal driver continue output non-selection waveforms. Sending serial data latched when display data character pattern corresponds last address display data (DDRAM). Since serial data latched when display data character pattern corresponds starting address enters internal shift register, HT16514 drives from head display. Cursor/Blink Control Circuit Cursor/blink control circuit generates cursor character blinking. cursor blinking will appear with digit located display data (DDRAM) address address counter (AC). example, when address counter 08H, cursor position displayed DDRAM address 08H.
Cursor/Blink Control Table
1-line Display
2-line Display Note: cursor blinking appears when address counter (AC) selects character generator (CGRAM). However, cursor blinking become meaningless when cursor blinking displayed meaningless position when CGRAM address.
Interface With Mode
Parallel Data Transfer (IM=1, MPU=1)
This interface (data transfer) with bits interface. However, internal registers consist bits. Using twice must perform data transfer bits. When using 4-bit parallel data transfer, pins remain Low. transfer order initially from higher bits then followed lower bits D3). checks performed before transferring higher bits. checks required before transferring lower bits.
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4-bit data transfer (M68)
8-bit data transfer (M68)
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Parallel mode (IM=1, MPU=0) When setting selected. HT16514, each time data sent from MPU, type pipeline process between LSIs performed through holder attached internal data bus. There certain restriction read sequence this display data RAM. Please advised that data specified address generated read instruction issued immediately after address setup. This data generated data read second time. Thus, dummy read required whenever address setup write cycle operation selected. This relationship shown following figure.
itin
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Serial Mode synchronous serial interface mode, instructions data sent between host module using 8-bit bytes. bytes required read/write cycle transmitted first. start byte contains high bits, Read/Write (R/W) control bit, Register Select (RS) control bit, bit. subsequent byte contains instruction/data bits. determines whether cycle read (high) write (low) cycle. used identify second byte instruction (low) data (high). This mode uses strobe (ST) control signal, Serial Clock (SCK) input, Serial (SI/SO) line transfer information. write cycle, bits clocked into module rising edge SCK. read cycle, bits start byte clocked into module rising edge SCK. After minimum wait time, each instruction/data byte read from module after each falling edge SCK. Each read/write cycle begins falling edge ends rising edge. valid read/write cycle, must high cycle.
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Commands Instruction Clear display Description Clear display, sets DDRAM address 00H. Sets DDRAM address 00H. Also returns display shifted original position. DDRAM contents remain unchanged. Sets cursor direction specifies display shift. These operations performed during writing/reading data. Sets display ON/OFF(D), cursor ON/OFF(C), cursor blink character position (B). Shifts display cursor, DDRAM contents.
Cursor home
Entry mode
Display On/Off
Cursor display shift
Function
Sets data length parallel data transfer) Number line Sets address CGRAM. After that, data DDRAM transferred. Sets address DDRAM. After that, data DDRAM transferred. Reads busy flag (BF) address counter. output always. Writes data into CGRAM DDRAM. Reads data from CGRAM DDRAM.
CGRAM address
DDRAM address
Read busy flag address Write data CGRAM DDRAM Read data from CGRAM DDRAM Note:
BF=0
Write data Read data
I/D=1: Increment, I/D=0: Decrement S=1: Display shift enable, S=0: Cursor shift enable S/C=1: Display shift, S/C=0: Cursor shift R/L=1: Right shift, R/L=0: Left shift DL=1: 8bit, DL=0: 4bit BR1, BR0= (00: 100%) (01: 75%) (10: (11: 25%) care ACG: CGRAM address ADD: DDRAM address ACC: Address counter DDRAM: Display Data CGRAM: Character Generator
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Clear Display
instruction:
Fills locations display data (DDRAM) with (Blank character). Clears contents address counter (ACC) 00H. Sets display zero character shifts (returns original position). Sets address counter point display data (DDRAM). cursor displayed, move cursor left most character line (upper line). Sets address counter (ACC) increment each access DDRAM CGRAM. When resetting
Cursor Home
instruction:
Clears contents address counter (ACC) 00H. Sets address counter point display data (DDRAM). Sets display zero character shifts (returns original position). cursor displayed, move cursor left most character line (upper line).
Entry Mode
This instruction selects whether cursor position increments decrements after each DDRAM CGRAM access determines direction information display shifts after each DDRAM write. instruction also enables disables display shifts after each DDRAM write (information display does shift after DDRAM read CGRAM access). DDRAM, CGRAM, cursor position affected this instruction. I/D=0: decrements after each DDRAM CGRAM access. S=1, information display shifts right character position after each DDRAM write. I/D=1: increments after each DDRAM CGRAM access. S=1, information display shifts left character position after each DDRAM write. S=0: S=1: display shift function disabled. display shift function enabled. Cursor Move Display Shift Entry Mode After Writing DDRAM Data Cursor moves character left. Cursor moves character right. After Reading DDRAM Data Cursor moves character right. Cursor moves character right.
Display shifts character right without cursor Cursor moves character left. movements. Display shifts character left without cursor moveCursor moves character right. ments.
When resetting
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Display ON/OFF
This instruction selects whether display cursor selects whether character current cursor position blinks. DDRAM, CGRAM, cursor position affected this instruction.
D=0: display (display blank). D=1: display (contents DDRAM displayed). C=0: cursor off. C=1: cursor (8th rows pixels). B=0: blinking character function disabled. B=1: blinking character function enabled Note: character with pixels will alternate with character displayed current cursor position rate with duty cycle.
When resetting
Cursor Display Shift This instruction shifts display and/or moves cursor left right, without reading writing DDRAM. selects movement cursor movement both cursor display.
S/C=1: Shift both cursor display. S/C=0: Shift only cursor. selects whether moving direction left right display and/or cursor. R/L=1: Shift character right. R/L=0: Shift character left.
Cursor Display Shift Function Cursor Position Decrements (left) Increments (right) Decrements (left) Increments (right) Information Display change change Shifts character position left Shifts character position right
This instruction sets width data parallel interface modes, number display lines, luminance level (brightness) VFD. DDRAM, CGRAM, cursor position affected this instruction.
DL=0: Sets data width parallel interface modes 4-bit (DB7~DB4). DL=1: Sets data width parallel interface modes 8-bit (DB7~DB0). N=0: Sets number display lines (this setting recommended). N=1: Sets number display lines
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BR1, flag brightness control modulate pulse width segment output follows. tDSP@200ms, tBLK@10ms Brightness 100%
Note: means number grid, T=nx (tDSP+tBLK) When resetting
CGRAM Address
This instruction places 6-bit CGRAM address specified DB5~DB0 into cursor position. Subsequent data writes (reads) will (from) CGRAM. DDRAM CGRAM contents affected this instruction. When resetting: care.
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DDRAM Address
This instruction places 7-bit DDRAM address specified DB6~DB0 into cursor position. Subsequent data writes (reads) will (from) DDRAM. DDRAM CGRAM contents affected this instruction. Valid DDRAM Address Ranges Number Character line line When resetting: care. Read Busy Flag Address Address Range 00H~27H 40H~67H
This instruction reads Busy Flag (BF)* value address counter binary This address counter used CGRAM DDRAM addresses, value determined previous instruction. address counter contents same instructions address address Note: means Busy Flag (BF) always outputs Write Data CGRAM DDRAM
This instruction writes 8-bit data byte DB7~DB0 into DDRAM CGRAM location addressed cursor position. most recent DDRAM CGRAM Address instruction determines whether write DDRAM CGRAM. This instruction also increments decrements cursor position shifts display according bits Entry Mode instruction. Read Data from CGRAM DDRAM
This instruction reads 8-bit data byte from DDRAM CGRAM location addressed cursor position DB7~DB0. most recent DDRAM CGRAM Address instruction determines whether read from DDRAM CGRAM. This instruction also increments decrements cursor position shifts display according bits Entry Mode instruction. Before sending this instruction, DDRAM CGRAM Address instruction should executed cursor position desired DDRAM CGRAM address read. After reading data, value address automatically increased decreased according selection Note: Address counter automatically increased decreased after data write instruction CGRAM DDRAM executed. this moment data pointed address counter cannot read data read instruction executed. Therefore, read data correctly, executing address instruction cursor shift instruction (the only case DDRAM data read) just before reading, reading second data case reading data continuously executing read data instruction.
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Power Reset After power-on reset, module initialize following conditions:
DDRAM locations (character code space). cursor position DDRAM address relationship between DDRAM addresses character positions non-shifted position. Entry Mode instruction bits:
I/D=1: cursor position increments after each DDRAM CGRAM access. S=1, information display shifts left character position after each DDRAM write. S=0: display shift function disabled.
Display On/Off Control instruction bits:
D=0: C=0: B=0:
display (display blank). cursor off. blinking character function disabled.
Function instruction bits:
DL=1: Sets data width parallel interface modes bits (DB7~DB0). N=1: Number display lines BR1, BR0=0,0: Sets luminance level 100%.
interface, duty ratio selection based following table.
Relationship between Status HT16514 Selection Power Reset Name TEST open open open open open open Function Self test mode Serial interface Parallel interface Duty= 1/16 display) Duty= 1/20 display) Duty= 1/24 display) Duty= 1/40 display) Extension driver should used. number line selected instruction. necessary extension driver. number line selected instruction. Remark This effective aging. SCK, DB7~DB4 DB7~DB0
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Example (8-bit Data Parallel, Data Increment Mode)
Initialization Sequence Data Initialization Programming Example Data (M68 series MPU) Description
Power Function Data length: bits Display line number: lines Brightness: CGRAM address
Write data CGRAM bytes characters)
DDRAM address
Write data DDRAM bytes characters)
Display ON/OFF Display cursor OFF, cursor blink
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Application Circuits
Note: ROSC=56kW oscillator resistor
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Package Information
144-pin LQFP Outline Dimensions
Symbol
Dimensions Min. 21.9 19.9 21.9 19.9 1.35 0.45 Nom. Max. 22.1 20.1 22.1 20.1 1.45 0.75
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October 2006
HT16514
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) Floor, Building No.889, Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit Productivity Building, Cross Science Road Gaoxin Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright 2006 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. products authorized critical components life support devices systems. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
Rev. 1.00
October 2006

Character Controller Driver Logic voltage: 2.7V~5.5V High voltage

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