Tools Information FAQs Application Note HA0017E Controlling Read/Write
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HT49RU80/HT49CU80 Type 8-Bit
Tools Information FAQs Application Note HA0017E Controlling Read/Write Function HT24 Series EEPROM Using HT49 Series MCUs HA0024E Using HT49 Series HA0025E Using Time Base HT49 Series HA0026E Using Ports HT49 Series HA0027E Using Timer/Event Counter HT49 Series
Operating voltage: Buzzer output On-chip crystal, 32768Hz crystal oscillator HALT function wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
input lines output lines bidirectional lines external interrupt inputs 8-bit 16-bit programmable timer/event
consumption
16-level subroutine nesting UART Universal Asynchronous Receiver
Transmitter
manipulation instruction 16-bit table read instruction 0.5ms instruction cycle with 8MHz system clock powerful instructions instructions executed within machine cycles voltage reset/detector functions 100-pin package
counters with programmable frequency divider function
driver with segments program memory data memory Real Time Clock 8-bit prescaler Watchdog Timer
General Description
These devices 8-bit, high performance, RISC architecture microcontrollers specifically designed wide range applications. mask version, HT49CU80, fully functionally compatible with version HT49RU80 device. advantages power consumption, flexibility, programmable frequency divider, timer functions, oscillator options, power-down wake-up functions buzzer driver addition flexible configurable interface, enhance versatility these devices control wide range LCD-based application possibilities such measuring scales, electronic multimeters, meters, timers, calculators, remote controllers many other LCD-based industrial home appliance applications.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Block Diagram
ifte
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Assignment
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Description
Name Options Description Bidirectional 8-bit input/output port. Each this port configured wake-up input configuration option. Configuration options deterWake-up mine whether pins PA0~PA3 configured CMOS outputs NMOS inCMOS NMOS put/output pins. PA0~PA3 configured NMOS input/output pins, Pull-high then pull-high options available apply pins, individual PA0/PA1 BZ/BZ pins. Pins PA4~PA7 always configured NMOS input/output pins with pull-high resistors connected. inputs Schmitt Trigger types. Pins PA0, pin-shared with respectively, function which chosen configuration options. 8-bit Schmitt Trigger input port. Each input connected internal pull-high resistor. Pins pin-shared with INT0 INT1 respectively. Pins PB2, pin-shared with TMR0, TMR1 TMR2 respectively. Bidirectional 8-bit input/output port. configuration options determine whether four pins PC0~PC3 four pins PC4~PC7 configured CMOS outputs NMOS input/output pins. Pins must configured CMOS outputs NMOS input/output pins blocks four pins, individual pins cannot selected. pins PC0~PC3 PC4~PC7 configured NMOS input/output pins, then pull-high option available each block four pins. Individual pins cannot selected have pull-high option. inputs Schmitt Trigger types. Pins pin-shared with UART pins respectively. 7-bit output port. Each setup either CMOS output output configuration options. power supply. This implemented power only. VLCD levels greater less than levels. maximum voltage, connect VDD, VLCD voltage pump duty cycle configuration option will determine whether COM3/SEG47 configured SEG47 segment driver common COM3 output driver panel. COM0~COM2 common outputs. driver outputs panel segments OSC1 OSC2 connected external network external crystal (determined configuration option) internal system clock. external system clock operation, OSC2 output system clock. oscillator pins OSC3 OSC4 used system clock, then OSC1 OSC2 pins should left floating. OSC3 OSC4 connected 32768Hz crystal form Real Time Clock timing purposes form system clock. Schmitt Trigger reset input, active low. Positive power supply Negative power supply, ground
PA0/BZ PA1/BZ PA3/PFD PA4~PA7
PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4/TMR2 PB5~PB7
PC0/TX PC1/RX PC2~PC7
CMOS NMOS Pull-high
PD0/SEG40~ PD6/SEG46 VLCD VMAX COM0~COM2 COM3/SEG47 SEG0~SEG39
CMOS Output Output 1/2, Duty
OSC1 OSC2
Crystal
OSC3 OSC4
System Clock
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Total .150mA Total Power Dissipation .500mW Storage Temperature .-50°C 125°C Operating Temperature.-40°C 85°C Total.-100mA
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
D.C. Characteristics
Symbol Parameter Test Conditions load, UART load, system HALT, HALT, UART load, system HALT, HALT, type, UART load, system HALT HALT, type, UART load, system HALT, HALT, type, bias, UART load, system HALT, HALT, type, bias, UART load, system HALT, HALT, type, bias, UART load, system HALT, HALT, type, bias, UART Conditions disabled, fSYS=4MHz disabled, fSYS=8MHz load, fSYS=4MHz, UART load, fSYS=4MHz, UART load, fSYS=8MHz, UART load, fSYS=8MHz, UART Min. Typ. Max.
Ta=25°C Unit
VLCD IDD1
Operating Voltage Power Supply (Note Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (fSYS=RTC OSC) Standby Current (*fS=fSYS/4) Standby Current (*fS=RTC OSC) Standby Current (*fS=WDT OSC) Standby Current (*fS=RTC OSC) Standby Current (*fS=RTC OSC) Standby Current (*fS=WDT OSC) Standby Current (*fS=WDT OSC)
IDD2 IDD3 IDD4 IDD5
ISTB1
ISTB2
ISTB3
ISTB4
ISTB5
ISTB6
ISTB7
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Symbol Parameter Input Voltage Ports, TMR0, TMR1, TMR2, INT0 INT1 Input High Voltage Ports, TMR0, TMR1, TMR2, INT0 INT1 Input Voltage (RES) Input High Voltage (RES) Port Sink Current IOH1 Port Source Current IOL2 Common Segment Current Common Segment Current Pull-high Resistance VLVR VLVD Note: Voltage Reset Voltage Voltage Detector Voltage VOH=0.9VA VOL=0.1VA VOH=0.9VDD Test Conditions Conditions Min. Typ. Max. Unit
VIL1
0.3VDD
VIH1 VIL2 VIH2 IOL1
VOL=0.1VDD
0.7VDD 0.9VDD -180
-160 -360
0.4VDD
IOH2
value refer driver section. please refer clock option
A.C. Characteristics
Symbol Parameter System Clock (Crystal OSC, OSC) System Clock (32768Hz Crystal OSC) Frequency Timer Frequency (50% duty) Test Conditions tRES tSST tLVR tINT Note: External Reset Pulse Width System Start-up Timer Period Voltage Width Reset Interrupt Pulse Width *tSYS= 1/fSYS1 1/fSYS2 2.2V~5.5V 3.3V~5.5V Wake-up from HALT Conditions 2.2V~5.5V 3.3V~5.5V Min. 0.25 Typ. 32768 32768 1024 Max. 4000 8000 4000 8000
Ta=25°C Unit *tSYS
fSYS1 fSYS2 fRTCOSC fTIMER
tWDTOSC Watchdog Oscillator Period
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Functional Description
Execution Flow system clock derived from either crystal oscillator 32768Hz crystal oscillator. internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. pipelining scheme makes possible each instruction effectively executed cycle. instruction changes value program counter, cycles required complete instruction. Program Counter program counter (PC) bits wide controls sequence which instructions stored program executed. contents
specify maximum 16384 addresses. After accessing program memory word fetch instruction code, value incremented then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call, initial reset, internal interrupt, external interrupt, returning from subroutine, manages program transfer loading address corresponding each instruction. conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction; otherwise program proceeds next instruction.
Execution Flow Program Counter BP.5 *12~*8 00000 00000 00000 00000 00000 00000 00000 *12~*8 #12~#8 S12~S8
Mode Initial Reset External Interrupt External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow UART Interrupt Multi Function Interrupt Skip Loading Jump, Call Branch Return from Subroutine
Program Counter (within current bank)
Program Counter Note: *13~*0: Program counter bits #12~#0: Instruction code bits
S13~S0: Stack register bits @7~@0: bits
Rev. 1.10
March 2007
HT49RU80/HT49CU80
lower byte known PCL, readable writeable register. Moving data into performs short jump. destination within locations. When control transfer takes place, additional dummy cycle required. Program Memory program memory used store program instructions which executed. also contains data, table, interrupt entries, organised into banks which addressed program counter table pointer. register bits5~bits7 used select Program Memory bank. When BP.7~BP.5 000B, Program Memory bank selected ranges from 0000H 1FFFH. When BP.7~BP.5 001B, Program Memory bank selected which ranges from 2000H 3FFFH. CALL instruction provide full bits addressing allow branching anywhere within program memory bank. When executing CALL instruction, highest address provided BP.5. When executing CALL instruction, bank select must correctly programmed ensure
that desired program memory bank addressed. return from CALL instruction interrupt executed, entire 14-bit program counter popped stack. Certain locations reserved special usage:
Location 000H
Location 000H reserved program initialisation. After chip reset, program always begins execution this location.
Location 004H
Location 004H reserved external interrupt service program. INT0 input activated, interrupt enabled, stack full, program will jump this location begin execution.
Location 008H
Location 008H reserved external interrupt service program also. INT1 input activated, interrupt enabled, stack full, program will jump this location begin execution.
Location 00CH
itia
Location 00CH reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program will jump this location begin execution.
Location 010H
Location 010H reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program will jump this location begin execution.
Location 014H
This location reserved UART interrupt service program. UART interrupt results from UART interrupt enabled stack full, program will jump this location begin execution.
Location 018H
Program Memory
This location reserved multi function interrupt service program. multi function interrupt results from Timer/Event Counter overflow, time base interrupt occurs, counter overflow, related interrupts enabled multi function interrupt enabled stack full, program will jump this location begin execution. Table Location
Instruction(s) TABRDC TABRDL
*13~*8 TBHP 111111
Table Location Note: *13~*0: Table location bits @7~@0: Bits TBLP TBHP: Table pointer higher-order bits
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Table location
location program memory used look-up tables. instructions (page specified TBHP TBLP) (the last page) transfer contents lower-order byte specified data memory, higher-order byte TBLH (08H). higher-order byte table pointer TBHP (1FH) lower-order byte table pointer TBLP (07H) read/write registers, which indicate table locations. Before accessing table data, location placed TBHP TBLP. TBLH register read only cannot restored. main routine interrupt service routine both employ table read instruction, contents TBLH register main routine likely changed table read instruction used interrupt service routine. this happens errors occur. Therefore, using table read instruction main routine interrupt service routine simultaneously should avoided. However, table read instruction used both main routine interrupt service routine interrupt should disabled prior executing table read instruction. should re-enabled until TBLH main routine been backed table related instructions require cycles execute. Stack Register STACK stack register special part memory used save contents program counter. stack organised into levels neither part data memory part program memory, neither readable writeable. activated level indexed stack pointer, known neither readable writeable. start subroutine call interrupt acknowledge, contents program counter pushed onto stack. subroutine interrupt routine, indicated return instruction, RETI, contents program counter restored their previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag recorded acknowledge still inhibited. Once Stack Pointer decremented, RETI, interrupt serviced. This feature prevents stack overflow, allowing programmer structure easily. Likewise, stack full, subsequently executed, stack overflow occurs first entry lost. Only most recent return addresses stored. Data Memory including memory, data memory, total capacity bits, divided into functional groups, namely, special function registers general purpose data memory most which readable/ writeable, although some read only.
General Purpose Data Memory subdivided into three banks, Banks each which capacity 8bits. bank pointer, selects which bank used, however care should exercised when manipulating bank pointer also used select Program Memory bank. 00000 00001 00010 00011 Bank
general purpose data memory, addressed from (bank0, used data control information under instruction commands. areas directly handle arithmetic, logic, increment, decrement, rotate operations. Except some dedicated bits, each reset manipulation instructions They also indirectly accessible through Memory pointer register MP0, Memory pointer register MP1. There also special part memory memory. Bits this special part memory mapped pixel one. This memory located data memory bank Indirect Addressing Registers Locations indirect addressing registers that physically implemented. read/write operation [00H] [02H] accesses data memory pointed MP1, respectively. Reading locations indirectly returns result 00H. Writing indirectly leads operation. direct transfer data between indirect addressing registers supported. memory pointer registers, MP1, both 8-bit registers used access data memory combining corresponding indirect addressing registers. only applied memory located bank while applied data memory from bank bank bank well display memory which located bank Accumulator accumulator, ACC, related operations. also mapped location data memory capable operating with immediate data. data transfers between data memory locations must pass through ACC.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Arithmetic Logic Unit This circuit performs 8-bit arithmetic logic operations provides following functions:
Arithmetic operations ADD, ADC, SUB, SBC, Logical operations AND, XOR, Rotations RLC, Increment Decrement INC, Branch decisions SNZ, SIZ, etc.
only saves results data operation also changes status register. Status Register STATUS status register bits wide contains, carry flag (C), auxiliary carry flag (AC), zero flag (Z), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). also records status information controls operation sequence. Except flags, bits status register altered instructions similar other registers. Data written into status register does alter flags. Operations related status register, however, yield different results from those intended. flags only changed Watchdog Timer overflow, device power-on, clearing Watchdog Timer executing instruction. flags reflect status latest operations. entering interrupt sequence executing subroutine call, status register will automatically pushed onto stack. contents status important, subroutine likely corrupt status register, precautions should taken save properly. Interrupts device provides external interrupts, three internal timer/event counters interrupts, internal time base interrupt, internal real time clock interrupt, UART TX/RX interrupt. interrupt control register INTC0, interrupt control register INTC1, both contain interrupt control bits that used enable/disable status record interrupt request flags. Once interrupt subroutine serviced, other interrupts blocked, clearing bit. This scheme prevent further interrupt nesting. Other interrupt requests take place during this interval, only interrupt request flag will recorded. certain interrupt requires servicing within service routine, corresponding INTC0 INTC1 register order allow interrupt nesting. Once stack full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack should prevented from becoming full.
Mapping Rev. 1.10
March 2007
HT49RU80/HT49CU80
Label Function operation results carry during addition operation borrow does take place during subtraction operation, otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction, otherwise cleared. result arithmetic logic operation zero, otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa, otherwise cleared. cleared either system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read STATUS (0AH) Register interrupts provide wake-up function. interrupt serviced, control transfer occurs pushing contents program counter onto stack followed branch subroutine specified program memory location. Only contents program counter pushed onto stack. contents register status register altered interrupt service program which corrupts desired control sequence, contents should saved advance. External interrupts triggered high transition INT0 INT1 pins, which will result their their related interrupt request flags, EIF0 EEF1, being set. After interrupt enabled, stack full, high transition occurs external interrupt pins, subroutine call location occurs. When interrupt service routine serviced, interrupt request flags, EIF0 EIF1, global enable bit, EMI, cleared disable other interrupts. internal Timer/Event Counter interrupt initialised setting Timer/Event Counter interrupt request flag, T0F. This will occur when timer overflows. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag, T0F, reset, cleared disable further interrupts. Timer/Event Counter operated same manner related interrupt request flag T1F, subroutine call location 10H. UART interrupt initialised setting interrupt request flag, URF, that caused regular UART receive signal, caused UART transmit signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag, URF, reset cleared disable further interrupts. multi function interrupt initialised setting interrupt request flag, MFF, that caused regular internal Timer/Event Counter overflow, caused Rev. 1.10 time base signal caused real time clock signal. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag, MFF, reset cleared disable further interrupts. During execution interrupt subroutine, other interrupt acknowledgments held until instruction executed related interrupt control both stack full). return from interrupt subroutine executed. RETI sets enables interrupt service, does not. Interrupts occurring interval between rising edges consecutive pulses serviced latter pulses corresponding interrupts enabled. case simultaneous requests, priorities following table apply. These masked resetting bit. Interrupt Source External interrupt External interrupt Timer/Event Counter overflow Timer/Event Counter overflow UART interrupt Multi function interrupt (Timer Time base, RTC) Priority Vector 004H 008H 00CH 010H 014H 018H
recommended that program should within interrupt subroutine. because interrupts often occur unpredictable manner require serviced immediately some applications. During that period, only stack left, enabling interrupt well controlled, operation interrupt subroutine damage original control sequence.
March 2007
HT49RU80/HT49CU80
Label EEI0 EEI1 ET0I EIF0 EIF1 Function Controls master (global) interrupt (1=enable; 0=disable) Controls external interrupt (1=enable; 0=disable) Controls external interrupt (1=enable; 0=disable) Controls Timer/Event Counter overflow interrupt (1=enable; 0=disable) External interrupt request flag (1=active; 0=inactive) External interrupt request flag (1=active; 0=inactive) Timer/Event Counter overflow request flag (1=active; 0=inactive) Unused bit, read INTC0 (0BH) Register Label ET1I EURI EMFI Function Controls Timer/Event Counter overflow interrupt (1=enable; 0=disable) Controls UART interrupt (1=enable; 0:disable) Controls multi-function interrupt (1=enable; 0:disable) Unused bit, read Timer/Event Counter overflow request flag (1=active; 0=inactive) UART interrupt request flag (1=active; 0=inactive) Multi function interrupt request flag (1=active; 0=inactive) INTC1 (1EH) Register Label ET2I ETBI ERTI Function Controls Timer/Event Counter overflow interrupt (1=enable; 0=disable) Controls time base interrupt (1=enable; 0=disable) Controls real time clock interrupt (1=enable; 0=disable) Unused bit, read Timer/Event Counter interrupt request flag (1=active; 0=inactive) Time base interrupt request flag (1=active; 0=inactive) Real time clock interrupt request flag (1=active; 0=inactive) MFIC (23H) Register
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Oscillator Configuration These devices contain three kinds system clocks, oscillator, crystal oscillator 32768Hz crystal oscillator, choice which determined configuration options. matter what type oscillator selected, signal used system clock. power down mode stops system oscillator crystal oscillator type. 32768Hz crystal system oscillator will continue even power down mode. 32768Hz crystal oscillator selected system oscillator, system oscillator will continue fSYS instruction execution will cease. Since system oscillator also designed timing purposes, internal timing such that RTC, time base operation continues even system enters power down mode. three oscillators, oscillator used, external resistor between OSC1 required, whose range should from 24kW 1MW. frequency equal system clock divided available OSC2. This used synchronisation purposes open drain output pull-high resistor should connected. oscillator provides most cost effective solution, but, frequency oscillation vary with VDD, temperature, process variations. therefore, suitable timing sensitive operations where accurate oscillator frequencies desired. crystal oscillator selected, crystal connected between OSC1 OSC2 needed provide feedback phase shift required oscillator. other external components required. resonator connected between OSC1 OSC2 replace crystal frequency reference, external capacitors connected between OSC1/OSC2 ground required. further oscillator circuit designed real time clock also exists. This operates sole frequency 32768Hz, which 32768Hz crystal should connected between pins OSC3 OSC4. oscillator circuit controlled start quickly clearing RTCC register. After power oscillator will quick start mode, recommended that turned after about seconds conserve power. oscillator free running on-chip oscillator requiring external components. Although when system enters power down mode, system clock stops, oscillator will continue with period approximately 65ms oscillator disabled configuration option conserve power. Watchdog Timer clock source sourced from dedicated oscillator (WDT oscillator), from instruction clock (system clock/4) real time clock oscillator (RTC oscillator). timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. disabled configuration option. disabled, instruction executions relating will lead operation. time-out period fS/215~fS/216.
illa
illa
illa
System Oscillator
Watchdog Timer
Rev. 1.10
March 2007
HT49RU80/HT49CU80
clock source chooses internal oscillator clock source, time-out period vary with temperature, VDD, process variations. clock source chosen instruction clock, then when power down mode entered, must noted that will stop counting lose protective function. When device operates noisy environment, using oscillator strongly recommended, since power down mode will stop system clock. overflow under normal operation initialises sets status power down mode, overflow initialises only program counter reset zero. clear contents, there three methods adopted. These external reset level pin), software instruction, instruction. There methods using software instructions clear Watchdog Timer, which must chosen configuration option. first option single instruction while second commands first option, simple execution will clear while second option, both must both executed successfully clear WDT. Note that this second option, used clear WDT, successive executions this instruction will have effect, only execution instruction will clear WDT. Similarly after instruction been executed, only successive instruction clear Watchdog Timer. Multi-function Timer These devices provide multi-function timer WDT, time base with different time-out periods. multi-function timer consists 8-stage divider 7-bit prescaler, with clock source coming from OSC, instruction clock which system clock divided multi-function timer also provides selectable frequency signal, ranging from fS/22 fS/28, driver circuits, selectable frequency signal, ranging from fS/22 fS/29, buzzer output selectable configuration options. obtain proper display, recommended that frequency near possible 4kHz selected driver circuits. Time Base time base offers periodic time-out period generate regular internal interrupt. time-out period ranges from /212 fS/215 selected configuration option. time base time-out occurs, related interrupt request flag, TBF, will set. interrupt enabled, stack full, subroutine call location will take place. time base time-out signal also applied clock source Timer/Event Counter order longer time-out period.
Real Time Clock real time clock, abbreviated RTC, operated same manner time base that used supply regular internal interrupt. time-out period ranges from fS/28 fS/215 actual value setup software programming Writing data RT2, bits RTCC register provides various time-out periods. time-out occurs, related interrupt request flag, RTF, will set. interrupt enabled, stack full, subroutine call location will take place. real time clock time-out signal also used clock source Timer/Event Counter order longer time-out periods. Clock Divided Factor 210* 211*
Note: recommended used
Real Time Clock Rev. 1.10 March 2007
HT49RU80/HT49CU80
Power Down Mode HALT power down mode initialised when instruction executed results following.
system oscillator fSYS turn
oscillator keeps running, oscillator real time clock selected.
contents data memory registers remain
unchanged.
cleared starts recounting,
wake-up event occurs, takes 1024 tSYS system clock periods resume normal operation. other words, dummy period inserted after wake-up. wake-up results from interrupt acknowledgment, actual interrupt subroutine execution delayed more than cycle. However, wake-up results next instruction execution, execution will performed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering power down mode. Reset There three ways which reset occur.
reset during normal operation reset during HALT time-out reset during normal operation
clock source sourced from oscillator real time clock oscillator.
ports maintain their original status. flag flag cleared. driver keeps running,
selected. system will exit from power down mode external reset, interrupt, external falling edge signal port overflow. external reset causes device initialisation, while overflow performs After examining flags, reason chip reset determined. flag cleared system power-up executing instruction, executing instruction. However flag time-out occurs, corresponding wake-up only resets program counter stack pointer, leaves other registers their original state. port wake-up interrupt methods considered continuation normal execution. Each port independently selected wake device using configuration options. Awakening from port stimulus, program resumes execution next instruction. When awakening from interrupt, sequences occur. related interrupt disabled interrupt enabled stack full, program resumes execution next instruction. interrupt enabled, stack full, regular interrupt response takes place. When interrupt request flag before entering power down mode, system cannot awakened using that interrupt.
time-out during power down differs from other chip reset conditions, will perform only that resets only program counter leaves other circuits their original state. Some registers remain unaffected during other reset conditions. Most registers reset their once reset conditions met. examining flags, program distinguish between different RESET Conditions reset during power-on reset during normal operation Wake-up HALT time-out during normal operation Wake-up HALT
Note: stands unchanged
Reset Circuit Note: Make length wiring, which connected short possible, avoid noise interference.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
input allows external events counted, time intervals pulse widths measured, accurate time base generated. Using internal clock allows accurate time base generated. Timer/Event Counter contains 16-bit programmable count-up counter whose clock sourced from external source internal clock source. internal clock source comes from fSYS/4. external clock input allows user count external events, measure time intervals pulse widths, generate accurate time base. There registers related Timer/Event Counter TMR0 TMR0C. physical registers mapped TMR0 location. Writing TMR0 places starting value Timer/Event Counter register while reading TMR0 takes contents Timer/Event Counter TMR0C register timer/event counter control register, which defines timer options. There three registers related Timer/Event Counter TMR1H, TMR1L TMR1C. Writing TMR1L will only transfer data into internal lower-order byte buffer (8-bit) writing TMR1H will transfer specified data contents lower-order byte buffer TMR1H TMR1L registers, respectively. Timer/Event Counter preload register changed each writing TRM1H operations. Reading TMR1H will latch contents TMR1H TMR1L counters destination lower-order byte buffer, respectively. Reading TMR1L will read contents lower-order byte buffer. TMR1C Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. There three registers related Timer/Event Counter TMR2H (20H), TMR2L (21H), TMR2C (22H). Writing TMR2L will only place written data internal lower-order byte buffer (8-bit) writing TMR2H will transfer specified data contents lower-order byte buffer TMR2H TMR2L registers, respectively. Timer/Event Counter preload register changed each writing TRM2H operations. Reading TMR2H will latch contents TMR2H TMR2L counters destination lower-order byte buffer, respectively. Reading TMR2L will read contents lower-order byte buffer. TMR2C Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C) T2M0, T2M1 (TMR2C) bits define operation mode. event count mode used count external events, which means that clock source from external (TMR0/TMR1/TMR2) pin. timer mode functions normal timer with clock source coming from
Reset Timing Chart
Reset Configuration guarantee that system oscillator running stabilised, (System Start-up Timer) provides extra delay 1024 system clock pulses when system awakes from power down mode. After awakening from power down mode, delay added. extra option load time delay added during reset power functional unit chip reset status shown below. Program Counter Interrupt Prescaler Timer/event Counter Input/output Ports Stack Pointer Timer/Event Counter Three timer/event counters implemented device, 8-bit programmable count-up counter 16-bit programmable count-up counter. Timer/Event Counter clock source sourced from system clock, system clock/4, time-out signal from external source. system clock source system clock/4 source selected configuration option. Timer/Event Counter clock source sourced from TMR0 overflow, system clock, time base time-out signal, system clock/4 external source. three former clock sources selected configuration options. Using external clock 000H Disabled Cleared Cleared. After master reset, starts counting Input mode Points stack
Rev. 1.10
March 2007
HT49RU80/HT49CU80
register states summarised below: Register Program Counter TBLP TBLH RTCC STATUS INTC0 TMR0 TMR0C TMR1H TMR1L TMR1C INTC1 TBHP TMR2H TMR2L TMR2C MFIC UCR1 UCR2 TXR/RXR Note: Reset (Power xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 0000H xxxx xxxx xxxx xxxx 0000 0111 xxxx -000 0000 xxxx xxxx 0000 1-xxxx xxxx xxxx xxxx 0000 1-1111 1111 xxxx xxxx 1111 1111 -111 1111 -000 -000 xxxx xxxx xxxx xxxx xxxx xxxx 00-0 1-000 -000 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx stands warm reset stands unchanged stands unknown Time-out (Norma Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 uuuu -000 0000 xxxx xxxx 0000 1-xxxx xxxx xxxx xxxx 0000 1-1111 1111 xxxx xxxx 1111 1111 -111 1111 -000 -000 uuuu uuuu xxxx xxxx xxxx xxxx 00-0 1-000 -000 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx Reset (Normal Operation) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 uuuu -000 0000 xxxx xxxx 0000 1-xxxx xxxx xxxx xxxx 0000 1-1111 1111 xxxx xxxx 1111 1111 -111 1111 -000 -000 uuuu uuuu xxxx xxxx xxxx xxxx 00-0 1-000 -000 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx Reset (HALT) uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 uuuu -000 0000 xxxx xxxx 0000 1-xxxx xxxx xxxx xxxx 0000 1-1111 1111 xxxx xxxx 1111 1111 -111 1111 -000 -000 uuuu uuuu xxxx xxxx xxxx xxxx 00-0 1-000 -000 0000 1011 0000 00x0 0000 0000 xxxx xxxx xxxx xxxx Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu 00uu uuuu uuuu -uuu uuuu uuuu uuuu uuuu u-uuuu uuuu uuuu uuuu uuuu u-uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u u-uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Rev. 1.10
March 2007
HT49RU80/HT49CU80
ternal selected clock source. Finally, pulse width measurement mode used count high level duration external signal (TMR0/TMR1/ TMR2), counting based internal selected clock source. event count timer mode, timer/event counter starts counting current contents timer/event counter ends (FFFFH). Once overflow occurs, counter reloaded from timer/event counter preload register, generates interrupt request flag (T0F: INTC0; T1F: INTC1; T2F: MFIC). pulse width measurement mode with values T0ON/T1ON/T2ON T0E/T1E/T2E bits equal after TMR0/TMR1/TMR2 received transient from high high T0E/T1E/T2E will start counting until TMR0/TMR1/ TMR2) returns original level resets T0ON/T1ON/T2ON. measured result remains timer/event counter even activated transient occurs again. other words, only 1-cycle measurement made until T0ON/T1ON/T2ON set. cycle measurement will re-function long receives further transient pulse. this operation mode, timer/event counter begins counting according logic level transient edges. case counter overflows, counter reloaded from timer/event counter register issues interrupt request, other modes, i.e., event timer modes. enable counting operation, Timer (T0ON/T1ON/T2ON; TMR0C/TMR1C/ TMR2C) should pulse width measurement mode, T0ON/T1ON/T2ON automatically cleared after measurement cycle completed. other modes, T0ON/T1ON/T2ON only reset instructions. overflow Timer/Event Counter wake-up sources also applied (Programmable Frequency Divider) output options. Only (PFD0 PFD1) applied options. matter what operation mode writing ET0I/ET1I/ET2I disables related interrupt service. When function selected, executing instruction enable output executing instruction disable output. case timer/event counter condition, writing data timer/event counter preload register also reloads that data timer/event counter. timer/event counter turned data written timer/event counter kept only timer/event counter preload register. timer/event counter still continues operation until overflow occurs. When timer/event counter (reading TMR0/TMR1/ TMR2) read, clock blocked avoid errors, this results counting error. Blocking clock should taken into account programmer. strongly recommended load desired value into TMR0/TMR1/TMR2 register first, before turning related timer/event counter, proper operation since initial value TMR0/TMR1/TMR2 unknown. timer/event counter scheme, programmer should special attention instruction enable then disable timer first time, whenever there need timer/event counter function, avoid unpredictable result. After this procedure, timer/event counter function operated normally. following example given, using 8-bit 16-bit width Timer (timer timer cascaded into 24-bit width. START: ET0I bits intc0, enable Timer global interrupt
ET1I enable intc1, Timer interrupt operating mode tmr1c, timer mode select mask option clock source 0a0h operating mode timer tmr0c, mode select system clock/4
tmr1c.4 Enable then disable Timer tmr1c.4 first time
tmr0, tmr1l, tmr1h,
Load desired value into TMR0/TMR1 register Normal operating
tmr0c.4 tmr1c.4
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Timer/Event Counter
Timer/Event Counter
Timer/Event Counter
Source Option
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Label Unused bit, read Defines TMR0 active edge timer/event counter: Event Counter Mode (T0M1,T0M0)=(0,1): count falling edge; count rising edge Pulse Width measurement mode (T0M1,T0M0)=(1,1): start counting rising edge, stop falling edge; start counting falling edge, stop rising edge Enables/disables timer counting (0=disable; 1=enable) multiplexer control inputs which selects timer/event counter clock source (0=RTC outputs; system clock system clock/4) Defines operating mode (T0M1, T0M0) Event count mode (External clock) Timer mode (Internal clock) Pulse Width measurement mode (External clock) Unused TMR0C (0EH) Register Label Unused bit, read Defines TMR1 active edge timer/event counter: Event Counter Mode (T1M1,T1M0)=(0,1): count falling edge; count rising edge Pulse Width measurement mode (T1M1,T1M0)=(1,1): start counting rising edge, stop falling edge; start counting falling edge, stop rising edge Enables/disables timer counting disable; enabled) multiplexer control inputs select timer/event counter clock source option clock source; system clock/4) Defines operating mode (T1M1, T1M0) Event count mode (External clock) Timer mode (Internal clock) Pulse Width measurement mode (External clock) Unused TMR1C (11H) Register Label Unused bit, read Defines TMR2 active edge timer/event counter: Event Counter Mode (T2M1,T2M0)=(0,1): count falling edge; count rising edge Pulse Width measurement mode (T2M1,T2M0)=(1,1): start counting rising edge, stop falling edge; start counting falling edge, stop rising edge Enables/disables timer counting (0=disable; 1=enable) Unused bit, read Defines operating mode (T2M1, T2M0): 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse width measurement mode (External clock) 00=Unused TMR2C (22H) Register Rev. 1.10 March 2007 Function Function Function
T0ON
T0M0 T0M1
T1ON
T1M0 T1M1
T2ON T2M0 T2M1
HT49RU80/HT49CU80
Input/Output Ports There 8-bit bidirectional input/output ports, 8-bit input 7-bit output mapped [12H], [14H], [16H] [18H] RAM, respectively. PA0~PA3 configured CMOS (output) NMOS (input/output) with without pull-high resistor options. PA4~PA7 always pull-high NMOS (input/output). NMOS (input) chosen, each port (PA0~PA7) configured wake-up input. only used input operation. configured CMOS output NMOS input/output with without pull-high resistor options. only used CMOS output operation. ports input operation (PA, PC), non-latched, that inputs should ready rising edge instruction (m=12H, 16H). output operation, data latched remain unchanged until output latch rewritten. When structures open drain NMOS type, should noted that, before reading data from pads, should written related bits disable NMOS device. That executing first instruction (i=0~7 disable related NMOS device, then stable data. After chip reset, these input lines remain high level left floating options). Each these output latches cleared [m], (m=12H 16H) instruction. Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. When line used line, related line options should configured NMOS with without pull-high resistor. Once line selected CMOS output, input function cannot used. input state line read from related pad. When configured NMOS with without pull-high resistor, should careful when applying read-modify-write instruction Since read-modify-write will read entire port state (pads state) first, execute specified instruction then write result port data register. When read operation executed, fault state (caused load effect floating state) read. Errors will then occur. There three function pins that share with port: PA0/BZ, PA1/BZ PA3/PFD. buzzer driving output pair programmable frequency divider output. user wants BZ/BZ function, related port should CMOS output. buzzer output signals controlled data registers defined following table. Data Register Data Register PA0/PA1 State PA0=BZ, PA1=BZ PA0=BZ, PA1=0 PA0=0, PA1=0
Note: stands unused output signal function controlled data register timer/event counter state. output signal frequency also dependent timer/event counter overflow period. definitions control signal output frequency listed following table. Timer Note: Timer Preload Value Data Register State Frequency fINT/
stands unused stands unknown TMR0. TMR1 used generate PFD, number should
After chip reset, these input/output lines remain high levels (pull-high options) floating state (non-pull-high options). suggested apply instructions port (since reading error occur). Using instruction avoid reading error suggested. 8-bit input port configuration Schmitt trigger with pull-high resistors. Each line capability waking-up device. PB0, PB1, PB2, pin-shared with INT0, INT1, TMR0, TMR1 TMR2 input functions, respectively.
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PA0~PA3 Input/Output Ports
PA4~PA7 Input/Output Ports
Input Port
PC0/TX Input/Output Port
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PC1/RX Input/Output Port
PC2~PC7 Input/Output Ports
Output Port
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Display Memory device provides area embedded data memory display. This area located from Bank data memory. bank pointer, used switch between general purpose data memory display memory. When value data written into locations 40H~6FH will influence display. When cleared data written into locations 40H~6FH will access general purpose data memory. display memory read written only using indirect addressing mode using memory pointer MP1. When data written into display data area, automatically read driver which then generates corresponding driving signals. turn display off, written corresponding display memory, respectively. figure illustrates mapping between display memory pattern device. Driver Output output number driver device
Display Memory selected configuration options, i.e., duty, duty duty. There types biasing, type type. bias type selected, external capacitors required. bias type selected, capacitor mounted between pins required. bias selected, capacitor mounted between ground required. bias selected, capacitors required connected between pins VSS. suggested value 0.1mF recommended capacitors.
Driver Output
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Driver Output (1/3 Duty, Bias, Type)
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driver requires clock source proper operation. clock source sourced from general purpose prescaler whose frequency value determined configuration options. clock frequency should selected close 4kHz possible. clock frequency options listed following table. Clock Source Same clock source Segments Output Port SEG40~SEG46 lines, individual configuration options, chosen either segment outputs outputs. When segment output selected, connection VMAX depends upon bias voltage that applied VLCD. details shown table. When used output, VMAX should connected VDD. Type Bias Type VMAX Bias Type Bias Bias Type Bias VDD> 3/2VLCD, user should connect VMAX VDD, else connect VMAX
Prescaler Stages fS/2 ~fS/28
VDD>VLCD, user should connect VMAX VDD, else connect VMAX VLCD
Voltage Reset/Detector Functions device contains voltage detector, LVD, voltage reset, LVR, circuits. These functions enabled disabled using configuration options. configuration options enable LVD, further enabled disabled using software, changing value RTCC.3 bit. RTCC.5 used read status LVD. Voltate Reset function, LVR, same effect external signal which executes chip reset.Its function selected configuration option. When device power down mode, disabled. RTCC register definitions shown table. Label RT0~RT2 LVDC QOSC LVDO Read/Write Function multiplexer control inputs select real time clock prescaler output enable/disable (1/0) 32768Hz quick start-up 0/1: quick/slow start detector output (1/0) voltage detected Unused bit, read RTCC (09H) Register
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HT49RU80/HT49CU80
UART Serial Interface HT49RU80/HT49CU80 devices contain integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain serial interface. UART function many features transmit receive data serially transferring frame data with eight nine data bits transmission well being able detect errors when data overwritten incorrectly framed. UART function possesses internal interrupt which used indicate when reception occurs when transmission terminates.
UART features
which also used general purpose pin, configured receiver, which occurs RXEN UCR2 register equal zero. Along with UARTEN bit, TXEN RXEN bits, set, will automatically setup these pins their respective output input conditions disable pull-high resistor option which exist pin.
UART data transfer scheme
integrated UART function contains following features:
Full-duplex, asynchronous communication bits character length Even, parity options stop bits Baud rate generator with 8-bit prescaler Parity, framing, noise overrun error detection Support interrupt address detect (last character bit=1) Separately enabled transmitter receiver 2-byte Deep Fifo Receive Data Buffer Transmit receive interrupts Interrupts initialized following conditions:
block diagram shows overall data transfer structure arrangement UART. actual data transmitted from first transferred register application program. data will then transferred Transmit Shift Register from where will shifted out, first, onto rate controlled Baud Rate Generator. Only register mapped onto Data Memory, Transmit Shift Register mapped therefore inaccessible application program. Data received UART accepted external pin, from where shifted first, Receiver Shift Register rate controlled Baud Rate Generator. When shift register full, data will then transferred from shift register internal register, where buffered manipulated application program. Only register mapped onto Data Memory, Receiver Shift Register mapped therefore inaccessible application program. should noted that actual register data transmission reception, although referred text, application programs, separate registers, only exists single shared register Data Memory. This shared register known TXR/RXR register used both data transmission data reception.
UART status control registers
Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect
UART external interfacing
communicate with external serial interface, internal UART external pins known UART transmitter pin, which used general purpose configured UART transmitter, which occurs when TXEN UCR2 control register equal zero. Similarly, UART receiver pin,
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There five control registers associated with UART function. USR, UCR1 UCR2 registers control overall function UART, while register controls Baud rate. actual data transmitted received serial interface managed through TXR/RXR data registers.
UART Data Transfer Scheme
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HT49RU80/HT49CU80
register
register status register UART, which read program determine present status UART. flags within register read only. Further explanation each flags given below:
RXIF flag cleared when register read with RXIF set, followed read from register, register data available.
TXIF TXIF flag transmit data register empty flag. When this read only flag indicates that character transferred transmit shift registers. When flag indicates that transmit shift register received character from data register. TXIF flag cleared reading UART status register (USR) with TXIF then writing data register. Note that when TXEN set, TXIF flag will also since transmit buffer full. TIDLE TIDLE flag known transmission complete flag. When this read only flag indicates that transmission progress. This flag will when TXIF flag when there transmit data, break character being transmitted. When TIDLE becomes idle. TIDLE flag cleared reading register with TIDLE then writing register. flag generated when data character, break queued ready sent. RXIF RXIF flag receive register status flag. When this read only flag indicates that read data register empty. When flag indicates that read data register contains data. When contents shift register transferred register, interrupt generated RIE=1 UCR2 register. more errors detected received word, appropriate receive-related flags FERR, and/or PERR within same clock cycle.
RIDLE RIDLE flag receiver status flag. When this read only flag indicates that receiver between initial detection start completion stop bit. When flag indicates that receiver idle. Between completion stop detection next start bit, RIDLE indicating that UART idle. OERR OERR flag overrun error flag, which indicates when receiver buffer overflowed. When this read only flag there overrun error. When flag overrun error occurs which will inhibit further transfers receive data register. flag cleared software sequence, which read status register followed access data register. FERR FERR flag framing error flag. When this read only flag indicates framing error. When flag indicates that framing error been detected current character. flag also cleared software sequence which will involve read status register followed access data register. flag noise flag. When this read only flag indicates noise condition. When flag indicates that UART detected noise receiver input. flag during same cycle RXIF flag will case overrun. flag cleared software sequence which will involve read status register, followed access data register.
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PERR PERR flag parity error flag. When this read only flag indicates that parity error been detected. When flag indicates that parity received word incorrect. This error flag applicable only Parity mode (odd even) selected. flag also cleared software sequence which involves read status register, followed access data register.
used, equal then only stop used.
This parity type selection bit. When this equal parity will selected, equal then even parity will selected. PREN This parity enable bit. When this equal parity function will enabled, equal then parity function will disabled. This used select data length format, which have choice either 8-bits 9-bits. this equal then 9-bit data length will selected, equal then 8-bit data length will selected. 9-bit data length selected then bits will used store received transmitted data respectively. UARTEN UARTEN UART enable bit. When UART will disabled pins will function General Purpose pins. When UART will enabled pins will function defined TXEN RXEN control bits. When UART disabled will empty buffer character remaining buffer will discarded. addition, baud rate counter value will reset. When UART disabled, error status flags will reset. TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR, bits will cleared, while TIDLE, TXIF RIDLE bits will set. Other control bits UCR1, UCR2, registers will remain unaffected. UART active UARTEN cleared, pending transmissions receptions will terminated module will reset defined above. When UART re-enabled will restart same configuration.
UCR1 register
UCR1 register together with UCR2 register UART control registers that used various options UART function, such overall on/off control, parity control, data transfer length etc. Further explanation each bits given below:
This only used 9-bit data transfers used, which case this location will store transmitted data, known TX8. used determine whether data transfers 8-bit 9-bit format. This only used 9-bit data transfers used, which case this location will store received data, known RX8. used determine whether data transfers 8-bit 9-bit format. TXBRK TXBRK Transmit Break Character bit. When this there break characters operates normally. When there transmit break characters transmitter will send logic zeros. When equal after buffered data been transmitted, transmitter output held minimum 13-bit length until TXBRK reset. STOPS This determines stop bits used. When this equal stop bits
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HT49RU80/HT49CU80
UCR2 register
UCR2 register second UART control registers serves several purposes. main functions control basic enable/disable operation UART Transmitter Receiver well enabling various UART interrupt sources. register also serves control baud rate speed, receiver wake-up enable address detect enable. Further explanation each bits given below:
Power Down Mode, edge transitions will wake-up device.
TEIE This enables disables transmitter empty interrupt. this equal when transmitter empty TXIF flag set, transmitter empty condition, UART interrupt request flag will set. this equal UART interrupt request flag will influenced condition TXIF flag. TIIE This enables disables transmitter idle interrupt. this equal when transmitter idle TIDLE flag set, UART interrupt request flag will set. this equal UART interrupt request flag will influenced condition TIDLE flag. This enables disables receiver interrupt. this equal when receiver overrun OERR flag receive data available RXIF flag set, UART interrupt request flag will set. this equal UART interrupt will influenced condition OERR RXIF flags. WAKE This enables disables receiver wake-up function. this equal Power Down Mode, going edge input will wake-up device. this equal
ADDEN ADDEN address detect mode bit. When this address detect mode enabled. When this occurs, bit, which corresponds BNO=0, bit, which corresponds BNO=1, value then received word will identified address, rather than data. corresponding interrupt enabled, interrupt request will generated each time received word address set, which depending value BNO. address interrupt will generated, received data will discarded. BRGH BRGH selects high speed mode Baud Rate Generator. This bit, together with value placed register, controls Baud Rate UART. this equal high speed mode selected. equal speed mode selected. RXEN RXEN Receiver Enable Bit. When this equal receiver will disabled with pending data receptions being aborted. addition buffer will reset. this situation used general purpose pin. RXEN equal receiver will enabled UARTEN equal will controlled UART. Clearing RXEN during transmission will cause data reception aborted will reset receiver. this occurs, used general purpose pin.
itte itte llin itte itte itte
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HT49RU80/HT49CU80
TXEN TXEN Transmitter Enable Bit. When this equal transmitter will disabled with pending transmissions being aborted. addition buffer will reset. this situation used general purpose pin. TXEN equal transmitter will enabled UARTEN equal will controlled UART. Clearing TXEN during transmission will cause transmission aborted will reset transmitter. this occurs, used general purpose pin.
programming BRGH which allows selection related formula programming required value register, required baud rate setup. Note that because actual baud rate determined using discrete value, placed register, there will error associated between actual requested value. following example shows register value error value calculated. Calculating register error values clock frequency 8MHz, with BRGH determine register value actual baud rate error value desired baud rate 9600. From above table desired baud rate fSYS Re-arranging this equation gives Giving value fSYS (BRx64)
Baud rate generator
setup speed serial data communication, UART function contains dedicated baud rate generator. baud rate controlled internal free running 8-bit timer, period which determined factors. first these value placed register second value BRGH within UCR2 control register. BRGH decides, baud rate generator used high speed mode speed mode, which turn determines formula that used calculate baud rate. value register determines division factor, which used following baud rate calculation formula. Note that decimal value placed register range between 255. UCR2 BRGH Baud Rate fSYS fSYS
8000000 12.0208 (9600x
obtain closest value, decimal value should placed into register. This gives actual calculated baud rate value 8000000 9615 [64(12 Therefore error equal
0.16%
following tables show actual values baud rate error values values BRGH. Baud Rate K/BPS 19.2 38.4 57.6 115.2 Baud Rates BRGH=0 fSYS=8MHz Kbaud 1.202 2.404 4.807 9.615 17.857 41.667 62.5 Error 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 8.51 fSYS=7.159MHz Kbaud 1.203 2.38 4.863 9.322 18.64 37.29 55.93 111.86 Error 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9 -2.9 fSYS=4MHz Kbaud 0.300 1.202 2.404 4.808 8.929 20.83 62.5 Error 0.00 0.16 0.16 0.16 -6.99 8.51 8.51 fSYS=3.579545MHz Kbaud 0.300 1.19 2.432 4.661 9.321 18.643 55.93 Error 0.00 -0.83 1.32 -2.9 -2.9 -2.9 -2.9
Baud Rates Error Values BRGH
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HT49RU80/HT49CU80
Baud Rate K/BPS 19.2 38.4 57.6 115.2 Baud Rates BRGH=1 fSYS=8MHz Kbaud 2.404 4.808 9.615 19.231 38.462 55.556 Error 0.16 0.16 0.16 0.16 0.16 -3.55 8.51 fSYS=7.159MHz Kbaud 2.405 4.811 9.520 19.454 37.287 55.93 111.86 Error 0.23 0.23 -0.832 1.32 -2.9 -2.9 -2.9 fSYS=4MHz Kbaud 1.202 2.404 4.808 9.615 19.231 35.714 62.5 Error 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 8.51 fSYS=3.579545MHz Kbaud 1.203 2.406 4.76 9.727 18.643 37.286 55.930 111.86 Error 0.23 0.23 -0.83 1.32 -2.9 -2.9 -2.9 -2.9
Baud Rates Error Values BRGH
Setting controlling UART
Introduction data transfer, UART function utilizes non-return-to-zero, more commonly known NRZ, format. This composed start bit, eight nine data bits, stop bits. Parity supported UART hardware, setup even, parity. most common data format, data bits along with parity stop bit, denoted used default setting, which setting power-on. number data bits stop bits, along with parity, setup programming corresponding BNO, PRT, PREN, STOPS bits UCR1 register. baud rate used transmit receive data setup using internal 8-bit baud rate generator, while data transmitted received first. Although transmitter receiver functionally independent, they both same data format baud rate. cases stop bits will used data transmission. Enabling/disabling UART basic on/off function internal UART function controlled using UARTEN UCR1 register. UART transmit receive pins, respectively, pin-shared with normal pins, basic functions UARTEN control control UART function these pins. UARTEN, TXEN RXEN bits set, then these pins will setup output input respectively, effect disabling normal function. data being transmitted then will default logic high value.
Clearing UARTEN will disable pins allow these pins used normal pins. When UART function disabled buffer will reset empty condition, same time discarding remaining residual data. Disabling UART will also reset error status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR being cleared while bits TIDLE, TXIF RIDLE will set. remaining control bits UCR1, UCR2 registers will remain unaffected. UARTEN UCR1 register cleared while UART active, then pending transmissions receptions will immediately suspended UART will reset condition defined above. UART then subsequently re-enabled, will restart again same configuration.
Data, parity stop selection format data transferred, composed various factors such data length, parity on/off, parity type, address bits number stop bits. These factors determined setup various bits within UCR1 register. controls number data bits which either controls choice even parity, PREN controls parity on/off function STOPS decides whether stop bits used. following table shows various formats data transmission. address identifies frame address character. number stop bits, which either two, independent data length.
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Start Data Bits Address Bits Parity Bits Stop
Example 8-bit Data Formats
Example 9-bit Data Formats
Transmitting data When UART transmitting data, data shifted from shift register, with least significant first. transmit mode, register forms buffer between internal transmitter shift register. should noted that 9-bit data format been selected, then will taken from UCR1 register. steps initiate data transfer summarized follows:
Make correct selection BNO, PRT, PREN STOPS bits define required word length, parity type number stop bits. Setup register select desired baud rate. TXEN ensure that used UART transmitter pin. Access register write data that transmitted into register. Note that this step will clear TXIF bit. This sequence events repeated send additional data.
Transmitter Receiver Data Format following diagram shows transmit receive waveforms both 8-bit 9-bit data formats.
UART transmitter
Data word lengths either bits, selected programming UCR1 register. When set, word length will bits. this case bit, which MSB, needs stored UCR1 register. transmitter core lies Transmitter Shift Register, more commonly known TSR, whose data obtained from transmit data register, which known register. data transmitted loaded into this register application program. register written with data until stop from previous transmission been sent out. soon this stop been transmitted, then loaded with data from register, available. should noted that register, unlike many other registers, directly mapped into Data Memory area such available application program direct read/write operations. actual transmission data will normally enabled when TXEN set, data will transmitted until register been loaded with data baud rate generator defined shift clock source. However, transmission also initiated first loading data into register, after which TXEN set. When transmission data begins, normally empty, which case transfer register will result immediate transfer TSR. during transmission TXEN cleared, transmission will immediately cease transmitter will reset. output will then return having normal general purpose function.
should noted that when TXIF=0, data will inhibited from being written register. Clearing TXIF flag always achieved using following software sequence: register access register write execution read-only TXIF flag UART hardware indicates that register empty that other data written into register without overwriting previous data. TEIE then TXIF flag will generate interrupt. During data transmission, write instruction register will place data into register, which will copied shift register present transmission. When there data transmission progress, write instruction register will place data directly into shift register, resulting commencement data transmission, TXIF being immediately set. When frame transmission complete, which happens after stop bits sent after break frame, TIDLE will set. clear TIDLE following software sequence used: register access register write execution Note that both TXIF TIDLE bits cleared same software sequence.
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HT49RU80/HT49CU80
Transmit break TXBRK then break characters will sent next transmission. Break character transmission consists start bit, followed bits stop bits, where N=1, etc. break character transmitted then TXBRK must first application program, then cleared generate stop bits. Transmitting break character will generate transmit interrupt. Note that break condition length least bits long. TXBRK continually kept logic high level then transmitter circuitry will transmit continuous break characters. After application program cleared TXBRK bit, transmitter will finish transmitting last break character subsequently send stop bits. automatic logic highs last break character will ensure that start next frame recognized.
RXEN ensure that used UART receiver pin.
this point receiver will enabled which will begin look start bit. When character received following sequence events will occur:
RXIF register will when register data available, least more character read. When contents shift register have been transferred register, then set, interrupt will generated. during reception, frame error, noise error, parity error, overrun error been detected, then error flags set.
RXIF cleared using following software sequence: register access register read execution
UART receiver
Introduction UART capable receiving word lengths either bits. set, word length will bits with being stored UCR1 register. receiver core lies Receive Serial Shift Register, commonly known RSR. data which received external input pin, sent data recovery block. data recovery block operating speed times that baud rate, while main receive serial shifter operates baud rate. After sampled stop bit, received data transferred receive data register, register empty. data which received external input sampled three times majority detect circuit determine logic level that been placed onto pin. should noted that register, unlike many other registers, directly mapped into Data Memory area such available application program direct read/write operations. Receiving data When UART receiver receiving data, data serially shifted external input pin, first. read mode, register forms buffer between internal receiver shift register. register byte deep FIFO data buffer, where bytes held FIFO while third byte continue received. Note that application program must ensure that data read from before third byte been completely shifted otherwise this third byte will discarded overrun error OERR will subsequently indicated. steps initiate data transfer summarized follows:
Receive break break character received UART will managed framing error. receiver will count expect certain number times specified values programmed into STOPS bits. break much longer than times, reception will considered complete after number times specified STOPS. RXIF set, FERR set, zeros loaded into receive data register, interrupts generated appropriate RIDLE set. long break signal been detected receiver received start bit, data bits invalid stop bit, which sets FERR flag, receiver must wait valid stop before looking next start bit. receiver will make assumption that break condition line next start bit. break regarded character that contains only zeros with FERR flag set. break character will loaded into buffer further data will received until stop bits received. should noted that RIDLE read only flag will high when stop bits have been received. reception break character UART registers will result following:
framing error flag, FERR, will set. receive data register, RXR, will cleared. OERR, PERR, RIDLE RXIF flags will possibly set.
Make correct selection BNO, PRT, PREN STOPS bits define word length, parity type number stop bits. Setup register select desired baud rate.
Idle status When receiver reading data, which means will between detection start reading stop bit, receiver status flag register, otherwise known RIDLE flag, will have zero value. between reception stop detection next start bit, RIDLE flag will have high value, which indicates receiver idle condition.
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HT49RU80/HT49CU80
Receiver interrupt read only receive interrupt flag RXIF register edge generated receiver. interrupt generated RIE=1, when word transferred from Receive Shift Register, RSR, Receive Data Register, RXR. overrun error also generate interrupt RIE=1.
interrupt will generated. However this rises same time RXIF which itself generates interrupt. Note that flag reset register read operation followed register read operation.
Managing receiver errors
Several types reception errors occur within UART module, following section describes various types they managed UART.
Overrun Error OERR flag register composed byte deep FIFO data buffer, where bytes held FIFO register, while third byte continue received. Before this third byte been entirely shifted data should read from register. this done, overrun error flag OERR will consequently indicated. event overrun error occurring, following will happen:
Framing Error FERR Flag read only framing error flag, FERR, register, zero detected instead stop bits. stop bits selected, both stop bits must high, otherwise FERR flag will set. FERR flag buffered along with received data cleared reset. Parity Error PERR Flag read only parity error flag, PERR, register, parity received word incorrect. This error flag only applicable parity enabled, PREN parity type, even selected. read only PERR flag buffered along with received data bytes. cleared reset. should noted that FERR PERR flags buffered along with corresponding word should read before reading data word.
OERR flag register will set. contents will lost. shift register will overwritten.
UART interrupt scheme
interrupt will generated set. OERR flag cleared access register followed read register.
Noise Error Flag Over-sampling used data recovery identify valid incoming data noise. noise detected within frame following will occur:
read only noise flag, register will rising edge RXIF bit. Data will transferred from Shift register register.
UART internal function possesses internal interrupt independent interrupt vector. Several individual UART conditions generate internal UART interrupt. These conditions are, transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect wake-up. When these conditions created, UART interrupt enabled stack full, program will jump UART interrupt vector where serviced before returning main program. Four these conditions, have corresponding register flag, which will generate UART interrupt associated interrupt enable flag
itte
itte
UART Interrupt Scheme
Rev. 1.10
March 2007
HT49RU80/HT49CU80
UCR2 register set. transmitter interrupt conditions have their corresponding enable bits, while receiver interrupt conditions have shared enable bit. These enable bits used mask individual UART interrupt sources. address detect condition, which also UART interrupt source, does have associated flag, will generate UART interrupt when address detect condition occurs function enabled setting ADDEN UCR2 register. wake-up, which also UART interrupt source, does have associated flag, will generate UART interrupt microcontroller woken going edge pin, WAKE bits UCR2 register set. Note that event wake-up interrupt occurring, there will delay 1024 system clock cycles before system resumes normal operation. Note that register flags read only cannot cleared application program, neither will they cleared when program jumps corresponding interrupt servicing routine, case some other interrupts. flags will cleared automatically when certain actions taken UART, details which given UART register section. overall UART interrupt disabled enabled EURI INTC1 interrupt control register prevent UART interrupt from occurring.
Address detect mode
exclusive functions. Therefore address detect mode enabled, then ensure correct operation, parity function should disabled resetting parity enable zero. ADDEN BNO=1, UART Interrupt BNO=0 Generated ADDEN Function
UART operation power down mode
When Power Down Mode UART will cease function. When device enters Power Down Mode, clock sources module shutdown. enters Power Down Mode while transmission still progress, then transmission will terminated external transmit will forced logic high level. similar way, enters Power Down Mode while receiving data, then reception data will likewise terminated. When enters Power Down Mode, note that USR, UCR1, UCR2, transmit receive registers, well register will affected. UART function contains receiver wake-up function, which enabled disabled WAKE UCR2 register. this bit, along with UART enable bit, UARTEN, receiver enable bit, RXEN receiver interrupt bit, RIE, before enters Power Down Mode, then falling edge will wake-up from Power Down Mode. Note that takes 1024 system clock cycles after wake-up, before normal microcontroller operation resumes, data received during this time will ignored. UART wake-up interrupt occur, addition bits wake-up being set, global interrupt enable bit, EMI, UART interrupt enable bit, EURI must also set. these bits then only wake event will occur interrupt will generated. Note also that takes 1024 system clock cycles after wake-up before normal microcontroller resumes, UART interrupt will generated until after this time elapsed.
Setting Address Detect Mode bit, ADDEN, UCR2 register, enables this special mode. this enabled then additional qualifier will placed generation Receiver Data Available interrupt, which requested RXIF flag. ADDEN enabled, then when data available, interrupt will only generated, highest received high value. Note that EURI interrupt enable bits must also enabled correct interrupt generation. This highest address BNO=1 BNO=0. this high, then received word will defined address rather than data. Data Available interrupt will generated every time last received word set. ADDEN enabled, then Receiver Data Available interrupt will generated each time RXIF flag set, irrespective data last status. address detect mode parity enable mutually
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Configuration Options following shows options device. these options should defined order ensure proper functioning system.Configuration options refer certain options within that programmed into device during programming process. During development process, these options selected using HT-IDE software development tools. these options programmed into device using hardware programming tools, once they selected they cannot changed later application software control over configuration options. options must defined proper system function, details which shown table. Options Options PA0~PA7 wake-up enable/disable PA0~PA3 CMOS/NMOS selection PA0~PA3 pull-high enable/disable PC0~PC3 CMOS/NMOS selection PC4~PC7 CMOS/NMOS selection PC0~PC3 pull-high enable/disable PC4~PC7 pull-high enable/disable Watchdog Options function: enable disable CLRWDT instructions: instructions Oscillator Options type selection: crystal fsys clock source: internal clock source: fSYS/4, Options output enable: enable disable clock selection: Timer/Event Counter Timer/Event Counter Timer Options Timer/Event Counter clock source: fSYS/4 fSYS Timer/Event Counter clock source: Timer/Event Counter overflow, Time Base fSYS Timer Base Options Time Base frequency: fS/212 fS/215 Buzzer Options Buzzer output enable: enable disable Buzzer frequency fS/22 fS/29 LVD/LVR Options function reset: enable disable Voltage Detect: enable disable Options clock: fS/22 fS/28 duty: 1/2, 1/3, bias: 1/2, bias type: type type on/off during power down: enable disable segment SEG40~SEG46 output PD0~PD6 output HALT mode oscillator enable disable
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Application Circuits
illa
illa
illa
following table shows values corresponding different crystal values. (For reference only) Crystal Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator 400kHz Resonator 10pF 25pF 25pF 35pF 100pF 200pF 200pF 300pF 12kW 12kW 12kW 12kW 12kW 14kW 14kW 12kW 12kW 12kW
function resistor ensure that oscillator will switch should voltage conditions occur. Such voltage, mentioned here, which less than lowest value operating voltage. Note however that enabled then removed.
Note:
resistance capacitance reset circuit should designed such ensure that stable remains within valid operating voltage range before bringing high. Make length wiring, which connected short possible, avoid noise interference.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Instruction Summary
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] data memory data memory immediate data data memory with carry data memory with carry Subtract immediate data from Subtract data memory from Subtract data memory from with result data memory Subtract data memory from with carry Subtract data memory from with carry result data memory Decimal adjust addition with result data memory 1(1) 1(1) 1(1) 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Description Instruction Cycle Flag Affected
Logic Operation A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA data memory data memory Exclusive-OR data memory data memory data memory Exclusive-OR data memory immediate data immediate data Exclusive-OR immediate data Complement data memory Complement data memory with result 1(1) 1(1) 1(1) 1(1)
Increment Decrement INCA DECA Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Clear data memory data memory 1(1) 1(1) None None Move data memory Move data memory Move immediate data 1(1) None None None Rotate data memory right with result Rotate data memory right Rotate data memory right through carry with result Rotate data memory right through carry Rotate data memory left with result Rotate data memory left Rotate data memory left through carry with result Rotate data memory left through carry 1(1) 1(1) 1(1) 1(1) None None None None Increment data memory with result Increment data memory Decrement data memory with result Decrement data memory 1(1) 1(1)
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Mnemonic Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT Note: operation Clear data memory data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles data memory Swap nibbles data memory with result Enter power down mode 1(1) 1(1) 1(1) None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read code (current page) data memory TBLH Read code (last page) data memory TBLH 2(1) 2(1) None None Jump unconditionally Skip data memory zero Skip data memory zero with data movement Skip data memory zero Skip data memory zero Skip increment data memory zero Skip decrement data memory zero Skip increment data memory zero with result Skip decrement data memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Immediate data Data memory address Accumulator number bits addr: Program memory address Flag affected Flag affected
loading register occurs, execution cycle instructions will delayed more cycle (four system clocks). skipping next instruction occurs, execution cycle instructions will delayed more cycle (four system clocks). Otherwise original instruction cycle unchanged. flags affected execution status. Watchdog Timer cleared executing WDT1 WDT2 instruction, cleared. Otherwise flags remain unchanged.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) data memory carry accumulator contents specified data memory, accumulator carry flag added simultaneously, leaving result accumulator. ACC+[m]+C
accumulator carry data memory contents specified data memory, accumulator carry flag added simultaneously, leaving result specified data memory. ACC+[m]+C
data memory accumulator contents specified data memory accumulator added. result stored accumulator. ACC+[m]
immediate data accumulator contents accumulator specified data added, leaving result accumulator. ACC+x
accumulator data memory contents specified data memory accumulator added. result stored data memory. ACC+[m]
Rev. 1.10
March 2007
HT49RU80/HT49CU80
A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) CALL addr Description Logical accumulator with data memory Data accumulator specified data memory perform bitwise logical_AND operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_AND operation. result stored accumulator.
Logical data memory with accumulator Data specified data memory accumulator perform bitwise logical_AND operation. result stored data memory.
Subroutine call instruction unconditionally calls subroutine located indicated address. program counter increments once obtain address next instruction, pushes this onto stack. indicated address then loaded. Program execution continues with instruction this address. Stack Program Counter+1 Program Counter addr
Operation
Affected flag(s)
Description Operation Affected flag(s)
Clear data memory contents specified data memory cleared
Rev. 1.10
March 2007
HT49RU80/HT49CU80
[m].i Description Operation Affected flag(s) Description Operation Clear data memory specified data memory cleared [m].i
Clear Watchdog Timer cleared (clears WDT). power down (PDF) time-out (TO) cleared.
Affected flag(s)
WDT1 Description
Preclear Watchdog Timer Together with WDT2, clears WDT. also cleared. Only execution this instruction without other preclear instruction just sets indicated flag which implies this instruction been executed flags remain unchanged. 00H*
Operation
Affected flag(s)
WDT2 Description
Preclear Watchdog Timer Together with WDT1, clears WDT. also cleared. Only execution this instruction without other preclear instruction, sets indicated flag which implies this instruction been executed flags remain unchanged. 00H*
Operation
Affected flag(s)
Description Operation Affected flag(s)
Complement data memory Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
CPLA Description Complement data memory place result accumulator Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa. complemented result stored accumulator contents data memory remain unchanged. Description
Operation Affected flag(s)
Decimal-Adjust accumulator addition accumulator value adjusted (Binary Coded Decimal) code. accumulator divided into nibbles. Each nibble adjusted code internal carry (AC1) will done nibble accumulator greater than adjustment done adding original value original value greater than carry set; otherwise original value remains unchanged. result stored data memory only carry flag affected. ACC.3~ACC.0 AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+AC1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s)
Description Operation Affected flag(s)
Decrement data memory Data specified data memory decremented [m]-1
DECA Description Operation Affected flag(s)
Decrement data memory place result accumulator Data specified data memory decremented leaving result accumulator. contents data memory remain unchanged. [m]-1
Rev. 1.10
March 2007
HT49RU80/HT49CU80
HALT Description Enter power down mode This instruction stops program execution turns system clock. contents registers retained. prescaler cleared. power down (PDF) time-out (TO) cleared. Program Counter Program Counter+1 Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Directly jump program counter replaced with directly-specified address unconditionally, control passed this destination. Program Counter
Operation
Affected flag(s)
Increment data memory Data specified data memory incremented [m]+1
Increment data memory place result accumulator Data specified data memory incremented leaving result accumulator. contents data memory remain unchanged. [m]+1
Move data memory accumulator contents specified data memory copied accumulator.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) operation operation performed. Execution continues with next instruction. Program Counter Program Counter+1 Move immediate data accumulator 8-bit data specified code loaded into accumulator.
Move accumulator data memory contents accumulator copied specified data memory (one data memories).
Logical accumulator with data memory Data accumulator specified data memory (one data memories) perform bitwise logical_OR operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_OR operation. result stored accumulator.
Logical data memory with accumulator Data data memory (one data memories) accumulator perform bitwise logical_OR operation. result stored data memory.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Description Operation Affected flag(s) Description Operation Return from subroutine program counter restored from stack. This 2-cycle instruction. Program Counter Stack
Return place immediate data accumulator program counter restored from stack accumulator loaded with specified 8-bit immediate data. Program Counter Stack
Affected flag(s)
RETI Description Operation
Return from interrupt program counter restored from stack, interrupts enabled setting bit. enable master (global) interrupt bit. Program Counter Stack
Affected flag(s)
Description Operation
Rotate data memory left contents specified data memory rotated left with rotated into [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7
Affected flag(s)
Description Operation
Rotate data memory left place result accumulator Data specified data memory rotated left with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Affected flag(s)
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Description Operation Rotate data memory left through carry contents specified data memory carry flag rotated left. replaces carry bit; original carry flag rotated into position. [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7 RLCA Description
Affected flag(s)
Rotate left through carry place result accumulator Data specified data memory carry flag rotated left. replaces carry original carry flag rotated into position. rotated result stored accumulator contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Operation
Affected flag(s)
Description Operation
Rotate data memory right contents specified data memory rotated right with rotated [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Affected flag(s)
Description Operation
Rotate right place result accumulator Data specified data memory rotated right with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0
Affected flag(s)
Description Operation
Rotate data memory right through carry contents specified data memory carry flag together rotated right. replaces carry bit; original carry flag rotated into position. [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Affected flag(s)
Rev. 1.10
March 2007
HT49RU80/HT49CU80
RRCA Description Rotate right through carry place result accumulator Data specified data memory carry flag rotated right. replaces carry original carry flag rotated into position. rotated result stored accumulator. contents data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0 A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) Description
Operation
Affected flag(s)
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result accumulator. ACC+[m]+C
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result data memory. ACC+[m]+C
Skip decrement data memory contents specified data memory decremented result next instruction skipped. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
SDZA Description
Decrement data memory place result ACC, skip contents specified data memory decremented result next instruction skipped. result stored accumulator data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Description Operation Affected flag(s) [m]. Description Operation Affected flag(s) Description data memory Each specified data memory
data memory specified data memory [m].i
Skip increment data memory contents specified data memory incremented result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
SIZA Description
Increment data memory place result ACC, skip contents specified data memory incremented result next instruction skipped result stored accumulator. data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
[m].i Description
Skip data memory specified data memory next instruction skipped. data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip
Operation Affected flag(s)
Rev. 1.10
March 2007
HT49RU80/HT49CU80
A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) SWAP Description Operation Affected flag(s) SWAPA Description Operation Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result accumulator. ACC+[m]+1
Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result data memory. ACC+[m]+1
Subtract immediate data from accumulator immediate data specified code subtracted from contents accumulator, leaving result accumulator. ACC+x+1
Swap nibbles within data memory low-order high-order nibbles specified data memory data memories) interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory place result accumulator low-order high-order nibbles specified data memory interchanged, writing result accumulator. contents data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Affected flag(s)
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Description Skip data memory contents specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
Description
Move data memory ACC, skip contents specified data memory copied accumulator. contents following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
[m].i Description
Skip data memory specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m].i=0
Operation Affected flag(s)
TABRDC Description Operation
Move code (current page) TBLH data memory byte code (current page) addressed table pointer (TBLP) moved specified data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Affected flag(s)
TABRDL Description Operation
Move code (last page) TBLH data memory byte code (last page) addressed table pointer (TBLP) moved data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Affected flag(s)
Rev. 1.10
March 2007
HT49RU80/HT49CU80
A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical accumulator with data memory Data accumulator indicated data memory perform bitwise logical Exclusive_OR operation result stored accumulator.
Logical data memory with accumulator Data indicated data memory accumulator perform bitwise logical Exclusive_OR operation. result stored data memory. flag affected.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical Exclusive_OR operation. result stored accumulator. flag affected.
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Package Information
100-pin Outline Dimensions
Symbol
Dimensions Min. 18.50 13.90 24.50 19.90 2.50 0.10 Nom. 0.65 0.30 0.10 Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.40 0.20
Rev. 1.10
March 2007
HT49RU80/HT49CU80
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) Floor, Building No.889, Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit Productivity Building, Cross Science Road Gaoxin Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com
Copyright 2007 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. products authorized critical components life support devices systems. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
Rev. 1.10
March 2007
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