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UCD9240 Digital Point Load System Controller FEATURES Controls po
Top Searches for this datasheetUCD9240 UCD9240 Digital Point Load System Controller FEATURES Controls power stages voltage feedback control loops. Supports PMBus version 1.1. Flexible configuration, device control: Four single dual power stages, 4-phase power stages, 2,4,6, 8-phase power stage. Supports switching frequencies 2MHz. Supports conversion ratio 2MHz with psec duty-cycle resolution. +/-1mV feed-back resolution. Hardware accelerated digital 3-pole/3-zero compensator. Internal regulator drives external pass element, giving wide supply voltage range. 12-bit digital monitoring power supply parameters, including: Vin, Vout, each rail, Iout, each power stage (phase), External Temperature, each stage. Multiple levels current fault protection: External current fault inputs, Fast analog comparators monitor current sense voltage, Digital current sense monitor average current. Eight Synchronous Rectifier Enable (SRE) outputs. Able synchronize clocks between multiple UCD9240 devices. Enhanced non-volatile memory with Programmable soft start soft stop ramps under closed loop control. Supports multiple soft-start soft-stop configuration including pre-bias start-up. Supports voltage tracking. Supports current sharing multi-phase power stages. Supports phase shedding multi-phase power stages based average current. Programmable control outputs. Programmable margining sequencing. Power+ Designer, full featured based design tool simulate, configure, monitor power supply performance. APPLICATIONS Industrial Networking Equipment Servers Storage Systems Telecommunications Equipment DESCRIPTION UCD9240 digital synchronous buck controller that control power stages multi-phase configuration feedback outputs with phases output. This device provides enhanced configurability control point load (POL) applications. device configured PMBus with Power+ Designer GUI. switching frequency, output configuration feedback compensation programmed through Power+ Designer. This allows UCD9240 support multiple converter arrangements meet dynamic converter performance broad range applications. Each high speed digital control loop dedicated 3-pole/3-zero compensator 250ps PWMs. This architecture enables wide input output voltage conversion ratio's switching frequency 2MHz. Additionally, UCD9240 able monitor manage power supply operating conditions report status host system through PMBus. management parameters configurable through Power+ Designer. design tool allows power supply designer easily configure control loop characteristics generate expected performance displaying Bode plots each controlled power stage. multi-phase power stage outputs, UCD9240 incorporates current balancing. average current each phase monitored duty cycle each phase adjusted balance average current. addition, UCD9240 supports "shedding" more phases (ganged power stages) commanded through PMBus average current demand. When phase dropped added UCD9240 automatically adjusts phase each output minimize output ripple well needed change loop compensation. PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice. WWW.TI.COM Copyright 2007, Texas Instruments Incorporated UCD9240 Digital Point Load System Controller FUNCTIONAL BLOCK DIAGRAM Fusion Power Peripherals EAP4 EAP4 EAN4 EAN4 Error Compensator 3P/3Z Digital High DPWMDPWM-4A DPWMDPWM-4B FAULTFAULT-4A FAULTFAULT-4B EAP3 EAP3 EAN3 EAN3 Error Compensator 3P/3Z Digital High DPWMDPWM-3A DPWMDPWM-3B FAULTFAULT-3A FAULTFAULT-3B EAP2 EAP2 EAN2 EAN2 Error Compensator 3P/3Z Digital High DPWMDPWM-2A DPWMDPWM-2B FAULTFAULT-2A FAULTFAULT-2B Error EAP1 EAP1 EAN1 EAN1 Compensator Diff 3P/3Z Coeff. Coeff. Regs Digital High DPWMDPWM-1A DPWMDPWM-1B FAULTFAULT-1A FAULT-1B FAULT- SYNC-IN SYNCSYNC -OUT BPCAP ADDRADDR-00 ADDRADDR-01 CSCS-1A CSCS-1B CS2A CSCS-2B CSCS-3A CSCS-3B CSCS-4A CSCS-4B Vtrack Temperature Analog Comparators TRIP1 ksps ARMARM-7 core Flash memory with control TRIP2 SRESRE-4B SRESRE-4A SRESRE-3B SRESRE-3A SRESRE-2B SRESRE-2A SRESRE-1B SRESRE-1A TRIP3 Vreg TRIP4 PMBus PMBusPMBus-Clk PMBusPMBus-Data PMBusPMBus-Alert PMBusPMBus-Cntl ADCREFIN POR/BOR www.ti.com UCD9240 Digital Point Load System Controller 64-PIN 80-PIN ASSIGNMENTS UCD9240-64pin EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4 AddrSens0 AddrSens1 CS-1A (COMP1) CS-2A (COMP2) CS-3A (COMP3) CS-4A (COMP4) CS-1B CS-2B Vtrack Temp DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-4A FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-4A SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-4A EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4 AddrSen0 AddrSen1 CS-1A (COMP1) CS-2A (COMP2) CS-3A (COMP3) CS-4A (COMP4) CS-1B CS-2B CS-3B CS-4B Vtrack Temp ADCref UCD9240-80pin DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-3B DPWM-4A DPWM-4B FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-3B FAULT-4A FAULT-4B SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-3B SRE-4A SRE-4B TMUX-0 TMUX-1 PMBus-Clk TMUX-2 PMBus-Data FAN-PWM PMBus-Alert (TCLK) FAN-TACH PMBus-Ctrl PowerGood (TMS) (TDI) SYNC-IN (TDO) SYNC-OUT -RESET -TRST TMUX-1 TMUX-2 TMUX-3 PMBus-Clk PMBus-Data PMBus-Alert PMBus-Ctrl PowerGood SYNC-IN SYNC-OUT FAN-PWM FAN-TACH Diag -TRST -RESET UCD9240 available plastic 64-pin package (RGC) 80-pin TQFP package (PFC). www.ti.com UCD9240 Digital Point Load System Controller TYPICAL APPLICATION SCHEMATIC diagram above shows UCD9240 Power Supply Controller working system which requires regulation four independent power supplies. loop each power supply created respective voltage outputs feeding into Error differential inputs, completed DPWM outputs feeding into UCD7230 drivers which PTD08A0x0 modules above diagram. www.ti.com UCD9240 Digital Point Load System Controller DESCRIPTIONS 64-Pin Package signal EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4 80-Pin Package signal EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4 Description Error Analog, differential voltage, Positive channel input. Error Analog, differential voltage, Negative channel input. Error Analog, differential voltage, Positive channel input. Error Analog, differential voltage, Negative channel input. Error Analog, differential voltage, Positive channel input. Error Analog, differential voltage, Negative channel input. Error Analog, differential voltage, Positive channel input. Error Analog, differential voltage, Negative channel input. AddrSens0 AddrSens1 CS-1A CS-2A CS-3A CS-4A CS-1B CS-2B Vtrack Temp AddrSens0 AddrSens1 CS-1A CS-2A CS-3A CS-4A CS-1B CS-2B Vtrack Temp CS-3B CS-4B ADCref PMBus address sense. Least significant address bits PMBus address sense. Most significant address bits. Power stage current sense input, Analog comparator Power stage current sense input, Analog comparator Power stage current sense input, Analog comparator Power stage current sense input, Analog comparator Power stage current sense input. Power stage current sense input. sense input. Voltage Tracking Temperature sense input Power stage current sense input. Power stage current sense input. analog input analog input Decoupling Ground reference. dPWM-1A dPWM-1B dPWM-2A dPWM-2B dPWM-3A dPWM-4A dPWM-1A dPWM-1B dPWM-2A dPWM-2B dPWM-3A dPWM-3B dPWM-4A dPWM-4B DPWM output. DPWM output. DPWM output. DPWM output. DPWM output. DPWM output. DPWM output. DPWM output. FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-4A FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-3B FAULT-4A FAULT-4B External Fault input External Fault input External Fault input External Fault input External Fault input External Fault input External Fault input External Fault input SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-4A SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-3B SRE-4A SRE-4B diag Synchronous Rectifier Enable Synchronous Rectifier Enable Synchronous Rectifier Enable Synchronous Rectifier Enable Synchronous Rectifier Enable Synchronous Rectifier Enable Synchronous Rectifier Enable Synchronous Rectifier Enable Diagnostic TMUX-0 TMUX-1 TMUX-2 TMUX-0 TMUX-1 TMUX-2 Temperature multiplexer select Temperature multiplexer select Temperature multiplexer select www.ti.com UCD9240 Digital Point Load System Controller FAN-PWM FAN-PWM PowerGood FAN-Tach control output. Power Good signal tachometer input FAN-Tach Sync_Out Sync_In PowerGood Sync_Out Sync_In Sync output from DPWM Sync input DPWM connect DVss. connect DVss. connect DVss. connect DVss nRESET PMBus_Clk PMBus_Data PMBus_Alert PMBus_Cntrl nRESET PMBus_Clk PMBus_Data PMBus_Alert PMBus_Cntrl Active device reset input. PMBus (Must have pull-up 3.3V) PMBus Data (Must have pull-up 3.3V) PMBUS Alert PMBUS Cntl V33FB V33A V33D V33DIO V33DIO BPCap V33FB V33A V33D V33DIO V33DIO BPCap 3.3V linear regulator Feedback connection. Analog supply Digital Core 3.3V supply Digital 3.3V supply. Digital 3.3V supply. 1.8V Bypass Capacitor Connection. AVss AVss AVss DVss DVss DVss AVss AVss AVss DVss DVss DVss Analog Ground. Analog Ground. Analog Ground. Digital Ground. Digital Ground. Digital Ground. www.ti.com UCD9240 Digital Point Load System Controller ELECTRICAL SPECIFIACTIONS Recommended operating conditions SYMBOL PARAMETER UNIT V33D,V33DIO,V33A Supply voltage during operation Operating free-air temperature range Absolute Maximum Ratings1 Voltage applied V33D DVss Voltage applied V33A AVss Voltage applied (see NOTE) Storage temperature, TSTG -0.3 -0.3 -0.3 V33D -40C 150C Electrical Characteristics Supply Current SYMBOL PARAMETER TEST CONDITION UNIT I33a Supply current V33A 3.3V I33dio Supply current V33DIO 3.3V I33d Supply current V33D 3.3V I33d Supply current V33D 3.3V storing configuration parameters flash memory Regulator Inputs/Outputs SYMBOL PARAMETER TEST CONDITION UNIT Vreg BPCap Bypass Capacitor Voltage 3.3V Linear Regulator 3.25 3.35 V33FB 3.3V linear Feedback I33FB Series pass base drive Beta Series pass device Bias Supply Generator supply voltages, required. internal series pass regulator generates from supply. requires bypass capacitor from BPCap ground. either supplied from external source, generated from with regulation circuitry built into UCD9240 that drives external series pass transistor. Transistor beta must least typical application circuit shows base Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE: voltages referenced VSS. www.ti.com UCD9240 Digital Point Load System Controller external connected pull resistor VD33FB pin. emitter becomes supply chip should bypassed ground with Analog Inputs/Outputs PARAMETER TEST CONDITIONS UNIT EAPn, EANn Vsense Differential Voltage Range Maximum Vsense excursion -0.3 EAP-EAN Small Signal Error voltage resolution during start/stop ramp during mode Error Voltage Accuracy "DAC commanded 1.01 Input impedance ground reference Input capacitance differential IBIAS Bias current PMBus Addr pins VADDR PMBus Address programming bins Table 0.141 2.50 VRANGE: CSxx voltage range current sense input VRANGE: Vin, Vtrack, Vtemp input voltage range VOVERCURRENT: CS1-A, CS2-A, CS3-A, CS4-A Analog Overcurrent Threshold Current Sense Input capacitance ADCRefIn External Reference (80-pin package) (Not currently supported Firmware!) V33A Timing PARAMETER TEST CONDITIONS UNIT Tretention Retention configuration parameters Years t(reset) Pulse length needed Reset Fault Detection Latency t(FAULT) time disable output High level FAULT t(CLF) time disable output Step change voltage from 1.0V 2.5V t(OC) time disable output overcurrrent detection average Step change voltage from PMBus programmed over-current threshold 150% threshold production tested. Limits verified design. www.ti.com UCD9240 Digital Point Load System Controller www.ti.com UCD9240 Digital Point Load System Controller Digital Inputs/Outputs PARAMETER TEST CONDITIONS UNIT Low-level output voltage IOH= mA3, V33DIO Dgnd 0.25 High-level output voltage mA4, V33DIO V33dio High-level input voltage V33DIO Low-level input voltage V33DIO PMBus/SMBus/I2C timing characteristics timing diagram communications interface that supports SMBus PMBus shown below. Table C/SMBus/PMBus Timing Characteristics -40°C 85°C, 3.0V 3.6V; Typical values 25°C 2.5V (Unless otherwise noted) PARAMETER TEST CONDITIONS UNIT FSMB SMBus/PMBus operating frequency Slave mode, SMBC duty cycle FI2C operating frequency Slave mode, duty cycle FMAS SMBus master clock frequency Master mode, clock slave extend 51.2 t(BUF) free time between start stop t(HD:STA) Hold time after (repeated) start t(SU:STA) Repeated start setup time t(SU:STO) Stop setup time t(HD:DAT) Data hold time Receive Mode Transmit Mode t(SU:DAT) Data setup time t(TIMEOUT) Error signal/detect below t(LOW) Clock period t(HIGH) Clock high period below t(LOW:SEXT) Cumulative clock slave extend time below t(LOW:MEXT) Cumulative clock master extend time below Clock/data fall time below Clock/data rise time (10) below 1000 maximum total current, IOHmax IOLmax, outputs combined, should exceed +/-12 hold maximum voltage drop specified. maximum total current, IOHmax IOLmax, outputs combined, should exceed +/-48 hold maximum voltage drop specified. UCD9110 times when clock exceeds t(TIMEOUT). t(HIGH), Max, minimum idle time. SMBC SMBD causes reset transaction involving UCD9110 that progress. This specification valid when NC_SMB control remains default cleared state (CLK[0]=0). t(LOW:SEXT) cumulative time slave device allowed extend clock cycles message from initial start stop. t(LOW:MEXT) cumulative time master device allowed extend clock cycles message from initial start stop. Rise time VILMAX 0.15) (VIHMIN 0.15) Fall time 0.9VDD (VILMAX 0.15) www.ti.com UCD9240 Digital Point Load System Controller coefficients filter sections generated thru modeling power stage load Power+ Designer. Several banks filter coefficients downloaded device which automatically switch them based operation power stage. Figure I2C/SMBus/PMBus Timing Diagram www.ti.com UCD9240 Digital Point Load System Controller FUNCTION OVERVIEW UCD9240 contains four Fusion Power Peripherals (FPP). Each configured drive from eight power stages. Each consists differential feedback input, circuits used output regulation voltage, error measurement circuits, digital hardware accelerated 3-pole/3-zero compensator digital engine. Each controller configured through PMBus serial interface. PMBus Interface PMBus serial interface specifically designed support power management. based SMBus interface, which built physical specification. UCD9240 supports interface through dedicated hardware firmware ARM-7 digital supervisory processor. UCD9240 supports revision PMBus standard. Wherever possible, standard PMBus commands used support function device. unique features UCD9240, MFR_SPECIFIC commands defined configure activate those features. firmware UCD9240 PMBus compliant, accordance with "Compliance" section PMBus specification. firmware also compliant with SMBus specification, including support SMBus ALERT function. hardware support either signaling, though present firmware defaults kHz. PMBus Address Decode ADC12 Reading pins allocated decode PMBus address. power-up device applies IBIAS each address detect voltage that captured internal 12-bit ADC. PMBus address calculated follows. PMBus Address 12*bin(VAD01) bin(VAD00) Where bin(VAD0x) address address shown www.ti.com UCD9240 Digital Point Load System Controller Table AddrSens0, AddrSens1 IBIAS On/Off Control Resistor PMBus Address Figure PMBus Address Detection Method www.ti.com UCD9240 Digital Point Load System Controller Table PMBus Address bins Address Voltage 2.299 1.815 1.463 1.177 0.953 0.749 0.604 0.486 0.383 0.308 0.249 0.196 0.157 Resistor 86.6 68.1 54.9 44.2 34.8 28.0 22.6 17.8 14.3 impedance (short) address produces voltage below minimum voltage will cause PMBus address default address 0x0B. high impedance (open) address that produces voltage above maximum voltage will also cause PMBus address default address 0x0B. Figure PMBus Voltage Adjustment Methods Output Voltage Adjustment Output Voltage programmed issuing VOUT_COMMAND, VOUT_TRIM VOUT_MARGIN, commands PMBus. Soft-Start, Soft-Stop Normal Operation During soft-start soft-stop internal gain changed have +-8mV resolution This allows have wider dynamic range during start/stop ramp. During normal operation gain adjusted +-1mv resolution tighter regulation. www.ti.com UCD9240 Digital Point Load System Controller Digital Compensator Each voltage rail controller UCD9240 includes digital compensator. compensator digital filter consisting second order infinite impulse response (IIR) filter section cascaded with first order filter section. based design tool program: development tool UCD9240 comes with "POWER+DESIGNER", which used assist defining compensator coefficients. design tool allows compensator described terms pole frequencies, zero frequencies gain desired control loop. addition, Design Tool used characterize power stage that compensator coefficients chosen based total loop gain each feedback system. coefficients filter sections generated thru modeling power stage load Power+ Designer. Additionally, UCD9240 allows several banks filter coefficients which configured switch automatically based operation power stage. compensator also allows minimum maximum duty cycle programmed. This again done issuing PMBus command device. Engine output compensator feeds high resolution engine. engine produces pulse width modulated gate drive output from device. operation, compensator calculates necessary duty cycle 16-bit number representing value from 1.0. This duty cycle value multiplied period generate duty period. resolution duty period psec. When UCD9240 configured drive multiple power stage circuits from compensator, each gate drive output pulse width adjusted correct current imbalance between connected power stage sections. This done monitoring current using input current sense pins increasing pulse width signal driving power stage with lowest current decreasing pulse width signal driving power stage with highest measured current. Each engine synchronized another engine external sync signal SYNC_IN SYNC_OUT pins. input sync signal causes ramp timer reset. Sync signal outputs from each four engines occur when ramp timer crosses programmed threshold. this phase multiple power stage drive signals tightly controlled. synchronization behavior programmed through MFR_SPECIFIC PMBus command. www.ti.com UCD9240 Digital Point Load System Controller Engine SysClk SyncIn high ramp counter reset Switch period Current balance Compensator output EADC trigger threshold SyncOut phase gate drive output EADC trigger SyncOut switching frequency issuing FREQUENCY_SWITCH PMBus command. Fault Handling UCD9240 several fault handling features. following faults handled. monitored over-voltage under-voltage. logic high signal from external source, such gate driver will cause fault immediately shut down engine. response event programmed through PMBus command. device contains programmable internal analog comparators that monitor current sense inputs. current sense input exceeds programmed threshold signal shut down. Monitoring averaging current sense inputs each multiphase power stage that makes output rail. Over current under current (negative) thresholds programmed PMBus each rail. response event also programmed through PMBus command. Temperature periodically measured compared PMBus configured over-temperature threshold. Temperature Measurement UCD9240 ability measure current temperature controlled power stage. Temp select pins TMUX0-2 used control external analog multiplexer which cycles through each power stage temperature measurement signals. programmed accept output from either linear device such LM20 temperature sensor diode forward voltage. www.ti.com UCD9240 Digital Point Load System Controller Figure Temperature (4-rail, 6-phase example) Current Measurement Pins CS1-A, CS1-B, CS2-A, CS2-B, CS3-A, CS3-B, CS4-A, CS4-B used measure output inductor current each controlled power stages. MFR_SPECIFIC PMBus commands used calibrate each measurement. When measured current exceeds either over-current undercurrent threshold FAULT declared UCD9240 performs PMBus programmed fault recovery. current measurements digitally filtered (averaged) before compared against FAULT threshold. response PMBus request current reading, device will return average current value. When UCD9240 configured drive multi-phase power converter, device will average current measurement each power stages tied power rail. Current Sense Detection Several mechanisms provide sense output current. This allows design power systems with multiple layers protection. logic high signal FAULT input will immediately drive signal associated page (rail/output) low. signal will driven between usec later. intelligent gate driver such UCD7230 used generate FAULT signal. UCD7230 monitors voltage drop across high side exceeds resistor programmed threshold, UCD7230 activates output turns drives. used drive FAULT input UCD9240. Typically, FAULT input used monitor protect against short circuit switches load. Therefore this threshold highest current setting multiple over-current settings. Four current sense inputs wired internal analog comparator, each page (rail/output). threshold current sense input 2.0V. This input used detect output current sense amplifier such amplifier UCD7230 which monitors current power stage inductor. current sense voltage exceeds 2.0V corresponding output immediately driven low. signal will driven between usec later. over-current threshold condition programmed choosing appropriate divider network input CSx.y pin. This forms "middle" level over-current protection. Each Current Sense input UCD9240 also monitored 12-bit ADC. This measured value averaged compared with PMBus programmable threshold. This threshold typically lowest overcurrent setting closest maximum allowed current design. www.ti.com UCD9240 Digital Point Load System Controller PACKAGING 64-pin Package Notes: linear dimensions millimeters. Dimensioning tolerancing ASME Y14.5-1994. This drawing subject change without notice. Quad Flatpack, no-leads (QFN) package configuration. www.ti.com UCD9240 Digital Point Load System Controller 80-pin Package Notes: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026 Ordering Information Part Number Package Operating Temp. Range, UCD9240PHR 80-pin UCD9240RHBR 64-pin www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 4-May-2007 PACKAGING INFORMATION Orderable Device UCD9240RGCR UCD9240RGCT Status PREVIEW PREVIEW Package Type Package Drawing Pins Package Plan 2000 Lead/Ball Finish Call Call Peak Temp Call Call marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device. Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material) MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. 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