16K-Bit Microwire Serial EEPROM FEATURES High speed operation: 3M
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CAT93C86 (Die Rev.
16K-Bit Microwire Serial EEPROM FEATURES
High speed operation: 3MHz power CMOS technology volt operation Selectable memory organization Self-timed write cycle with auto-clear Hardware software write protection Power-up inadvertant write protection Sequential read Program enable (PE) 1,000,000 Program/erase cycles year data retention
E
Commercial, industrial automotive
temperature ranges
RoHS-compliant packages
DESCRIPTION
CAT93C86 16K-bit Serial EEPROM memory device which configured either registers bits (ORG VCC) bits (ORG GND). Each register written read) serially using pin. CAT93C86 manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. device designed endure 1,000,000 program/erase cycles data retention years. device available 8-pin DIP, 8-pin SOIC 8-pad TDFN packages.
CONFIGURATION
Package
FUNCTIONAL SYMBOL
SOIC Package
SOIC Package
SOIC Package
FUNCTIONS
Name Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization Program Enable
TDFN Package (ZD4)
View
Ordering Information details, page
Note: When connected VCC, organization selected. When connected ground, selected. left unconnected, then internal pullup device will select organization.
Catalyst Semiconductor, Inc. Characteristics subject change without notice.
Doc. 1091, Rev.
CAT93C86 ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground(1) -2.0V +VCC +2.0V with Respect Ground -2.0V +7.0V Package Power Dissipation Capability 25°C) 1.0W Lead Soldering Temperature secs) 300°C Output Short Circuit Current(2) RELIABILITY CHARACTERISTICS
Symbol NEND(3) TDR(3) VZAP(3) ILTH(3)(4) Parameter Endurance Data Retention Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 1,000,000 2000 Units Cycles/Byte Years Volts
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
D.C. OPERATING CHARACTERISTICS +1.8V +5.5V, unless otherwise specified.
Symbol ICC1 ICC2 ISB1 ISB2 VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including pin) Input Voltage Input High Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Test Conditions 1MHz 5.0V 1MHz 5.0V ORG=GND CS=0V ORG=Float VOUT VCC, 4.5V 5.5V 4.5V 5.5V 1.8V 4.5V 1.8V 4.5V 4.5V 5.5V 2.1mA 4.5V 5.5V -400µA 1.8V 4.5V 1.8V 4.5V -100µA -0.1 VCC+1 Units
Note: minimum input voltage -0.5V. During transitions, inputs undershoot -2.0V periods less than Maximum voltage output pins +0.5V, which overshoot +2.0V periods less than Output shorted more than second. more than output shorted time. This parameter tested initially after design process change that affects parameter. Latch-up protection provided stresses address data pins from +1V.
Doc. 1091, Rev.
CAT93C86
CAPACITANCE Symbol COUT
Test Output Capacitance (DO) Input Capacitance (CS, ORG)
Conditions VOUT=0V VIN=0V
Units
CIN(1)
INSTRUCTION Start Address Opcode A10-A0 A10-A0 A10-A0
11XXXXXXXXX 00XXXXXXXXX 10XXXXXXXXX 01XXXXXXXXX
Data A9-A0 A9-A0 A9-A0 D7-D0 Comments Read Address Clear Address D15-D0 Write Address Write Enable Write Disable Clear Addresses D7-D0 D15-D0 Write Addresses
Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL
11XXXXXXXX 00XXXXXXXX 10XXXXXXXX 01XXXXXXXX
A.C. CHARACTERISTICS Limits 1.8V-5.5V Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tCSMIN tSKHI tSKLOW SKMAX Parameter Setup Time Hold Time Setup Time Hold Time Output Delay Output Delay Output Delay High-Z Program/Erase Pulse Width Minimum Time Minimum High Time Minimum Time Output Delay Status Valid Maximum Clock Frequency 100pF Test Conditions 1000 2.5V-5.5V 0.15 0.15 0.15 3000 4.5V-5.5V 0.15 0.15 Units
Doc. 1091, Rev.
CAT93C86
POWER-UP TIMING (1)(2) Symbol tPUR tPUW Parameter Power-up Read Operation Power-up Write Operation Units
A.C. TEST CONDITIONS Input Rise Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages
50ns 0.4V 2.4V 0.8V, 2.0V 0.2VCC 0.7VCC 0.5VCC
4.5V 5.5V 4.5V 5.5V 1.8V 4.5V 1.8V 4.5V
NOTE: This parameter tested initially after design process change that affects parameter. tPUR tPUW delays required from time stable until specified operation initiated. input levels timing reference points shown Test Conditions" table.
DEVICE OPERATION
CAT93C86 16,384-bit nonvolatile memory intended with industry standard microprocessors. CAT93C86 organized either registers bits bits. When organized X16, seven 13-bit instructions control reading, writing erase operations device. When organized seven 14-bit instructions control reading, writing erase operations device. CAT93C86 operates single power supply will generate chip, high voltage required during write operation. Instructions, addresses, write data clocked into rising edge clock (SK). normally high impedance state except when reading data from device, when checking ready/busy status after write operation. ready/busy status determined after start write operation selecting device high) polling pin; indicates that write operation completed, while high indicates that device ready next instruction. necessary, placed back into high impedance state during chip select shifting dummy into pin. will enter high impedance state falling edge clock (SK). Placing into high impedance state recommended applications where tied together form common DI/O pin. format instructions sent device logical start bit, 2-bit 4-bit) opcode, 10-bit address additional when organized write operations 16-bit data field (8-bit organizations).
Enabled mode. Write Enable Write Disable instruction PE=don't care.
Read Upon receiving READ command address (clocked into pin), CAT93C86 will come high impedance state and, after sending initial dummy zero bit, will begin shifting data addressed (MSB first). output data bits will toggle rising edge clock stable after specified time delay (tPD0 tPD1). After initial data word been shifted remains asserted with clock continuing toggle, device will automatically increment next address shift next data word sequential READ mode. long continuously asserted continues toggle, device will keep incrementing next address automatically until reaches address space, then loops back address sequential READ mode, only initial data word preceeded dummy zero bit. subsequent data words will follow without dummy zero bit. Write After receiving WRITE command, address data, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking clear data store cycle memory location specified instruction. clocking necessary after device entered self clocking mode. ready/busy status CAT93C86 determined selecting device polling pin. Since this device features AutoClear before write, necessary erase memory location before written into.
Note: Write, Erase, Write Erase instructions require PE=1. left floating, 93C86 Program
Doc. 1091, Rev.
CAT93C86
Figure Sychronous Data Timing
tSKHI tDIS tCSS tDIS tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW
Figure Read Instruction Timing
Don't Care AN-1
HIGH-Z
Dummy
Address
Address
Address
Figure Write Instruction Timing
tCSMIN HIGH-Z BUSY READY HIGH-Z AN-1 STATUS VERIFY STANDBY
Doc. 1091, Rev.
CAT93C86
Erase Upon receiving ERASE command address, (Chip Select) must deasserted minimum tCSMIN. falling edge will start self clocking clear cycle selected memory location. clocking necessary after device entered self clocking mode. ready/busy status CAT93C86 determined selecting device polling pin. Once cleared, content cleared location returns logical state. Erase/Write Enable Disable CAT93C86 powers write disable state. writing after power-up after EWDS (write disable) instruction must first preceded EWEN (write enable) instruction. Once write instruction enabled, will remain enabled until power device removed, EWDS instruction sent. EWDS instruction used disable CAT93C86 write clear instructions, will prevent accidental writing clearing device. Data read normally from device regardless write enable/disable status. Erase Upon receiving ERAL command, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking clear cycle memory locations device. clocking necessary after device entered self clocking mode. ready/busy status CAT93C86 determined selecting device polling pin. Once cleared, contents memory bits return logical state. Write Upon receiving WRAL command data, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking data write memory locations device. clocking necessary after device entered self clocking mode. ready/busy status CAT93C86 determined selecting device polling pin. necessary memory locations cleared before WRAL command executed.
Figure Erase Instruction Timing
HIGH-Z AN-1
STATUS VERIFY
STANDBY
BUSY READY HIGH-Z
Doc. 1091, Rev.
CAT93C86
Figure EWEN/EWDS Instruction Timing
STANDBY
ENABLE=11 DISABLE=00
Figure ERAL Instruction Timing
STATUS VERIFY
STANDBY
BUSY READY HIGH-Z
HIGH-Z
Figure WRAL Instruction Timing
STATUS VERIFY tCSMIN
STANDBY
BUSY READY HIGH-Z
Doc. 1091, Rev.
CAT93C86 8-LEAD WIDE PLASTIC
SYMBOL
0.38 3.05 0.36 1.14 9.02 7.62 6.17 7.87 2.79
4.57 3.81 0.56 1.52 10.16 8.26 7.49 9.65 3.81
8-Lead_DIP_(300).eps
0.46
7.87 6.35 2.54
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC Standard MS001. Dimensioning tolerancing ANSI Y14.5M-1982
Doc. 1091, Rev.
CAT93C86 8-LEAD WIDE SOIC
SYMBOL
0.10 1.35 0.33 0.19 4.80 5.80 3.80
0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 0.25 0.40 0.50 1.27
24C16_8-LEAD_SOIC.eps
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC specification MS-012.
Doc. 1091, Rev.
CAT93C86 8-LEAD SOIC
SYMBOL
0.05 0.36 0.19 5.13 7.75 5.13
0.25 2.03 0.48 0.25 5.33 8.26 5.38
1.27 0.51 0.76
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with EIAJ specification EDR-7320.
Doc. 1091, Rev.
CAT93C86 8-PAD TDFN PACKAGE (ZD4)
INDEX AREA
SYMBOL
0.70 0.00 0.45 0.25 2.90 2.20 2.90 1.40 0.20
0.75 0.02 0.55 0.20 0.30 3.00 2.30 3.00 1.50 0.65 0.30
0.80 0.05 0.65 0.35 3.10 2.40 3.10 1.60
0.40
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC specification MO-229C.
TDFN 8-Lead 3x3.eps
Doc. 1091, Rev.
CAT93C86 ORDERING INFORMATION
Prefix Device 93C86 Product Number 93C86 Suffix -1.8
Company
Temperature Range Industrial (-40°C 85°C) Automotive (-40°C 105°C) Extended (-40°C 125°C) Package PDIP SOIC, JEDEC SOIC, JEDEC SOIC, EIAJ(5) TDFN (3x3mm) Operating Voltage Blank 2.5V 5.5V) 1.8V 5.5V)
Revision 93C86: Tape Reel Tape Reel 2000/Reel(5) 3000/Reel
Lead Finish Blank: Matte-Tin NiPdAu
Notes: packages RoHS-compliant (Lead-free, Halogen-free). standard finish NiPdAu. device used above example CAT93C86VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V 5.5V Operating Voltage, NiPdAu, Tape Reel). Product revision letter marked package suffix production date code (e.g., AYWWE.) additional information, please contact your Catalyst sales office. SOIC, EIAJ package standard lead finish Matte-Tin. This package available 2000 pcs/reel, i.e. CAT93C86XI-T2. additional package temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. 1091, Rev.
REVISION HISTORY
Date 05/14/04 Revision Comments Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 CAT93C86 have been separtated into single data sheets Revision Letter Update Features Update Description Update Condition Functional Diagram Update Function Update D.C. Operating Characteristics Update Capacitance Update Instruction Update Device Operation Update Ordering Information Added TDFN Package minor changes Update Features Update Configuration Update Functions Update D.C. Operating Characteristics (VCC Range) Update A.C. Characteristics (VCC Range) Update Ordering Information
08/10/04 9/3/04 10/13/06
Copyrights, Trademarks Patents
Catalyst Semiconductor, Inc. Trademarks registered trademarks Catalyst Semiconductor include each following: Beyond Memory EZDim MiniPotand Quad-ModeCatalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products. complete list patents issued Catalyst Semiconductor contact Company's corporate office 408.542.1000.
CATALYST SEMICONDUCTOR MAKES WARRANTY, REPRESENTATION GUARANTEE, EXPRESS IMPLIED, REGARDING SUITABILITY PRODUCTS PARTICULAR PURPOSE, THAT PRODUCTS WILL INFRINGE INTELLECTUAL PROPERTY RIGHTS RIGHTS THIRD PARTIES WITH RESPECT PARTICULAR APPLICATION SPECIFICALLY DISCLAIMS LIABILITY ARISING SUCH APPLICATION, INCLUDING LIMITED CONSEQUENTIAL INCIDENTAL DAMAGES.
Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Santa Clara, 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com
Publication Revison: Issue date:
1091 10/13/06
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