8K-Bit Microwire Serial EEPROM High speed operation: 3MHz 2.5V po

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8K-Bit Microwire Serial EEPROM High speed operation: 3MHz 2.5V po

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CAT93C76 (Rev.
8K-Bit Microwire Serial EEPROM
High speed operation: 3MHz 2.5V power CMOS technology volt operation Selectable memory organization Self-timed write cycle with auto-clear Software write protection Power-up inadvertant write protection 1,000,000 Program/erase cycles year data retention Industrial extended temperature ranges Sequential read "Green" package option available
DESCRIPTION
CAT93C76 8K-bit Serial EEPROM memory device which configured either registers bits (ORG Connected) bits (ORG GND). Each register written read) serially using pin. CAT93C76 manufactured using Catalyst's advanced CMOS EEPROM floating gate technology. device designed endure 1,000,000 program/erase cycles data retention years. device available 8-pin PDIP, SOIC, TSSOP 8-pad TDFN packages.
CONFIGURATION
PDIP (L), SOIC TSSOP (Y), TDFN (ZD4)
FUNCTIONAL SYMBOL
FUNCTION
Name Function Chip Select Serial Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization Connection Ordering Information details, page
Note: When connected VCC, organization selected. When connected ground, organization selected. left unconnected, then internal pull-up device will select organization.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-1090 Rev.
CAT93C76 (Rev.
ABSOLUTE MAXIMUM RATINGS Parameters Temperature Under Bias Storage Temperature Voltage with Respect Ground with Respect Ground Lead Soldering Temperature seconds) Output Short Circuit Current
Ratings +125 -2.0 +VCC +2.0 -2.0 +7.0
Units
RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) TDR(4) VZAP(4) ILTH(4)(5) Parameter Endurance Data Retention Susceptibility Latch-Up Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 1,000,000 2000 Units Cycles/Byte Years
D.C. OPERATING CHARACTERISTICS +1.8V +5.5V unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILORG VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter
Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current Leakage Current Input Voltage Input High Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage
Test Conditions
1MHz; 5.0V 1MHz; 5.0V Float VOUT VCC, 4.5V 5.5V 4.5V 5.5V 1.8V 4.5V 1.8V 4.5V 4.5V 5.5V; 2.1mA 4.5V 5.5V; -400µA 1.8V 4.5V; 100µA 1.8V 4.5V; -100µA
0(6) 0(6)
Units
-0.1
Notes: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability. minimum input voltage -0.5V. During transitions, inputs undershoot -2.0V periods less than 20ns. Maximum voltage output pins +0.5V, which overshoot +2.0V periods less than 20ns. Output shorted more than second. These parameters tested initially after design process change that affects parameter. Latch-up protection provided stresses pins from +1V. defined less than 900nA.
Doc. MD-1090 Rev.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT93C76 (Rev.
CAPACITANCE Symbol COUT Test Output Capacitance (DO) Input Capacitance (CS, ORG) Conditions VOUT Units
INSTRUCTION Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Start Address Opcode A10-A0 A10-A0 A10-A0 11XXXXXXXXX 00XXXXXXXXX 10XXXXXXXXX 01XXXXXXXXX A9-A0 A9-A0 A9-A0 11XXXXXXXX 00XXXXXXXX 10XXXXXXXX 01XXXXXXXX D7-D0 D15-D0 D7-D0 D15-D0 Data Comments Read Address Clear Address Write Address Write Enable Write Disable Clear Addresses Write Addresses
A.C. CHARACTERISTICS Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tCSMIN tSKHI tSKLOW SKMAX Parameter Setup Time Hold Time Setup Time Hold Time Output Delay Output Delay Output Delay High-Z Program/Erase Pulse Width Minimum Time Minimum High Time Minimum Time Output Delay Status Valid Maximum Clock Frequency
(1)(4)
Test Conditions
1.8V 2.5V
2.5V 5.5V Units 3000
100pF
1000
POWER-UP TIMING Symbol tPUR tPUW
Parameter Power-up Read Operation Power-up Write Operation
Units
Notes: These parameters tested initially after design process change that affects parameter. Address 1,024x8 org. 512x16 org. "don't care" bits, must kept either READ, WRITE ERASE commands. input levels timing reference points shown Test Conditions" table. tPUR tPUW delays required from time stable until specified operation initiated.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-1090 Rev.
CAT93C76 (Rev.
A.C. TEST CONDITIONS Input Rise Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages 50ns 0.4V 2.4V 0.8V, 2.0V 0.2VCC 0.7VCC 0.5VCC 4.5V 5.5V 4.5V 5.5V 1.8V 4.5V 1.8V 4.5V
DEVICE OPERATION
CAT93C76 8192-bit nonvolatile memory intended with industry standard microprocessors. CAT93C76 organized either registers bits bits. When organized X16, seven 13-bit instructions control read, write erase operations device. When organized seven 14-bit instructions control read, write erase operations device. CAT93C76 operates single power supply will generate chip, high voltage required during write operation. Instructions, addresses, write data clocked into rising edge clock (SK). normally high impedance state except when reading data from device, when checking ready/busy status after write operation. ready/busy status determined after start write operation selecting device high) polling pin; indicates that write operation completed, while high indicates that device ready next instruction. necessary, placed back into high impedance state during chip select shifting dummy into pin. will enter high impedance state falling edge clock (SK). Placing into high impedance state recommended applications where tied together form common DI/O pin. format instructions sent device logical start bit, 2-bit 4-bit) opcode, 10-bit address additional when organized write operations 16-bit data field (8-bit organizations). most significant address "don't care" must present. Read Upon receiving READ command address (clocked into pin), CAT93C76 will come high impedance state and, after sending initial dummy zero bit, will begin shifting data addressed (MSB first). output data bits will toggle rising edge clock stable after specified time delay (tPD0 tPD1). CAT93C76, after initial data word been shifted remains asserted with clock continuing toggle, device will automatically increment next address shift next data word sequential READ mode. long continuously asserted continues toggle, device will keep incrementing next address automatically until reaches address space, then loops back address sequential READ mode, only initial data word preceeded dummy zero bit. subsequent data words will follow without dummy zero bit. Write After receiving WRITE command, address data, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking clear data store cycle memory location specified instruction. clocking necessary after device entered self clocking mode. ready/busy status CAT93C76 determined selecting device polling pin. Since this device features Auto-Clear before write, necessary erase memory location before written into.
Doc. MD-1090 Rev.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT93C76 (Rev.
Figure Sychronous Data Timing
tSKHI tDIS tCSS tDIS tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH
Figure Read Instruction Timing
Don't Care AN-1
HIGH-Z
Dummy
Address
Address
Address
Figure Write Instruction Timing
tCSMIN HIGH-Z BUSY READY HIGH-Z AN-1 STATUS VERIFY STANDBY
Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-1090 Rev.
CAT93C76 (Rev.
Erase Upon receiving ERASE command address, (Chip Select) must deasserted minimum tCSMIN. falling edge will start self clocking clear cycle selected memory location. clocking necessary after device entered self clocking mode. ready/busy status CAT93C76 determined selecting device polling pin. Once cleared, content cleared location returns logical state. Erase/Write Enable Disable CAT93C76 powers write disable state. writing after power-up after EWDS (write disable) instruction must first preceded EWEN (write enable) instruction. Once write instruction enabled, will remain enabled until power device removed, EWDS instruction sent. EWDS instruction used disable CAT93C76 write clear instructions, will prevent accidental writing clearing device. Data read normally from device regardless write enable/disable status. Erase Upon receiving ERAL command, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking clear cycle memory locations device. clocking necessary after device entered self clocking mode. ready/busy status CAT93C76 Figure Erase Instruction Timing
determined selecting device polling pin. Once cleared, contents memory bits return logical state. Write Upon receiving WRAL command data, (Chip Select) must deselected minimum tCSMIN. falling edge will start self clocking data write memory locations device. clocking necessary after device entered self clocking mode. ready/busy status CAT93C76 determined selecting device polling pin. necessary memory locations cleared before WRAL command executed. Note After last data been sampled, Chip Select (CS) must brought before next rising edge clock (SK) order start selftimed high voltage cycle. This important because brought before after this specific frame window, addressed location will programmed erased. Power-On Reset (POR) CAT93C76 incorporates Power-On Reset (POR) circuitry which protects device against malfunctioning while lower than recommended operating voltage. device will power into read-only state will power-down into reset state when crosses level ~1.3
AN-1
STATUS VERIFY
STANDBY
HIGH-Z
BUSY READY HIGH-Z
Doc. MD-1090 Rev.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT93C76 (Rev.
Figure EWEN/EWDS Instruction Timing
STANDBY
ENABLE=11 DISABLE=00
Figure ERAL Instruction Timing
STATUS VERIFY
STANDBY
BUSY READY HIGH-Z
HIGH-Z
Figure WRAL Instruction Timing
STATUS VERIFY tCSMIN
STANDBY
BUSY READY HIGH-Z
Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-1090 Rev.
CAT93C76 (Rev. PACKAGE OUTLINE DRAWING
PDIP 8-Lead 300mils (1)(2)
SYMBOL
5.33 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 7.87 2.92 3.30 3.30 0.46 1.52 0.25 9.27 7.87 2.54 6.35 7.11 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25
IDENTIFICATION
VIEW
SIDE VIEW
VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC MS-001.
Doc. MD-1090 Rev.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT93C76 (Rev.
SOIC 8-Lead 150mils (1)(2)
SYMBOL
1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 0.25 0.40
1.75 0.25 0.51 0.25 5.00 6.20 4.00 0.50 1.27
IDENTIFICATION VIEW
VIEW
SIDE VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC MS-012.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-1090 Rev.
CAT93C76 (Rev.
TSSOP 8-Lead (1)(2)
SYMBOL
1.20 0.05 0.80 0.19 0.09 2.90 6.30 4.30 3.00 6.40 4.40 0.65 1.00 0.50 0.60 0.75 0.90 0.15 1.05 0.30 0.20 3.10 6.50 4.50
VIEW
SIDE VIEW
VIEW
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC MO-153.
Doc. MD-1090 Rev.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT93C76 (Rev.
TDFN 8-Pad (ZD4)
(1)(2)
PIN#1 IDENTIFICATION
SYMBOL
0.70 0.00 0.50 0.23 2.90 2.20 2.90 1.40 0.20
0.75 0.02 0.55 0.20 0.30 3.00 2.30 3.00 1.50 0.65 0.30
0.80 0.05 0.60 0.37 3.10 2.40 3.10 1.60 0.40
current Tape Reel information, download file from:
Notes: dimensions millimeters. Angles degrees. Complies with JEDEC MO-229.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-1090 Rev.
CAT93C76 (Rev. EXAMPLE ORDERING INFORMATION
Prefix
Company Product Number ZD4:
Device Suffix 93C76
Package PDIP SOIC, JEDEC TSSOP TDFN 3mm)
Temperature Range Industrial Extended
Lead Finish Blank: Matte-Tin NiPdAu
93C76
Tape Reel Tape Reel 2000 units/Reel 3000 units/Reel
Notes: packages RoHS-compliant (Lead-free, Halogen-free). standard lead finish NiPdAu. device used above example 93C76VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape Reel) Product revision letter marked package suffix production date code (e.g., AYWWA.) additional information, please contact your Catalyst sales office. TDFN package Tape Reel 2000 pcs/reel, others 3000 pcs/reel. additional package temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. MD-1090 Rev.
REVISION HISTORY
Date 08/11/2004 09/21/2007 Rev. Comments Initial Issue Added Package Outline Drawings Updated Example Ordering Information
Copyrights, Trademarks Patents Catalyst Semiconductor, Inc. Trademarks registered trademarks Catalyst Semiconductor include each following: Beyond MemoryTM, DPPTM, EZDimTM, LDDTM, MiniPotand Quad-ModeCatalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products. CATALYST SEMICONDUCTOR MAKES WARRANTY, REPRESENTATION GUARANTEE, EXPRESS IMPLIED, REGARDING SUITABILITY PRODUCTS PARTICULAR PURPOSE, THAT PRODUCTS WILL INFRINGE INTELLECTUAL PROPERTY RIGHTS RIGHTS THIRD PARTIES WITH RESPECT PARTICULAR APPLICATION SPECIFICALLY DISCLAIMS LIABILITY ARISING SUCH APPLICATION, INCLUDING LIMITED CONSEQUENTIAL INCIDENTAL DAMAGES. Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Santa Clara, 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com
Document MD-1090 Revision: Issue date: 09/21/07

8K-Bit Microwire Serial EEPROM High speed operation: 3MHz 2.5V po

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