440GRx PowerPC 440GRx Embedded Processor PowerPC® processor
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Part Number 440GRx Revision 1.08 October 2007
440GRx
PowerPC 440GRx Embedded Processor
PowerPC® processor operating 667MHz with 32KB I-cache D-cache with parity checking. 16KB on-chip SRAM.
Preliminary Data Sheet
Ethernet 10/100/1000Mbps half- fullduplex interfaces. Operational modes supported with packet reject, Jumbo frames, interrupt coalescing. four serial ports (16750 compatible UART).
Selectable processor:bus clock ratios N:1, N:2. Dual bridged Processor Local Buses (PLBs) with 128-bit widths. Double Data Rate (DDR2/1) Synchronous DRAM (SDRAM) interface operating 166MHz (333 data transfer rate) with optional ECC. support external peripherals, internal UART memory. V2.2 interface (3.3V only). Thirty-two bits 66MHz. Programmable interrupt controller supports interrupts from variety sources. Programmable General Purpose Timers (GPT). External peripheral (32-bit data) devices with external mastering. interfaces (one with bootstrap capability). NAND Flash interface. interface. General Purpose (GPIO) interface. JTAG interface board level testing. Boot from memory, Flash external peripheral bus, NAND Flash NAND Flash interface. Optional security feature (PPC440GRx-S). Available RoHS compliant, lead-free package.
Description
Designed specifically address high-end embedded applications, PowerPC 440GRx (PPC440GRx) provides high-performance, low-power solution that interfaces wide range peripherals incorporates on-chip power management features. This chip contains high-performance RISC processor, on-chip SRAM, DDR2/1 SDRAM controller, interface, control external peripherals, with scatter/gather support, Ethernet ports, serial ports, interfaces, interface, NAND Flash interface, optional security feature (PPC440GRx-A), general purpose I/O. Technology: CMOS Cu-11, 0.13m. Package: 35mm, 680-ball thermally enhanced plastic ball grid array (TE-PBGA). RoHS compliant package available. Typical power (estimated): Approximately 533MHz. Supply voltages required: 3.3V, 2.5V, 1.8V (DDR2) 2.5V (DDR1), 1.5V.
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Contents
Ordering Information Address Maps Block Diagram PowerPC Processor SRAM Controller Internal Buses Security Function (optional) KASUMI Algorithm (optional) Controller DDR2/1 SDRAM Memory Controller External Peripheral Controller (EBC) Ethernet Controller DMA-to-PLB3 (64-bit) Controller Serial Ports (UART) Controller Serial Peripheral Controller (SPI/SCP) NAND Flash Controller General Purpose Timers (GPT) General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) JTAG Package Diagram Signal Lists Signal Descriptions Device Characteristics Spread Spectrum Clocking Specifications DDR2/1 SDRAM Specifications SDRAM Write Operation SDRAM Read Operation Strapping Serial EEPROM
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Figures
Figure Order Part Number Figure PPC440GRx Functional Block Diagram Figure 35mm, 680-Ball TE-PBGA Package Figure Overshoot Waveform Figure Timing Waveform Figure Input Setup Hold Waveform Figure Output Delay Float Timing Waveform Figure Input Setup Hold Waveform RGMII Signals Figure Output Delay Hold Timing Waveform RGMII Signals Figure SDRAM Simulation Signal Termination Model Figure SDRAM Write Cycle Timing Figure SDRAM Read Timing
Tables
Table System Memory Address Table Address Table Recommended Reflow Soldering Profile Table JEDEC Moisture Sensitivity Level Ball Composition Table Signals Listed Alphabetically Table Signals Listed Ball Assignment Table Summary Table Reserved Connections Table Signal Functional Description Table Absolute Maximum Ratings Table Recommended Operating Conditions Table Input Capacitance Table Overshoot Undershoot Table Typical Power Supply Requirements Using DDR2 Memory Table Typical Power Supply Requirements Using DDR1 Memory Table Supply Power Dissipation Table Power Supply Loads Table Package Thermal Specifications Table Clocking Specifications Table Peripheral Interface Clock Timings Table Specifications-All Speeds Table Specifications-400MHz 667MHz Table SDRAM Output Driver Specifications Table SDRAM Write Operation Conditions Table Timing-DDR SDRAM Table Timing-DDR SDRAM TSK, TSA,
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Timing-DDR SDRAM Table Strapping Assignments
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Ordering Information
information availability following parts, contact your local AMCC sales office. additional information part number structure Figure
Product Name PPC440GRx PPC440GRx
Order Part Number (see Notes) PPC440GRx-SpAfffTs PPC440GRx-NpAfffTs
Package 35mm, TE-PBGA 35mm, TE-PBGA
Revision Level
Value 0x216218D0 0x216218D4
JTAG 0x0440F1E1 0x0440F1E1
Notes: Characters following dash (-): Security feature present, Security feature present Package type: lead-free (RoHS compliant), contains lead Chip revision level Processor frequency: 400MHz, 533MHz, 667MHz Case temperature range -40°C +100°C Shipping package type: tape-and-reel. Blank tray
Each part number contains revision code. This mask revision number included part number identification purposes only. (Processor Version Register) JTAG register software accessible (read-only) contain information that uniquely identifies part. Refer PPC440GRx User's Manual details accessing these registers. Figure Order Part Number
PPC440GRx-SUA667TZ
Shipping Package AMCC Part Number Security Feature Package Case Temperature Range Processor Frequency Revision Level
Note: example above contains security feature, lead-free, capable running MHz, shipped tape-and-reel packaging.
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Block Diagram
Figure PPC440GRx Functional Block Diagram
External Interrupts Clock Control, Reset Timers
PPC440
Power Mgmt DCRs 83MHz 30-bit addr 32/16-bit data 66MHz bits devices
Processor JTAG 32KB D-Cache Security (optional) Trace 32KB I-Cache SRAM 16KB (PLB4-128 bits) Controller
External Peripheral Controller NAND Flash Controller Bridge
Bridge (X-bar)
(PLB3-64 bits)
Bridge
Controller
DDR2/1 SDRAM Controller 333MHz data rate 14-bit addr 64/32-bit data Ethernet 10/100/1000 ZMII RGMII
On-chip Peripheral (OPB
GPIO
UART
PPC440GRx system chip (SOC) using CoreConnect BusArchitecture.
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Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Address Maps
PPC440GRx incorporates address maps. first fixed processor System Memory Address Map. This address defines possible contents various address regions which processor access. second Address Device Configuration Registers (DCRs). DCRs accessed software running PPC440GRx processor through mtdcr mfdcr instructions.
Table System Memory Address (Sheet
Function Total System Memory Address Space SDRAM Local Memory Reserved SRAM On-Chip Memory Reserved Security Function Security (PPC440GRx-S) KASUMI Algorithm Reserved Reserved Reserved Reserved Configuration Registers Reserved Interrupt Ack/Special Cycle Reserved Local Configuration Registers Reserved EEC0 0008 EED0 0000 EED0 0004 EF40 0000 EF40 0040 EECF FFFF EED0 0003 EF3F FFFF EF40 003F EF4F FFFF E000 0000 E800 0000 E801 0000 E880 0000 EC00 0000 EEC0 0000 E7FF FFFF E800 FFFF 1E87F FFFF EBFF FFFF EEBF FFFF EEC0 0007 56MB 64KB Memory Controller E001 4000 E010 0000 E018 0000 E018 0800 8000 0000 C000 0000 E00F FFFF E017 FFFF E018 07FF 7FFF FFFF BFFF FFFF DFFF FFFF 512MB 512KB 8000 0000 E001 0000 E000 FFFF E001 3FFF 16KB Function Start Address 0000 0000 0000 0000 Address FFFF FFFF 7FFF FFFF Size
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table System Memory Address (Sheet
Function Reserved General Purpose Timer Reserved UART0 Reserved UART1 Reserved UART2 Reserved UART3 Reserved IIC0 Reserved IIC1 Reserved Internal Peripherals Reserved OPB0 Arbiter Reserved GPIO0 Controller Reserved GPIO1 Controller Reserved Ethernet ZMII Reserved Ethernet Controller Reserved Ethernet Controller Reserved Ethernet RGMII Reserved Boot space Notes: relocatable, this reflects suggested configuration. Bank Function Start Address EF50 0000 EF60 0000 EF60 0200 EF60 0300 EF60 0308 EF60 0400 EF60 0408 EF60 0500 EF60 0508 EF60 0600 EF60 0608 EF60 0700 EF60 0720 EF60 0800 EF60 0820 EF60 0900 EF60 0907 EF60 0A00 EF60 0A40 EF60 0B00 EF60 0B80 EF60 0C00 EF60 0C80 EF60 0D00 EF60 0D10 EF60 0E00 EF60 0E78 EF60 0F00 EF60 0F78 EF60 1000 EF60 1080 F000 0000 FFE0 0000 Address EF5F FFFF EF60 01FF EF60 02FF EF60 0307 EF60 03FF EF60 0407 EF60 04FF EF60 0507 EF60 05FF EF60 0607 EF60 06FF EF60 071F EF60 07FF EF60 081F EF60 08FF EF60 0906 EF60 09FF EF60 0A3F EF60 0AFF EF60 0B7F EF60 0BFF EF60 0C7F EF60 0CFF EF60 0D0F EF60 0DFF EF60 0E77 EF60 0EFF EF60 0F77 EF60 0FFF EF60 1103 EFFF FFFF FFDF FFFF FFFF FFFF 254MB 264B 120B 120B 128B 128B 512B Size
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Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Address
Function Total Address Space1 function: Reserved Clocking Power Reset (CPR0) System DCRs (SDR0) Memory Controller (SDRAM0) External Controller (EBC0) Reserved PLB4-to-PLB3 Bridge PLB3-to-PLB4 Bridge Reserved PLB3 Arbiter PLB4 Arbiter PLB3-to-OPB0 Bridge Reserved Power Management Reserved Interrupt Controller Interrupt Controller Interrupt Controller Power Management Reserved DMA-to-PLB3 Controller Reserved Ethernet Reserved DMA-to-PLB4 Controller Reserved Chip Memory (SRAM Controller) Reserved Notes: addresses bits (1024 unique addresses). Each unique address represents single 32-bit (word) register. kiloword (1024W) equals (4096 128W Start Address Address Size (4KB)1
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440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
PowerPC Processor
PowerPC processor designed high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. implements Book PowerPC embedded architecture uses 128-bit version IBM's on-chip CoreConnect Architecture. Features include: 667MHz operation PowerPC Book architecture 32KB I-cache, 32KB D-cache UTLB Word Wide parity data address parity with exception force Three logical regions D-cache: locked, transient, normal D-cache full line flush capability 41-bit virtual address, 36-bit (64GB) physical address Superscalar, out-of-order execution 7-stage pipeline execution pipelines Dynamic branch prediction Memory management unit 64-entry, full associative, unified with optional parity Separate instruction data micro-TLBs Storage attributes write-through, cache-inhibited, guarded, little endian Debug facilities Multiple instruction data range breakpoints Data value compare Single step, branch, trap events Non-invasive real-time trace interface instructions Single cycle multiply multiply-accumulate integer multiply 32-bit
SRAM Controller
internal SRAM controller (ISC) supports following features: bank (Bank 16KB configurable 4KB, 16KB (128 bits wide) 128-bit slave attachment addressable master Transfers slave cycles: Single-beat read write bytes 64-bit masters, bytes 128-bit masters) 4-word line read write 8-word line read write Double word read write bursts 64-bit masters Quadword read write bursts 128-bit masters Slave-terminated double word quadword fixed length bursts Master-terminated variable length bursts Guarded memory access boundaries Data parity checking Data transfers occur speeds. Power management
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440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Internal Buses
PowerPC 440GRx features four standard internal buses: Processor Local Buses (PLBs), On-Chip Peripheral Buses (OPBs), Device Control Register (DCR). high performance, high bandwidth cores such PowerPC processor, SDRAM memory controller, bridge connect PLBs. OPB0 hosts lower data rate peripherals. daisy-chained provides lower bandwidth path passing status control information between processor other on-chip cores. Features include: PLB4 (128-bit) 128-bit implementation architecture Separate simultaneous read write data paths 36-bit address Simultaneous control, address, data phases Four levels pipelining Byte-enable capability supporting unaligned transfers 64-byte burst transfers 166MHz, maximum 5.3GB/s (simultaneous read write) Processor:bus clock ratios PLB3 (64-bit) 64-bit implementation architecture 32-bit address 166MHz (1:1 ratio with PLB4), maximum 1.3GB/s simultaneous read write) OPBs (OPB0) 32-bit data path 32-bit address 83MHz 32-bit data path 10-bit address
Security Function (optional)
built-in security function (PPC440GRx-S only) cryptographic engine attached 128-bit with builtin interrupt controllers. Features include: Federal Information Processing Standard (FIPS) 140-2 design Support unlimited number Security Associations (SA) Different formats each supported protocol (IPsec/SSL/TLS/sRTP) Internet Protocol Security (IPSec) features Full packet transforms (ESP Complete header trailer processing (IPv4 IPv6) Multi-mode automatic padding "Mutable bit" handler including IPv4 option IPv6 extension headers Secure Socket Layer (SSL) Transport Layer Security (TLS) features Packet transforms One-pass hash-then-encrypt packet transforms inbound packet using Stream Cipher Secure Real-Time Protocol (sRTP) features Packet transforms removal insertion Variable bypass offset header length packet IPsec/SSL security acceleration engine DES, 3DES, AES, ARC-4 encryption MD-5, SHA-1 hashing, HMAC encrypt-hash hash-decrypt, KASUMI
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Public acceleration RSA, Diffie-Hellman True pseudo random number generators Non-deterministic true random numbers Pseudo random numbers with lengths ANSI X9.17 Annex compliant using algorithm Interrupt controller Fifteen programmable, maskable interrupts Initiate commands input interrupt Sixteen programmable interrupts indicating completion certain operations interrupts mapped level- edge-sensitive programmable interrupt output controller Autonomous, 4-channel 1024-words bits/word) transfer Scatter/gather capability with byte aligned addressing
KASUMI Algorithm (optional)
scheduling hardware algorithm support Automatic data padding mechanism algorithm KASUMI encryption decryption modes 32-bit slave interface Fully synchronous clock
Controller
interface allows connection devices PowerPC processor local memory. This interface designed Version Specification supports devices. Reference Specifications: PowerPC CoreConnect (PLB) Specification Version Specification Version Power Management Interface Specification Version Features include: Frequency 66MHz 32-bit Host Bridge Adapter Device's interface Internal arbitration function, supporting external devices, that disabled with external arbiter Support Message Signaled Interrupts Simple message passing capability Asynchronous Power Management register addressable both from on-chip processor device sides Ability boot from memory Error tracking/status Supports initiation transfers following types: Single beat reads writes Single beat burst memory reads writes Single beat configuration reads writes (type type Single beat special cycles
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440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
DDR2/1 SDRAM Memory Controller
Double Data Rate (DDR2/1) SDRAM memory controller supports industry standard discrete devices that compatible with both DDR1 DDR2 specifications. correct supply voltage must provided types devices: DDR1 devices require +2.5V DDR2 devices require +1.8V. Global memory timings, address bank sizes, memory addressing modes programmable. Features include: 32-bit memory interface DDR1 64-bit memory interface DDR2 Optional Error Checking Correcting (ECC) 2.6-GB/s peak data rate memory banks each Maximum capacity Support 256-Mb, 512-Mb, 1-Gb devices, with latencies Support DDR266/333 DDR2-266/333. (Faster parts used must clocked faster than 166MHz) Page mode accesses open pages) with configurable paging policy Programmable address mapping timing Software initiated self-refresh Power management (self-refresh, suspend, sleep) chip selects
External Peripheral Controller (EBC)
Features include: ROM, EPROM, SRAM, Flash memory, slave peripheral banks supported 83MHz operation Burst non-burst devices 32-bit byte-addressable data Data parity 30-bit address Peripheral Device pacing with external "Ready" Latch data Ready, synchronous asynchronous Programmable access timing device Wait States non-burst Burst Wait States first access Wait States subsequent accesses Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping External Slave Support External master interface Write posting from external master Read prefetching external master reads Bursting capable from external master Allows external master access non-EBC slaves External master control slaves access
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Ethernet Controller
Ethernet support provided PPC440GRx interfaces physical layer included chip: 10/100/1000 interfaces running full- half-duplex modes providing: Gigabit Media Independent Interface (GMII) Media Independent Interface (MII) Reduced Gigabit (RGMII) Serial (SMII) 100/10Mbps. Packet reject support Jumbo frame support capability Interrupt coalescence
DMA-to-PLB3 (64-bit) Controller
This controller provides interface between OPB0 PLB3. Features include: Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/Gather capability programming multiple operations 32-byte buffer 16-, 32-bit peripheral support (OPB external) 32-bit addressing Address increment decrement Supports internal external peripherals Support memory mapped peripherals Support peripherals running slower frequency buses
Serial Ports (UART)
Features include: four ports following combinations: 8-pin (UART0) 4-pin (UART0 UART1) 4-pin (UART0) 2-pin (UART1 UART2) Four 2-pin (UART0, UART1, UART2, UART3) Selectable internal external serial clock allow wide range baud rates Register compatibility with NS16750 register Complete status reporting capability Fully programmable serial-interface characteristics Supports using internal function PLB3
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440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Controller
Features include: interfaces provided Support Philips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters independent byte data buffers Twelve memory-mapped, fully programmable configuration registers programmable interrupt request signal Provides full management protocols Programmable error recovery Includes integrated bootstrap controller (BSC) that multiplexed with second interface
Serial Peripheral Controller (SPI/SCP)
Serial Peripheral Interface (also known Serial Communications Port) full-duplex, synchronous, character-oriented (byte) port that allows exchange data with other serial devices. master serial port supporting 3-wire interface (receive, transmit, clock), slave OPB. Features include: Three-wire serial port interface Full-duplex synchronous operation master slave Programmable clock rate divider Clock inversion Reverse data Local data loop back test
NAND Flash Controller
NAND Flash controller provides simple interface between four separate external NAND Flash devices. provides both direct command, address, data access external device well memory-mapped linear region that generates data accesses. NAND Flash data transferred peripheral data bus. Features include: four banks supported Direct interface Discrete NAND Flash devices four devices) SmartMedia Card socket (22-pins) Device sizes: larger supported read/write access 256MB boot-from-NAND flash (size supported depends addressing mode) (512 16)-B 64)-B page sizes supported Boot-from-NAND Execute boot code first block. Automatic page read accesses performed based device configuration addressing mode. provides single-bit error correction double-bit error detection each 256B stored data
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
General Purpose Timers (GPT)
Provides separate time base counter additional system timers addition those defined processor. Features include: 32-bit Time Base Counter driven clock Seven 32-bit compare timers
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed memory-mapped master accesses. GPIOs multiplexed with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. Each GPIO output separately programmable emulate open drain driver (that drives zero, tri-stated output
Universal Interrupt Controller (UIC)
Universal Interrupt Controllers (UIC) employed. They provide control, status, communications necessary between external internal sources interrupts on-chip PowerPC processor.
Note:
Processor specific interrupts (for example, page faults) resources.
Features include: external interrupts Edge triggered level-sensitive Positive negative active Non-critical critical interrupt on-chip processor Programmable interrupt priority ordering Programmable critical interrupt vector faster vector processing
JTAG
Features include: IEEE 1149.1 Test Access Port JTAG Boundary Scan Description Language (BSDL) Refer list AMCC partners supplying probes with this port.
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440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Package Diagram
Figure 35mm, 680-Ball TE-PBGA Package
View
Part Number
PPC440GRx
PPC440GRx-nprffft ccccccc
24.0 30.0
Gold Gate Release Corresponds Ball Location
1YWWBZZZZZ
Number (ZZZZZ)
Bottom View 35.0 35.0 33.0 Mold Compound Thermal Balls 2.65
0.60 0.10 Solder Ball
Substrate
Notes: dimensions
Package available with lead lead-free (RoHS compliant). Package conforms JEDEC MS-034.
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Assembly Recommendations
Table Recommended Reflow Soldering Profile
Profile Feature Average ramp-up rate Preheat Temperature Temperature Time (min max) Time Maintained Above: Temperature Time Peak Temperature Time within Actual Peak Temperature Ramp-down Rate Time 25°C Peak Temperature Sn-Pb Eutectic Assembly 3°C/second Free Reflow Assembly 3°C/second
100°C 150°C 60-120 Seconds
150°C 180°C 60-120 Seconds
183°C 60-150 Seconds +0/-5°C 10-30 Seconds 6°C/Second Minutes
230°C 30-50 Seconds +5/-0°C 10-20 Seconds 6°C/Second Minutes
Table JEDEC Moisture Sensitivity Level Ball Composition
Sn-Pb Eutectic Assembly Level Solder Ball Metallurgy 63Sn/37Pb Sn/4Ag/05Cu Free Reflow Assembly
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Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Signal Lists
following table lists external signals alphabetical order shows ball (pin) number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signals brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page Table page where signals indicated interface group begin. cases where signals same interface group (for example, Ethernet) have different names distinguish variations mode operation, names separated comma with primary mode name appearing first. cases where signals have same function associated with different ports (for example, UART), signals separated slash (/). These signals listed only once, appear alphabetically primary mode primary port name. Alphabetical Signal List Table Signals Listed Alphabetically (Sheet
Signal Name AGND AVDD BankSel0 BankSel1 [BusReq]GPIO31 ClkEn [DMAAck0][IRQ8]GPIO47 [DMAAck1][IRQ4]GPIO44 [DMAAck2][PerAddr06]GPIO01 [DMAAck3][PerAddr03]GPIO04 [DMAReq0][IRQ7]GPIO46 [DMAReq1]IRQ5[ModeCtrl] [DMAReq2][PerAddr07]GPIO00 [DMAReq3][PerAddr04]GPIO03 Ball AP25 Power AP24 AJ03 AK03 AP08 AH02 SDRAM AH01 AH04 AN09 AL21 AM18 AP15 AL14 AE04 AB03 AN10 External Slave Peripheral External Slave Peripheral SDRAM External Master Peripheral SDRAM SDRAM SDRAM Interface Group Page
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440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DrvrInh1 [DrvrInh2]Halt EAGND EAVDD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 [EOT0/TC0][IRQ9]GPIO48 [EOT1/TC1][IRQ6]GPIO45 [EOT2/TC2][PerAddr05]GPIO02 [EOT3/TC3][PerAddr02]GPIO05 EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD [ExtAck]GPIO30 Ball AM21 AM19 AL16 AM13 AE03 AB04 AP10 System AP27 Power AP28 AM11 AL11 AM09 AL09 SDRAM AP11 AN11 AM10 AP09 External Slave Peripheral AA22 AB21 AC33 AF30 AH30 AJ30 Power AK26 AK28 AK29 AK33 AN23 AN30 External Master Peripheral AMCC Proprietary SDRAM Interface Group Page
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [ExtReq]GPIO27 ExtReset GMCCD, GMC1RxClk GMCCrs, GMC1TxClk GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMCRefClk, SMIIRefClk GMCRxClk, GMC0RxClk SMIISync GMCRxD0, GMC0RxD0, TBIRxD0, RTBI0RxD0, SMII0RxD GMCRxD1, GMC0RxD1 SMII1RxD GMCRxD2, GMC0RxD2 GMCRxD3, GMC0RxD3 GMCRxD4, GMC1RxD0 GMCRxD5, GMC1RxD1 GMCRxD6, GMC1RxD22 GMCRxD7, GMC1RxD3 GMCRxDV, GMC0RxCtl GMCRxEr, GMC1RxCtl GMCTxClk GMCTxD0, GMC0TxD0 SMII0TxD GMCTxD1, GMC0TxD, SMII1TxD [GMCTxD2, GMC0TxD2] GPIO24 [GMCTxD3, GMC0TxD3] GPIO25 [GMCTxD4, GMC1TxD0] GPIO16 [GMCTxD5, GMC1TxD1] GPIO17 [GMCTxD6, GMC1TxD2] GPIO18 [GMCTxD7, GMC1TxD3] GPIO19 GMCTxEr, GMC1TxCtl GMCTxEn, GMC0TxCtl AJ32 AK32 AM27 AL34 AK34 AJ33 AN28 AL28 AP29 AM28 AN29 AM29 AP30 AP31 AM30 AJ31 AL33 AL27 AL24 AN25 AM25 AL25 AP26 AL26 AN26 AM26 AM24 AN24 Ethernet Ball Interface Group External Master Peripheral External Master Peripheral Page
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440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Power Ball Interface Group Page
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Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Power Ball Interface Group Page
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Power Ball Interface Group Page
AMCC Proprietary
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440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name AA14 AA15 AA17 AA18 AA20 AA21 AB13 AB15 AB17 AB18 AB20 AB22 AD01 AE05 AE30 AG02 Power Ball Interface Group Page
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball AG05 AG30 AG33 AJ01 AK04 AK05 AK08 AK10 AK16 AK17 AK19 AK25 AK27 AK30 AK31 AL03 AL04 AL05 AL06 AL29 AL30 AL31 AL32 AM01 AM02 AM03 AM04 AM31 AM32 AM33 AM34 AN01 AN02 AN03 AN04 AN08 AN16 Power Interface Group Page
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball AN19 AN27 AN31 AN32 AN33 AN34 Power AP01 AP02 AP03 AP32 AP33 AP34 Interface Group Page
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name GPIO00[PerAddr07][DMAReq2] GPIO01[PerAddr06][DMAAck2] GPIO02[PerAddr05][EOT2/TC2] GPIO03[PerAddr04][DMAReq3] GPIO04[PerAddr03][DMAAck3] GPIO05[PerAddr02][EOT3/TC3] GPIO06[PerCS1][NFCE1] GPIO07[PerCS2][NFCE2] GPIO08[PerCS3][NFCE3] GPIO09[PerCS4] GPIO10[PerCS5] GPIO11[PerErr] GPIO12[NFREn] GPIO13[NFWEn] GPIO14[NFCLE] GPIO15[NFALE] GPIO16[GMCTxD4, GMC1TxD0] GPIO17[GMCTxD5, GMC1TxD1] GPIO18[GMCTxD6, GMC1TxD2] GPIO19[GMCTxD7, GMC1TxD3] GPIO20[RejectPkt0] GPIO21[RejectPkt1] GPIO22[NFRdyBusy] GPIO23[SCPDO] GPIO24[GMCTxD2, GMC0TxD2] GPIO25[GMCTxD3, GMC0TxD3] [GPIO26]IIC0SData GPIO27[USB2RxErr][ExtReq] GPIO28[USB2TxVal] GPIO29[USB2Susp][HoldAck] GPIO30[USB2XcvrSel][ExtAck] GPIO31[USB2TermSel][BusReq] System AP26 AL26 AN26 AM26 AM23 AL23 AB31 AM25 AL25 AB33 Ball Interface Group Page
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name GPIO32[USB2OM0][PerDataPar2] GPIO33[USB2OM1][PerDataPar3] GPIO38[UART0_DTR/UART1_Tx] GPIO39[UART0_RI/UART1_Rx] GPIO40[IRQ0] GPIO41[IRQ1] GPIO42[IRQ2] GPIO43[IRQ3] GPIO44[IRQ4][DMAAck1] GPIO45[IRQ6][EOT1/TC1] GPIO46[IRQ7][DMAReq0] GPIO47[IRQ8[DMAAck0] GPIO48[IRQ9][EOT0/TC0] GPIO49[TrcBS0] GPIO50[TrcBS1] GPIO51[TrcBS2] GPIO52[TrcES0] GPIO53[TrcES1] GPIO54[TrcES2] GPIO55[TrcES3] GPIO56[TrcES4] GPIO57[TrcTS0] GPIO58[TrcTS1] GPIO59[TrcTS2] GPIO60[TrcTS3] GPIO61[TrcTS4] GPIO62[TrcTS5] GPIO63[TrcTS6] Halt[DrvrInh2] [HoldAck]GPIO29 HoldPri[LeakTest] HoldReq[RcvrInh] IIC0SClk IIC0SData[GPIO26] AD33 AC31 AD34 System AE34 AE32 AE33 AE31 AF34 AF33 AF32 AF31 AG34 AG31 AH33 AH34 AH32 AJ34 AH31 AB32 IIC0 Peripheral AB33 External Master Peripheral System Ball Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [IIC1SClk]SCPClkOut [IIC1SData]SCPDI [IRQ0]GPIO40 [IRQ1]GPIO41 [IRQ2]GPIO42 [IRQ3]GPIO43 [IRQ4]GPIO44[DMAAck1] IRQ5[ModeCtrl][DMAReq1] [IRQ6]GPIO45[EOT1/TC1] [IRQ7]GPIO46[DMAReq0] [IRQ8]GPIO47[DMAAck0] [IRQ9]GPIO48[EOT0/TC0] [LeakTest]HoldPri LeakTest2 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemAddr13 MemClkOut MemClkOut Ball AC34 IIC1 Peripheral AC32 AD33 AC31 AD34 Interrupts System AM05 AP04 AP05 AM06 AP06 AN06 AL07 SDRAM AN07 AM07 AP07 AL02 AL08 AM08 AG04 AL01 SDRAM AK01 Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AN22 AP22 AM20 AL20 AL22 AM22 AN21 AP21 AP20 AL18 AN17 AP17 AN20 AP19 AN18 AP18 SDRAM AM16 AP16 AL15 AP14 AL17 AM17 AN15 AM15 AP13 AN13 AP12 AL12 AM14 AN14 AL13 AM12 Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemODT0 MemODT1 [ModeCtrl]IRQ5[DMAReq1] Ball AF03 AF01 AD04 AD03 AG03 AF02 AE02 AE01 AC03 AC01 AA04 AA03 AD02 AC04 AB01 AB02 SDRAM AA02 AA01 AH03 SDRAM AG01 System Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [NFALE]GPIO15 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO06 [NFCE2][PerCS2]GPIO07 [NFCE3][PerCS3]GPIO08 [NFCLE]GPIO14 [NFRdyBusy]GPIO22 [NFREn]GPIO12 [NFWEn]GPIO13 NAND Flash Ball Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Ball F06-F29 G06-G29 H06-H29 J06-J29 K06-K29 L06-L29 M06-M29 N06-N12 N23-N29 P06-P12 P23-P29 R06-R12 R23-R29 T06-T12 T23-T29 U06-U12 U23-U29 V06-V12 V23-V29 W06-W12 W23-W29 Y06-Y12 Y23-Y29 AA06-AA12 AA23-AA29 AB06-AB12 AB23-AB29 AC06-AC29 AD06-AD29 AE06-AE29 AF06-AF29 AG06-AG29 AH06-AH29 AJ06-AJ29 physical ball does exist these ball coordinates. Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Power Ball Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0/BE0 PCIC1/BE1 PCIC2/BE2 PCIC3/BE3 PCIClk PCIDevSel PCIFrame AA32 Ball Interface Group Page
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Table Signals Listed Alphabetically (Sheet
Signal Name PCIGnt0/Req PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY AA33 AA34 AB34 AA31 Ball Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [PerAddr02]GPIO05[EOT3/TC3] [PerAddr03]GPIO04[DMAAck3] [PerAddr04]GPIO03[DMAReq3] [PerAddr05]GPIO02[EOT2/TC2] [PerAddr06]GPIO01[DMAAck2] [PerAddr07]GPIO00[DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0[NFCE0] [PerCS1][NFCE1]GPIO06 [PerCS2][NFCE2]GPIO07 [PerCS3][NFCE3]GPIO08 [PerCS4]GPIO09 [PerCS5]GPIO10 External Slave Peripheral External Slave Peripheral External Slave Peripheral External Master Peripheral Ball Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 [PerDataPar2]GPIO32 [PerDataPar3]GPIO33 [PerErr]GPIO11 PerOE PerReady External Slave Peripheral External Master Peripheral External Slave Peripheral External Slave Peripheral Ball Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PSROOut [RcvrInh]HoldReq RefEn [RejectPkt0]GPIO20 [RejectPkt1]GPIO21 Reserved Reserved Reserved Reserved Reserved Reserved SCPClkOut[IIC1SClk] SCPDI[IIC1SData] [SCPDO]GPIO23 SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD External Slave Peripheral AJ04 AM23 Ethernet AL23 Reserved AC34 AC32 AB31 AA13 AB14 AC02 AF05 AH05 AJ05 Power AK02 AK06 AK07 AK09 AK18 AN05 AN12 Serial Peripheral (SPI) System SDRAM System System Ball Interface Group External Slave Peripheral Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name SVREF1A SVREF1B SVREF2A SVREF2B SysClk SysErr SysReset TestEn TherMonA TherMonB TmrClk [TrcBS0]GPIO49 [TrcBS1]GPIO50 [TrcBS2]GPIO51 TrcClk [TrcES0]GPIO52 [TrcES1]GPIO53 [TrcES2]GPIO54 [TrcES3]GPIO55 [TrcES4]GPIO56 [TrcTS0]GPIO57 [TrcTS1]GPIO58 [TrcTS2]GPIO59 [TrcTS3]GPIO60 [TrcTS4]GPIO61 [TrcTS5]GPIO62 [TrcTS6]GPIO63 TRST AL10 SDRAM AF04 AL19 AP23 AD32 AD31 System AE34 AE32 AE33 AG32 AE31 AF34 AF33 AF32 AF31 AG34 AG31 AH33 AH34 AH32 AJ34 AH31 JTAG Trace Trace Trace Trace System JTAG System System System JTAG JTAG JTAG System Ball Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [UART0_DTR/UART1_Tx]GPIO38 [UART0_RI/UART1_Rx]GPIO39 UART0_Rx UARTSerClk UART0_Tx UART Peripheral Ball Interface Group Page
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Power Ball Interface Group Page
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440GRx PPC440GRx Embedded Processor
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball AA05 AA16 AA19 AA30 AB05 AB16 AB19 AB30 AC05 AC30 AD05 Power AD30 AK11 AK12 AK13 AK14 AK15 AK20 AK21 AK22 AK23 AK24 AJ02 SDRAM Interface Group Page
Signals Ball Assignment Order following table, only primary (default) signal name shown each ball. Multiplexed multifunction signals marked with asterisk (*). determine what other signals functions those balls, look primary signal name Table page
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
GPIO27* Reserved TRST PerClk GPIO10* GPIO09* PerData13 PerData08 PerData06 PerData02 PerR/W PerWBE0 GPIO13* GPIO22* GPIO14* PerAddr28 PSROOut PerAddr22 PerAddr18 PerAddr15 PerAddr13 PerAddr08 GPIO03* UARTSerClk GPIO36* PCIAD01 PCIAD03
Signal Name
Ball
Signal Name
Ball
Signal Name
PerData17 GPIO29* GPIO28* GPIO11* LeakTest2 TestEn PerData15 PerData11 PerData07 PerData04 PerData00 PerWBE2 TherMonA PerReady PerAddr30 PerAddr27 PerAddr24 PerAddr20 PerAddr17 PerAddr14 PerAddr09 GPIO01* GPIO05* UART0_Rx* GPIO34* GPIO35* PCIAD02
Ball
Signal Name
PerData20 PerData18 ExtReset HoldReq* GPIO08* GPIO07* PerCS0* PerData12 PerData09 PerData05 PerData01 PerWBE3 TherMonB GPIO12* PerAddr29 PerAddr26 PerAddr23 PerAddr19 PerAddr16 PerAddr12 PerAddr10 GPIO02* GPIO04* UART0_Tx* GPIO38* PCIAD00 PCIAD04
OVDD RefEn PerBLast GPIO06* PerData14 PerData10 OVDD PerData03 PerOE PerWBE1 GPIO15* PerAddr31 PerAddr25 PerAddr21 OVDD PerAddr11 GPIO00* GPIO39* GPIO37* OVDD
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
Signal Name
PerData21 OVDD PerData16 PerData19 OVDD OVDD OVDD OVDD OVDD OVDD OVDD Halt* OVDD PCIAD06
Ball
Signal Name
PerData25 PerData24 PerData23 PerData22 OVDD Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball OVDD PCIAD05 PCIAD07 PCIAD08 PCIAD09
Ball
Signal Name
PerData29 PerData28 PerData26 PerData27 OVDD Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball OVDD PCIAD10 PCIC0/BE0 PCIAD11 PCIAD12
Ball
Signal Name
PerData31 PerData30 Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIAD13 PCIAD14 PCIAD15
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
Signal Name
Reserved Reserved OVDD OVDD Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball OVDD PCIC1/BE1 PCIPar PCIPErr PCISErr
Ball
Signal Name
Ball
Signal Name
OVDD OVDD Reserved OVDD Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIAD16 PCIFrame PCIAD17 PCIC2/BE2
Ball
OVDD
Signal Name
GPIO30* Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIAD19 PCIAD18 OVDD PCIAD20
Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIStop PCIDevSel PCIIRDY PCITRDY
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
Reserved Reserved Ball Ball Ball Ball Ball Ball Ball OVDD OVDD Ball Ball Ball Ball Ball Ball Ball PCIAD21 PCIAD23 PCIAD22 PCIC3/BE3
Signal Name
Ball
Signal Name
HoldPri* TmrClk GPIO31* Ball Ball Ball Ball Ball Ball Ball OVDD OVDD Ball Ball Ball Ball Ball Ball Ball PCIAD24 PCIAD26 PCIAD25 PCIAD27
Ball
Signal Name
MemData59 DrvrInh1 GPIO32* GPIO33* Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIAD28 PCIAD29 PCIAD30 PCIAD31
Ball
Signal Name
MemData62 MemData63 MemData58 Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIIDSel GPIO48* GPIO47*
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
Signal Name
MemData56 MemData57 DQS7 Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball OVDD PCIReq1 GPIO46* GPIO45* GPIO43*
Ball
Signal Name
MemData61 MemData60 MemData51 MemData50 SOVDD Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIReq3 GPIO44* PCIReq2 PCIReq0/Gnt
Ball
Signal Name
MemData55 MemData54 DQS6 Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIReq5 PCIReq4 IRQ5*
Ball
Signal Name
MemData49 MemData48 SVREF1A Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball PCIGnt3 PCIGnt2 PCIGnt1 PCIGnt0/Req
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34
Signal Name
MemData53 MemData52 MemData43 MemData42 Ball Ball Ball Ball Ball Ball Ball SOVDD EOVDD Ball Ball Ball Ball Ball Ball Ball PCIReset PCIClk PCIGnt4 PCIGnt5
Ball
AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34
Signal Name
MemData46 MemData47 DQS5 Ball Ball Ball Ball Ball Ball Ball SOVDD EOVDD Ball Ball Ball Ball Ball Ball Ball GPIO23* IIC0SClk GPIO26* PCIINT
Ball
AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34
Signal Name
MemData41 SOVDD MemData40 MemData45 Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball GPIO41* SCPDI* EOVDD SCPClkOut*
Ball
AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34
Signal Name
MemData44 MemData35 MemData34 Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball SysReset SysErr GPIO40* GPIO42*
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34
Signal Name
MemData39 MemData38 DQS4 Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball GPIO52* GPIO50* GPIO51* GPIO49*
Ball
AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34
Signal Name
MemData33 MemData37 MemData32 SVREF2A SOVDD Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball EOVDD GPIO56* GPIO55* GPIO54* GPIO53*
Ball
AG01 AG02 AG03 AG04 AG05 AG06 AG07 AG08 AG09 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34
Signal Name
MemODT1 MemData36 MemAddr13 Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball GPIO58* TrcClk GPIO57*
Ball
AH01 AH02 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34
Signal Name
BankSel1 BankSel0 MemODT0 SOVDD Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball EOVDD GPIO63* GPIO61* GPIO59* GPIO60*
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440GRx PPC440GRx Embedded Processor
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
AJ01 AJ02 AJ03 AJ04 AJ05 AJ06 AJ07 AJ08 AJ09 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 SOVDD Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball Ball EOVDD GMCRxDV* GMCCD* GMCRefClk* GPIO62*
Signal Name
Ball
AK01 AK02 AK03 AK04 AK05 AK06 AK07 AK08 AK09 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34
Signal Name
MemClkOut SOVDD SOVDD SOVDD SOVDD SOVDD EOVDD EOVDD EOVDD GMCCrs* EOVDD GMCMDIO
Ball
AL01 AL02 AL03 AL04 AL05 AL06 AL07 AL08 AL09 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34
Signal Name
MemClkOut MemAddr10 MemAddr06 MemAddr11 ECC3 SVREF1B ECC1 MemData27 MemData30 MemData18 DQS2 MemData20 MemData09 SVREF2B MemData03 MemData04 GPIO21* GMCTxD0* GPIO25* GPIO17* GMCTxClk* GMCRxD0* GMCRxEr* GMCMDClk
Ball
AM01 AM02 AM03 AM04 AM05 AM06 AM07 AM08 AM09 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34
Signal Name
MemAddr00 MemAddr03 MemAddr08 MemAddr12 ECC2 ECC6 ECC0 MemData31 DQS3 MemData28 MemData23 MemData16 MemData21 DQS1 MemData02 DQS0 MemData05 GPIO20* GMCTxEr* GPIO24* GPIO19* GMCGTxClk* GMCRxD2* GMCRxD4* GMCRxD7*
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball
AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 SOVDD MemAddr05 MemAddr07 ClkEn ECC5 SOVDD MemData25 MemData29 MemData22 MemData10 MemData14 MemData12 MemData06 MemData00 EOVDD GMCTxEn* GMCTxD1* GPIO18* GMCRxClk* GMCRxD3* EOVDD
Signal Name
Ball
AP01 AP02 AP03 AP04 AP05 AP06 AP07 AP08 AP09 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34
Signal Name
Ball
Signal Name
Ball
Signal Name
MemAddr01 MemAddr02 MemAddr04 MemAddr09 ECC7 DQS8 ECC4 MemData26 MemData24 MemData19 MemData17 MemData11 MemData15 MemData13 MemData08 MemData07 MemData01 SysClk AVDD AGND GPIO16* EAGND EAVDD GMCRxD1* GMCRxD5* GMCRxD6*
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Preliminary Data Sheet
Signal Descriptions
PPC440GRx embedded controller packaged 456-ball enhanced plastic ball grid array (E-PBGA). following tables describe package level pinout. Table Summary
Group
Signal pins, non-multiplexed Signal pins, multiplexed Total Signal Pins AVDD AGND EAVDD EAGND OVDD SOVDD EOVDD Total Power Pins Reserved Total Pins
Pins
Table page each signal listed along with short description function. Active-low signals (for example, RAS) marked with overline. Please Table page (ball) number which each signal assigned. Multiplexed Signals Some signals multiplexed same that used different functions. most cases, signal names shown this table accompanied signal names that multiplexed same pin. need know what, any, signals multiplexed with particular signal, look name Table page expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible.
Note: Signals multiplexed with GPIO default GPIO receivers float after reset. Initialization software must configure GPIO registers desired function described GPIO chapter user's manual. these signals requiring particular state prior running initialization code must terminated pull pull downs.
Multipurpose Signals addition multiplexing, some pins also multi-purpose. example, peripheral controller address pins (PerAddr) used outputs PPC440GRx broadcast address external slave devices when PPC440GRx control external bus. When during normal operation external master gains ownership external bus, these same pins used inputs which driven external master received PPC440GRx. this example, pins also bidirectional, serving both inputs outputs.
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Multimode Signals some cases (for example, Ethernet) function vary with different modes operation. When multiple signal names assigned distinguish different modes operation, names shown. Strapping Pins group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 86). Note that these multiplexed pins since function pins programmable. Reserved Pins pins classified Reserved functional must connected shown Table
Table Reserved Connections
Connection Open Open OVDD
Unused I/Os Termination unused receivers generally required; however, there some exceptions that reduce eliminate need termination. Signals Multiplexed with GPIO: default after reset, signals shared with GPIO pins configured GPIO receivers. Termination however, needed GPIO during initialization configured outputs. configure drivers, clear appropriate bits GPIOx_ODR, GPIOx_TCR GPIOx_OR registers described GPIO chapter user's manual. PCI: When bridge unused, configure controller park pulling PCIReq0[Gnt] signal low. Parking forces PLB3 bridge actively drive PCIAD31:0 PCIC3:0[BE3:0]. remaining control signals must terminated follows: Disable internal arbiter enable sychronous mode (See Boot Strap Chapter User's Manual).
Note: Synchronous mode supported when operating bus. This mode should only used terminating unused interface).
Individually connect PCISErr, PCIPErr, PCITRDY, PCISTOP through resistors +3.3V. Individually connect PCIReq1:5 through resistors +3.3V. Connect PCIReq0[Gnt] through resistor GND. DDR: mode, termination needed upper data, strobe mask signals when controller configured mode, SDR0_DDRCFG[64B32B]=0 DDR0_14[REDUC=1. Termination unused signals (ECC0:7, DM8, DQS8) needed.
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Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value OVDD (EOVDD Ethernet) Must pull down (recommended value used, must pull (recommended value OVDD (EOVDD Ethernet) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Interface PCIAD00:31 PCIC0:3/BE0:3 PCIClk PCIDevSel Address/Data (bidirectional). Command/Byte Enables. Provides timing interface transactions. Indicates driving device decoded address target current access. (PCI specification requires 8.2k pull host system). Driven current master indicate beginning duration access. (PCI specification requires 8.2k pull host system). Indicates that specified agent granted access bus. When internal arbiter enabled, output PCIGnt0. When internal arbiter disabled, output Req. Indicates that specified agent granted access bus. Used only when internal arbiter enabled. Used chip select during configuration read write transactions. Level sensitive interrupt. Indicates initiating agent's ability complete current data phase transaction. (PCI specification requires 8.2k pull host system). Even parity. Reports data parity errors during transactions except Special Cycle. (PCI specification requires 8.2k pull host system). Indicates arbiter that specified agent wishes bus. When internal arbiter enabled, input PCIReq0. When internal arbiter disabled, input Gnt. indication arbiter that specified agent wishes bus. Used only when internal arbiter enabled. Brings device registers logic consistent state. Reports address parity errors, data parity errors Special Cycle command, other catastrophic system errors. (PCI specification requires 8.2k pull host system). Indicates current target requesting master stop current transaction. (PCI specification requires 8.2k pull host system). 3.3V 3.3V 3.3V 3.3V Description Type
Notes
PCIFrame
3.3V
PCIGnt0/Req
3.3V
PCIGnt1:5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
PCIReq0/Gnt
3.3V
PCIReq1:5 PCIReset PCISErr
3.3V 3.3V 3.3V
PCIStop
3.3V
PCITRDY
Indicates target agent's ability complete current data phase transaction. (PCI specification requires 8.2k pull host system).
3.3V
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value OVDD (EOVDD Ethernet) Must pull down (recommended value used, must pull (recommended value OVDD (EOVDD Ethernet) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name DDR2/1 SDRAM Interface BA0:2 BankSel0:1 ClkEn DM0:7 DQS0:7 DQS8 ECC0:7 MemAddr00:13 MemData00:63 MemClkOut MemClkOut MemODT0:1 SVREF1A:B SVREF2A:B Bank Address supporting eight internal banks. Selects external SDRAM banks. Column Address Strobe. Clock Enable. Memory write data byte lane masks. byte lane mask byte lane. Byte lane data strobe. Byte lane data strobe ECC. check bits 0:7. Memory address bus. Memory data (MemData32:63 available DDR2 only). 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR Diff driver 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR 2.5V (1.8V) SDRAM-DDR Volt receiver (1.25V 0.9V) Volt driver (1.25V 0.9V) Description Type
Notes
Subsystem clock.
DDR2 On-die termination enable (not used with DDR1). Address Strobe. Write Enable. SDRAM reference voltage input. SDRAM reference voltage input.
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value OVDD (EOVDD Ethernet) Must pull down (recommended value used, must pull (recommended value OVDD (EOVDD Ethernet) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Ethernet Interface GMCRxD0:1, GMC0RxD0:1, SMII0:1RxD GMCRxD2:3, GMC0RxD2:3 GMCRxD4:7, GMC1RxD0:3 GMCTxD0:1, GMC0TxD0:1, SMII0:1TxD GMCTxD2:3, GMC0TxD2:3 GMCTxD4:7, GMC1TxD0:3 GMCRxEr, GMC1RxCtl GMCRxClk, GMC0RxClk, SMIISync GMCRxDV, GMC0RxCtl GMCCrs, GMC1TxClk GMCTxEr, GMC1TxCtl GMCTxEn, GMC0TxCtl GMCTxClk GMCCD, GMC1RxClk GMCMDClk GMCMDIO GMCGTxClk, GMC0TxClk GMCRefClk, SMIIRefClk RejectPkt0:1 GMII/MII: Receive data. RGMII Receive data. SMII 0:1: Receive data. GMII/MII: Receive data. RGMII Receive data. GMII/MII: Receive data. RGMII Receive data GMII/MII: Transmit data. RGMII Transmit data. SMII 0:1: Transmit data. GMII/MII: Transmit data. RGMII Transmit data. GMII/MII: Transmit data. RGMII Transmit data. GMII/MII: Receive error. RGMII Receive control. GMII/MII: Receive clock. RGMII Receive clock. SMII: Synchronizing signal. GMII/MII: Receive data valid. RGMII Receive control. GMII/MII: Carrier sense. RGMII Transmit clock. GMII/MII: Transmit error. RGMII Transmit control. GMII/MII: Transmit enable. RGMII Transmit control. MII: Transmit clock MII. GMII/MII: Collision detect. Management data clock Management data GMII: Transmit clock GMII. RGMII Transmit clock. GMII, RGMII: Reference clock. SMII: Reference clock. External request reject packet. 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS Rcvr 3.3V tolerant 2.5V CMOS Description Type
Notes
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value OVDD (EOVDD Ethernet) Must pull down (recommended value used, must pull (recommended value OVDD (EOVDD Ethernet) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name External Slave Peripheral Interface DMAAck0:3 DMAReq0 DMAReq1 DMAReq2:3 EOT0:3/TC0:3 PerAddr02:07 PerAddr08:31 Used PPC440GRx indicate that data transfers have occurred. Used slave peripherals indicate they prepared transfer data. Used slave peripherals indicate they prepared transfer data. Used slave peripherals indicate they prepared transfer data. Transfer/Terminal Count. Peripheral address used PPC440GRx when external master mode; otherwise, used external master. Peripheral address used PPC440GRx when external master mode; otherwise, used external master. Peripheral data used PPC440GRx when external master mode; otherwise, used external master. Note: PerData00 most significant (msb) this bus. Peripheral data parity used PPC440GRx when external master mode; otherwise, used external master. Used either peripheral controller, controller, external master indicates last transfer memory access. External peripheral device select. External peripheral device select. Used either peripheral controller controller depending upon type transfer involved. When PPC440GRx master, enables selected device drive bus. Used peripheral slave indicate ready transfer data. Used PPC440GRx when external master mode, output either peripheral controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. Otherwise, used external master input indicate direction transfer. External peripheral data byte enables. External Error. Used input record external slave peripheral errors. 3.3V LVTTL 3.3V LVTTL 3.3VLVTTL 3.3VLVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Description Type
Notes
PerData00:31
3.3V LVTTL
PerDataPar0:3
3.3V LVTTL
PerBLast PerCS0 PerCS1:5
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
PerOE
3.3V LVTTL
PerReady
3.3V LVTTL
PerR/W
3.3V LVTTL
PerWBE0:3 PerErr
3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value OVDD (EOVDD Ethernet) Must pull down (recommended value used, must pull (recommended value OVDD (EOVDD Ethernet) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name External Master Peripheral Interface BusReq ExtAck ExtReq Request. Used when PPC440GRx needs regain control peripheral interface from external master. External Acknowledgement. Used PPC440GRx indicate that data transfer occurred. External Request. Used external master indicate prepared transfer data. Peripheral Reset. Used external master synchronous peripheral slaves. Note: state signals clocks cannot guaranteed until ExtReset signal been de-asserted. Hold Acknowledge. Used PPC440GRx transfer ownership peripheral external master. Hold Request. Used external master request ownership peripheral bus. Hold Primary. Used external master indicate priority given external master tenure. Peripheral Clock. Used external master synchronous peripheral slaves. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Description Type
Notes
ExtReset
3.3V LVTTL
HoldAck HoldReq HoldPri PerClk
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL
UART Peripheral Interface UART interface configured follows: 8-pin, where 4-pin, where 4-pin, where 2-pin, where Four 2-pin, where UARTSerClk SerClk input provides alternative internally generated serial clock. used cases where allowable internally generated clock rates satisfactory. Receive data. Transmit data. Data Carrier Detect. Data Ready. Clear Send. Data Terminal Ready. Request Send. Ring Indicator. 3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RTS UARTn_RI Peripheral Interface IIC0SClk IIC0SData IIC1SClk IIC1SData
IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data.
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value OVDD (EOVDD Ethernet) Must pull down (recommended value used, must pull (recommended value OVDD (EOVDD Ethernet) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name NAND Flash Interface NFALE NFCE0:3 NFCLE Address Latch Enable. Chip Enable (multiplexed with PerCS0:3 signals). Command Latch Enable. Latches operational commands into NAND Flash. Ready/Busy. Indicates status device during program erase page read. This signal wire-OR connected from NAND Flash devices. Read Enable. Data latched rising edge. Write Enable. Data latched rising edge. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Description Type
Notes
NFRdyBusy
3.3V LVTTL
NFREn NFWEn Serial Peripheral Interface SCPClkOut SCPDI SCPDO Interrupts Interface IRQ0:4 IRQ5 IRQ6:9 JTAG Interface TRST
3.3V LVTTL 3.3V LVTTL
Clock output. Data input. Data output.
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External interrupt requests through External interrupt request External interrupt requests through
3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL
Test Clock. Test Data Test Data Out. Test Mode Select. Test Reset.
3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value OVDD (EOVDD Ethernet) Must pull down (recommended value used, must pull (recommended value OVDD (EOVDD Ethernet) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name System Interface SysClk SysErr Main system clock input. when machine check generated. Main system reset. External logic drive this bidirectional (minimum cycles) initiate system reset. system reset also initiated software. Implemented open-drain output (two states; open circuit). Halt from external debugger. Processor timer external input clock. General purpose I/O. access these functions, software must register bits. General purpose I/O. access these functions, software must register bits. General purpose I/O. access these functions, software must register bits. Test Enable. Note: connect normal operation. Receiver Inhibit. Active only when TestEn active. Used manufacturing test only. Mode Control. Active only when TestEn active. Used manufacturing test only. Leakage Test. Active only when TestEn active. Used manufacturing test only. Reference Enable. Active only when TestEn active. Used manufacturing test only. Driver Inhibit. Active only when TestEn active. Used manufacturing test only. specified Note normal operation. On-chip thermal monitor transistor. emitter base. collector grounded. Module characterization screening. test purposes only. down specified Note normal operation. 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V LVTTL Rcvr w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V LVTTL Rcvr w/pulldown 3.3V LVTTL 3.3V tolerant 2.5V CMOS Rcvr 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up Thermal monitor Perf screen ring Description Type
Notes
SysReset
Halt TmrClk GPIO00:15 GPIO22:23 GPIO26:48 GPIO16:21 GPIO24:25 GPIO49:63
TestEn
RcvrInh
ModeCtrl LeakTest LeakTest2 RefEn
DrvrInh1:2
TherMonA:B PSROOut
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value OVDD (EOVDD Ethernet) Must pull down (recommended value used, must pull (recommended value OVDD (EOVDD Ethernet) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Trace Interface TrcBS0:2 TrcClk TrcES0:4 TrcTS0:6 Power OVDD EOVDD SOVDD AVDD AGND EAVDD EAGND Reserved Reserved avoid noise pickup, balls this chip classified Reserved must connected shown Table page +1.5V-Logic voltage. +3.3V-I/O (except DDR2 SDRAM Ethernet). +2.5V-I/O Ethernet. +1.8V (DDR2) +2.5V (DDR1)-I/O SDRAM. Ground logic voltage. +1.5V-Filtered voltage system PLLs (analog). Ground system voltage (analog). +1.5V-Filtered voltage Ethernet PLLs (analog). Ground Ethernet voltage (analog). Trace branch execution status. Trace data capture clock, runs frequency processor. Trace Execution Status presented every fourth processor clock cycle. Additional information trace execution branch status. 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS Description Type
Notes
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Device Characteristics
Table Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device. None performance specification contained this document guaranteed when operating these maximum ratings.
Characteristic Internal logic supply voltage supply voltage Ethernet supply voltage DDR2 (DDR1) SDRAM supply voltage System analog supply voltage Ethernet analog supply voltage Storage Temperature Range Case temperature under bias Notes: OVDD 0.4V, required that 0.4V. Supply excursions meeting this criteria must limited less than 25ms duration during each power power down event. This value specification operational temperature range, stress rating only. Symbol OVDD EOVDD SOVDD AVDD EAVDD TSTG Value +1.65 +3.6 +2.7 +1.94 (+2.7V) +1.65 +1.65 +150 +120 Unit Notes
Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Supply Voltage Ethernet Supply Voltage DDR2 (DDR1) SDRAM Supply Voltage System Analog Supply Voltages Ethernet Analog Voltage DDR2 (DDR1) SDRAM Reference Voltage Input Logic High 3.3V Input Logic High 3.3V LVTTL Input Logic High 2.5V CMOS, 3.3V tolerant Input Logic High 1.8V DDR2 (2.5V DDR1)
Symbol OVDD EOVDD SOVDD AVDD EAVDD SVREF
Minimum +1.425 +3.15 +2.4 +1.7 (+2.4) +1.425 +1.425 +0.85 (+1.19) 0.5OVDD +2.0
Typical +1.5 +3.3 +2.5 +1.8 (+2.5) +1.5 +1.5 +0.9 (+1.25)
Maximum +1.6 +3.45 +2.6 +1.9 (+2.6) +1.6 +1.6 +0.95 (+1.31) OVDD+0.5 +3.6 +3.6 (3.0)
Unit
Notes
+1.7 SVREF 0.125 (0.15)
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Input Logic 3.3V Input Logic 3.3V LVTTL Input Logic 2.5V CMOS Input Logic 1.8V DDR2 (2.5V DDR1) Output Logic High 3.3V Output Logic High 3.3V LVTTL
Symbol
Minimum -0.5
Typical
Maximum 0.35OVDD +0.8 +0.7 SVREF 0.125 (0.15) +3.6 +2.7 +1.95 (+2.7) 0.1OVDD +0.4 +0.4 +0.43 (+0.54) (MPUL) (MPUL) +3.9
Unit
Notes
-0.3 (-0.3) 0.9OVDD +2.4
Output Logic High 2.5V CMOS Output Logic High 1.8V DDR2 (2.5V DDR1) Output Logic 3.3V Output Logic 3.3V LVTTL Output Logic 2.5V CMOS Output Logic 1.8V DDR2 (2.5V DDR1) Input Leakage Current pull-up pull-down) Input Leakage Current pull-down Input Leakage Current pull-up Input Allowable Overshoot 3.3V LVTTL Input Allowable Undershoot 3.3V LVTTL Output Allowable Overshoot 3.3V LVTTL Output Allowable Undershoot 3.3V LVTTL Case Temperature Notes: drivers meet specifications. SVREF SOVDD/2. SOVDD +1.8V DDR2 memory +2.5V DDR1 memory. analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440GRx. "Absolute Maximum Ratings" page Startup sequencing power supply voltages required. power-down cycle must complete (OVDD below +0.4V) before power-up cycle started IOL= 10ma. Case temperature, measured center case surface with device soldered circuit board. IIL1 IIL2 IIL3 VIMAO VIMAU VOMAO VOMAU3 -0.6 +100 -0.6 +3.9 (LPDL) -150 (LPDL) +2.0 +0.95 (+1.7)
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Input Capacitance
Parameter 2.5V/1.8V 3.3V LVTTL 3.3V tolerant CMOS Symbol CIN1 CIN2 CIN3 CIN5 Maximum Unit Notes
Figure Overshoot Waveform
Overshoot Overshoot
TCYC
Undershoot Undershoot
Table Overshoot Undershoot
Receiver 3.3V LVTTL 2.5V (3.3V tolerant) Overshoot 1.2*SOVDD 1.2*OVDD Overshoot SOVDD OVDD Undershoot -0.16 -0.16 -0.3 -0.5 Undershoot -0.6 -0.6 -0.6 -0.2*OVDD 0.1*TCYC1 0.1*TCYC1 0.1/MemClkOut 0.1/PCIClk
Notes: TCYC period clock. 1/PerClk NAND flash interfaces. 1/GMCRXClk GMII modes 1/SMIIRefClk SMII mode 1/GMCGRXClk RGMII mode 1/TrcClk instruction trace interface 1/IIC0Clk 1/IIC1Clk interfaces 1/SPIClkOut
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Power Sequencing Startup sequencing power supply voltages required. However, power-down cycle must complete (OVDD below +0.4V) before power-up cycle started. Analog Voltage Filter
analog voltages (AVdd EAVdd) used on-chip PLLs derived from logic voltage, must filtered before entering PPC440GRx. Separate filter, shown below, recommended each voltage.
filter should keep analog voltage analog ground compression/expansion noise less than +/50
Keep wire lengths short possible. Analog grounds must brought connected digital ground plane filter capacitor. impedance ferrite bead should much greater than that capacitor frequencies where noise expected.
AVDD, SAVDD ferrite bead chip, Murata BLM21PG600SN1 ceramic AGND, SAGND
Table Typical Power Supply Requirements Using DDR2 Memory
Frequency (MHz) +1.5V Supply (VDD+AVDD+EAVDD) 1.35 1.45 +1.8V Supply (SOVDD) +2.5V Supply (EOVDD) +3.3V Supply (OVDD+UAVDD) Total 3.15 3.25 Unit Notes
Notes: Typical power estimated based nominal voltage +1.5V, 85°C, while running Linux test application that exercises each functiion with representative traffic.
Table Typical Power Supply Requirements Using DDR1 Memory
Frequency (MHz) +1.5V Supply (VDD+AVDD+EAVDD) 1.35 1.45 +1.8V Supply (SOVDD) +2.5V Supply (SOVDD EOVDD) +3.3V Supply (OVDD+UAVDD) Total 3.35 3.45 Unit Notes
Notes: Typical power estimated based nominal voltage +1.5V, 85°C, while running Linux test application that exercises each functiion with representative traffic.
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Supply Power Dissipation
Frequency (MHz) +1.425V 1.25 +1.5V 1.35 1.45 +1.6V 1.55 Unit Notes
Notes: Power estimated based specified table 85°C, while running Linux test application that exercises each function with representative traffic.
Table Power Supply Loads
Parameter (+1.5V) active operating current OVDD (+3.3V) active operating current EOVDD (+2.5V) active operating current SOVDD (+1.8V) DDR2 active operating current SOVDD (+2.5V) DDR1 active operating current AVDD (+1.5V) input current EAVDD (+1.5V) active operating current Notes: "Absolute Maximum Ratings" page filter recommendations. SOVDD will either +2.5V +1.8V, both. maximum current values listed above guaranteed highest obtainable. These values dependent many factors including type applications running, clock rates, internal functional capabilities, external interface usage, case temperature, power supply voltages. Your specific application produce significantly different results. (logic) current power primarily dependent applications running internal chip functions (DMA, PCI, Ethernet, on). OVDD (I/O) current power primarily dependent capacitive loading, frequency, utilization external buses. Typical current estimated 667MHz with +1.5V, OVDD +3.3V, EOVDD +2.5V, SOVDD +2.5V (DDR1) +1.8V (DDR2), +85°C. Maximum current estimated 667MHz with +1.6V, OVDD +3.45V, EOVDD +2.6V, SOVDD +2.6V (DDR1) +1.9V (DDR2), +100°C, best-case process (which drives worst-case power). Symbol IODD IEODD ISODD2 ISODD1 IADD IEADD Typical 1600 Maximum 2900 Unit Notes
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Package Thermal Specifications
Thermal resistance values TE-PBGA package convection environment 6.3W follows:
Airflow ft/min (m/sec) Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink (0.51) 11.7 (1.02) 10.9 (1.53 10.5 (2.04) 10.3 (2.55) °C/W °C/W
Parameter
Symbol
Unit
Notes
13.1 11.1
Resistance Value Junction-to-case thermal resistance Junction-to-board thermal resistance Notes: Case temperature, measured center case surface with device soldered circuit board. where ambient temperature power consumption.
°C/W °C/W
TCMax TJMax where TJMax maximum junction temperature (+125°C) power consumption. preceding equations assume that chip mounted board with least signal power planes. Values table were achieved using JEDEC standard board with following characteristics: 114.5mm 101.6mm 1.6mm, layers. board thermal vias (same number thermal balls TE-PBGA package). Values attached heat sink were achieved with 35mm 35mm 15mm unit (see Thermal Management below), attached with 0.1mm thickness adhesive having thermal conductivity 1.3W/mK.
Thermal Management following heat sink used above thermal analysis: ALPHA LPD35-15B (35mm 35mm x15mm) heat sink manufactured Alpha Novatech, Inc. (www.alphanovatech.com) Sapena Court, Santa Clara, 95054 Phone: 408-567-8082
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Thermal Monitor Thermal monitoring chip accomplished using transistor provided chip. collector transistor connected ground (GND). emitter (TherMonA) base (TherMonB) connected chip pins. voltage measurement (VBE1 VBE2) across TherMonA TherMonB pins current values provides chip temperature according equation: (q/nk)(VBE2-VBE1)/ln(I2/I1) where 1.602 0.015, 1.380
Note: VBE2 VBE1 should specified Volts. units measure provided they same. small values require precision measurement current sources.
PPC440GRx TherMonB Note: bias voltage should between +0.5V +0.7V. TherMonA (Max 300A) VBE1, VBE2
Test Conditions Clock timing switching characteristics specified accordance with operating conditions shown table Table page specifications characterized with +1.5V, 50pF test load shown figure right.
Output 50pF
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Clocking Specifications
Symbol SysClk Input Frequency Period Edge stability (cycle-to-cycle jitter) High time time 33.33 nominal period nominal period 66.66 ±0.15 nominal period nominal period Parameter Units Notes
Note: Input slew rate 1V/ns Frequency Period 0.750 1333.33 1.66
Processor (CPU) Clock Frequency Period 333.33 666.66
MemClkOut Clock Clock Notes: maximum supported processor clock frequency part specified part number (see "Ordering Information" page Frequency Period 83.33 22.2 Frequency Period High time 133.33 nominal period 166.66 nominal period
Figure Timing Waveform
1.7V (2.0V)
0.7V (0.8V)
Note:
SysClk GMCRefClk 2.5V (3.3V tolerant). Slew rate should measured between 0.7V 1.7V.
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Spread Spectrum Clocking
Care must taken when using spread spectrum clock generator (SSCG) with PPC440GRx. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC440GRx following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC440GRx with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board PPC440GRx peripherals impose more stringent requirements. Peripheral Clock logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. Ethernet operation unaffected. operation unaffected. Important: system designer ensure that SSCG used with PPC440GRx meets above requirements does adversely affect other aspects system.
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Specifications
Table Peripheral Interface Clock Timings
Parameter PCIClk frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk high time PCIClk time GMCMDClk frequency GMCMDClk period GMCMDClk high time GMCMDClk time GMCTxClk frequency GMCTxClk period GMCTxClk high time GMCTxClk time GMCRxClk frequency GMCRxClk period GMCRxClk high time GMCRxClk time GMCRefClk frequency GMCRefClk period GMCRefClk high time GMCRefClk time PerClk (and Clock) frequency (for ext. master sync. slaves) GMCRefClk Edge stability (cycle-to-cycle jitter) GMCRefClk Slew Rate PerClk period PerClk high time PerClk time UARTSerClk frequency UARTSerClk period UARTSerClk high time UARTSerClk time nominal period nominal period nominal period nominal period nominal period nominal period nominal period nominal period 33.33MHz nominal period nominal period 2TOPB1+2 TOPB1+1 TOPB1+1 66.66 nominal period nominal period nominal period nominal period 83.33 +0.15 nominal period nominal period 1000 (2TOPB1+2ns) Units V/ns Notes
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Peripheral Interface Clock Timings (continued)
Parameter TmrClk frequency TmrClk period TmrClk high time TmrClk time Notes: TOPB period clock. internal clock runs frequency clock. maximum clock frequency MHz. internal improves this duty cycle worst case minimum, maximum. nominal period nominal period nominal period nominal period Units Notes
Figure Input Setup Hold Waveform
Clock 1.25V(1.5V) Inputs Valid
Figure Output Delay Float Timing Waveform
Clock 1.25V(1.5V)
Outputs
High (Drive) Float (High-Z) (Drive) Valid Valid
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Figure Input Setup Hold Waveform RGMII Signals
GMCnRxClk
1.25V
Inputs Valid Valid
RGMII 1000Mb timing with reference raising falling edge GMCnRxClk. RGMII 10/100Mb timing with reference only raising edge GMCnRxClk.
Figure Output Delay Hold Timing Waveform RGMII Signals
GMCnTxClk
1.25V
Outputs High (Drive) Float (High-Z) (Drive) Valid Valid Valid
Valid
RGMII 1000Mb timing with reference raising falling edge GMCnTxClk. RGMII 10/100Mb timing with reference only raising edge GMCnTxClk.
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440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal Interface PCIAD31:00 PCIC3:0/BE3:0 PCIClk PCIDevSel PCIFrame PCIGnt0:5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0:5 PCIReset PCISErr PCIStop PCITRDY Ethernet Interface GMCCD GMCCrs GMCMDClk GMCMDIO GMCRxClk GMCRxD0:3 GMCTxD0:3 GMCRxDV GMCRxEr GMCTxClk GMCTxEr GMCTxEn Ethernet GMII Interface GMCCD GMCCrs GMCGTxClk GMCMDClk GMCMDIO GMCRefClk GMCRxClk GMCRxD0:7 GMCTxD0:7 GMCRxDV GMCRXEr GMCTxEr GMCTxEn GMCRxClk GMCGTxClk GMCRxClk GMCRxClk GMCGTxClk GMCGTxClk GMCMDClk async async GMCTxClk GMCTxClk GMCRxClk GMCTxClk GMCRxClk GMCRxClk GMCMDClk async async PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk async PCIClk PCIClk PCIClk PCIClk async PCIClk PCIClk async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 27.7 27.7 27.7 27.7 27.7 27.7 15.3 19.1 19.1 19.1 19.1 (minimum) 12.8 12.8 12.8 12.8 12.8 12.8 10.2 async async async async async SMIIRefClk SMIIRefClk SMIIRefClk SMIIRefClk SMIIRefClk GMC1RxClk GMC1RxClk GMC1TxClk GMC1TxClk GMC0RxClk GMC0RxClk GMC0TxClk GMC0TxClk Clock Notes
Ethernet RGMII Interface GMC0RxClk GMC0TxClk GMC0RxD0:3 GMC0RxCtl GMC0TxD0:3 GMC0TxCtl GMC1RxClk GMC1TxClk GMC1RxD0:3 GMC1RxCtl GMC1TxD0:3 GMC1TxCtl GMCRefClk Ethernet SMII Interface SMIIRefClk SMIISync SMII0RxD SMII1RxD SMII0TxD SMII1TxD Internal Peripheral Interface IIC0SClk IIC0SData IIC1SClk IIC1SData SCPClkOut SCPDI SCPDO UARTSerClk UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RI UARTn_RTS Interrupts Interface IRQ0:9 JTAG Interface TRST
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal System Interface SysClk TmrClk SysReset Halt SysErr TestEn DrvrInh1:2 RcvrInh GPIO00:11 GPIO12:25 GPIO26:48 GPIO49:63 Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6 19.1 14.6 async async async async async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Specifications-400MHz 667MHz
Notes: PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 19.1 19.1 19.1 19.1 19.1 19.1 14.6 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 (minimum) PerClk PerClk PerClk PerClk PerClk PerClk PerClk Clock Notes
External Slave Peripheral Interface DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr02:31 PerBLast PerCS0:5 PerData00:15 PerData16:31 PerOE PerReady PerR/W PerWBE0:1 BusReq ExtAck ExtReq ExtReset HoldAck HoldReq HoldPri PerClk PerErr NAND Flash Interface NFALE NFCE0:3 NFCLE NFRdyBusy NFREn NFWEn PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
External Master Peripheral Interface
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440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
DDR2/1 SDRAM Specifications
DDR2/1 SDRAM controller times operation with internal clock signal generates MemClkOut from clock. clock internal signal that cannot directly observed. However MemClkOut same frequency clock signal phase with clock signal. Read capture logic controller captures read data using delayed version internally resynchronizes data clock.The PPC440GRx contains three independently programmable digital delay lines (DLLs) that control timing indicated signals read write operations: (with respect MemClkOut) write operations. MemData, ECC, (with respect MemClkOut) write operations. (with respect inbound MemData) read operations. There also master delay line calibration. Programming details found PPC440GRx Embedded Processor Users Manual. signals terminated indicated Figure timing data following sections. PPC440GRx uses clock forwarding scheme which drives clock memory devices. Data signals divided into eight subgroups-one each byte lane (see Table page 85)- plus ninth subgroup byte lane. These signals include MemData00:63, DQS0:8, DM0:8, ECC0:7 signals. Signals within data subgroup (byte lane) should routed together. Command Operation command (MemAddr, RAS, CAS, ClkEn, BankSel, MemODT) driven 180° out-of-phase with MemClkOut, corresponding delay line. Therefore, board designers must consider different types systems: registered DIMMs unbuffered DIMMs. system clocking design must also considered. avoid crosstalk, command signals data signals should routed together. Board Layout Restrictions paths (traces) data associated data strobe signal should routed with same length between PPC440GRx SDRAM devices, allowing rising falling edges strobe arrive capture logic same time data transition. following timing assumes trace velocity 167ps/in. Board designs must meet following criteria: Skew signals byte lane should exceed 50ps (0.3 in). Data subgroup trace lengths must more than 5in. (800ps) have difference more than 2.5in. (400ps). Byte lane subgroup trace length must less than 1.25 (209ps). example, traces that average 3.00in. length 167ps/in., meet maximum 50ps skew requirement, would have maximum length difference 0.3in. they would between 2.85in. 3.15in. length. above timing recommendations followed, package wire bond lengths ignored. Clocking Clocking skew DRAMs must minimized. maximum allowed considered 10ps. Because stringent requirements device clock inputs, expected that board designers will some type external suitable redrive clock SDRAMs. such system, acts like zero-delay insertion buffer.
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440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
When using unbufferred DIMMS, loading address will considerably greater than clock loads double-sided DIMMs). this case, strongly suggested that delay 500ps clock path that Address/Command setup time DIMMs met. This delay sufficient meet setup time, without having change programmable delay (internal PPC440GRx) between DQS/DQ/DM clock (assuming nominal settings specified PPC440GRx Users Manual). While clock 500ps later than nominal arrival time, this still falls well within window allowed JEDEC spec TDQSS 0.25 cycle, 1.5ns 166MHz). case where possible anticipate which kind DIMMs employed system, always safe this 500ps clock delay, since registered DIMMs (the least heavily loaded) will have more than enough margin (almost cycle) accommodate slight decrease address hold time. Termination Model Figure SDRAM Simulation Signal Termination Model
MemClkOut 10pF 10pF MemClkOut SOVDD/2
PPC440GRx
Addr/Ctrl (DDR2) Addr/Ctrl/Data/DQS/DM (DDR1)
30pF
Note: This diagram illustrates model SDRAM interface used when generating simulation timing data. recommended physical circuit design this interface. actual interface design will depend many factors, including type memory used board layout.
DDR2 SDRAM On-Die Termination Impedance Setting DDR2 applications, On-Die Termination (ODT) impedance value must ohms DIMM Extended Mode Register (EMR) order optimize data transmission during memory write operations. Table SDRAM Output Driver Specifications (Sheet
Signal Path Write Data MemData00:63 ECC0:7 DM0:8 MemClkOut MemAddr00:13 BA0:2 Output Current (mA) (maximum) (maximum)
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table SDRAM Output Driver Specifications (Sheet
Signal Path BankSel0:1 ClkEn DQS0:8 MemODT0:1 Output Current (mA) (maximum) (maximum)
SDRAM Write Operation rising edge MemClkOut aligns with first rising edge signal writes. following data generated means simulation includes logic, driver, package RLC, lengths. Values calculated over best case worst case processes with speed, junction temperature, voltage follows: Table SDRAM Write Operation Conditions
Case Best Worst Process Speed Fast Slow Junction Temperature (°C) +125 Voltage +1.6 +1.425
Note: following tables timing diagrams, minimum values measured under best case conditions maximum values measured under worst case conditions. timing numbers following sections obtained using simulation that assumes model shown Figure SDRAM Simulation Signal Termination Model.
AMCC Proprietary
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440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
following diagram illustrates relationship among signals involved with write operation. Figure SDRAM Write Cycle Timing
MemClkOut Addr/Cmd
MemData
Delay from falling edge MemClkOut rising/falling edge signal (skew) Setup time address command signals MemClkOut Hold time address command signals from MemClkOut Setup time data signals (minimum time data valid before rising/falling edge DSQ) Hold time data signals (minimum time data valid after rising/falling edge DSQ) Delay from rising/falling edge clock rising/falling edge
Note: timing data following tables based simulation runs using Einstimer.
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440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Table Timing-DDR SDRAM
Notes: signals referenced MemClkOut with delay line programmed cycle. Clock speed 166MHz.
Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 (ns) Minimum -0.030 -0.030 -0.050 -0.110 -0.140 -0.120 -0.060 -0.010 -0.140 Maximum +0.650 +0.620 +0.580 +0.480 +0.410 +0.480 +0.580 +0.690 +0.420
Table Timing-DDR SDRAM TSK, TSA,
Notes: Clock speed 166MHz. referenced MemClkOut falling edge. referenced MemClkOut rising edge. timing this table assumes single registered DIMM load outputs. adjust timing unbuffered DIMMs, following values subtracting them from adding them THA: loads adjust 0.41ns loads adjust 1.12ns loads adjust 2.12ns obtain adjusted values lower clock frequencies, cycle time lower clock frequency subtract maximum (0.5TCYC TSKmax). obtain adjusted values lower clock frequencies, cycle time lower clock frequency minimum (0.5TCYC TSKmin).
Signal Name MemAddr00:13 BA0:2 BankSel0:1 ClkEn -0.960 -0.270 3.27 2.04 (ns) Minimum Maximum (ns) Minimum (ns) Minimum
AMCC Proprietary
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440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Table Timing-DDR SDRAM
Notes: measured under worst case conditions. Clock speed values table 166MHz. time values table include cycle 166MHz (6ns 0.25 ns). obtain adjusted values lower clock frequencies, subtract from values table cycle time lower clock frequency (for example, 0.25TCYC).
Signal Names MemData00:07, MemData08:15, MemData16:23, MemData24:31, MemData32:39, MemData40:47, MemData48:55, MemData56:63, ECC0:7, Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 (ns) 1.37 1.41 1.40 1.41 1.45 1.40 1.46 1.45 1.46 (ns) 1.23 1.18 1.17 1.20 1.18 1.18 1.17 1.10 1.18
SDRAM Read Operation read data capture logic responsible capturing data outputs from SDRAM devices passing data back system clock domain. data strobe signal (DQS) signals used capture data delayed ensure that rising falling edges these strobes middle valid window data. devices send coincident with read data that data reliably captured PPC440GRx. edges these strobe signals aligned with data output SDRAM devices. order reliably latch data into synchronizing FIFO, PPC440GRx produces internal, delayed version DQS. amount delay user programmable. example shown Figure SDRAM Read Timing, delay approximately system clock. delay compensation circuit PPC440GRx keeps this delay constant. Figure SDRAM Read Timing
MemClkOut MemData Delayed (data strobe) delay
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Initialization
PPC440GRx provides option setting initial parameters based default values reading them from slave PROM attached IIC0 (see "Serial EEPROM" below). Some default values altered strapping external pins (see "Strapping" below).
Strapping
While SysReset input (system reset), state certain pins read enable certain default initial conditions prior PPC440GRx start-up. actual capture instant nearest reference clock edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. These pins used strap functions only during reset. Following reset they used normal functions. signal names assigned pins normal operation shown parentheses following number. Note: When UART0_DCD, UART0_DSR UART0_CTS used functionally, straps should isolated from UART transceiver during reset transceiver overdrive straps cause PPC440GRx read incorrect straps. following table lists strapping pins along with their functions strapping options:
Table Strapping Assignments
Strapping Function Option (UART0_DCD) (UART0_DSR) (UART0_CTS)
Serial device disabled. Each options combination boot source, boot-source width, clock frequency specifications. Refer Bootstrap Controller chapter PPC440GRx Embedded Processor User's Manual details.
Serial device enabled. option being selected IIC0 slave address that will respond with strapping data.
(0xA8) (0xA4)
Serial EEPROM
During reset, initial conditions other than those obtained from strapping pins read from device connected IIC0 port. de-assertion reset, bootstrap controller enabled, PPC440GRx sequentially reads from device IIC0 port sets SDR0_SDSTP0, SDR0_SDSTP1, SDR0_SDSTP2 SDR0_SDSTP3 registers accordingly. initialization settings their default values covered detail PowerPC 440GRx User's Manual.
AMCC Proprietary
Revision 1.08 October 2007
440GRx PPC440GRx Embedded Processor
Preliminary Data Sheet
Revision
Date 04/11/2006 04/24/2006 Version 1.01 1.02 Initial creation document. Correct security designation. new/updated power current values. Correct list containing balls ball number. Update power temperature data. clocking information. Update EEPROM. Change delete incorrect MemClkEn references Correct enable/disable specifications Gnt/Req signals. Change analog voltage filter circuit inductor Part number. Correct designation some Ethernet signals. Remove leaded PNs. Correct descriptions LeakTest, RcvrInh, ModeCtrl, RefEn, DrvrInh1:2 signals. information concerning address loading SDRAMs. Restore leaded PNs. Update DDR2/1 SDRAM timing board design data. Added more information Thermal Monitor section. Changes Figure Added assembly recommendations, Tables Added recommendations Unused I/O. Updated signal description table 9for signals SPCClkOUT, SCPDI, SCPDO, LeakTest LeakTest2. Updated Table include reference clocks. Removed references RTBI these modes supported errata: Chip_4 Chip_5. Added voltage reference Figures Corrected comments UART Ethernet signals Table Removed Note from Table 10and added section Analog Voltage Filter Added Figure Table Overshoot Undershoot. Added section Power Sequencing. Added slew rate jitter requirements GMCRefClk Table Added note Strapping section Changed GPIO26[IIC0SData] [GPIO26]IIC0SData Table Added figures showing setup, hold, output valid output hold timing RGMII signals. Corrected number Corrected phone numbers last page Corrected RGMII timing relative GMCnTXClk Table Added pull recommendations Table signals. Contents Modification
05/30/2006
1.03
11/02/2006
1.04
12/28/2006
1.05
01/10/2007 07/25/2007
1.06 1.07
10/15/2007
1.08
AMCC Proprietary
440GRx PPC440GRx Embedded Processor
Revision 1.08 October 2007
Preliminary Data Sheet
Applied Micro Circuits Corporation Moffett Park Drive, Sunnyvale, 94089 Phone: (408) 542-8600 (800) 840-6055 Fax: (408) 542-8601 http://www.amcc.com
AMCC reserves right make changes products, data sheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available data sheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered Trademark Applied Micro Circuits Corporation. Copyright 2006 Applied Micro Circuits Corporation. Rights Reserved.
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