440EP Power 440EP Embedded Processor PowerPC® processor core
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Part Number 440EP Revision 1.26 April 2007
440EP
Power 440EP Embedded Processor
PowerPC® processor core operating 667MHz with 32KB I-cache D-cache with parity checking. Selectable processor:bus clock ratios N:1, N:2. Floating Point Unit with single- doubleprecision single-cycle throughput. Dual bridged Processor Local Buses (PLBs) with 128-bit widths. Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating 133MHz with ECC. support external peripherals, internal UART memory. V2.2 interface (3.3V only). Thirty-two bits 66MHz. Programmable interrupt controller supports interrupts from variety sources. Programmable General Purpose Timers (GPT).
Data Sheet
Ethernet 10/100Mbps half- full-duplex interfaces. Operational modes supported MII, RMII, SMII with packet reject. four serial ports (16750 compatible UART). ports. Host interface with on-chip PHY. Device interface, with dedicated DMA, configured on-chip UTMI. External peripheral (16-bit data) devices with external mastering. interfaces (one with boot parameter read capability). NAND Flash interface. interface. General Purpose (GPIO) interface. JTAG interface board level testing. Boot from memory, Flash external peripheral bus, NAND Flash NAND Flash interface. Available RoHS compliant lead-free package.
Description
Designed specifically address high-end embedded applications, PowerPC 440EP (PPC440EP) provides high-performance, low- power solution that interfaces wide range peripherals incorporates on-chip power management features. This chip contains high-performance RISC processor, floating point unit, SDRAM controller, interface, control external peripherals, with scatter-gather support, Ethernet ports, serial ports, interfaces, interface, ports, NAND Flash interface, general purpose I/O. Technology: CMOS Cu-11, 0.13m. Package: 35mm, 456-ball standard plastic ball grid array (E-PBGA), with without lead (RoHS compliant). Typical power (measured): Less than 533MHz, 2.5W 400MHz. Supply voltages required: 3.3V, 2.5V, 1.5V.
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440EP PPC440EP Embedded Processor
Data Sheet
Contents
Ordering Information Address Maps Block Diagram PowerPC Processor Core Internal Buses Floating Point Unit (FPU) Interface SDRAM Memory Controller External Peripheral Controller (EBC) Ethernet Controller Interface Controller Controller Serial Ports (UART) Interface Serial Peripheral Interface (SPI/SCP) Universal Serial (USB) NAND Flash Controller General Purpose Timers (GPT) General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) JTAG Package Diagram Signal Lists Signal Descriptions Device Characteristics Spread Spectrum Clocking Specifications DDR1 SDRAM Specifications SDRAM Write Operation SDRAM Read Operation Strapping EEPROM
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Figures
Figure Order Part Number Figure PPC440EP Functional Block Diagram Figure 35mm, 456-Ball E-PBGA Figure Timing Waveform Figure Input Setup Hold Waveform Figure Output Delay Float Timing Waveform Figure SDRAM Simulation Signal Termination Model Figure SDRAM Write Cycle Timing Figure SDRAM MemClkOut0 Read Clock Delay Figure SDRAM Read Data Path Figure SDRAM Read Cycle Timing-Example Figure SDRAM Read Cycle Timing-Example Figure SDRAM Read Cycle Timing-Example
Tables
Table System Memory Address Table Address (4KB Device Configuration Registers) Table Signals Listed Alphabetically Table Signals Listed Ball Assignment Table Summary Table Signal Functional Description Table Absolute Maximum Ratings Table Recommended Operating Conditions Table Input Capacitance Table Typical Power Supply Requirements Table Supply Power Dissipation Table Power Supply Current Loads Table Package Thermal Specifications Table Clocking Specifications Table Peripheral Interface Clock Timings Table Specifications-All Speeds Table Specifications-333MHz 533MHz Table SDRAM Output Driver Specifications Table Timing-DDR SDRAM Table Timing-DDR SDRAM TSK, TSA, Table Timing-DDR SDRAM Table Timing-DDR SDRAM TSIN TDIN Table Strapping Assignments
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440EP PPC440EP Embedded Processor
Data Sheet
Ordering Information
information availability following parts, contact your local AMCC sales office.
Product Name PPC440EP PPC440EP Notes:
Order Part Number (see Notes:) PPC440EP-3pbfffCx PPC440EP-3pbfffCx
Package 35mm, ball, E-PBGA 35mm, ball, E-PBGA
Revision Level
Value 0x422218D3 0x422218D4
JTAG 0x2A950049 0x2A950049
Module Package type standard (E-PBGA) contains lead. standard (E-PBGA) lead-free (RoHS compliant) Chip revision level Revision level (2.0) Revision level (2.1) Processor frequency 333MHz 400MHz 533MHz 667MHz Case temperature range: -40°C +100°C 333MHz, 400MHz, 533MHz parts package -40°C +85°C 667MHz parts E-PBGA package Shipping package type tape-and-reel Blank tray
Each part number contains revision code. This mask revision number included part number identification purposes only. (Processor Version Register) JTAG register software accessible (read-only) contain information that uniquely identifies part. Refer PPC440EP User's Manual details accessing these registers. Figure Order Part Number
PPC440EP-3JC667CZ
Shipping Package AMCC Part Number Grade Reliability Package Case Temperature Range Processor Frequency Revision Level
Note: example above standard lead-free, revision package, capable running 667MHz, shipped tape-and-reel packaging.
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440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Block Diagram
Figure PPC440EP Functional Block Diagram
External Interrupts Clock Control Reset Timers
Power Mgmt DCRs 66MHz 30-bit addr 16-bit data 66MHz bits devices
PPC440
Processor Core JTAG 32KB D-Cache Performance Monitor (PLB4-128 bits) Trace 32KB I-Cache
External Peripheral Controller NAND Flash Controller Bridge
Bridge Bridge
(PLB3-64 bits)
Controller SDRAM Controller
Bridge
Controller
On-chip Peripheral (OPB
266MHz 13-bit addr 32-bit data
Device UTMI 1.1PHY
Host 1.1PHY
GPIO
UART
Ethernet 10/100 ZMII
RMII SMII
D+/D-
D+/D-
PPC440EP system chip (SOC) using CoreConnect BusArchitecture.
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440EP PPC440EP Embedded Processor
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Address Maps
PPC440EP incorporates address maps. first fixed processor System Memory Address Map. This address defines possible contents various address regions which processor access. second Address Device Configuration Registers (DCRs). DCRs accessed software running PPC440EP processor through mtdcr mfdcr instructions.
Table System Memory Address (Sheet
Function Local Memory1 Function SDRAM Reserved Arbiter (OPB Reserved Device Device Reserved Memory Reserved Reserved Reserved Configuration Registers Reserved Interrupt Special Cycle Reserved Local Configuration Registers Reserved EEC0 0000 EEC0 0008 EED0 0000 EED0 0004 EF40 0000 EF40 0040 EEC0 0007 EECF FFFF EED0 0003 EF3F FFFF EF40 003F EF4F FFFF 5000 0100 5000 0180 8000 0000 A000 0000 E000 0000 E800 0000 E801 0000 E880 0000 EC00 0000 5000 017F 7FFF FFFF 9FFF FFFF DFFF FFFF E7FF FFFF E800 FFFF E87F FFFF EBFF FFFF EEBF FFFF 56MB 64KB 512MB 128B Start Address 0000 0000 4000 0000 5000 0000 5000 0040 Address 3FFF FFFF 4FFF FFFF 5000 003F 5000 00FF Size
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440EP PPC440EP Embedded Processor
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Data Sheet
Table System Memory Address (Sheet
Function Reserved General Purpose Timer Reserved UART0 Reserved UART1 Reserved UART2 Reserved UART3 Reserved IIC0 Reserved IIC1 Internal Peripherals Reserved Reserved Arbiter (OPB Reserved GPIO0 Controller Reserved GPIO1 Controller Reserved Ethernet ZMII Reserved Ethernet Controller Ethernet Controller Host Reserved Boot space (EBC Bank PCI) Notes: SDRAM located anywhere Local Memory area memory map. relocatable, this reflects suggested configuration. Function Start Address EF50 0000 EF60 0000 EF60 0100 EF60 0300 EF60 0308 EF60 0400 EF60 0408 EF60 0500 EF60 0508 EF60 0600 EF60 0608 EF60 0700 EF60 0720 EF60 0800 EF60 0820 EF60 0900 EF60 0907 EF60 0A00 EF60 0A40 EF60 0B00 EF60 0B80 EF60 0C00 EF60 0C80 EF60 0D00 EF60 0D10 EF60 0E00 EF60 0F00 EF60 1000 EF60 1080 F000 0000 FFE0 0000 Address EF5F FFFF EF60 00FF EF60 02FF EF60 0307 EF60 03FF EF60 0407 EF60 04FF EF60 0507 EF60 05FF EF60 0607 EF60 06FF EF60 071F EF60 07FF EF60 081F EF60 08FF EF60 0906 EF60 09FF EF60 0A3F EF60 0AFF EF60 0B7F EF60 0BFF EF60 0C7F EF60 0CFF EF60 0D0F EF60 0DFF EF60 0EFF EF60 0FFF EF60 107F EFFF FFFF FFDF FFFF FFFF FFFF 254MB 256B 256B 128B 128B 128B 256B Size
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440EP PPC440EP Embedded Processor
Data Sheet
Table Address (4KB Device Configuration Registers)
Function Total Address Space1 function: Reserved Clocking Power Reset (CPR) System DCRs (SDR) Memory Controller (SDRAM) External Controller (EBC) Reserved Performance Monitor (PPM) Reserved Bridge Bridge Reserved Arbiter Arbiter Bridge Reserved Bridge Power Management Reserved Interrupt Controller Interrupt Controller Reserved Controller Reserved Ethernet Bridge Reserved Controller Reserved Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register. kiloword (1024W) equals (4096 128W 512W 512W Start Address Address Size (4KB)1
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440EP PPC440EP Embedded Processor
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Data Sheet
PowerPC Processor Core
PowerPC processor core designed high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. first processor core implement Book PowerPC embedded architecture first 128-bit version IBM's on-chip CoreConnect Architecture. Features include: 667MHz operation PowerPC Book architecture 32KB I-cache, 32KB D-cache UTLB Word Wide parity data address parity with exception force Three logical regions D-cache: locked, transient, normal D-cache full line flush capability 41-bit virtual address, 36-bit (64GB) physical address Superscalar, out-of-order execution 7-stage pipeline execution pipelines Dynamic branch prediction Memory management unit 64-entry, full associative, unified with optional parity Separate instruction data micro-TLBs Storage attributes write-through, cache-inhibited, guarded, little endian Debug facilities Multiple instruction data range breakpoints Data value compare Single step, branch, trap events Non-invasive real-time trace interface instructions Single cycle multiply multiply-accumulate integer multiply 32-bit
Floating Point Unit (FPU)
Features include: Five stages with MFlops/MHz Hardware support IEEE Single- double-precision Single-cycle throughput most instructions Thirty-two 64-bit floating point registers
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440EP PPC440EP Embedded Processor
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Internal Buses
PowerPC 440EP features five standard on-chip buses: Processor Local Buses (PLBs), On-Chip Peripheral Buses (OPBs), Device Control Register (DCR). high performance, high bandwidth cores such PowerPC processor core, SDRAM memory controller, bridge connect PLBs. primary hosts lower data rate peripherals. secondary dedicated DMA. daisy-chained provides lower bandwidth path passing status control information between processor core other on-chip cores. Features include: (PLB4) 128-bit implementation architecture Separate simultaneous read write data paths 36-bit address Simultaneous control, address, data phases Four levels pipelining Byte-enable capability supporting unaligned transfers 64-byte burst transfers 133MHz, maximum 4.25GB/s (simultaneous read write) Processor:bus clock ratios (PLB3) 64-bit implementation architecture 32-bit address 133MHz (1:1 ratio with 128), maximum 1.1GB/s simultaneous read write) 32-bit data path 32-bit address 66.66MHz 32-bit data path 10-bit address
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440EP PPC440EP Embedded Processor
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Interface
interface allows connection devices PowerPC processor local memory. This interface designed Version Specification supports devices. Reference Specifications: PowerPC CoreConnect (PLB) Specification Version Specification Version Power Management Interface Specification Version Features include: Frequency 66MHz 32-bit Host Bridge Adapter Device's interface Internal arbitration function, supporting external devices, that disabled with external arbiter Support Message Signaled Interrupts Simple message passing capability Asynchronous Power Management register addressable both from on-chip processor device sides Ability boot from memory Error tracking/status Supports initiation transfer following address spaces: Single beat reads writes Single beat burst memory reads writes Single beat configuration reads writes (type type Single beat special cycles
SDRAM Memory Controller
Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. four 256MB logical banks supported limited configurations. Global memory timings, address bank sizes, memory addressing modes programmable. Features include: Registered non-registered industry standard discrete devices 32-bit memory interface with optional 8-bit (SEC/DED) Sustainable 1.1GB/s peak bandwidth 133MHz SSTL_2 logic chip selects latencies supported DDR200/266 support Page mode accesses eight open pages) with configurable paging policy Programmable address mapping timing Hardware software initiated self-refresh Power management (self-refresh, suspend, sleep)
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External Peripheral Controller (EBC)
Features include: ROM, EPROM, SRAM, Flash memory, slave peripheral banks supported 66.66MHz operation Burst non-burst devices 16-bit byte-addressable data 30-bit address Peripheral Device pacing with external "Ready" Latch data Ready, synchronous asynchronous Programmable access timing device Wait States non-burst Burst Wait States first access Wait States subsequent accesses Programmable CSon, CSoff relative address Programmable OEon, WEon, WEoff clock cycles) relative Programmable address mapping External Slave Support External master interface Write posting from external master Read prefetching external master reads Bursting capable from external master Allows external master access non-EBC slaves External master control slaves access control
Ethernet Controller Interface
Ethernet support provided PPC440EP interfaces physical layer included chip: 10/100 interfaces running full- half-duplex modes full Media Independent Interface (MII) with 4-bit parallel data transfer Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer Serial Media Independent Interfaces (SMII) Packet reject support
Controller
This controller provides interface between 64-bit PLB. Features include: Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/Gather capability programming multiple operations 32-byte buffer 16-, 32-bit peripheral support (OPB external) 32-bit addressing Address increment decrement Supports internal external peripherals Support memory mapped peripherals Support peripherals running slower frequency buses
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440EP PPC440EP Embedded Processor
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Data Sheet
Controller
This controller provides interface dedicated device ports 128-bit PLB. Features include: independent channels supporting internal Device endpoints Support memory-to-memory, peripheral-to-memory, memory-to-peripheral transfers Scatter/gather capability 128-byte buffer with programmable thresholds
Serial Ports (UART)
Features include: four ports following combinations: 8-pin 4-pin 4-pin 2-pin Four 2-pin Selectable internal external serial clock allow wide range baud rates Register compatibility with NS16750 register Complete status reporting capability Fully programmable serial-interface characteristics Supports using internal function
Interface
Features include: interfaces provided Support Philips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers Twelve memory-mapped, fully programmable configuration registers programmable interrupt request signal Provides full management protocols Programmable error recovery Includes integrated boot-strap controller that multiplexed with second interface
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Serial Peripheral Interface (SPI/SCP)
Serial Peripheral Interface (also known Serial Communications Port) full-duplex, synchronous, character-oriented (byte) port that allows exchange data with other serial devices. master serial port supporting 3-wire interface (receive, transmit, clock), slave OPB. Features include: Three-wire serial port interface Full-duplex synchronous operation master slave Programmable clock rate divider Clock inversion Reverse data Local data loop back test
Universal Serial (USB)
interfaces provide both device host support version device support version 2.0. Support Transceiver Macrocell Interface (UTMI) specification included. Features include: Host port with internal Device UTMI Device Device support provides points out) 1024B FIFO (double buffering 512B packets) FIFOs shared between endpoints Endpoints support high-bandwidth isochronous transfers device points have dedicated channels (DMA 128)
NAND Flash Controller
NAND Flash controller provides simple interface between four separate external NAND Flash devices. provides both direct command, address, data access external device well memory-mapped linear region that generates data accesses. NAND Flash device data appears peripheral data bus. Features include: banks supported Direct Interfacing Discrete NAND Flash devices devices) SmartMedia Card socket (22-pins) Device sizes 4MB-256MB supported (512 16)-B 64)-B device page sizes supported Boot-from-NAND: Execute linear sequence boot code single page first block (512B) Support allow direct, no-processor-intervention block copy from NAND Flash SDRAM provides single-bit error correction double-bit error detection each 256B stored data Chip selects shared with
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440EP PPC440EP Embedded Processor
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General Purpose Timers (GPT)
Provides separate time base counter additional system timers addition those defined processor core. Features include: 32-bit Time Base Counter driven clock Seven 32-bit compare timers
General Purpose (GPIO) Controller
Controller functions GPIO registers programmed accessed memory-mapped master accesses. GPIOs multiplexed with other functions. DCRs control whether particular that GPIO capabilities acts GPIO used another purpose. Each GPIO output separately programmable emulate open drain driver (that drives zero, tri-stated output
Universal Interrupt Controller (UIC)
Universal Interrupt Controllers (UIC) employed. They provide control, status, communications necessary between external internal sources interrupts on-chip PowerPC processor. Note: Processor specific interrupts (for example, page faults) resources. Features include: external interrupts Edge triggered level-sensitive Positive negative active Non-critical critical interrupt on-chip processor core Programmable interrupt priority ordering Programmable critical interrupt vector faster vector processing
JTAG
Features include: IEEE 1149.1 Test Access Port RISCWatch Debugger support JTAG Boundary Scan Description Language (BSDL)
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Package Diagram
Figure 35mm, 456-Ball E-PBGA
View
Part Number
PPC440EP
nprffft 1YWWBZZZZZ
Number
Gold Gate Release Corresponds Ball Location
Notes: dimensions
Package available both lead-free leaded versions.
0.20 35.0 31.75 0.20 0.25 0.35 35.0±0.2 0.75 0.15 SOLDERBALL 0.30 0.15 0.6±0.1 2.65 Substrate Thermal Balls Mold Compound 1.27
Bottom View
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440EP PPC440EP Embedded Processor
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Data Sheet
Signal Lists
following table lists external signals alphabetical order shows ball (pin) number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signals brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin. cases where signals same interface group (for example, Ethernet) have different names distinguish variations mode operation, names separated comma with primary mode name appearing first. These signals listed only once, appear alphabetically primary mode name. Table Signals Listed Alphabetically (Sheet
Signal Name AGND AVDD BankSel0 BankSel1 BankSel2 BankSel3 [BusReq][USB2TermSel]GPIO31 ClkEn [DMAAck0][IRQ8]GPIO47 [DMAAck1][IRQ4]GPIO44 [DMAAck2][PerAddr06]GPIO01 [DMAAck3][PerAddr03]GPIO04 [DMAReq0][IRQ7]GPIO46 DMAReq1[IRQ5][ModeCtrl] [DMAReq2][PerAddr07]GPIO00 [DMAReq3][PerAddr04]GPIO03 DQS0 DQS1 DQS2 DQS3 DQS8 [DrvrInh1]USB2LS0[RejectPkt] [DrvrInh2]Halt AMCC Proprietary Ball AE17 Power AD17 AF03 SDRAM AF04 SDRAM AA23 AF05 AE05 AD07 AF07 External Slave Peripheral AC12 External Slave Peripheral AD09 AC08 AC06 System SDRAM SDRAM External Master Peripheral SDRAM SDRAM Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 [EMCCD, EMC1RxErr]GPIO25[NFRdyBusy] [EMCCrS, EMC0CrsDV]GPIO22 [EMCDV, EMC1CrsDV]GPIO21[NFREn] EMCMDClk EMCMDIO EMCRxClk [EMCRxD0, EMC0RxD0, EMC0RxD]GPIO12 [EMCRxD1, EMC0RxD1, EMC1RxD]GPIO13 [EMCRxD2, EMC1RxD0]GPIO14 [EMCRxD3, EMC1RxD1]GPIO15 [EMCRxErr, EMC0RxErr]GPIO20 EMCTxClk, EMCRefClk [EMCTxD0, EMC0TxD0, EMC0TxD]GPIO16 [EMCTxD1, EMC0TxD1, EMC1TxD]GPIO17 [EMCTxD2, EMC1TxD0]GPIO18[NFCLE] [EMCTxD3, EMC1TxD1]GPIO19[NFALE] [EMCTxEn, EMC0TxEn, EMCSync]GPIO24 [EMCTxErr, EMC1TxEn]GPIO23[NFWEn] [EOT0/TC0][IRQ9]GPIO48 [EOT1/TC1][IRQ6]GPIO45 [EOT2/TC2][PerAddr05]GPIO02 [EOT3/TC3][PerAddr02]GPIO05 [ExtAck][USB2XcvrSel]GPIO30 [ExtReq][USB2RxErr]GPIO27 ExtReset Ball SDRAM AC16 AD15 AF17 AE16 AC18 AF19 AD19 AE20 AD18 Ethernet AC17 AD16 AC15 AD14 AF13 AF14 AC14 AF20 AF18 External Slave Peripheral AA25 AD26 External Master Peripheral External Master Peripheral External Master Peripheral Interface Group Page
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440EP PPC440EP Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball AA01 AA26 AB09 AB13 AB18 AC01 AC04 AC07 AC23 Power Interface Group Page
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440EP PPC440EP Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name Ball AD03 AD24 AE01 AE02 AE25 AF01 Power AF06 AF11 AF16 AF21 AF25 AF26 Interface Group Page
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440EP PPC440EP Embedded Processor
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Table Signals Listed Alphabetically (Sheet
Signal Name GPIO00[PerAddr07][DMAReq2] GPIO01[PerAddr06][DMAAck2] GPIO02[PerAddr05][EOT2/TC2] GPIO03[PerAddr04][DMAReq3] GPIO04[PerAddr03][DMAAck3] GPIO05[PerAddr02][EOT3/TC3] GPIO06[PerCS1][NFCE1] GPIO07[PerCS2][NFCE2] GPIO08[PerCS3][NFCE3] GPIO09[PerCS4] GPIO10[PerCS5] GPIO11[PerErr] GPIO12[EMCRxD0, EMC0RxD0, EMC0RxD] GPIO13[EMCRxD1, EMC0RxD1, EMC1RxD] GPIO14[EMCRxD2, EMC1RxD0] GPIO15[EMCRxD3, EMC1RxD1] GPIO16[EMCTxD0, EMC0TxD0, EMC0TxD] GPIO17[EMCTxD1, EMC0TxD1, EMC1TxD] GPIO18[EMCTxD2, EMC1TxD0][NFCLE] GPIO19[EMCTxD3, EMC1TxD1][NFALE] GPIO20[EMCRxErr, EMC0RxErr] GPIO21[EMCDV, EMC1CrsDV][NFREn] GPIO22[EMCCrS, EMC0CrsDV] GPIO23[EMCTxErr, EMC1TxEn][NFWEn] GPIO24[EMCTxEn, EMC0TxEn, EMCSync] GPIO25[EMCCD, EMC1RxErr][NFRdyBusy] GPIO26[USB2RxDV] GPIO27[USB2RxErr][ExtReq] GPIO28[USB2TxVal] GPIO29[USB2Susp][HoldAck] GPIO30[USB2XcvrSel][ExtAck] GPIO31[USB2TermSel][BusReq] Ball AD19 AE20 AD18 AC17 System AD14 AF13 AF14 AC14 AD16 AF17 AD15 AF18 AF20 AC16 AC26 AD26 AB25 AA25 AA23 Interface Group Page
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440EP PPC440EP Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name GPIO32[USB2OM0] GPIO33[USB2OM1] GPIO36[UART0_CTS/UART3_Rx] GPIO37[UART0_RTS/UART3_Tx] GPIO38[UART0_DTR/UART1_Tx] GPIO39[UART0_RI/UART1_Rx] GPIO40[IRQ0] GPIO41[IRQ1] GPIO42[IRQ2] GPIO43[IRQ3] GPIO44[IRQ4][DMAAck1] GPIO45[IRQ6][EOT1/TC1] GPIO46[IRQ7][DMAReq0] GPIO47[IRQ8][DMAAck0] GPIO48[IRQ9][EOT0/TC0] GPIO49[TrcBS0] GPIO50[TrcBS1] GPIO51[TrcBS2] GPIO52[TrcES0] GPIO53[TrcES1] GPIO54[TrcES2] GPIO55[TrcES3] GPIO56[TrcES4] GPIO57[TrcTS0] GPIO58[TrcTS1] GPIO59[TrcTS2] GPIO60[TrcTS3] GPIO61[TrcTS4] GPIO62[TrcTS5] GPIO63[TrcTS6] Halt[DrvrInh2] [HoldAck][USB2Susp]GPIO29 [HoldPri]USB2LS1[LeakTest] [HoldReq]USB2RxAct[RcvrInh] IIC0SClk IIC0SData Ball AB26 System AE21 AC25 AA24 AA04 AB03 AB04 AF22 AC22 AE24 AD04 AD06 AC09 AD12 AE15 AB25 IIC0 Peripheral External Master Peripheral System Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [IIC1SClk]SCPClkOut [IIC1SData]SCPDI [IRQ0]GPIO40 [IRQ1]GPIO41 [IRQ2]GPIO42 [IRQ3]GPIO43 [IRQ4]GPIO44[DMAAck1] [IRQ5][ModeCtrl]DMAReq1 [IRQ6]GPIO45[EOT1/TC1] [IRQ7]GPIO46[DMAReq0] [IRQ8]GPIO47[DMAAck0] [IRQ9]GPIO48[EOT0/TC0] [LeakTest]USB2LS1[HoldPri] MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 Ball IIC1 Peripheral Interrupts AC12 AB02 AD01 AD02 AF12 SDRAM AE13 SDRAM System Interface Group Page
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440EP PPC440EP Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 MemSelfRef [ModeCtrl][IRQ5]DMAReq1 Ball AE12 AD13 AC13 AE11 AF10 AE10 AC11 AF09 AE09 AD10 AF08 AE08 AC10 AE07 AD08 AD05 SDRAM AE03 AC05 AF02 AC03 AC02 AA03 AA02 AE04 AC12 SDRAM System Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [NFALE][EMCTxD3, EMC1TxD1]GPIO19 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO06 [NFCE2][PerCS2]GPIO07 [NFCE3][PerCS3]GPIO08 [NFCLE][EMCTxD2, EMC1TxD0]GPIO18 [NFRdyBusy][EMCCD, EMC1RxErr]GPIO25 [NFREn][EMCDV, EMC1CrsDV]GPIO21 [NFWEn][EMCTxErr, EMC1TxEn]GPIO23 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Ball AC14 AF14 AC16 AF17 AF18 physical ball does exist these ball coordinates. NAND Flash Interface Group Page
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440EP PPC440EP Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Ball physical ball does exist these ball coordinates. Interface Group Page
AMCC Proprietary
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Ball physical ball does exist these ball coordinates. Interface Group Page
AMCC Proprietary
440EP PPC440EP Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Ball physical ball does exist these ball coordinates. Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Ball physical ball does exist these ball coordinates. Interface Group Page
AMCC Proprietary
440EP PPC440EP Embedded Processor
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Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball Ball physical ball does exist these ball coordinates. Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 Power physical ball does exist these ball coordinates. Interface Group Page
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0/BE0 PCIC1/BE1 PCIC2/BE2 PCIC3/BE3 PCIClk PCIDevSel PCIFrame Ball Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PCIGnt0/Req PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY Ball Interface Group Page
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [PerAddr02]GPIO05[EOT3/TC3] [PerAddr03]GPIO04[DMAAck3] [PerAddr04]GPIO03[DMAReq3] [PerAddr05]GPIO02[EOT2/TC2] [PerAddr06]GPIO01[DMAAck2] [PerAddr07]GPIO00[DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0[NFCE0] [PerCS1][NFCE1]GPIO06 [PerCS2][NFCE2]GPIO07 [PerCS3][NFCE3]GPIO08 [PerCS4]GPIO09 [PerCS5]GPIO10 Ball External Slave Peripheral External Slave Peripheral External Slave Peripheral External Master Peripheral Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 [PerErr]GPIO11 PerOE PerReady PerR/W PerWBE0 PerWBE1 PSROOut [RcvrInh]USB2RxAct[HoldReq] [RefEn]USB2TxRdy [RejectPkt]USB2LS0[DrvrInh1] SAGND SAVDD SCPClkOut[IIC1SClk] SCPDI[IIC1SData] SCPDO Ball External Slave Peripheral External Slave Peripheral AF15 Power AE14 Serial Peripheral (SPI) System SDRAM System System Ethernet External Master Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral Interface Group Page
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440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVREF1 SVREF2A SVREF2B SysClk SysErr SysReset TestEn TmrClk [TrcBS0]GPIO49 [TrcBS1]GPIO50 [TrcBS2]GPIO51 TrcClk Ball Power AA05 AA22 AB06 AB07 AB08 AB14 AB19 AB20 AB21 AE06 AE19 AB01 AE18 AD11 AE21 AC25 AA24 AC19 Trace Trace System System System JTAG JTAG JTAG System System JTAG SDRAM Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [TrcES0]GPIO52 [TrcES1]GPIO53 [TrcES2]GPIO54 [TrcES3]GPIO55 [TrcES4]GPIO56 [TrcTS0]GPIO57 [TrcTS1]GPIO58 [TrcTS2]GPIO59 [TrcTS3]GPIO60 [TrcTS4]GPIO61 [TrcTS5]GPIO62 [TrcTS6]GPIO63 TRST [UART0_CTS/UART3_Rx]GPIO36 [UART0_RTS/UART3_Tx]GPIO37 UART0_Rx UART0_Tx [UART0_DTR/UART1_Tx]GPIO38 [UART0_RI/UART1_Rx]GPIO39 UARTSerClk Ball AA04 AB03 AB04 AF22 AC22 AE24 AD04 AD06 AC09 AD12 AE15 UART Peripheral JTAG Trace Trace Interface Group Page
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name USB1Clk USB1DevXcvr USB1DevXcvr USB1HostXcvr USB1HostXcvr USB2Clk USB2DI0 USB2DI1 USB2DI2 USB2DI3 USB2DI4 USB2DI5 USB2DI6 USB2DI7 USB2DO0 USB2DO1 USB2DO2 USB2DO3 USB2DO4 USB2DO5 USB2DO6 USB2DO7 USB2LS0[DrvrInh1][RejectPkt] USB2LS1[LeakTest][HoldPri] [USB2OM0]GPIO32 [USB2OM1]GPIO33 USB2RxAct[HoldReq][RcvrInh] [USB2RxDV]GPIO26 [USB2RxErr]GPIO27[ExtReq] [USB2Susp]GPIO29[HoldAck] [USB2TermSel]GPIO31[BusReq] USB2TxRdy[RefEn] [USB2TxVal]GPIO28 [USB2XcvrSel]GPIO30[ExtAck] Ball AD25 AD22 AD21 AE23 AF24 AC21 AE26 AB23 AC24 AB24 AD20 AE22 AC20 Universal Serial AF23 AD23 AB26 AC26 AD26 AB25 AA23 AA25 Interface Group Page
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power AB05 AB10 AB11 AB12 AB15 AB16 AB17 AB22 SDRAM Interface Group Page
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440EP PPC440EP Embedded Processor
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Data Sheet
following table, only primary (default) signal name shown each pin. Multiplexed multifunction signals marked with asterisk (*). determine what signals functions multiplexed those pins, look primary signal name Table Signals Listed Alphabetically. Table Signals Listed Ball Assignment (Sheet
Ball TestEn GPIO07* GPIO02* PerAddr09 PerAddr13 GPIO10* PerAddr23 PerAddr22 PerAddr24* PerAddr28* PCIAD03 PCIAD05 GPIO48* PCIAD09 PCIReq4 PCIAD12 PCIAD13 PCIGnt2 Signal Name Ball Signal Name PerData15 PerOE GPIO05* GPIO01* GPIO08* PerAddr11 PerAddr14 GPIO09* PerAddr19 PerAddr20 PerAddr25* PerAddr27* PerAddr29* PCIAD00 PCIAD04 PCIC0/BE0 PCIReq2 PCIReq1 PCIClk PCIAD11 ExtReset GPIO46* Ball Signal Name PerData12 PerClk PerWBE1 PerReady GPIO06* GPIO04* GPIO00* PerAddr10 PerAddr15 PerAddr16 PerAddr18 PerAddr26* PerAddr30 PCIAD01 PCIAD06 PCIAD08 PCIReq3 PCIAD10 PCIAD14 PCIPar Halt[DrvrInh2] PSROOut Ball Signal Name PerData10 GPIO40* PerR/W PerCS0 TRST GPIO03* PerAddr08 PerAddr12 PerBLast PerAddr17 PerAddr21 PerAddr31 PCIAD02 PCIAD07 PCIGnt0/Req GPIO47* PCIReset PCIINT PCIAD15 PCIPErr PCIGnt3 PCIDevSel
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name PerData06 PerData09 PerData14 GPIO11* OVDD OVDD OVDD OVDD OVDD OVDD OVDD PCIStop PCIGnt5 PCIIRDY PCIC3/BE3 Ball Signal Name GPIO42* PerData11 PerData13 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD PCIC1/BE1 PCIC2/BE2 PCIAD17 Ball Signal Name PerData02 GPIO43* PerData07 GPIO41* OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD PCITRDY PCIFrame GPIO44* PCIIDSel Ball Signal Name PerData00 PerWBE0 PerData05 PerData08 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD GPIO45* PCIAD16 PCIGnt4 PCIReq5
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440EP PPC440EP Embedded Processor
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Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball PerData03 PerData04 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball PCISErr PCIAD18 PCIAD21 Signal Name Ball DQS2 PerData01 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball PCIAD19 PCIAD20 PCIAD23 PCIAD24 Signal Name Ball Signal Name ECC6 ball ball ball ball ball OVDD OVDD ball ball ball ball ball PCIAD22 PCIGnt1 PCIAD27 Ball Signal Name ECC2 ECC3 ECC7 DQS3 ball ball ball ball ball OVDD OVDD ball ball ball ball ball PCIAD26 PCIAD25 PCIAD30
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name BankSel3 ECC1 ECC4 ECC5 ball ball ball ball ball ball ball ball ball ball OVDD PCIAD28 GPIO38* PCIReq0/Gnt PCIAD29 Ball Signal Name MemAddr00 ECC0 SVREF2A MemAddr01 SVDD ball ball ball ball ball ball ball ball ball ball UARTSerClk GPIO39* UART0_Tx PCIAD31 Ball Signal Name BankSel2 BankSel1 MemAddr10 BankSel0 ball ball ball ball ball SVDD SVDD ball ball ball ball ball USB1DevXcvr USB1DevXcvr GPIO34* GPIO37* Ball MemAddr02 MemData30 MemAddr03 ball ball ball ball ball SVDD SVDD ball ball ball ball ball SCPDO IIC0SData UART0_Rx Signal Name
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440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name MemAddr04 MemData31 MemData29 MemAddr06 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball USB2DO7 SCPClkOut* IIC0SClk GPIO35* Ball MemAddr05 MemData26 MemData24 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball USB2DO5 USB2LS1* SCPDI* GPIO36* Signal Name Ball Signal Name MemData28 MemData27 MemAddr07 SVREF1 SVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball SVDD USB2TxRdy* GPIO32* USB1HostXcvr USB1HostXcvr Ball Signal Name MemData25 MemAddr08 GPIO52* MemData22 SVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball SVDD USB2RxAct* GPIO28* USB2LS0* USB2DO6
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 MemData23 MemData21 GPIO53* SVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball SVDD GPIO31* GPIO51* GPIO30* Signal Name Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 Signal Name SysErr MemAddr09 GPIO54* GPIO55* SVDD SVDD SVDD SVDD SVDD SVDD SVDD USB2DI5 USB2DI7 GPIO29* GPIO33* Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 MemData20 MemData19 MemData17 DQS8 DQS1 GPIO61* MemData12 MemData06 IRQ5* MemData02 GPIO19* EMCTxClk* GPIO25* GPIO15* EMCMDIO TrcClk USB2DO2 USB2DI3 GPIO57* USB2DI6 GPIO50* GPIO26* Signal Name Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 Signal Name MemAddr11 MemAddr12 GPIO59* MemData15 GPIO60* MemData14 DQS0 MemData09 TmrClk GPIO62* MemData01 GPIO16* GPIO22* GPIO20* AVDD GPIO14* GPIO12* USB2DO0 USB2DI0 USB2Clk USB2DO4 USB1Clk GPIO27*
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 MemData16 MemSelfRef SVREF2B MemData13 MemData11 MemData08 MemData05 MemData03 MemData00 MemClkOut0 SAVDD GPIO63* EMCMDClk AGND SysReset SysClk GPIO13* GPIO49* USB2DO1 USB2DI1 GPIO58* USB2DI4 Signal Name Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name MemData18 ClkEn MemData10 MemData07 MemData04 MemClkOut0 GPIO17* GPIO18* SAGND GPIO21* GPIO23* EMCRxClk GPIO24* GPIO56* USB2DO3 USB2DI2 Ball Signal Name Ball Signal Name
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440EP PPC440EP Embedded Processor
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Signal Descriptions
PPC440EP embedded controller packaged 456-ball enhanced plastic ball grid array (E-PBGA). following tables describe package level pinout.
Table Summary
Group
Total Signal Pins AVDD SAVDD SAGnd AGnd OVDD SVDD Total Power Pins Reserved Total Pins
Pins
table "Signal Functional Description" page each signal listed along with short description function. Active-low signals (for example, RAS) marked with overline. Please "Signals Listed Alphabetically" page (ball) number which each signal assigned. Multiplexed Signals Some signals multiplexed same that used different functions. most cases, signal names shown this table accompanied signal names that multiplexed same pin. need know what, any, signals multiplexed with particular signal, look name "Signals Listed Alphabetically" page expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. circuit type multiplexed signals shown "Multiplex." actual circuit type same primary signal. Multipurpose Signals addition multiplexing, some pins also multi-purpose. example, peripheral controller address pins (PerAddr) used outputs PPC440EP broadcast address external slave devices when PPC440EP control external bus. When during course normal chip operation external master gains ownership external bus, these same pins used inputs which driven external master received PPC440EP. this example, pins also bidirectional, serving both inputs outputs.
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440EP PPC440EP Embedded Processor
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Data Sheet
Multimode Signals some cases (for example, Ethernet) function vary with different modes operation. When multiple signal names assigned distinguish different modes operation, names shown. Strapping Pins group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Strapping" page 80). Note that these multiplexed pins since function pins programmable.
AMCC Proprietary
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Interface PCIAD00:31 PCIC0:3/BE0:3 PCIClk PCIDevSel PCIFrame Address/Data (bidirectional). Command/Byte Enables. Provides timing interface transactions. Indicates driving device decoded address target current access. Driven current master indicate beginning duration access. Indicates that specified agent granted access bus. When internal arbiter enabled, output PCIGnt0. When internal arbiter disabled, output Req. Indicates that specified agent granted access bus. Used only when internal arbiter enabled. Used chip select during configuration read write transactions. Level sensitive interrupt. Indicates initiating agent's ability complete current data phase transaction. Even parity. Reports data parity errors during transactions except Special Cycle. Indicates arbiter that specified agent wishes bus. When internal arbiter enabled, input PCIReq0. When internal arbiter disabled, input Gnt. indication arbiter that specified agent wishes bus. Used only when internal arbiter enabled. Brings device registers logic consistent state. Reports address parity errors, data parity errors Special Cycle command, other catastrophic system errors. Current target requesting master stop current transaction. 3.3V 3.3V 3.3V 3.3V 3.3V Description Type
Notes
PCIGnt0/Req
3.3V
PCIGnt1:5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
PCIReq0/Gnt
3.3V
PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY
3.3V 3.3V 3.3V 3.3V 3.3V
Target agent's ability complete current data phase
transaction.
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name SDRAM Interface BA0:1 BankSel0:3 ClkEn DM0:3 DQS0:3 DQS8 ECC0:7 MemAddr00:12 MemClkOut0 MemClkOut0 MemData00:31 MemSelfRef SVREF1 SVREF2A:B Bank Address supporting four internal banks. Selects four external SDRAM banks. Column Address Strobe. Clock Enable. Memory write data byte lane masks. byte lane mask byte lane. Byte lane data strobe. DQS8 data strobe byte lane. check bits 0:7. Memory address bus. Subsystem clock. Memory data bus. Self refresh. Address Strobe. Write Enable. SSTL reference voltage. Supplemental SSTL reference voltage. 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 2.5V SSTL_2 Diff driver 2.5V SSTL_2 3.3V tolerant 2.5V CMOS 2.5V SSTL_2 2.5V SSTL_2 Volt receiver Volt (supplemental) Description Type
Notes
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440EP PPC440EP Embedded Processor
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Ethernet Interface EMCCD, EMC1RxErr EMCCrS, EMC0CrsDV EMCDV, EMC1CrsDV EMCMDClk EMCMDIO EMCRxClk EMCRxD0:1, EMC0RxD0:1 EMC0:1RxD EMCRxD2:3, EMC1RxD0:1 EMCRxErr, EMC0RxErr EMCTxClk, EMCRefClk EMCTxD0:1, EMC0TxD0:1 EMC0:1TxD EMCTxD2:3, EMC1TxD0:1 EMCTxEn, EMC0TxEn, EMCSync EMCTxErr, EMC1TxEn RejectPkt MII: Collision detection. RMII Receive error. MII: Carrier sense. RMII Carrier sense data valid. MII: Data valid. RMII Carrier sense data valid. MII, RMII, SMII: Management data clock. MII, RMII, SMII: Transfer command status information with PHY. MII: Receive clock. MII: Receive data. RMII Receive data. SMII Receive data. MII: Receive data. RMII Receive data. MII: Receive error. RMII Receive error. MII: Transmit clock. RMII SMII: Transmit clock (max 125MHz SMII). MII: Transmit data. RMII Transmit data. SMII Transmit data. MII: Transmit data. RMII Transmit data. MII: Transmit data enabled. RMII Transmit data enabled. SMII: Sync signal. MII: Transmit error. RMII Transmit data enabled. External request reject packet. 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS Description Type
Notes
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name External Slave Peripheral Interface DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr02:07 PerAddr08:31 Used PPC440EP indicate that data transfers have occurred. Used slave peripherals indicate they prepared transfer data. Transfer/Terminal Count. Peripheral address used PPC440EP when external master mode, otherwise used external master. Peripheral address used PPC440EP when external master mode, otherwise used external master. Used either peripheral controller, controller, external master indicate last transfer memory access. External peripheral device select. Peripheral data used PPC440EP when external master mode, otherwise used external master. Note: PerData00 most significant (msb) this bus. Used either peripheral controller controller depending upon type transfer involved. When PPC440EP master, enables selected device drive bus. Used peripheral slave indicate ready transfer data. Used PPC440EP when external master mode, output either peripheral controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. Otherwise, used external master input indicate direction transfer. External peripheral data byte enables. External Error. Used input record external slave peripheral errors. Multiplex Multiplex Multiplex 3.3V LVTTL 3.3V LVTTL Description Type
Notes
PerBLast PerCS0:5 PerData00:15
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
PerOE
3.3V LVTTL
PerReady
3.3V LVTTL
PerR/W
3.3V LVTTL
PerWBE0:1 PerErr
3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
Revision 1.26 April 2007
440EP PPC440EP Embedded Processor
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name External Master Peripheral Interface BusReq ExtAck ExtReq ExtReset HoldAck HoldReq HoldPri PerClk UART Peripheral Interface UARTSerClk UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RTS UARTn_RI Peripheral Interface IIC0SClk IIC0SData IIC1SClk IIC1SData IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data. 3.3V LVTTL 3.3V LVTTL Multiplex Multiplex Serial clock input that provides alternative internally generated serial clock. Used cases where allowable internally generated clock rates satisfactory. UART Receive data. UART Transmit data. UART Data Carrier Detect. UART Data Ready. UART Clear Send. UART Data Terminal Ready. UART Request Send. UART Ring Indicator. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Request. Used when PPC440EP needs regain control peripheral interface from external master. External Acknowledgement. Used PPC440EP indicate that data transfer occurred. External Request. Used external master indicate prepared transfer data. Peripheral Reset. Used external master synchronous peripheral slaves. Hold Acknowledge. Used PPC440EP transfer ownership peripheral external master. Hold Request. Used external master request ownership peripheral bus. Hold Primary. Used external master indicate priority given external master tenure. Peripheral Clock. Used external master synchronous peripheral slaves. Multiplex Multiplex Multiplex 3.3V LVTTL Multiplex Multiplex Multiplex 3.3V LVTTL Description Type
Notes
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name USB/UTMI Peripheral Interface USB2DI0:7 USB2DO0:7 USB2TxRdy USB2RxAct USB2RxDV USB2RxErr USB2LS0 USB2LS1 USB2TxVal USB2Susp USB2XcvrSel USB2TermSel USB2OM0:1 USB1HostXcvr USB1HostXcvr USB1DevXcvr USB1DevXcvr USB2Clk Unidirectional data inputs. Unidirectional data outputs. Transmit data ready. Receive active. Receive data valid. Receive error. Line state Line state Transmit valid. Suspend. Transceiver select. Termination select. Operational mode. Host differential transceiver. Device differential transceiver. Clock Requires 60MHz signal operation mode. Host Clock (48MHz) Note: used USB, must connected clock signal with frequency between 32kHz 48MHz. 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS tolerant diff xcvr tolerant diff xcvr 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS Description Type
Notes
USB1Clk
AMCC Proprietary
Revision 1.26 April 2007
440EP PPC440EP Embedded Processor
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name NAND Flash Interface NFALE NFCE0:3 NFCLE NFRdyBusy NFREn NFWEn Serial Peripheral Interface Clock output. SCPClkOut, serial port master clock out, used synchronize data movement both into device through serial data ports. Normally, data shifted rising edge clock shifted negative edge. SCPClkOut also used shift data into slave device. When SPMODE register reset, SCPClkOut forced Data Data received from connected slave device captured synchronously with SysClk. Data output. Data sent connected slave device synchronously with SysClk. Address Latch Enable. Chip Enable (multiplexed with PerCS0:3 signals). Command Latch Enable. Ready/Busy. Indicates status device during program erase page read. This signal wire-or connected from NAND Flash devices. Read Enable strobe. Write Enable strobe. Multiplex Multiplex Multiplex Multiplex Multiplex Multiplex Description Type
Notes
SCPClkOut
3.3V LVTTL
SCPDI
3.3V LVTTL
SCPDO Interrupts Interface IRQ0:4 IRQ5 IRQ6:9 JTAG Interface TRST
3.3V LVTTL
External interrupt requests through External interrupt request External interrupt requests through
3.3V LVTTL 3.3V tolerant 2.5V CMOS 3.3V LVTTL
Test Clock. Test Data Test Data Out. Test Mode Select. Test Reset.
3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name System Interface SysClk SysErr Main system clock input. when machine check generated. Main system reset. External logic drive this bidirectional (minimum cycles) initiate system reset. system reset also initiated software. Implemented open-drain output (two states; open circuit). Halt from external debugger. Processor timer external input clock. General purpose through access these functions, software must register bits. Test Enable. Receiver Inhibit. Active only when TestEn active. Used manufacturing test only. Mode Control. Active only when TestEn active. Used manufacturing test only. Leakage Test. Active only when TestEn active. Used manufacturing test only. Reference Enable. Active only when TestEn active. Used manufacturing test only. Driver Inhibit. Active only when TestEn active. Used manufacturing test only. Driver Inhibit. Active only when TestEn active. Used manufacturing test only. Module characterization screening. test purposes only. down specified Note normal operation. Clock 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V LVTTL 3.3V tolerant 2.5V CMOS Multiplex 3.3V LVTTL Multiplex Multiplex Multiplex Multiplex 3.3V tolerant 2.5V CMOS 3.3V LVTTL Perf screen ring Description Type
Notes
SysReset
Halt TmrClk GPIO00:63 TestEn RcvrInh ModeCtrl LeakTest RefEn DrvrInh1 DrvrInh2 PSROOut
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Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis Must pull (recommended value 3.3V) Must pull down (recommended value used, must pull (recommended value 3.3V) used, must pull down (recommended value Strapping input during reset; pull-up pull-down required
Signal Name Trace Interface TrcBS0:2 TrcClk TrcES0:4 TrcTS0:6 Power OVDD SVDD AVDD AGND SAVDD SAGND 1.5V supply-Logic voltage. 3.3V supply-I/O (except SDRAM, Ethernet). 2.5V supply-SDRAM, Ethernet. Ground. 1.5V-Filtered voltage system PLLs (analog). (analog) voltage ground. 1.5V-Filtered voltage memory (analog). (analog) memory voltage ground. Trace branch execution status. Trace data capture clock, runs frequency processor. Trace Execution Status presented every fourth processor clock cycle. Additional information trace execution branch status. 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOSL 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS Description Type
Notes
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Device Characteristics
Table Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device. None performance specification contained this document guaranteed when operating these maximum ratings.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O, except SDRAM, Ethernet) Supply Voltage (SDRAM, Ethernet) Supply Voltage SDRAM Supply Voltage Input Voltage (3.3V LVTTL receivers) Storage Temperature Range Case temperature under bias Notes: OVDD 0.4V, required that 0.4V. Supply excursions meeting this criteria must limited less than 25ms duration during each power power down event. analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440EP. separate filter, shown below, recommended each voltage: ferrite bead chip, Murata BLM21PG600SN1 AVDD, SAVDD Symbol OVDD SVDD AVDD SAVDD TSTG Value +1.65 +3.6 +2.7 +1.65 +1.65 +3.6 +150 +120 Unit Notes
ceramic
This value specification operational temperature range, stress rating only.
Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Supply Voltage SDRAM Supply Voltage Supply Voltages SDRAM Voltage SDRAM Reference Voltage
Symbol OVDD SVDD AVDD SAVDD SVREF
Minimum +1.4 +3.0 +2.3 +1.4 +1.4 +1.15
Typical +1.5 +3.3 +2.5 +1.5 +1.5 +1.25
Maximum +1.6 +3.6 +2.7 +1.6 +1.6 +1.35
Unit
Notes
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Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Input Logic High (2.5V SSTL) Input Logic High (2.5V CMOS, 3.3V tolerant receiver)
Symbol
Minimum SVREF+0.18
Typical
Maximum SVDD+0.3
Unit
Notes
Input Logic High (3.3V PCI) Input Logic High (3.3V LVTTL) Input Logic (2.5V SSTL) Input Logic (2.5V CMOS, 3.3V tolerant receiver) Input Logic (3.3V PCI) Input Logic (3.3V LVTTL) Output Logic High (2.5V SSTL) Output Logic High (2.5V CMOS, 3.3V tolerant receiver) Output Logic High (3.3V PCI) Output Logic High (3.3V LVTTL) Output Logic (2.5V SSTL) Output Logic (2.5V CMOS, 3.3V tolerant receiver) Output Logic (3.3V PCI) Output Logic (3.3V LVTTL) Input Leakage Current pull-up pull-down) Input Leakage Current Pull-Down Input Leakage Current Pull-Up Input Allowable Overshoot (3.3V LVTTL) Input Allowable Undershoot (3.3V LVTTL) Output Allowable Overshoot (3.3V LVTTL) Output Allowable Undershoot (3.3V LVTTL) Case Temperature: 333MHz, 400MHz, 533MHz parts package 667MHz parts E-PBGA package 667MHz parts TE-PBGA package. Notes: drivers meet specifications. SVREF SVDD/2 analog voltages used on-chip PLLs derived from logic voltage, must filtered before entering PPC440EP. "Absolute Maximum Ratings" page IIL1 IIL2 IIL3 VIMAO VIMAU VOMAO VOMAU3 -0.6 -0.6 +3.9 (LPDL) -150 (LPDL) 0.9OVDD +2.4 OVDD OVDD 0.55 0.1OVDD +0.4 (MPUL) (MPUL) +3.9 -0.5 +1.95 0.35OVDD +0.8 SVDD SVDD 0.5OVDD +2.0 -0.3 OVDD+0.5 +3.6 SVREF-0.18
+100
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Power Sequencing Startup sequencing power supply voltages required. However, power-down cycle must complete (OVDD below +0.4V) before power-up cycle started.
Table Input Capacitance
Parameter Group (2.5V SSTL I/O) Group (3.3V LVTTL I/O) Group (PCI I/O) Group (Receivers) Group (3.3V tolerant CMOS I/O) Group (USB) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 Maximum Unit Notes
Table Typical Power Supply Requirements
Frequency (MHz) +1.5V Supply (VDD+AVDD+SAVDD) 1.15 1.24 1.43 2.08 +2.5V Supply (SVDD) 1.15 1.15 1.15 1.15 +3.3V Supply (OVDD) 0.04 0.04 0.04 0.04 Total 2.34 2.43 2.62 3.27 Unit Notes
Notes: Typical Power based nominal voltage +1.5V max. specified Table page while running Linux test application that exercises each core with representative traffic.
Table Supply Power Dissipation
Frequency (MHz) +1.4V 0.96 1.04 1.20 1.74 +1.5V 1.15 1.24 1.43 2.08 +1.6V 1.38 1.49 1.71 2.52 Unit Notes
Notes: Power based specified table max. specified Table page while running Linux test application that exercises each core with representative traffic.
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Table Power Supply Current Loads
Parameter (1.5V) active operating current OVDD (3.3V) active operating current SVDD (2.5V) active operating current AVDD (1.5V) input current SAVDD (1.5V) active operating current Symbol IODD ISDD IADD ISADD Typical 1380 6.05 Maximum 2200 Unit Notes
Notes: "Absolute Maximum Ratings" page filter recommendations. maximum current values listed above guaranteed highest obtainable. These values dependent many factors including type applications running, clock rates, internal functional capabilities, external interface usage, case temperature, power supply voltages. Your specific application produce significantly different results. current power primarily dependent applications running internal chip functions (DMA, PCI, Ethernet, on). OVDD current power primarily dependent capacitive loading, frequency, utilization external buses. Typical current estimated 667MHz with +1.5V, OVDD +3.3V, SVDD +2.5V, +85°C, while running Linux test application that exercises each core with representative traffic. Maximum current estimated 667MHz with +1.6V, OVDD +3.6V, SVDD +2.7V, +85°C, best-case process (which drives worst-case power), while running Linux test application that exercises each core with representative traffic.
Table Package Thermal Specifications
Thermal resistance values E-PBGA TE-PBGA package follows:
Airflow ft/min (m/sec) Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink (0.51) 18.7 11.9 Resistance Value Junction-to-case thermal resistance Junction-to-board thermal resistance Notes: Case temperature, measured center case surface with device soldered circuit board. where ambient temperature power consumption. (1.02) 17.9 10.5 °C/W °C/W
Parameter
Symbol
Package
Unit
Notes
E-PBGA E-PBGA
20.0 15.3
E-PBGA E-PBGA
14.3
°C/W °C/W
TCMax TJMax where TJMax maximum junction temperature (+125°C) power consumption. preceding equations assume that chip mounted board with least signal power planes. Values table were achieved with JEDEC standard board: 114.5mm 101.6mm 1.6mm, layers. Values attached heat sink were achieved with 35mm 35mm 15mm unit (see Thermal Management below), attached with 0.1mm thickness adhesive having thermal conductivity 1.3W/mK.
Thermal Management following heat sinks were used above thermal analysis: ALPHA W35-15W (35mm 35mm x15mm) ALPHA LPD35-15B (35mm 35mm x15mm)
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heat sinks manufactured Alpha Novatech, Inc. (www.alphanovatech.com) Sapena Court, Santa Clara, 95054 Phone: 408-567-8082 Test Conditions Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized with 1.5V, +125 50pF test load shown figure right.
Output 50pF
Table Clocking Specifications
Symbol SysClk Input Frequency Period Edge stability (cycle-to-cycle jitter) High time time 33.33 nominal period nominal period 66.66 ±0.15 nominal period nominal period Parameter Units
Note: Input slew rate 1V/ns MemClkOut Clock Clock Frequency Period 83.33 22.2 Frequency Period 0.7496 1334 1.66 Frequency Period High time nominal period 133.33 nominal period
Figure Timing Waveform
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Spread Spectrum Clocking
Care must taken when using spread spectrum clock generator (SSCG) with PPC440EP. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with PPC440EP following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC440EP with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board PPC440EP peripherals impose more stringent requirements. Peripheral Clock logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. Ethernet operation unaffected. operation unaffected. Important: system designer ensure that SSCG used with PPC440EP meets above requirements does adversely affect other aspects system.
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Specifications
Table Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk input high time PCIClk input time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output time EMCTxClk input frequency MII(RMII) EMCTxClk period MII(RMII) EMCTxClk input high time EMCTxClk input time EMCRxClk input frequency MII(RMII) EMCRxClk period MII(RMII) EMCRxClk input high time EMCRxClk input time PerClk (and clock) output frequency (for ext. master sync. slaves) PerClk period PerClk output high time PerClk output time UARTSerClk input frequency UARTSerClk period UARTSerClk input high time UARTSerClk input time USB2Clk input frequency USB1Clk input frequency nominal period nominal period 2.5(5) 40(20) nominal period nominal period 2.5(5) 40(20) nominal period nominal period nominal period nominal period 2TOPB+2 TOPB+1 TOPB+1 66.66 nominal period nominal period 25(50) 400(200) 25(50) 400(200) 66.66 nominal period nominal period 1000/(2TOPB1+2ns) Units Notes
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Table Peripheral Interface Clock Timings (Continued)
Parameter TmrClk input frequency TmrClk period TmrClk input high time TmrClk input time Notes: TOPB period clock. internal clock runs frequency clock. maximum clock frequency 66.66 MHz. nominal period nominal period nominal period nominal period Units Notes
Figure Input Setup Hold Waveform
Clock
Inputs Valid
Figure Output Delay Float Timing Waveform
Clock
Outputs
High (Drive) Float (High-Z) (Drive) Valid Valid
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Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal Interface PCIAD31:00 PCIC3:0/BE3:0 PCIClk PCIDevSel PCIFrame PCIGnt0:5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0:5 PCIReset PCISErr PCIStop PCITRDY Ethernet Interface EMCCD EMCCrS EMCDV EMCMDClk EMCMDIO EMCRxClk EMCRxD0:3 EMCRxErr EMCTxClk EMCTxD0:3 EMCTxEn EMCTxErr RejectPkt Ethernet RMII Interface EMC0CRSDV EMC0RxD0:1 EMC0RxErr EMC0TxD0:1 EMC1CRSDV EMC1RxD0:1 EMC1RxErr EMC1TxD0:1 EMCRefClk 12.5 12.5 EMCRefClk EMCRefClk EMCRefClk async EMCRefClk EMCRefClk EMCRefClk 0481 0.277 EMCTxClk EMCTxClk EMCTxClk EMCRxClk EMCRxClk EMCRxClk EMCMDClk async async async MII, RMII, SMII async async PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk async PCIClk PCIClk async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
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Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal Ethernet SMII Interface EMC0RxD EMC0TxD EMC1RxD EMC1TxD EMCRefClk Internal Peripheral Interface IIC0SClk IIC0SData IIC1SClk IIC1SData SCPClkOut SCPDI SCPDO UARTSerClk UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RI UARTn_RTS USB1Clk USB1DevXcvr USB1DevXcvr USB1HostXcvr USB1HostXcvr USB2Clk USB2DI0:7 USB2DO0:7 USB2LS0:1 USB2OM0:1 USB2RxAct USB2RxDV USB2RxErr USB2Susp USB2TermSel USB2TxRdy USB2TxVal USB2XcvrSel Interrupts Interface IRQ0:9 0.05 0.02 0.05 15.3 15.3 15.3 15.3 15.3 15.3 15.3 10.3 10.3 10.3 10.2 10.2 10.2 10.2 10.2 10.2 10.2 EMCRefClk EMCRefClk EMCRefClk EMCRefClk async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
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Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal JTAG Interface TRST System Interface SysClk TmrClk SysReset Halt SysErr TestEn DrvrInh1:2 RcvrInh GPIO00:63 PSROOut Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6 10.3 10.3 10.3 10.3 10.3 10.3 async async async async async 15.3 10.2 async async async async async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) (minimum) Clock Notes
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Table Specifications-333MHz 533MHz
Notes: PerClk rising edge package with 10pF load trails internal clock approximately 1.3ns.
Input (ns) Signal Setup Time (TIS min) 11.7 11.7 11.7 Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 15.3 15.3 15.3 15.3 10.3 15.3 15.3 15.3 15.3 15.3 15.3 15.3 10.3 10.3 (minimum) 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 10.2 PerClk Clock Notes
External Slave Peripheral Interface DMAAck0:1 DMAAck2:3 DMAReq0:3 EOT0:1/TC0:1 EOT2:3/TC2:3 PerAddr02:31 PerBLast PerCS0:5 PerData00:15 PerOE PerReady PerR/W PerWBE0:1 BusReq ExtAck ExtReq ExtReset HoldAck HoldReq HoldPri PerClk PerErr NAND Flash Interface NFALE NFCE0:3 NFCLE NFRdyBusy NFREn NFWEn PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
External Master Peripheral Interface
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DDR1 SDRAM Specifications
DDR1 SDRAM controller times operation with internal clock signals generates MemClkOut0 from clock. clock internal signal that cannot directly observed. However MemClkOut0 same frequency clock signal phase with clock signal. Note: MemClkOut0 advanced with respect clock means SDRAM0_CLKTR programming register. typical system, users advance MemClkOut 90°. This depends specific application requires thorough understanding memory system general (refer SDRAM controller chapter PowerPC 440EP User's Manual). following sections, label MemClkOut0(0) refers MemClkOut0 when been phase-shifted, MemClkOut0(90) refers MemClkOut0 when been phase-advanced 90°. Advancing MemClkOut0 creates cycle setup time cycle hold time address control signals relation MemClkOut0(90). rising edge MemClkOut0(90) aligns with first rising edge signal. following data generated means simulation includes logic, driver, package RLC, lengths. Values calculated over best case worst case processes with speed, temperature, voltage follows: Best Case Fast process, -40°C, +1.6V Worst Case Slow process, +85°C, +1.4V Note: following tables timing diagrams, minimum values measured under best case conditions maximum values measured under worst case conditions. signals terminated indicated figure below timing data following sections. Figure SDRAM Simulation Signal Termination Model
MemClkOut0 10pF 10pF MemClkOut0 SVDD/2
PPC440EP
Addr/Ctrl/Data/DQS
30pF
Note: This diagram illustrates model SDRAM interface used when generating simulation timing data. recommended physical circuit design this interface. actual interface design will depend many factors, including type memory used board layout.
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Table SDRAM Output Driver Specifications
Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 DQS0:8 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 Output Current (mA) (maximum) (minimum)
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SDRAM Write Operation
following diagram illustrates relationship among signals involved with write operation. Figure SDRAM Write Cycle Timing
MemClkOut0
MemClkOut0(90)
Addr/Cmd MemData
Delay from rising edge MemClkOut0(0) rising/falling edge signal (skew) Setup time address command signals MemClkOut0(90) Hold time address command signals from MemClkOut0(90) Setup time data signals (minimum time data valid before rising/falling edge DSQ) Hold time data signals (minimum time data valid after rising/falling edge DSQ) Delay from rising/falling edge clock rising/falling edge
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Note: timing data following tables based simulation runs using Einstimer. Table Timing-DDR SDRAM
Notes: signals referenced MemClkOut0(0). Clock speed 133MHz. values table include cycle 133MHz (7.5ns 0.75 5.625 ns). obtain adjusted values lower clock frequencies, subtract 5.625 from values table cycle time lower clock frequency (TDS 5.625 0.75TCYC).
Signal Name DQS0 DQS1 DQS2 DQS3 DQS8 (ns) Minimum 5.76 5.78 5.82 5.79 5.75 Maximum 5.86 5.91 5.90 5.89 5.88
Table Timing-DDR SDRAM TSK, TSA,
Notes: Clock speed 133MHz. referenced MemClkOut0(0). referenced MemClkOut0(90). obtain adjusted values lower clock frequencies, cycle time lower clock frequency subtract maximum (0.75TCYC TSKmax). obtain adjusted values lower clock frequencies, cycle time lower clock frequency minimum (0.25TCYC TSKmin).
Signal Name MemAddr00:12 BA0:1 BankSel0:3 ClkEn0:3 (ns) Minimum 0.11 0.07 0.05 0.07 0.05 0.05 0.08 Maximum 0.32 0.31 0.25 0.28 0.31 0.28 0.22 (ns) Minimum 5.31 5.32 5.38 5.35 5.32 5.35 5.41 (ns) Minimum 1.99 1.95 1.93 1.95 1.93 1.93 1.96
Table Timing-DDR SDRAM
Notes: measured under worst case conditions. Clock speed values table 133MHz. time values table include cycle 133MHz (7.5ns 0.25 1.875 ns). obtain adjusted values lower clock frequencies, subtract 1.875 from values table cycle time lower clock frequency (e.g., 1.875 0.25TCYC).
Signal Names MemData00:07, MemData08:15, MemData16:23, MemData24:31, ECC0:7, Reference Signal DQS0 DQS1 DQS2 DQS3 DQS8 (ns) 1.795 1.775 1.745 1.765 1.685 (ns) 1.866 1.865 1.862 1.864 1.857
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SDRAM Read Operation
following examples timing SDRAM read operations based relationship between incoming data clock signal. Since clock cannot directly observed, delay MemClkOut(0) relative clock (TMD) provided. internal Read Clock signal, like MemClkOut0, derived from clock delayed relative clock programming RDCT RDCD fields SDRAM0_TR1 register. delay programmed from cycle steps using RDCT. Setting RDCD results cycle delay plus value RDCT. delay Read Clock relative clock (TRD) shown below assumes programmable Read Clock delay zero. Figure SDRAM MemClkOut0 Read Clock Delay
MemClkOut0(0) TMDmin 600ps TMDmax 1100ps
Read Clock TRDmin 300ps TRDmax 740ps Note: values assume best case conditions. values assume worst case conditions.
operation, following receipt address read command from PPC440EP, SDRAM generates data signals coincident with MemClkOut0. data latched into PPC440EP using signal that delayed cycle. order accommodate timing variations introduced system designs using this chip, three-stage data path shown below used eliminate metastability allow data sampling adjusted minimum latency. This adjustment requires programming Read Clock delay selection Stage Stage Stage data sampling RDSP.
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Figure SDRAM Read Data Path
Package pins
RDSP
Stage
Stage
Stage
Data
Cycle Delay Clock
Programmed Read Clock Delay
Read Select (SDRAM0_TR1)
Timing: Input setup time 0.2ns Input hold time 0.1ns Propagation delay 0.4ns maximum
Flip-Flop Transparent Latch
Table Timing-DDR SDRAM TSIN TDIN
Notes: TSIN Delay from package Stage TDIN Delay from data package Stage Clock speed values table 133MHz. time values TSIN include cycle 133MHz (7.5ns 0.25 1.875 ns).
Signal Name DQS0 DQS1 DQS2 DQS3 DQS8 TSIN (ns) minimum 2.74 2.75 2.74 2.76 2.77 TSIN (ns) maximum 3.70 3.69 3.69 3.69 3.68 Signal Name MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 TDIN (ns) minimum 0.86 0.87 0.89 0.88 0.89 TDIN (ns) maximum 1.87 1.86 1.86 1.85 1.83
following examples, data strobes (DQS) data shown coincident. There actually slight skew specified SDRAM specifications, there additional skew loading signal routing. recommended that signal length eight signals matched.
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Example data-to-PLB clock timing shown example below, then read clock delayed Stage data sampled (1). Except small, frequency memory systems with memory located physically close PPC440EP, unlikely that Stage data sampled. When data comes later, necessary sample Stage Stage data. (see Examples Another desired data-to-PLB timing allow Stage sampling buffer MemClkOut0 skew enough guarantee timing. this example, system dependent taken into account controller initialization software. Figure SDRAM Read Cycle Timing-Example
Data TSIN Stage
Data Stage TDIN
High
Data Stage
Data RDSP with
High
Clock
High Data RDSP
TSIN Delay from package Stage Propagation delay through TDIN Delay from data package Stage Propagation delay, Stage input RDSP input
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Example this example Read Clock delayed almost cycle. Without ECC, Stage data sampled (2). enabled, Stage data must sampled (see Example this example, system dependent taken into account controller initialization software. Figure SDRAM Read Cycle Timing-Example
Data TSIN
Stage Data Stage TDIN
High Data Stage
Clock Read Clock Delayed High Data Stage High Data RDSP with High
Data RDSP without
Data RDSP without
High
Propagation delay from Stage input RDSP input Propagation delay from Stage input RDSP input with
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Example this example, enabled. This requires that Stage data sampled (3). disabled, system will still work, there will more latency before data sampled into RDSP. this example, system dependent taken into account controller initialization software. Figure SDRAM Read Cycle Timing-Example
Data TSIN
Stage Data Stage TDIN
High Data Stage
Clock Read Clock Delayed High Data Stage High Data RDSP with High
Data Stage with
Data RDSP with
High
Propagation delay from Stage input RDSP input Propagation delay from Stage input RDSP input with
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Initialization
PPC440EP provides option setting initial parameters based default values reading them from slave PROM attached IIC0 (see "EEPROM" below). Some default values altered strapping external pins (see "Strapping" below).
Strapping
While SysReset input (system reset), state certain pins read enable certain default initial conditions prior PPC440EP start-up. actual capture instant nearest reference clock edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. These pins used strap functions only during reset. Following reset they used normal functions. signal names assigned pins normal operation shown parentheses following number. following table lists strapping pins along with their functions strapping options:
Table Strapping Assignments
Ball Strapping Function Option (UART0_DCD) (UART0_DSR) (UART0_CTS)
Serial device disabled. Each options combination boot source, boot-source width, clock frequency specifications. Refer Bootstrap Controller chapter PPC440EP Embedded Processor User's Manual details.
Serial device enabled. option being selected IIC0 slave address that will respond with configuration data. Note: reading configuration data from serial device fails, PPC440EP defaults configuration
(0xA8)
(0xA4)
EEPROM
During reset, initial conditions other than those obtained from strapping pins read from device connected IIC0 port. de-assertion reset, bootstrap controller enabled, PPC440EP sequentially reads bytes from device IIC0 port sets SDR0_SDSTP0, SDR0_SDSTP1, SDR0_SDSTP2 SDR0_SDSTP3 registers accordingly. initialization settings their default values covered detail PowerPC 440EP User's Manual.
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Revision
Date 08/21/2003 09/22/2003 10/07/2003 10/13/2003 10/31/2003 11/03/2003 11/25/2003 12/15/2003 12/19/2003 01/12/2004 Version Initial creation document. Misc. updates corrections. Misc. updates corrections. timing. Miscellaneous updates. Correct initialization strapping pins response interface. Correct OVDD SVDD assignments. Delete heat sink mounting information placeholders remove Confidential status. Restore Confidential status. Update SDRAM interface timing section. Correct MemClkOut0 assignment. Correct SDRAM voltage. Note UARTn_CTS signal. Correct SDRAM worst case spec temperature. Change 333MHz 400MHz. Correct label Ethernet transmit signals. Convert AMCC format. Modify headers flip between left right pages like footers. Change part numbers AMCC part numbers. Remove Confidential status, again clock frequency numbers. Number table figure captions. Correct block diagram description. Update formatting book marking. missing SDRAM timing data. Miscellaneous updates. RejectPkt signal Y25. Issue Corrected numbering PCIReq signal. Issue Added notes signals correctly define required pull-ups pull-downs. Issue Correct typo voltage specification SAVDD Power Supply Loads table. Issue Misc. typo corrections. Issue 11/19/2004 11/22/2004 12/17/2004 Change bootstrap option numbers letters options. Correct bootstrap settings match letter designations. Revision part numbers both leaded lead-free packages tape-and-reel shipping. input capacitance values. Update missing voltage supply currents. Update SDRAM timing. Change circuit type info some system interface signals move RejectPkt Ethernet group. Contents Modification
03/15/2004
04/7/2004 09/2/2004
09/8/2004
09/28/2004
10/06/2004 10/12/2004 10/28/2004
11/18/2004
01/18/2005 01/31/2005 02/08/2005
AMCC Proprietary
Revision 1.26 April 2007
440EP PPC440EP Embedded Processor
Data Sheet
Date 02/15/2005 03/10/2005 03/25/2005 04/27/2005 05/24/2005 06/14/2005 07/06/2005 08/08/2005 10/05/2005 1.20 Version Miscellaneous updates Miscellaneous updates Correct timing specs ExtReq signal. SDRAM timing updates. RoHS compliance statement. Updates additions power thermal specifications. 667MHz remove 466MHz PNs. Change maximum NAND Flash 256MB. Change solder ball size specification thermally enhanced package specification. Miscellaneous updates Remove metal-layer specification from technology description. Change default configuration when bootstrap read fails from option configuration package nomenclature. Correct MemClkOut duty cycle. Correct move PerErr signal description from master slave. Change maximum freqruency 1334MHz. revision level part number number. Update power dissipation additional temperature data. Correct enable/disable specifications Gnt/Req signals. Change analog voltage filter circuit inductor part number. Change multiplexed GPIO signal defaults GPIO signals. Change AC12 default from IRQ5 DMAReq1. Correct descriptions LeakTest, RcvrInh, ModeCtrl, RefEn, DrvrInh1:2 signals Remove "Preliminary" status from header. Remove thermally enhanced package. Contents Modification
11/18/2005
1.21
02/16/2006 05/24/2006 07/19/2006
1.22 1.23 1.24
12/18/2006
1.25
04/25/2007
1.26
AMCC Proprietary
440EP PPC440EP Embedded Processor
Revision 1.26 April 2007
Data Sheet
Printed United States America, April 2007 following trademarks AMCC Corporation United States, other countries, both: AMCC Other company, product, service names trademarks service marks others. April 2007 This document contains information product under development AMCC. AMCC reserves right change discontinue this product without notice. This document preliminary edition PowerPC 440EP data sheet. Make sure using correct edition level product. While information contained herein believed accurate, such information preliminary, should relied upon accuracy completeness, representations warranties accuracy completeness made. information contained this document subject change withdrawal time without notice being provided basis without warranty indemnity kind, whether express implied, including without limitation, implied warranties non-infringement, merchantability, fitness particular purpose. products, services, programs discussed this document sold licensed under AMCC's standard terms conditions, copies which obtained from your local AMCC representative. Nothing this document shall operate expressed implied license indemnity under intellectual property rights AMCC third parties. Without limiting generality foregoing, performance data contained this document determined specific controlled environment submitted formal AMCC test. Therefore, results obtained other operating environments vary significantly. Under circumstances will AMCC liable damages whatsoever arising resulting from document information contained herein.
AMCC Proprietary
Revision 1.26 April 2007
440EP PPC440EP Embedded Processor
Data Sheet
Applied Micro Circuits Corporation Moffett Park Drive, Sunnyvale, 94089 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products, data sheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available data sheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered Trademark Applied Micro Circuits Corporation. Copyright 2007 Applied Micro Circuits Corporation.
AMCC Proprietary
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