405EZ PowerPC 405EZ Embedded Processor AMCC PowerPC® 32-bit
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Part Number 405EZ Revision 1.27 August 2007
405EZ
PowerPC 405EZ Embedded Processor
AMCC PowerPC® 32-bit RISC processor core operating 416MHz On-chip 32-bit peripheral (OPB) operating On-chip 64-bit processor local (PLB) operating 166MHz 8-bit direct interface NAND Flash devices 32KB on-chip, high-speed SRAM accessible Inter-chip connectivity (SPI IIC)
Preliminary Data Sheet
IEEE 1588 Precision Timing Protocol (PTP) controller Chameleon Timerand pulse width modulator (PWM) Analog-to-Digital Converter (ADC) with eight inputs 10-bit resolution 300k samples/sec Digital-to-Analog Converter (DAC) with input 10-bit resolution samples/sec 2.0B protocol 11898-1 compliant channels serial ports (16750 compatible UART)
External 8-,16-, 32-bit peripheral (EBC) operating 83MHz Boot from bootstrap controller, EBC, NAND Flash, support on-chip slaves external bus, including on-chip SRAM, ADC, DAC, UARTs, devices external peripheral 10/100 Mbps Ethernet interface (half- full-duplex) external Three ports: Host Device with Full-Speed on-chip PHYs Programmable universal interrupt controller (UIC)
interface operating 400kHz supporting standard EEPROMs (SCP) synchronous full-duplex channel operating general purpose I/Os (GPIOs), each with programmable interrupts outputs Supports JTAG board-level testing System power management, power dissipation small form factor RoHS compliant (lead-free)
Description
With speeds 416MHz, flexible on-chip offchip memory architecture, combination ADC, DAC, programmable Chameleon Timer/PWM, IEEE 1588 PTP, diverse communications package that includes 1.1, Ethernet, CAN, PowerPC 405EZ embedded processor provides power small footprint system-on-a-chip solution wide range high performance, costconstrained embedded applications. This includes industrial control, high-precision AC/DC servo drive control, instrumentation, data acquisition, industrial automation, building enclosure management, commercial retail systems, Internet
AMCC Proprietary
appliances, intelligent peripherals. easily programmable general purpose, 32-bit RISC controller that offers upgrade path applications need performance connectivity improvements. Technology: CU-11 CMOS, 130nm Package: 324-ball, lead-free, plastic ball grid array (EPBGA), ball pitch Typical Power (Est.): 1.05W MHz;1.48W
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Contents
Features Description Table Contents List Figures List Tables Ordering, PVR, JTAG Information Address Maps Power Processor Core Internal Buses On-Chip Memory (OCM) Controller External Controller NAND Flash Controller Controller Interface Controller Area Network (CAN) UART Interface Serial Peripheral Interface (SPI/SCP) Chameleon Timer General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) 10/100 Ethernet IEEE 1588 Precision Timing Protocol Controller Analog-to-Digital Converter (ADC) Digital-to-Analog Converter (DAC) JTAG Signal Lists Signal Functional Descriptions Ratings Specifications Spread Spectrum Clocking Initialization
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
List Figures
Figure PPC405EZ Embedded Controller Functional Block Diagram Figure 23mm, 324-Ball EPBGA Core Figure Clocking Waveform Figure Input Setup Hold Timing Waveform Figure Output Delay Float Timing Waveform
List Tables
Table System Memory Address (4GB System Memory) Table Address Table Signals Listed Alphabetically Table Signals Listed Ball Assignment Table Groups Table Signal Functional Description Table Absolute Maximum Ratings Table Package Thermal Specifications Table Recommended Operating Conditions Table Input Capacitance Table Typical Power Supply Requirements Table Power Supply Loads Table System Clocking Specifications Table Peripheral Interface Clock Timings Table Specifications-All Speeds Table Specifications-416 Table Strapping Assignments
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Ordering, PVR, JTAG Information
This section provides part number nomenclature. availability, contact your local AMCC sales office.
Order Part Number (see Notes:) PPC405EZ-CSAfffTx Level
Product Name PPC405EZ Notes:
Package 23mm, 324-ball, EPBGA
Value 0x41511460
JTAG 0x0405A1E1
enabled Lead-free EPBGA package (RoHS compliant) Chip revision level Processor frequency 166MHz 266MHz 333MHz 416MHz Case temperature range, -40°C +105°C Shipping package type tape-and-reel blank tray
part number contains part modifier. Included modifier revision code. This refers mask revision number specified part numbering scheme identification purposes only. (Processor Version Register) JTAG register software accessible (read-only) contain information that uniquely identifies part. PPC405EZ Embedded Processor User's Manual details about accessing these registers. Order Part Number
PPC405EZ-CSA416TZ
Shipping Package AMCC Part Number
Case Temperature Range Processor Speed (MHz)
enabled
Package
Revision Level
Note: example above enabled, lead-free, capable running 416MHz, shipped tape-and-reel packaging.
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Block Diagram
Figure PPC405EZ Embedded Controller Functional Block Diagram
Universal Interrupt Controller
Clock Control Reset
Power Mgmt
32KB SRAM
Timers PowerPC Core JTAG
D-OCM I-OCM DCRs
Ctrl UART Arbiter On-chip Peripheral (OPB) IIC/ GPIO Timer/ (SCP)
Trace
16KB D-Cache 16KB I-Cache Controller (4-Channel) OPB/PLB Bridges Ethernet 10/100 Host/Dev IEEE 1588
Arbiter
Processor Local (PLB) bit, PLB3 External Controller NAND Flash Controller
PPC405EZ designed using Microelectronics Blue Logicmethodology which major functional blocks integrated together create application-specific ASIC product. This approach provides consistent create complex ASICs using CoreConnectBus Architecture.
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Address Maps
PPC405EZ incorporates address maps. first address defines possible addressable memory regions that processor access. second address defines Device Configuration Register (DCR) addresses (numbers). DCRs accessed software running PPC405EZ processor through mtdcr mfdcr instructions. Table System Memory Address (4GB System Memory)
Function General Reserved UART Registers UART Registers Registers Arbiter Registers GPIO Controller Registers GPIO Controller Registers EMAC Registers Reserved Registers Registers Chameleon Timer Registers IEEE 1588 Sync Controller Registers Host Registers Reserved Registers Registers Serial Communication Port Registers Reserved Device Registers Reserved Boot Address Range Notes: peripheral boot selected, peripheral bank automatically configured reset address range listed above. After boot process, software reassign boot memory regions other uses. Subfunction Start Address 0000 0000 E000 0000 EF60 0300 EF60 0400 EF60 0500 EF60 0600 EF60 0700 EF60 0800 EF60 0900 EF60 0A00 EF60 1000 EF60 1800 EF60 2000 EF60 2800 EF60 3000 EF60 3200 EF60 3300 EF60 3400 EF60 3500 EF60 3600 EF64 0000 EF68 0000 FFE0 0000 Address DFFF FFFF EF60 02FF EF60 03FF EF60 04FF EF60 05FF EF60 06FF EF60 07FF EF60 08FF EF60 09FF EF60 0FFF EF60 17FF EF60 1FFF EF60 27FF EF60 2FFF EF60 31FF EF60 32FF EF60 33FF EF60 34FF EF60 35FF EF63 FFFF EF67 FFFF FFDF FFFF FFFF FFFF 262KB 256B 256B 256B 512B 256B 256B 256B 256B 256B 256B 256B Size 3.7GB
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Address
Function Total Address Space Reserved Reserved Reserved Controller Reserved Arbiter Reserved PLB-to-OPB Bridge Reserved OPB-to-PLB Bridge Reserved Reserved Reserved IEEE 1588 Snapshot Source Reserved Reserved Notes: address bits (1024 unique addresses). Each unique address represents single 32-bit (word) register, kiloword (KW) (which equals KB).
Start Address 0x000 0x000 0x00C 0x00E 0x010 0x012 0x014 0x020 0x030 0x080 0x090 0x0A0 0x0A8 0x0B0 0x0B4 0x0B8 0x0BC 0x0C0 0x0D0 0x0E0 0x0F0 0x100 0x140 0x380
Address 0x3FF 0x00B 0x00D 0x00F 0x011 0x013 0x01F 0x02F 0x07F 0x08F 0x09F 0x0A7 0x0AF 0x0B3 0x0B7 0x0BB 0x0BF 0x0CF 0x0DF 0x0EF 0x0FF 0x13F 0x2FF 0x3FF
Size (4KB)1 578B 128B
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Power Processor Core
PPC405 core fixed-point, 32-bit RISC processor. Features include: Five-stage pipeline with single-cycle execution most instructions, including loads stores Separate, configurable I-caches, both 2-way associative Thirty-two 32-bit general purpose registers (GPRs) Unaligned load/store support Hardware multiply/divide Parity detection reporting instruction cache, data cache, translation look-aside buffer (TLB) Double word instruction fetch from cache Translation logical address space into physical addresses On-chip memory (OCM) interface Built-in timer debug support Power management 32-bit interface
Internal Buses
PPC405EZ contains three internal buses: on-chip peripheral (OPB), processor local (PLB), device control register (DCR) bus. High bandwidth devices such processor core utilize PLB. Lower bandwidth interfaces such communications timer interfaces utilize OPB. provides 32-bit address data interfaces, operates 83MHz. There bridge between PLB. Features include: Pipelined read support Dynamic sizing Single-cycle data transfer between masters slaves Processor Local (PLB) high-performance on-chip used connect PLB-equipped master slave devices PPC405 CPU. provides 64-bit data path with 32-bit addressing operates to166MHz. There bridge between OPB. Features include: Overlapping read write transfers Decoupled address data buses Address pipelining Late master request abort capability Hidden (overlapped) request/grant protocol arbitration-locking mechanism Byte-enable capability allows unaligned half word transfers transfers Support 16-, 32-, 64-B line data transfers Read word address capability Sequential burst protocol Guarded unguarded memory transfers buffered, flyby, peripheral-to-memory, memory-to-peripheral, memory-to-memory operations
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
daisy-chained provides path passing status control information between processor core other on-chip cores. DCRs bits width.
On-Chip Memory (OCM) Controller
controller connects 405EZ processor core non-overlapping banks single-port, on-chip, configurable 32KB SRAM memory. also transfer data between internal SRAM banks. Features include: Simultaneous PLB3, instruction-Side data-Side access slave cycles support: 64-bit slave attachment addressable master Single-beat read write bytes) 16-word line read write Double word word read write bursts Slave-terminated double word word bursts Master-terminated variable length bursts Data parity generation checking Read/Write protection bank Instruction side interface supports: One-Wait state access with 1-deep write buffer Data parity checking Data side interface supports: One-wait state access with 1-deep write buffer Data parity generation checking Read/Write protection bank Processor side data port highest access priority (maintains predictable memory accesses OCM)
External Controller
external controller (EBC) transfers data between external memory peripheral devices attached external peripheral bus. provides direct attachment memory devices such SRAM, device paced memory devices, peripheral devices. Features include: speed 16-, 32-bit data bus, 28-bit address eight chip selects Arbitration multi-master supported Flash interface Boot from (including NAND Flash interface) support Direct support 8-,16-, 32-bit SRAM external peripherals CRAM/PSRAM support
NAND Flash Controller
NAND Flash controller (NDFC) provides simple interface between External Controller (EBC) variety NAND Flash-based storage devices. Features include: Attachment internal slave device (refer PPC405EZ Embedded Processor User's Manual
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
more details) Direct 8-bit interfacing discrete NAND Flash devices four banks NAND Flash supported Device size 4MB-256MB (32Mb 2Gb) supported 512B device page sizes supported generation hamming code, single-bit correction, double-bit detection (SEC/DED) Eight-bit command write, address write, data read/write Interrupt device ready (after long page write block erase operations) Boot from NAND Executes boot code first block Automatic page read accesses performed based device configuration read address
Controller
Direct Memory Access (DMA) controller Processor Local (PLB) master that enables faster data transfer between memory peripherals than possible under program control. 4-channel controller handles data transfers between memory peripherals from memory-to-memory. Each channel independent registers needed data transfer: control register, source address register, destination address register, transfer count register. Features include: Memory-to-memory transfers Buffered memory-to-peripheral transfers Buffered peripheral-to-memory transfers Four independent channels Scatter/gather capability dynamically programming multiple transfers Programmable address increment decrement Internal data buffering transfer data to/from slave, including external
Interface
support provides separate Host Device interfaces compliant with USB1.1 Specification Features include: USB1.1 Host ports) Compliant with Specification OHCI version 1.0a Host Controller Specification Compatible with Full-Speed peripherals Supports Low-Speed (1.5Mbps) operation transfer types (Isochronous, Interrupt, Control, Bulk) supported FIFOs: 16-entries 32-bits each Independent 32-bit master slave interfaces (master slave operate asynchronously) Programmable slave base address connected devices supported USB1.1 Device port) Full- Low-Speed device controller 32-bit, slave interface Three Endpoints supported (Endpoint used control) Endpoints OUT, OUT, IN/OUT programmable Endpoints configurable support Interrupt/Bulk only, Isochronous only, Interrupt/Bulk Isochronous (programmable) transfer types Endpoints configurable support maximum packet size bytes Endpoint configurable support maximum packet size bytes Full Speed Mbps) each ports Tolerates shorting 5.25V shorting ground driving signal conditions meet those specified
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Universal Serial Specification
Controller Area Network (CAN)
controller module supports concept mailboxes. contains receive buffers, each with message filter, transmit buffers with prioritized arbitration scheme. optimal support Higher Level Protocols (HLP) such DeviceNet SDC, message filter covers first data bytes. Features include: 2.0B protocol compliant 11898-1 compliant Transmit message holding registers, programmable priority arbitration Message abort command supported Receive buffers (each with message filter) Message filtering: IDE, Remote Transmission Request (RTR), data byte data byte Message buffers linked together build bigger message arrays Automatic response handler Message Abort command supported Maximum baud rate 1Mbps with 8MHz system clock Listen-only debugging supported Global masking supported 32-bit slave interface Internal loopback
UART
Universal Asynchronous Receiver/Transmitter (UART) interface provides ports. UART performs serial-to-parallel conversion data received from peripheral device modem, parallel-to-serial conversion data received from processor. Features include: ports (UART_0 UART_1) Software modem control functions (CTS, RTS, DSR, DTR, DCD) UART_0 Programmable auto flow (data flow controlled signals) 8-bit characters Programmable start, stop, parity insertion byte FIFOs buffer data sub-bus specification compliant line break generation/detection false start detection Programmable internal/external loopback capabilities Power Sleep mode Register conformance (after reset) configuration NS16450 register Hold shift registers (eliminate need precise synchronization between processor serial data character mode) Complete status reporting Full prioritized interrupt system controls Independently controlled transmit, receive, line status, data interrupts Programmable baud generator (divides serial clock input generates clock) Ability add/delete standard asynchronous communication bits such start, stop, parity to/from serial data Even, odd, no-parity generation detection 1.5-, 2-stop generation Variable baud rate Internal diagnostic capability
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PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Loopback controls isolating communications link faults Break, parity, overrun, framing error simulation interface with optional support
Interface
Inter-Integrated Circuit (IIC) interface provides Philips I2C® compatible interface operating 400kHz either master, slave, both with bootstrap controller (BSC) included. During chip reset, bootstrap controller read configuration data from compatible memory device (e.g., EEPROM). This data used replace default configuration settings provided chip. Features include: channel Compliant with Philips Semiconductors Specification, dated 1995 operation 8-bit data 7-bit address Slave Transmit Receive Master Transmit Receive Multiple masters supported Programmable master, slave, master/slave Boot parameters read from attached memory with bootstrap controller 32-bit slave interface
Serial Peripheral Interface (SPI/SCP)
Serial Peripheral Interface (SPI) (also known Serial Communications Port SCP) full-duplex, synchronous, character-oriented (byte) port that allows exchange data with other serial devices. master serial port supporting 3-wire interface (receive, transmit, clock), slave OPB. Features include: SPI/SCP channel, full duplex synchronous SPI/SCP master Programmable internal loopback capabilities Multi-master protocol supported Independent masking interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, receive FIFO overflow) Dynamic control serial rate data transfer (serial-master mode only) Data Item size each data transfer under programmer control (4-to-16 bits) Boot from supported 32-bit slave interface
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Chameleon Timer
Chameleon Timer's Timer Service Engine (TSE) controls local Timer configured 32-bit words fifteen 24-bit timer channels, each with Input Capture Register Output Compare Register. Chameleon Timer interfaces OPB. Features include: Pulse Width Modulation (PWM) space vector functions with non-overlap times Programmable "deadband" intervals Pulse period measurement 48-bit input capture function 48-bit output compare function IEEE1588 time stamps Automatic down, up-then-down counting with modulus Autonomous Timer Service Engine (TSE) manages timer channels programs "registers" Timer SRAM (120x32 bits) timer channels timebase channel Pulse period measurements Configurable seven 48-bit channels 24-bit channels timebases available simultaneously Each time base four optional sources: three internal (Timebase Timebase IEEE1588) external Speed/resolution: 166MHz counter, 2-clock (20ns) minimum period Latency: 0.49sec worst case (based 133MHz system clock) External "Fault" automatically disable timer channel outputs switching noise Unused Timer pins available GPIO 32-bit slave interface
General Purpose (GPIO) Controller
GPIO controller enables multiplexing module pins with multiple functions within chip. That single package assigned multiple functions. Which function assigned determined register settings controlled software. This significantly reduces number package pins needed support multiple groups. Features include: GPIOs available GPIOs multiplexed with alternate functions dedicated functions, I/Os available GPIOs Direct control functions from registers programmed means master accesses Time multiplexing controller outputs module outputs Programmable conversion module outputs open-drain outputs (enables sharing active outputs externally) Time multiplexing module inputs controller inputs
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Universal Interrupt Controller (UIC)
Universal Interrupt Controller (UIC) provides control, status, communications necessary between various sources interrupts PPC405 processor. Features include: interrupt sources supported external) Generate interrupt level (high low) edge (rising falling) Programmable synchronous (edge-capture level-sensitive) asynchronous (edge- level-sensitive triggering) Each interrupt source/bit programmable critical critical 32-bit interface Optional interrupt handler vector generation Programmable vector base address Programmable vector offset size Programmable interrupt priority ordering Programmable polarity interrupt types Interrupts same type need contiguous positions Status registers provide: current state interrupts, current state enabled interrupts
10/100 Ethernet
Ethernet support provides single 10/100 Mbps interface. Features include: ANSI/IEEE Std. 802.3 IEEE 802.3u supplement compliant Half-duplex full-duplex supported interface external byte receive FIFOs with programmable thresholds control transmit/receive packets Multiple packet handling transmit receive FIFOs Unicast, multicast, broadcast, promiscuous address filtering 64-bit hash filters unicast multicast frames Automatic retransmission collided frames Runt frame rejection Programmable inter-frame IEEE 802.3x compliant frame-based flow control mechanism, including self-assembled control frame transmitting) Wake-on-LAN Power-over-Internet supported Programmable internal/external loopback capabilities 32-bit slave (MAC) master (MAL) interfaces Extensive error/status vector generation each processed packet VLAN supported (according IEEE Draft 802.3ac/D1.0 standard) Programmable automatic source address inclusion/replacement transmit packets Programmable automatic Pad/FCS stripping receive packets Programmable VLAN inclusion/replacement transmit packets
IEEE 1588 Precision Timing Protocol Controller
distributed control system containing multiple clocks, this feature defines messages used exchange timing information precision network synchronization purposes. second PPC405EZ dedicated generating snapshot triggers IEEE 1588 controller from interrupt source chip.
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Analog-to-Digital Converter (ADC)
mixed-signal core. uses successive approximation (binary search) conversion technique achieve minimal conversion time. analog input range 0.0V Vref. Features include: Internal 10-bit resolution Sample hold Support multiple conversion times such 3.25 with 4-MHz input clock with 250-kHz input clock Comparator Digital controller 8-channel analog input (3.3 with analog multiplexer 10-bit parallel digital outputs Input trigger from Chameleon Timer supported interface with optional support
Digital-to-Analog Converter (DAC)
1-channel converter, optimized power applications. provides unbuffered single-ended analog current output. single analog current output tied directly output resistor provide twoscomplementary, single-ended voltage outputs. Features include: 10-bit resolution samples/sec Segmented Single-ended current outputs (6mA maximum swing 3.3V) Monotonicity ensured Straight binary input Internal bandgap voltage reference Power management means Sleep Mode Integrated functional test logic Input trigger from Chameleon Timer supported interface with optional support
JTAG
Features include: IEEE 1149.1 test access port JTAG Boundary Scan Description Language (BSDL) Refer list AMCC partners supplying probes with JTAG interface.
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Figure 23mm, 324-Ball EPBGA Core
Gold Gate Release Corresponds Ball Location
View
Logo View
Part Number Number
PPC405EZ
1YWWBZZZZZ
Epoxy Mold Compound Substrate
2.65
23.0
Bottom View
21.0
23.0
0.60 SOLDERBALL
Notes: dimensions Package lead-free (RoHS compliant) Package conforms JEDEC SPEC.MS-034
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Signal Lists
following table lists external signals alphabetical order shows ball (pin) number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal brackets. Multiplexed signals appear alphabetically multiple times list-once each signal name ball. Page column indicates page within table "Signal Functional Description" page which signals indicated interface group begin. Table Signals Listed Alphabetically (Sheet
Signal Name ADC_AGND ADC_AVDD ADC_In0 ADC_In1 ADC_In2 ADC_In3 ADC_In4 ADC_In5 ADC_In6 ADC_In7 ADC_InTrig[TS6][GPIO109] ADC_VRef BusReq[GPIO007] CAN0_Rx CAN0_Tx CAN0_TxE CAN1_Rx CAN1_Tx CAN1_TxE CRAM_AdV[GPIO010] CRAM_Clk[GPIO008] DAC_AGND DAC_AVDD DAC_CRef DAC_GRef DAC_IOutP DAC_IPTrig[TS5][GPIO108] DAC_IRRef DAC_VRef DebugEn DMAAck[GPIO027] DMAEOT/TC[GPIO026] DMAReq[GPIO025] EMCCOL EMCCRS EMCMDC EMCMDIO Ball AB07 AB08 AA01 AB02 AB03 AB04 AB06 Ethernet External Peripheral System Digital Analog Converter (DAC) External Peripheral Power Controller Area Network External Peripheral Analog Digital Converter (ADC) Power Interface Group Page
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name EMCRxClk EMCRxDv EMCRxD0 EMCRxD1 EMCRxD2 EMCRxD3 EMCRxEr EMCTxClk EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn EMCTxEr Ball Ethernet Ethernet Interface Group Page
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power Interface Group Page
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball AA02 AA04 AA05 AA21 AB01 AB05 AB09 AB14 AB18 AB22 Power Interface Group Page
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [GPIO000]PerCS4 [GPIO001]PerCS5[NFCE1] [GPIO002]PerCS6[NFCE2] [GPIO003]PerCS7[NFCE3] [GPIO004]HoldReq [GPIO005]HoldPri [GPIO006]HoldAck [GPIO007]BusReq [GPIO008]CRAM_Clk [GPIO009]PerReady [GPIO010]CRAM_AdV [GPIO011]NFCLE [GPIO012]NFData7 [GPIO013]NFData6 [GPIO014]NFData5 [GPIO015]NFData4 [GPIO016]NFData3 [GPIO017]NFData2 [GPIO018]NFData1 [GPIO019]NFData0 [GPIO020]NFALE [GPIO021]NFCE0 [GPIO022]NFRE [GPIO023]NFWE [GPIO024]NFRB [GPIO025]DMAReq [GPIO026]DMAEOT/TC [GPIO027]DMAAck [GPIO028]PWM_OE1[TS1O] [GPIO029]PWM_OE2[TS2O] [GPIO030]PWM_OE3[TS3] [GPIO031]PWM_8 Ball AA03 AA06 AA07 AA08 AA09 AA10 System Interface Group Page
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [GPIO100]PWM_9 [GPIO101]PWM_10 [GPIO102]PWM_11 [GPIO103]PWM_12 [GPIO104]PWM_13 [GPIO105]PWM_14 [GPIO106]PWM_15 [GPIO107]PWM_DivClk[IRQ4] [GPIO108]DAC_IPTrig[TS5] [GPIO109]ADC_InTrig[TS6] [GPIO110]UART0_DCD [GPIO111]UART0_DSR [GPIO112]UART0_CTS [GPIO114]UART0_RTS[SPI_SS_2] [GPIO115]UART0_RI[SPI_SS_3] [GPIO116][SPI_SS_In]SPI_SS1 [GPIO117]IRQ0[TrcClk] [GPIO118]IRQ1[TS1E] [GPIO119]IRQ2[TS2E] [GPIO120]IRQ3[TS4] GPIO121 Halt HoldAck[GPIO006] HoldPri[GPIO005] HoldReq[GPIO004] IIC0SClk IIC0SData IRQ0[TrcClk][GPIO117] IRQ1[TS1E][GPIO118] IRQ2[TS2E][GPIO119] IRQ3[TS4][GPIO120] [IRQ4]PWM_DivClk[GPIO107] NFALE[GPIO020] NFCE0[GPIO021] [NFCE1]PerCS5[GPIO001] [NFCE2]PerCS6[GPIO002] [NFCE3]PerCS7[GPIO003] NFCLE[GPIO011] NFData0[GPIO019] NFData1[GPIO018] NFData2[GPIO017] NFData3[GPIO016] NFData4[GPIO015] NFData5[GPIO014] NFData6[GPIO013] NFData7[GPIO012] Ball AA08 AA07 AA06 AA03 AMCC Proprietary NAND Flash NAND Flash NAND Flash Interrupt IEEE 1588 Network Synchronization Peripheral External Peripheral System System Interface Group Page
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name NFRB[GPIO024] NFRE[GPIO022] NFWE[GPIO023] OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 Ball AA10 AA09 Power Power NAND Flash Interface Group Page
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4[GPIO000] PerCS5[NFCE1][GPIO001] PerCS6[NFCE2][GPIO002] PerCS7[NFCE3][GPIO003] Ball External Peripheral External Peripheral Interface Group Page
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerOE PerReady[GPIO009] PerRW PerWBE0 PerWBE1 PerWBE2 PerWBE3 PLL_AGND PLL_AVDD PWM_DivClk[IRQ4][GPIO107] PWM_OE0 PWM_OE1[TS1O][GPIO028] PWM_OE2[TS2O][GPIO029] PWM_OE3[TS3][GPIO030] PWM_TBA Ball AA11 AA12 AB13 AA13 AB15 AA14 AA15 AB16 AB17 AA16 AA17 AA18 AB19 AA19 AB20 AA20 AB21 AA22 AB11 AB12 Chameleon Timer Power Chameleon Timer External Peripheral External Peripheral External Peripheral External Peripheral External Peripheral Interface Group Page
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PWM_1 PWM_2 PWM_3 PWM_4 PWM_5 PWM_6 PWM_7 PWM_8[GPIO031] PWM_9[GPIO100] PWM_10[GPIO101] PWM_11[GPIO102] PWM_12[GPIO103] PWM_13[GPIO104] PWM_14[GPIO105] PWM_15[GPIO106 Reserved SPI_ClkOut SPI_DI SPI_DO SPI_SS0 SPI_SS1[SPI_SS_In][GPIO116] [SPI_SS2]UART0_RTS[GPIO114] [SPI_SS3]UART0_RI[GPIO115] [SPI_SS_In]SPI_SS1[GPIO116] SysClk SysErr SysReset TestEn [TrcClk]IRQ0[GPIO117] TRST [TS1E]IRQ1[GPIO118] [TS2E]IRQ2[GPIO119] [TS1O]PWM_OE1[GPIO028] [TS2O]PWM_OE2[GPIO029] [TS3]PWM_OE3[GPIO030] [TS4]IRQ3[GPIO120] [TS5]DAC_IPTrig[GPIO108] [TS6]ADC_InTrig[GPIO109] Ball AB10 Trace JTAG System Trace JTAG JTAG System Serial Peripheral Other Pins Chameleon Timer Interface Group Page
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name UART0_CTS[GPIO112] UART0_DCD[GPIO110] UART0_DSR[GPIO111] UART0_RI[SPI_SS_3][GPIO115] UART0_RTS[SPI_SS_2][GPIO114] UART0_Rx UART0_Tx UART1_Rx UART1_Tx USB_FClk USB1Dev0 USB1Dev0 USB1Host0 USB1Host0 USB1Host1 USB1Host1 Ball Power UART Peripheral UART Peripheral Interface Group Page
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Preliminary Data Sheet
following table, only primary (default) signal name shown each ball. Multiplexed multifunction signals marked with asterisk (*). determine what signals functions multiplexed those balls, look primary signal name "Signals Listed Alphabetically" page 17.The following table lists signals ball assignment. Table Signals Listed Ball Assignment (Sheet
Ball CAN1_TxE PWM_DivClk* DAC_IOutP DAC_AGND DAC_AVDD PWM_9* PWM_6 PWM_5 PWM_4 PWM_OE2* PWM_OE0 SPI_SS0 DMAAck* DMAEOT/TC* TestEn Signal Name Ball Signal Name UART0_Rx CAN0_Tx CAN1_Tx PWM_14* DAC_VRef DAC_GRef DAC_CRef DAC_IRRef PWM_10* PWM_7 PWM_3 PWM_1 PWM_TBA PWM_OE1* IIC0SClk SPI_ClkOut SysReset Reserved SysErr CRAM_AdV* Ball Signal Name CAN0_TxE CAN0_Rx CAN1_Rx PWM_16* PWM_12* PWM_13* DAC_IPTrig* PWM_11* PWM_8* PWM_2 PWM_OE3* GPIO121 IIC0SData SPI_DO DebugEn Halt DMAReq* PerReady* HoldAck* Ball Signal Name UART0_DSR* UART0_DCD* UART0_Tx OVDD1 OVDD1 OVDD1 SPI_SS1* OVDD1 SPI_DI OVDD1 BusReq* HoldPri* HoldReq*
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball UART0_RI* UART0_CTS* OVDD1 ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD2 PerOE PerCS7* Signal Name Ball Signal Name UART1_Tx UART1_Rx UART0_RTS* UART0_DTR* ball ball ball ball ball ball ball ball ball ball ball ball ball ball CRAM_Clk* PerCS5* PerCS6* PerCS3 Ball Signal Name TRST USB_FClk OVDD1 ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD2 PerCS4* PerCS2 PerCS1 Ball USB1Host0 USB1Host0 ball ball ball ball ball ball ball ball ball ball ball ball ball ball PerCS0 PerWBE3 PerWBE1 Signal Name
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball USB1Host1 USB1Host1 EMCCRS ball ball ball ball OVDD1 OVDD1 ball ball ball ball PerWBE2 PerWBE0 PerRW Signal Name Ball Signal Name USB1Dev0 USB1Dev0 ball ball ball ball OVDD1 OVDD2 ball ball ball ball PerClk PerAddr31 PerAddr30 Ball Signal Name EMCRxD1 EMCRxD0 ball ball ball ball ball ball ball ball OVDD2 PerAddr29 PerAddr28 PerAddr27 Ball Signal Name EMCRxClk EMCRxD2 EMCRxEr OVDD1 ball ball ball ball ball ball ball ball PerAddr24 PerAddr25 PerAddr26
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name EMCRxD3 EMCTxD0 EMCMDIO ball ball ball ball OVDD1 OVDD2 ball ball ball ball PerAddr21 PerAddr22 PerAddr23 Ball EMCTxD1 EMCTxD2 EMCTxD3 ball ball ball ball OVDD1 OVDD2 ball ball ball ball PerAddr16 PerAddr19 PerAddr20 Signal Name Ball Signal Name EMCRxDv EMCTxClk EMCMDC ball ball ball ball ball ball ball ball ball ball ball ball ball ball PerAddr15 PerAddr17 PerAddr18 Ball Signal Name ADC_In0 EMCTxEr IRQ0* OVDD1 ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD2 PerAddr12 PerAddr13 PerAddr14
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name ADC_In1 EMCCOL EMCTxEn ADC_InTrig* ball ball ball ball ball ball ball ball ball ball ball ball ball ball PerAddr04 PerAddr08 PerAddr10 PerAddr11 Ball IRQ1* IRQ2* OVDD1 ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD2 PerAddr05 PerAddr09 Signal Name Ball Signal Name ADC_In2 IRQ3* NFCLE* OVDD1 OVDD1 OVDD2 PerData12 OVDD2 PerData22 OVDD2 PerData31 PerAddr06 PerAddr07 Ball Signal Name ADC_In3 NFData6* NFData5* NFData4* NFData2* NFData0* NFCE0* NFWE* PerData00 PerData04 PerData07 PerData11 PerData14 PerData16 PerData19 PerData20 PerData25 PerData30 PerData28
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 Signal Name ADC_In4 NFData7* NFData3* NFData1* NFALE* NFRE* NFRB* PerData01 PerData02 PerData05 PerData08 PerData09 PerData15 PerData17 PerData18 PerData23 PerData26 PerData29 Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 ADC_In5 ADC_In6 ADC_In7 ADC_VRef ADC_AGND ADC_AVDD SysClk PLL_AGND PLL_AVDD PerData03 PerData06 PerData10 PerData13 PerData21 PerData24 PerData27 Signal Name Ball Signal Name Ball Signal Name
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Group List following table provides summary number package pins (balls) associated with each functional interface group. Table Groups
Group
Total Signal Pins OVDD1 OVDD2 ADC_AVDD ADC_GND DAC_AVDD DAC_GND PLL_AVDD PLL_GND Reserved Total Pins
Pins
table "Signal Functional Description" page each external signal listed along with short description signal function. Active-low signals (for example, Halt) marked with overline. preceding table, "Signals Listed Alphabetically" page (ball) number which each signal assigned. Multiplexed Pins Some signals multiplexed same package that used different functions. most cases, signal names shown this table accompanied signal names that multiplexed same pin. need know what, any, signals multiplexed with particular signal, look name "Signals Listed Alphabetically" page expected that single application particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. Initialization Strapping group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Initialization" page 51). Note that these pins strapping considered multiplexing since strapping function programmable. Pull-Up Pull-Down Resistors Pull-up pull-down resistors used strapping during reset retain unused undriven inputs appropriate state. recommended pull-up value +3.3V pull-down value GND, applies only individually terminated signals. prevent possible damage device, I/Os capable becoming outputs must never tied together terminated through common resistor. your system-level test methodology permits, input-only signals connected together terminated through either common resistor directly +3.3V GND. When resistor used, value must ensure that grouped I/Os reach valid logic zero logic state when accounting total input current into PPC405EZ.
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Signal Functional Descriptions
following table provides description signals PPC405EZ. Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
Ethernet Interface
EMCCOL EMCCRS EMCMDC EMCMDIO EMCRxClk EMCRxDV EMCRxEr EMCRxD0:3 EMCTxClk EMCTxD0:3 EMCTxEn EMCTxEr Collision signal from PHY. Carrier sense signal from PHY. Management data clock PHY. Management data between Ethernet controller PHY. Input receive clock from PHY. Receive data valid. Receive error from PHY. Receive data from PHY. EMCRxD3 msb. Input transmit clock from PHY. Transmit data PHY. EMCTxD3 msb. Transmit enable. Transmit error PHY. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
IEEE 1588 Network Synchronization Interface
IEEE_1588TS Test signal. 3.3V LVTTL
Peripheral Interface
IIC0SClk IIC0SData Serial Clock. Serial Data. 3.3V 3.3V
Interrupts Interface
IRQ0:4 Interrupt requests. 3.3V LVTTL
JTAG Interface
TRST Test clock. Test data Test data out. Test mode select. Test reset. Must power-on initialize JTAG controller normal operation PPC405EZ. 3.3V LVTTL Rcvr w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Rcvr w/pull-up
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
System Interface
SysClk SysErr SysReset TestEn DebugEn Halt TmrClk GPIO000:03 GPIO004:05 GPIO006:08 GPIO009 GPIO010:11 GPIO012:19 GPIO019:27 GPIO028:31 GPIO100:12 GPIO113:14 GPIO115:21 General purpose I/O. GPIO signals multiplexed with other signals. Which signal connected depends setting bits GPIO registers. System input clock. Machine check exception occurred. Main system reset. This signal driven PPC405EZ cause board level reset occur. Test enable. Reserved manufacturing LSSD test. Debug enable. External request stop processor. Processor timer external input. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Trace Interface
TrcClk TS1E TS2E TS1O TS2O TS3:6 Trace interface clock. Operates half core frequency. Even trace execution status. trace execution status. Trace status. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Chameleon Timer Interface
PWM_DivClk PWM_OE0 PWM_OE1:3 PWM_TBA PWM_1:15 Divided-down clock. Output enable input. Output enable input. Time Base Interface bus. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
Analog Digital (ADC) Interface
ADC_In0:7 ADC_InTrig ADC_VRef Analog inputs. Analog inputs should referenced ADC_AGND should exceed value VRef. Input trigger. Analog input reference voltage. Allowable voltage range 2V-ADC_AVDD. Analog WideWire receiver 3.3V LVTTL Analog WideWire receiver
Digital Analog (DAC) Interface
DAC_CRef Reference voltage gate current sources. This voltage should connected DAC_AVDD voltage with filter capacitor signal pin. Analog positive output current. Input trigger. Analog input reference current. Analog band voltage reference input. Allowable voltage range 1.15V-1.26V, with typical value 1.174V. Reference voltage gate cascode device current sources. This voltage should connected DAC_AVDD voltage with filter capacitor signal pin. Analog WideWire driver Analog WideWire driver 3.3V LVTTL Analog WideWire driver Analog WideWire driver Analog WideWire driver
DAC_IOutP DAC_IPTrig DAC_IRRef
DAC_VRef
DAC_GRef
Controller Area Network Interface
CAN0_Rx CAN0_Tx CAN0_TxE CAN1_Rx CAN1_Tx CAN1_TxE Receive input. Transmit output. Transmit enable. Receive input. Transmit output. Transmit enable. 3.3V LVTTL Rcvr w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
External Peripheral Interface
CRAM_AdV CRAM_Clk PerAddr04:31 BusReq PerClk PerCS0:7 PerData00:31 PerOE PerReady PerRW PerWBE0:3 DMAAck DMAEOT/TC DMAReq HoldReq HoldAck HoldPri Address valid signal PSRAM/CRAM support. PerClk gated PSRAM/CRAM support. Memory address 4:31. External request. Clock output. Chip selects 0:7. Memory data 0:31. Output enable. Wait PSRAM/CRAM support. Read/Write. Write enable 0:3. External peripheral acknowledge. External peripheral end-of-transmission/terminal count. External peripheral request. External request access. External request acknowledge. External request priority. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
NAND Flash Interface
NFALE NFCE0:3 NFCLE NFData0:7 NFRB NFRE NFWE Address latch enable. Cchip selects 0:3. Command latch enable. Data bits Read/Busy. low, indicates that Read/Erase command process. high, indicates that command complete. Read enable. Write enable. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Serial Peripheral Interface
SPI_ClkOut SPI_DI SPI_DO SPI_SS0:3 SPI_SS_In Serial peripheral interface clock. Master slave input. Master slave output. Slave Select 0:3. Slave Select Input multi-master collision detection. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
UART Peripheral Interface
UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_Rx UART1_Tx Clear send. Data carrier detect. Data ready. Data terminal ready. Ring indicator. Request send. Receive data. Transmit data. Receive data Transmit data 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Interface
USB1FClk USB1DEV0 USB1DEV0 USB1HOST0 USB1HOST0 USB1HOST1 USB1HOST1 clock Device differential data signal Device differential data signal Host differential data signal Host differential data signal Host differential data signal Host differential data signal 3.3V LVTTL tolerant Diff tolerant Diff tolerant Diff tolerant Diff tolerant Diff tolerant Diff
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
Power
OVDD1 OVDD2 ADC_AVDD ADC_AGND Logic supply. Non-EBC supply. supply. System ground. analog supply. analog ground. analog supply. recommended that this voltage provided means voltage supply voltage plane separate from logic voltage. analog ground. analog supply. "Absolute Maximum Ratings" page filter recommendations. analog ground. Analog WideWire receiver Analog WideWire receiver Analog WideWire receiver Analog WideWire receiver
DAC_AVDD
DAC_AGND PLL_AVDD PLL_AGND
Other Pins
Reserved Reserved pins. make voltage, ground, signal connections these pins.
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Ratings Specifications
Table Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device. None performance specification contained this document guaranteed when operating these maximum ratings.
Characteristic Supply Voltage (Internal Logic) Non-EBC Supply Voltage Supply Voltage Analog Supply Voltage Analog Supply Voltage Analog Supply Voltage Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Junction temperature Symbol OVDD1 OVDD2 PLL_AVDD ADC_AVDD DAC_AVDD TSTG TJMax Value +1.6 +3.6 +3.6 +1.6 +3.465 +3.465 +3.6 +5.5 +150 +120 +125 Unit Notes
voltages specified with respect GND. analog voltages system PLL, ADC, derived from OVDD1, must filtered shown below before entering PPC405EZ. separate filter each voltage. maximum value ADC_PLL DAC_PLL must limited values shown this table. OVDD2 must limited maximum value +3.3V CRAM/PSRAM devices attached interface. This limitation imposed CRAM/PSRAM devices, PPC405EZ.
PLL_AVDD
Murata BLM18AG121SN1D ceramic
PLL_AGND
OVDD1 ADC_GND, DAC_GND ADC_PLL, DAC_PLL Murata BLM18AG121SN1D ceramic 0.01F ceramic
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Package Thermal Specifications
PPC405EZ designed operate within case temperature range -40°C +105°C. Thermal resistance values EPBGA packages convection environment follows:
Parameter Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink Symbol (0.51) 24.1 14.3 Airflow ft/min (m/sec) (1.02) 22.9 12.3 (1.52) 22.4 11.5 (2.02) 22.0 11.1 (3.03) 21.6 10.7 °C/W °C/W Unit
29.3 22.7
Resistance Value Junction-to-case thermal resistance Junction-to-board thermal resistance Notes: Values table achieved with following JEDEC standard board: 114.5mm 101.6mm 1.6mm, layers. chip mounted card with least signal power planes, following relationships exist: Case temperature, measured center case surface with device soldered circuit board. where ambient temperature power consumption. PxJC, where TJMax maximum junction temperature power consumption. Values with heat sink were achieved with 38.1mm 38.1mm 16.5mm unit, attached chip using 0.1mm thickness adhesive having thermal conductivity 1.3W/mK. 11.9 16.4 °C/W °C/W
Thermal Management following heat sink used above thermal analysis: Aavid Thermalloy, 79985 heat sink manufactured Aavid Thermalloy Commercial Concord, 03301 Tel: (603)224-9988 URL: www.aavidthermalloy.com
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Recommended Operating Conditions
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Supply Voltage (for non-EBC I/O) Supply Voltage (for I/O) Analog Supply Voltage Analog Supply Voltage Analog Supply Voltage Input (3.3V LVTTL) Input High (3.3V LVTTL) Output (3.3V LVTTL) Output High (3.3V LVTTL) High (USB, tolerant) (USB, tolerant) Input High (IIC) Input (IIC) Output High (IIC) Output (IIC) Input Leakage Current pull-up pull-down) Input Leakage Current (with internal pull-down) Maximum Allowable Overshoot (3.3V LVTTL) Maximum Allowable Undershoot (3.3V LVTTL) Case Temperature Notes: When using CRAM PSRAM memory interface, this voltage must limited maximum +3.3V. This limitation imposed CRAM/PSRAM devices, PPC405EZ. Symbol OVDD1 OVDD2 PLL_AVDD ADC_AVDD DAC_AVDD IIL1 IIL2 VMAO VMAU -0.6 +105 +0.4 +3.9 0.7OVDD -0.3 Minimum +1.425 +3.0 +3.0 +1.4 +3.135 +3.135 +2.0 +2.4 +2.8 +0.3 OVDD +0.3OVDD Typical +1.5 +3.3 +3.3 +1.5 +3.3 +3.3 Maximum +1.575 +3.6 +3.6 (see Note +1.6 +3.465 +3.465 +0.8 +3.6 +0.4 +3.6 Unit Notes
Table Input Capacitance
Parameter 3.3V LVTTL Tolerant Symbol CIN1 CIN2 CIN3 Maximum Unit Notes
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Typical Power Supply Requirements
Frequency (MHz) +1.5V Supply 0.81 0.97 1.13 +3.3V Supply 0.24 0.25 0.29 0.28 Total 1.05 1.22 1.42 1.48 Unit Notes
Table Power Supply Loads
Parameter (+1.5V) active operating current OVDD (+3.3V) active operating current AVDD (+1.5V) active operating current ADC_AVDD (3.3V) input current DAC_AVDD (3.3V) input current Notes: Typical Maximum values estimates subject change. Symbol IODD IADD IADCDD IDACDD Typical Maximum Unit Notes
Test Conditions Clock timing switching characteristics specified accordance with minimum operating conditions shown table "Recommended Operating Conditions" page signals, specifications characterized 85°C with 50pF test load shown figure right.
Output
50pF
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table System Clocking Specifications
Symbol SysClk Input SCFC SCTCS SCTCH SCTCL SCRT TrcClk Output TCFC TCTCS Other Clocks VCOFC PLBFC OPBFC frequency frequency frequency 1333.33 Clock output frequency Clock edge stability (phase jitter, cycle cycle) PFC/2 Frequency Edge stability (phase jitter, cycle cycle) Input high time Input time Rise time 33.33 Processor clock frequency (must SCFC) 133.33 Parameter Units
Note: Input slew rate 1V/ns
Figure Clocking Waveform
2.0V 1.5V 0.8V
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Spread Spectrum Clocking
Care must taken using spread spectrum clock generator (SSCG) with PPC405EZ. This controller uses clock generation inside chip. accuracy with which follows SSCG called tracking skew. bandwidth phase angle determine much tracking skew exists between SSCG given frequency deviation modulation frequency. using SSCG with PPC405EZ following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC405EZ with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation must exceed -3%, modulation frequency must exceed 40kHz. some cases, on-board PPC405EZ peripherals impose more stringent requirements (see Note peripheral clock logic that synchronous peripheral because this clock tracks modulation. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur, assuming that connected device running precise baud rates. external serial clock used, baud rate unaffected modulation. Ethernet operation unaffected. operation unaffected. Caution: system designer must ensure that SSCG used with PPC405EZ meets these requirements does adversely affect other aspects system.
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PPC405EZ PowerPC 405EZ Embedded Processor
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Preliminary Data Sheet
Table Peripheral Interface Clock Timings
Clock EMCTxClk frequency EMCTxClk high time EMCTxClk time EMCRxClk frequency EMCRxClk high time EMCRxClk time TmrClk PerClk USB1FClk (48MHz 0.05%) PWM_TBA nominal nominal nominal nominal 47.976 48.024 Units
Figure Input Setup Hold Timing Waveform
System Clock
1.5V
Inputs
1.5V
Valid
Figure Output Delay Float Timing Waveform
System Clock 1.5V
Outputs
1.5V Valid
Outputs
1.5V
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. Timing shown with EMAC noise filter selected. interfaces, specified specified Maximum skew between output signals 6ns. Maximum skew between output signals 3ns. inputs signals latched with less than skew between channels. Maximum skew between output signals 3.75ns. input signals latched with less than 2.5ns skew between channels.
Input (ns) Signal Ethernet Interface EMCRxD[0:3] EMCTxD[0:3] EMCRxEr EMCMDIO EMCRxDv EMCCRS EMCTxEr EMCTxEn EMCMDC EMCCOL Internal Peripheral Interface IIC0SClk IIC0SData UART0_CTS UART0_RTS UART0_Rx UART0_Tx UART1_Rx UART1_Tx USB_FClk USB1DEV0 USB1DEV0 USB1HOST0 USB1HOST0 USB1HOST1 USB1HOST1 SPI_ClkOut SPI_DI SPI_DO SPI_SS0:3 SPI_SS_In CAN0_Rx CAN0_Tx CAN0_TxE CAN1_Rx CAN1_Tx CAN1_TxE ADC_In0:7 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 AMCC Proprietary 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 EMCTxClk EMCTxClk async async EMCRxClk async EMCRxClk EMCTxClk EMCRxClk async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (min) (min) Clock Notes
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. Timing shown with EMAC noise filter selected. interfaces, specified specified Maximum skew between output signals 6ns. Maximum skew between output signals 3ns. inputs signals latched with less than skew between channels. Maximum skew between output signals 3.75ns. input signals latched with less than 2.5ns skew between channels.
Input (ns) Signal ADC_InTrig ADC_VRef DAC_CRef DAC_IOutP DAC_IPTrig DAC_IRRef DAC_VRef DAC_GRef PWM_DivClk PWM_OE[0] PWM_OE[1:3] PWM_TBA PWM_1:15 IEEE_1588TS Interrupts Interface [IRQ0:4] JTAG Interface TRST System Interface GPIO000:31 GPIO100:20 Halt SysErr SysReset TestEn DebugEn SysClk 22.5 25.5 19.1 19.1 19.1 19.1 async async 22.5 22.5 19.1 19.1 Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (min) 19.1 19.1 19.1 19.1 19.1 19.1 19.1 (min) Clock Notes
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Table Specifications-416
Notes: PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns. specified specified
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) 7.35 7.35 7.35 -0.7 2.16 2.15 2.15 2.15 Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 (minimum) Clock Notes
External Peripheral Interface PerClk CRAM_Clk CRAM_AdV PerAddr04:31 BusReq PerCS0:7 PerData00:31 HoldReq HoldAck HoldPri PerOE PerReady PerRW PerWBE0:3 NFALE NFCE0 NFCLE NFData0:7 NFRB NFRE NFWE DMAAck DMAEOT/TC DMAReq PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk PerClk/ CRAM_Clk
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Initialization
following describes method which initial chip settings established when system reset occurs. Strapping When SysReset input driven (system reset), state certain pins read order enable default initial conditions before PPC405EZ start-up. actual instant capture nearest system clock edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. recommended pull-up +3.3V, +5V. recommended pull-down GND. These pins only used strap functions during reset. They used other signals during normal operation. following table lists strapping pins along with their functions strapping options. signal names assigned pins normal operation appear below number. Table Strapping Assignments
Strapping Function Option bits wide Initialize from bits wide bits wide page, addr cycle Initialize from NAND Flash page, addr cycle page, addr cycle page, addr cycle Initialize from Reserved Slow Fast (GPIO114) Initialize from Note: reading initialization data from interface fails, PPC405EZ defaults strapping option 0010. (GPIO112) (GPIO111) (GPIO110)
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Revision
Date 01/13/2006 Version 1.08 Initial distribution review. Misc. corrections. Correct AMCC address. revision log. Change three signals match previous chips (HoldAck, HoldPri, HoldReq). Misc. corrections. pull-up/pull-down notes. Update clock timings. Correct Bootstrap numbers. Correct number swaps. circuit types signal descriptions. Reduce recommended logic voltage range 0.025V. 266MHz 333MHz speeds. Allow 3.3V power supply DAC. output currents tables. Correct Recommended Operating Conditions. Remove Tolerant input current curve. output current values (based circuit type) tables Correct filter circuit component units-of-measure from Correct ADC_In6 ADC_In7 pins assignment. Correct EBC_Dbus24 EBC_Dbus25 pins assignment. Change signal name NI_DivClk PWM_DivClk. typical power requirements. Split OVDD voltage pins into sets voltage different from other necessary. Update from engineering review. Timing updates. Chameleon Timer IEEE 1588 updates. package thermal data. Analog voltage filter updates. Part number updates. Remove package references "industrial" from thermal package data. Remove watermark change status Preliminary. heat sink data increase case temperature range +105°C. Change minimum frequency 133.33MHz. power supply current load values. Change assignments Ethernet data signals. Alter prefixes remove extraneous characters from some signal names make them consistent with previous chips. There functional (ball) number changes. Correct JTAG Remove disable option. Reduce maximum speed. Change power specifications Description. link AMCC partners supplying probes. Deleted internal clock signal timing table. Added PerClk signal external peripheral timing table. Restrict analog voltage filters OVDD1. Typographical Updates Contents Modification
03/09/2006
1.09
04/10/2006
1.10
04/21/2006
1.11
05/12/2006
1.12
06/13/2006 07/18/2006 08/8/2006
1.13 1.14 1.15
08/30/2006
1.16
09/05/2006
1.17
09/18/2006
1.18
10/18/2006
1.19
02/07/2007
1.20
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Date 02/20/2007 02/21/2007 02/27/2007 03/05/2007 04/02/2007 04/23/2007 08/22/2007 Version 1.21 1.22 1.23 1.24 1.25 1.26 1.27 Contents Modification VCOFc minimal value System Clock Specification Table Changed instead Changes UART section Ethernet section Added sentence NAND Flash Controller section Change picture page Added overline signal CRAM_AdV. Changed value page Added missing information table
AMCC Proprietary
PPC405EZ PowerPC 405EZ Embedded Processor
Revision 1.27 August 2007
Preliminary Data Sheet
Applied Micro Circuits Corporation Moffett Park Drive, Sunnyvale, 94089 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products, datasheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available datasheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered Trademark Applied Micro Circuits Corporation. Copyright 2007 Applied Micro Circuits Corporation.
AMCC Proprietary
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