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Part Number 405EZ Revision 1.27 - August 22, 2007

405EZ

Part Number 405EZ Revision 1.27 - August 22, 2007
405EZ
PowerPC 405EZ Embedded Processor
Features
· AMCC PowerPC® 405 32-bit RISC processor core operating at up to 416MHz · On-chip 32-bit peripheral bus (OPB) operating at up to 83 MHz · On-chip 64-bit processor local bus (PLB) operating at up to 166MHz · 8-bit direct interface for NAND Flash devices · 32KB of on-chip, high-speed SRAM accessible by CPU and DMA · Inter-chip connectivity (SPI and IIC)
Preliminary Data Sheet
· IEEE 1588 Precision Timing Protocol (PTP) controller · Chameleon Timer and pulse width modulator (PWM) · Analog-to-Digital Converter (ADC) with eight inputs and 10-bit resolution at 300k samples / sec · Digital-to-Analog Converter (DAC) with one input and 10-bit resolution at 30M samples / sec · Two CAN 2.0B protocol and ISO 11898-1 compliant channels · Two serial ports (16750 compatible UART)
· External 8-, 16-, or 32-bit peripheral bus (EBC) operating at up to 83MHz · Boot from IIC bootstrap controller, EBC, NAND Flash, and SPI · DMA support for all on-chip slaves and external bus, including on-chip SRAM, ADC, DAC, UARTs, and devices on the external peripheral bus · One 10 / 100 Mbps Ethernet MII interface (half- and full-duplex) to external PHY · Three USB 1.1 ports: two Host and one Device with Full-Speed on-chip PHYs · Programmable universal interrupt controller (UIC)
· One IIC interface operating at up to 400kHz and supporting all standard IIC EEPROMs · One SPI (SCP) synchronous full-duplex channel operating at up to 40 MHz · 54 general purpose I / Os (GPIOs), each with programmable interrupts and outputs · Supports JTAG for board-level testing · System power management, low power dissipation and small form factor · RoHS compliant (lead-free)
Description
With speeds up to 416MHz, a flexible on-chip and offchip memory architecture, a combination of an ADC, a DAC, a programmable Chameleon Timer / PWM, an IEEE 1588 PTP, and a diverse communications package that includes USB 1.1, Ethernet, and CAN, the PowerPC 405EZ embedded processor provides a low power and small footprint system-on-a-chip solution for a wide range of high performance, costconstrained embedded applications. This includes industrial control, high-precision AC / DC and servo drive control, instrumentation, data acquisition, industrial automation, building and enclosure management, commercial and retail systems, Internet
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table of Contents
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
List of Figures
List of Tables
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Ordering, PVR, and JTAG Information
This section provides the part number nomenclature. For availability, contact your local AMCC sales office.
Order Part Number (see Notes:) PPC405EZ-CSAfffTx Rev Level A
Product Name PPC405EZ Notes: 1. 2. 3. 4.
Package 23mm, 324-ball, EPBGA
PVR Value 0x41511460
JTAG ID 0x0405A1E1
PPC405EZ-CSA416TZ
Shipping Package AMCC Part Number
Case Temperature Range Processor Speed (MHz)
CAN enabled
Package
Revision Level
Note: The example P / N above is CAN enabled, lead-free, capable of running at 416MHz, and is shipped in tape-and-reel packaging.
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Block Diagram
Figure 1. PPC405EZ Embedded Controller Functional Block Diagram
Universal Interrupt Controller
Clock Control Reset
Power Mgmt
32KB SRAM
Timers MMU PowerPC 405 Core JTAG
D-OCM I-OCM DCRs
OCM Ctrl UART x2 Arbiter On-chip Peripheral Bus (OPB) CAN x2 IIC / BSC SPI GPIO Timer / DAC (SCP) PWM ADC
Trace
16KB D-Cache 16KB I-Cache DMA Controller (4-Channel) OPB / PLB Bridges MAL Ethernet 10 / 100 USB 1.1 Host / Dev IEEE 1588 PTP
Arbiter
Processor Local Bus (PLB) 64 bit, PLB3 PHY External Bus Controller NAND Flash Controller
The PPC405EZ is designed using the IBM Microelectronics Blue Logic methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect Bus Architecture.
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Address Maps
The PPC405EZ incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EZ processor through the use of mtdcr and mfdcr instructions. Table 1. System Memory Address Map (4GB System Memory)
Function General Use Reserved UART 0 Registers UART 1 Registers IIC Registers OPB Arbiter Registers GPIO 0 Controller Registers GPIO 1 Controller Registers EMAC Registers Reserved CAN 0 Registers CAN 1 Registers Chameleon Timer Registers IEEE 1588 Sync Controller Registers USB 1.1 Host Registers Reserved DAC Registers ADC Registers Serial Communication Port Registers Reserved USB 1.1 Device Registers Reserved Boot Address Range Notes: 1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. After the boot process, software may reassign the boot memory regions for other uses. Subfunction Start Address 0x 0000 0000 0x E000 0000 0x EF60 0300 0x EF60 0400 0x EF60 0500 0x EF60 0600 0x EF60 0700 0x EF60 0800 0x EF60 0900 0x EF60 0A00 0x EF60 1000 0x EF60 1800 0x EF60 2000 0x EF60 2800 0x EF60 3000 0x EF60 3200 0x EF60 3300 0x EF60 3400 0x EF60 3500 0x EF60 3600 0x EF64 0000 0x EF68 0000 0x FFE0 0000 End Address 0x DFFF FFFF 0x EF60 02FF 0x EF60 03FF 0x EF60 04FF 0x EF60 05FF 0x EF60 06FF 0x EF60 07FF 0x EF60 08FF 0x EF60 09FF 0x EF60 0FFF 0x EF60 17FF 0x EF60 1FFF 0x EF60 27FF 0x EF60 2FFF 0x EF60 31FF 0x EF60 32FF 0x EF60 33FF 0x EF60 34FF 0x EF60 35FF 0x EF63 FFFF 0x EF67 FFFF 0x FFDF FFFF 0x FFFF FFFF 2 MB 262KB 256B 256B 256B 2KB 2KB 2KB 2KB 512B 256B 256B 256B 256B 256B 256B 256B Size 3.7GB
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 2. DCR Address Map
Function Total DCR Address Space Reserved CPR SDR Reserved EBC Reserved OCM Controller Reserved PLB Arbiter Reserved PLB-to-OPB Bridge Reserved OPB-to-PLB Bridge Reserved CPM Reserved UIC Reserved IEEE 1588 Snapshot Source Reserved DMA Reserved MAL Notes: 1. DCR address is 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB).
Start Address 0x000 0x000 0x00C 0x00E 0x010 0x012 0x014 0x020 0x030 0x080 0x090 0x0A0 0x0A8 0x0B0 0x0B4 0x0B8 0x0BC 0x0C0 0x0D0 0x0E0 0x0F0 0x100 0x140 0x380
End Address 0x3FF 0x00B 0x00D 0x00F 0x011 0x013 0x01F 0x02F 0x07F 0x08F 0x09F 0x0A7 0x0AF 0x0B3 0x0B7 0x0BB 0x0BF 0x0CF 0x0DF 0x0EF 0x0FF 0x13F 0x2FF 0x3FF
Size 1KW (4KB)1 12B 2B 2B 2B 2B 12B 16B 80B 16B 16B 8B 8B 4B 4B 4B 4B 16B 16B 16B 16B 64B 578B 128B
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Power PC 405 Processor Core
The PPC405 core is a fixed-point, 32-bit RISC processor. Features include: · Five-stage pipeline with single-cycle execution of most instructions, including loads and stores · Separate, configurable 16 KB D- and I-caches, both 2-way set associative · Thirty-two 32-bit general purpose registers (GPRs) · Unaligned load / store support · Hardware multiply / divide · Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB) · Double word instruction fetch from cache · Translation of the 4GB logical address space into physical addresses · On-chip memory (OCM) interface · Built-in timer and debug support · Power management · 32-bit DCR interface
Internal Buses
The PPC405EZ contains three internal buses: the on-chip peripheral bus (OPB), the processor local bus (PLB), and the device control register (DCR) bus. High bandwidth devices such as the processor and the DMA core utilize the PLB. Lower bandwidth I / O interfaces such as communications and timer interfaces utilize the OPB. OPB The OPB provides 32-bit address and data interfaces, and operates up to 83MHz. There is a bridge between the OPB and the PLB. Features include: · - Pipelined read support · - Dynamic bus sizing · - Single-cycle data transfer between masters and slaves PLB The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and slave devices to the PPC405 CPU. It provides a 64-bit data path with 32-bit addressing and operates at up to166MHz. There is a bridge between the PLB and the OPB. Features include: · Overlapping read and write transfers · Decoupled address and data buses · Address pipelining · Late master request abort capability · Hidden (overlapped) bus request / grant protocol · Bus arbitration-locking mechanism · Byte-enable capability allows for unaligned half word transfers and 3-B transfers · Support for 16-, 32-, and 64-B line data transfers · Read word address capability · Sequential burst protocol · Guarded and unguarded memory transfers · DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
DCR Bus The daisy-chained DCR bus provides a path for passing status and control information between the processor core and the other on-chip cores. All DCRs are 32 bits in width.
On-Chip Memory (OCM) Controller
The OCM controller connects the 405EZ processor core to two non-overlapping banks of single-port, on-chip, configurable 32KB SRAM memory. The OCM can also transfer data between the PLB and internal SRAM banks. Features include: · Simultaneous PLB3, instruction-Side OCM and data-Side OCM access · PLB slave cycles support: - 64-bit slave attachment addressable by any PLB master - Single-beat read and write (1 to 8 bytes) - 4-, 8-, and 16-word line read and write - Double word and word read and write bursts - Slave-terminated double word and word bursts - Master-terminated variable length bursts - Data parity generation and checking - Read / Write protection per bank · Instruction side interface supports: - One-Wait state OCM access with 1-deep write buffer - Data parity checking · Data side interface supports: - One-wait state OCM access with 1-deep write buffer - Data parity generation and checking - Read / Write protection per bank · Processor side data port has highest access priority (maintains predictable memory accesses to OCM)
External Bus Controller
The external bus controller (EBC) transfers data between the PLB and external memory or peripheral devices attached to the external peripheral bus. The EBC provides direct attachment of memory devices such as ROM and SRAM, DMA device paced memory devices, and DMA peripheral devices. Features include: · Up to 83 MHz speed · 8-, 16-, or 32-bit data bus, 28-bit address bus · Up to eight chip selects · Arbitration and multi-master supported · Flash ROM interface · Boot from EBC (including NAND Flash interface) support · Direct support for 8-, 16-, or 32-bit SRAM and external peripherals · CRAM / PSRAM support
NAND Flash Controller
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
· · · · · · · · more details) Direct 8-bit interfacing to discrete NAND Flash devices Up to four banks of NAND Flash supported Device size 4MB-256MB (32Mb to 2Gb) supported 512B + 16B or 2kB + 64B device page sizes supported ECC generation - hamming code, single-bit correction, double-bit detection (SEC / DED) Eight-bit command write, address write, and data read / write Interrupt on device ready (after long page write or block erase operations) Boot from NAND - Executes up to 4 KB of boot code out of first block - Automatic page read accesses performed based on device configuration and read address
DMA Controller
The Direct Memory Access (DMA) controller is a Processor Local Bus (PLB) master that enables faster data transfer between memory and peripherals than is possible under program control. The 4-channel DMA controller handles data transfers between memory and peripherals and from memory-to-memory. Each channel has an independent set of registers needed for data transfer: a control register, a source address register, a destination address register, and a transfer count register. Features include: · Memory-to-memory transfers · Buffered memory-to-peripheral transfers · Buffered peripheral-to-memory transfers · Four independent DMA channels · Scatter / gather capability for dynamically programming multiple DMA transfers · Programmable address increment or decrement · Internal data buffering · Can transfer data to / from any PLB and OPB slave, including OCM and external bus
USB Interface
The USB support provides separate Host and Device interfaces compliant with the USB1.1 Specification Features include: · USB1.1 Host (2 ports) - Compliant with USB 1.1 Specification and OHCI version 1.0a Host Controller Specification - Compatible with USB 2.0 Full-Speed peripherals - Supports Low-Speed (1.5Mbps) operation - All transfer types (Isochronous, Interrupt, Control, and Bulk) supported - Tx and Rx FIFOs: 16-entries x 32-bits each - Independent 32-bit OPB master and slave interfaces (master and slave can operate asynchronously) - Programmable OPB slave base address - Up to 127 connected devices supported · USB1.1 Device (1 port) - Full- and Low-Speed device controller - 32-bit, OPB slave interface - Three Endpoints supported (Endpoint 0 is used for control) · Endpoints 1-2 can be IN, OUT, IN and OUT, IN / OUT programmable · Endpoints 1-2 configurable to support Interrupt / Bulk only, Isochronous only, Interrupt / Bulk or Isochronous (programmable) transfer types · Endpoints 1-2 configurable to support maximum packet size of 8, 16, 32, or 64 bytes · Endpoint 0 configurable to support maximum packet size of 8 or 16 bytes · Full Speed (12 Mbps) USB PHY for each of the 3 USB ports - Tolerates shorting to 5.25V and shorting to ground if driving signal conditions meet those specified in the
10 AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Universal Serial Bus Specification
Controller Area Network (CAN)
The CAN controller module supports the concept of mailboxes. It contains 32 receive buffers, each one with its own message filter, and 32 transmit buffers with a prioritized arbitration scheme. For optimal support of Higher Level Protocols (HLP) such as DeviceNet or SDC, the message filter covers the first two data bytes. Features include: · CAN 2.0B protocol compliant · ISO 11898-1 compliant · 32 Transmit message holding registers, programmable priority arbitration · Message abort command supported · 32 Receive buffers (each with own message filter) - Message filtering: ID, IDE, Remote Transmission Request (RTR), data byte 1, and data byte 2 · Message buffers can be linked together to build bigger message arrays · Automatic RTR response handler · Message Abort command supported · Maximum baud rate of 1Mbps with 8MHz system clock · Listen-only for debugging supported · Global masking supported · 32-bit OPB slave interface · Internal loopback
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
· Loopback controls for isolating communications link faults · Break, parity, overrun, framing error simulation · OPB interface with optional DMA support
IIC Bus Interface
The Inter-Integrated Circuit (IIC) interface provides a Philips I2C® compatible interface operating up to 400kHz either as a master, a slave, or both with a bootstrap controller (BSC) included. During chip reset, the bootstrap controller can read configuration data from an IIC compatible memory device (e.g., EEPROM). This data can be used to replace the default configuration settings provided by the chip. Features include: · One IIC channel · Compliant with Philips Semiconductors I2C Specification, dated 1995 · 100 kHz or 400 kHz operation · 8-bit data · 10- or 7-bit address · Slave Transmit and Receive · Master Transmit and Receive · Multiple bus masters supported · Programmable as master, slave, or master / slave · Boot parameters read from IIC attached memory with IIC bootstrap controller · 32-bit OPB slave interface
Serial Peripheral Interface (SPI / SCP)
The Serial Peripheral Interface (SPI) (also known as the Serial Communications Port or SCP) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SPI is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB. Features include: · One SPI / SCP channel, full duplex synchronous · SPI / SCP master · Up to 40 MHz · Programmable internal loopback capabilities · Multi-master protocol supported · Independent masking of all interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, receive FIFO overflow) · Dynamic control of serial bit rate of data transfer (serial-master mode only) · Data Item size for each data transfer under programmer control (4-to-16 bits) · Boot from SPI supported · 32-bit OPB slave interface
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Chameleon Timer
General Purpose I / O (GPIO) Controller
The GPIO controller enables multiplexing of module I / O pins with multiple functions within the chip. That is, a single package pin can be assigned to multiple I / O functions. Which function the pin is assigned to is determined by register bit settings controlled by software. This significantly reduces the number of package pins needed to support multiple I / O groups. Features include: · Up to 54 GPIOs available - GPIOs are multiplexed with alternate functions - If not in use for dedicated functions, I / Os are available as GPIOs · Direct control of all functions from registers programmed by means of OPB bus master accesses · Time multiplexing of controller outputs to module outputs · Programmable conversion of module outputs to open-drain outputs (enables sharing of active low outputs externally) · Time multiplexing of module inputs to controller inputs
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the PPC405 processor. Features include: · 32 interrupt sources supported (5 external) · Generate interrupt on level (high or low) or edge (rising or falling) · Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive triggering) · Each interrupt source / bit programmable as critical or non critical · 32-bit DCR bus interface · Optional interrupt handler vector generation - Programmable vector base address - Programmable vector offset size - Programmable interrupt priority ordering · Programmable polarity for all interrupt types · Interrupts of the same type do not need to be in contiguous bit positions · Status registers provide: current state of all interrupts, current state of enabled interrupts
10 / 100 Ethernet
The Ethernet support provides a single 10 / 100 Mbps interface. Features include: · ANSI / IEEE Std. 802.3 and IEEE 802.3u supplement compliant · Half-duplex and full-duplex supported · MII interface to external PHY · 512 byte receive FIFOs with programmable thresholds · FCS control for transmit / receive packets · Multiple packet handling in transmit and receive FIFOs · Unicast, multicast, broadcast, and promiscuous address filtering · Two 64-bit hash filters for unicast and multicast frames · Automatic retransmission of collided frames · Runt frame rejection · Programmable inter-frame gap · IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame transmitting) · Wake-on-LAN and Power-over-Internet supported · Programmable internal / external loopback capabilities · 32-bit OPB slave (MAC) and PLB master (MAL) interfaces · Extensive error / status vector generation for each processed packet · VLAN tag ID supported (according to IEEE Draft 802.3ac / D1.0 standard) · Programmable automatic source address inclusion / replacement for transmit packets · Programmable automatic Pad / FCS stripping for receive packets · Programmable VLAN Tag inclusion / replacement for transmit packets
IEEE 1588 Precision Timing Protocol Controller
In a distributed control system containing multiple clocks, this feature defines messages used to exchange timing information for precision network synchronization purposes. A second UIC in the PPC405EZ is dedicated to generating snapshot triggers to the IEEE 1588 PTP controller from any interrupt source in the chip.
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Analog-to-Digital Converter (ADC)
The ADC is a mixed-signal core. It uses the successive approximation (binary search) conversion technique to achieve minimal conversion time. The analog input range is 0.0V to Vref. Features include: · Internal 10-bit resolution SAR ADC · Sample and hold · Support for multiple conversion times such as - 3.25 s with 4-MHz input clock - 52 s with 250-kHz input clock · Comparator · Digital controller · 8-channel analog input (3.3 V) with 8:1 analog multiplexer · 10-bit parallel digital outputs · Input trigger from Chameleon Timer supported · OPB interface with optional DMA support
Digital-to-Analog Converter (DAC)
The DAC is a 1-channel converter, optimized for low power applications. It provides unbuffered single-ended analog current output. The single analog current output can be tied directly to an output resistor to provide twoscomplementary, single-ended voltage outputs. Features include: · 10-bit resolution at 30M samples / sec · Segmented DAC · Single-ended current outputs (6mA maximum swing at 3.3V) · Monotonicity ensured · Straight binary input · Internal bandgap voltage reference · Power management by means of Sleep Mode · Integrated functional test logic · Input trigger from Chameleon Timer supported · OPB interface with optional DMA support
Features include: · IEEE 1149.1 test access port · JTAG Boundary Scan Description Language (BSDL) Refer to http://www.amcc.com / Embedded / Partners for a list of AMCC partners supplying probes for use with the JTAG interface.
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Figure 2. 23mm, 324-Ball EPBGA Core
Gold Gate Release Corresponds to A01 Ball Location
Top View
Logo View
Part Number Lot Number
PPC405EZ
1YWWBZZZZZ
Epoxy Mold Compound PCB Substrate
2.65 max
Bottom View
1.0 TYP
Notes: 1. All dimensions are in mm. 2. Package is lead-free (RoHS compliant) 3. Package conforms to JEDEC SPEC.MS-034
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Signal Lists
The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list-once for each signal name on the ball. The Page column indicates the page within the table "Signal Functional Description" on page 35 on which the signals in the indicated interface group begin. Table 3. Signals Listed Alphabetically (Sheet 1 of 11)
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 2 of 11)
Signal Name EMCRxClk EMCRxDv EMCRxD0 EMCRxD1 EMCRxD2 EMCRxD3 EMCRxEr EMCTxClk EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn EMCTxEr Ball M01 R01 L02 L01 M02 N01 M03 R02 N02 P02 P03 P04 U03 T02 Ethernet 35 Ethernet 35 Interface Group Page
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 3 of 11)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball A01 A02 A05 A09 A14 A18 A22 B02 B21 C03 C09 C20 D04 D06 D08 D09 D12 D15 D19 E01 E22 H04 H19 J01 J09 J11 J12 J14 J22 K10 K11 K13 L04 L09 L11 L12 L13 L14 Power 40 Interface Group Page
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 4 of 11)
Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball M09 M10 M11 M12 M14 M19 N10 N12 N13 P01 P09 P11 P12 P14 P22 R04 R19 V01 V22 W04 W06 W08 W09 W11 W15 W19 Y03 Y06 Y20 AA02 AA04 AA05 AA21 AB01 AB05 AB09 AB14 AB18 AB22 Power 40 Interface Group Page
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 5 of 11)
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 6 of 11)
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 7 of 11)
Signal Name NFRBGPIO024 NFREGPIO022 NFWEGPIO023 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD1 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 OVDD2 Ball AA10 AA09 Y10 D05 D07 D11 D16 D18 E04 G04 J10 J13 K09 M04 N09 P10 T04 V04 W05 W07 E19 G19 K14 L19 N14 P13 T19 V19 W12 W16 W18 Power 40 Power 40 NAND Flash 38 Interface Group Page
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 8 of 11)
Signal Name PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4GPIO000 PerCS5NFCE1GPIO001 PerCS6NFCE2GPIO002 PerCS7NFCE3GPIO003 Ball U19 V20 W21 W22 U20 V21 U21 U22 T20 T21 T22 R20 P19 R21 R22 P20 P21 N20 N21 N22 M20 M21 M22 L22 L21 L20 K22 K21 K20 H20 G22 G21 F22 G20 F20 F21 E21 External Peripheral 38 External Peripheral 38 Interface Group Page
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 9 of 11)
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 10 of 11)
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 3. Signals Listed Alphabetically (Sheet 11 of 11)
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
In the following table, only the primary (default) signal name is shown for each ball. Multiplexed or multifunction signals are marked with an asterisk (). To determine what signals or functions are multiplexed on those balls, look up the primary signal name in "Signals Listed Alphabetically" on page 17.The following table lists the signals by ball assignment. Table 4. Signals Listed by Ball Assignment (Sheet 1 of 6)
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 2 of 6)
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 3 of 6)
Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 GND USB1Host1 USB1Host1 EMCCRS No ball No ball No ball No ball GND OVDD1 GND GND OVDD1 GND No ball No ball No ball No ball PerWBE2 PerWBE0 PerRW GND Signal Name Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 Signal Name USB1Dev0 USB1Dev0 TDO VDD No ball No ball No ball No ball OVDD1 GND GND VDD GND OVDD2 No ball No ball No ball No ball VDD PerClk PerAddr31 PerAddr30 Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 Signal Name EMCRxD1 EMCRxD0 TDI GND No ball No ball No ball No ball GND VDD GND GND GND GND No ball No ball No ball No ball OVDD2 PerAddr29 PerAddr28 PerAddr27 Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 Signal Name EMCRxClk EMCRxD2 EMCRxEr OVDD1 No ball No ball No ball No ball GND GND GND GND VDD GND No ball No ball No ball No ball GND PerAddr24 PerAddr25 PerAddr26
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 4 of 6)
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PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 5 of 6)
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PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 4. Signals Listed by Ball Assignment (Sheet 6 of 6)
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Pin Group List The following table provides a summary of the number of package pins (balls) associated with each functional interface group. Table 5. Pin Groups
Group
No. of Pins
In the table "Signal Functional Description" on page 35, each external signal is listed along with a short description of the signal function. Active-low signals (for example, Halt) are marked with an overline. See the preceding table, "Signals Listed Alphabetically" on page 17, for the pin (ball) number to which each signal is assigned. Multiplexed Pins Some signals are multiplexed on the same package pin so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in "Signals Listed Alphabetically" on page 17. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. Initialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Initialization" on page 51). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3k to +3.3V and pull-down value of 1k to GND, applies only to individually terminated signals. To prevent possible damage to the device, I / Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I / Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405EZ.
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Signal Functional Descriptions
The following table provides a description of the I / O signals on the PPC405EZ. Table 6. Signal Functional Description (Sheet 1 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required.
Signal Name Description I / O Type
Notes
Ethernet Interface
EMCCOL EMCCRS EMCMDC EMCMDIO EMCRxClk EMCRxDV EMCRxEr EMCRxD0:3 EMCTxClk EMCTxD0:3 EMCTxEn EMCTxEr Collision signal from the PHY. Carrier sense signal from the PHY. Management data clock to the PHY. Management data I / O between the Ethernet controller and the PHY. Input receive clock from the PHY. Receive data valid. Receive error from the PHY. Receive data from the PHY. EMCRxD3 is the msb. Input transmit clock from the PHY. Transmit data to the PHY. EMCTxD3 is the msb. Transmit enable. Transmit error to the PHY. I I O I / O I I I I I O O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 5 5 5
IEEE 1588 Network Synchronization Interface
IIC Peripheral Interface
IIC0SClk IIC0SData IIC Serial Clock. IIC Serial Data. I / O I / O 3.3V IIC 3.3V IIC 1, 5 1, 5
Interrupts Interface
IRQ0:4 Interrupt requests. I 3.3V LVTTL 1, 5
JTAG Interface
TCK TDI TDO TMS TRST Test clock. Test data in. Test data out. Test mode select. Test reset. Must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405EZ. I I O I I 3.3V LVTTL Rcvr w / pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Rcvr w / pull-up 5 5 5 5
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required.
Signal Name Description I / O Type
Notes
System Interface
SysClk SysErr SysReset TestEn DebugEn Halt TmrClk GPIO000:03 GPIO004:05 GPIO006:08 GPIO009 GPIO010:11 GPIO012:19 GPIO019:27 GPIO028:31 GPIO100:12 GPIO113:14 GPIO115:21 General purpose I / O. All of the GPIO signals are multiplexed with other signals. Which signal a pin is connected to depends on the setting of bits in the GPIO registers. System input clock. Machine check exception has occurred. Main system reset. This signal may be driven by the PPC405EZ to cause a board level reset to occur. Test enable. Reserved for manufacturing LSSD test. Debug enable. External request to stop the processor. Processor timer external input. I O I I I I I I / O I / O I / O I / O I / O I / O I / O I / O I / O I / O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 5 5 5 4 5 5 5 4
Trace Interface
TrcClk TS1E TS2E TS1O TS2O TS3:6 Trace interface clock. Operates at half the CPU core frequency. Even trace execution status. Odd trace execution status. Trace status. I I I I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Chameleon Timer Interface
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required.
Signal Name Description I / O Type
Notes
Analog to Digital (ADC) Interface
Digital to Analog (DAC) Interface
Controller Area Network Interface
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required.
Signal Name Description I / O Type
Notes
External Peripheral Interface
NAND Flash Interface
NFALE NFCE0:3 NFCLE NFData0:7 NFRB NFRE NFWE Address latch enable. Cchip selects 0:3. Command latch enable. Data bits 0:7 Read / Busy. If low, indicates that Read / Erase command is in process. If high, indicates that the command is complete. Read enable. Write enable. O O O I / O I O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Serial Peripheral Interface
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required.
Signal Name Description I / O Type
Notes
UART Peripheral Interface
USB Interface
USB1FClk USB1DEV0 USB1DEV0 USB1HOST0 USB1HOST0 USB1HOST1 USB1HOST1 48 MHz clock for USB Device differential + data signal Device differential - data signal Host 0 differential + data signal Host 0 differential - data signal Host 1 differential + data signal Host 1 differential - data signal I I / O I / O I / O I / O I / O I / O 3.3V LVTTL 5V tolerant USB Diff 5V tolerant USB Diff 5V tolerant USB Diff 5V tolerant USB Diff 5V tolerant USB Diff 5V tolerant USB Diff
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 6)
Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 34 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset pull up or pull down as required.
Signal Name Description I / O Type
Notes
Power
Other Pins
Reserved Reserved pins. Do not make voltage, ground, or signal connections to these pins. na na na
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Ratings and Specifications
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings.
VDD L1 C1
L1 - Murata BLM18AG121SN1D C1 - 0.1 F ceramic
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 8. Package Thermal Specifications
The PPC405EZ is designed to operate within a case temperature range of -40°C to +105°C. Thermal resistance values for the EPBGA packages in a convection environment are as follows:
Parameter Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink Symbol 0 (0) 100 (0.51) 24.1 14.3 Airflow ft / min (m / sec) 200 (1.02) 22.9 12.3 300 (1.52) 22.4 11.5 400 (2.02) 22.0 11.1 600 (3.03) 21.6 10.7 °C / W °C / W Unit
Thermal Management The following heat sink was used in the above thermal analysis: Aavid Thermalloy, PN 79985 The heat sink is manufactured by: Aavid Thermalloy 70 Commercial St. Concord, NH 03301 USA Tel: (603)224-9988 URL: www.aavidthermalloy.com
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 9. Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability.
Table 10. Input Capacitance
Parameter 3.3V LVTTL I / O USB 5V Tolerant I / O IIC I / O Symbol CIN1 CIN2 CIN3 Maximum 1.9 3.2 5.8 Unit pF pF pF Notes
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 11. Typical DC Power Supply Requirements
Frequency (MHz) 166 266 333 416 +1.5V Supply 0.81 0.97 1.13 1.2 +3.3V Supply 0.24 0.25 0.29 0.28 Total 1.05 1.22 1.42 1.48 Unit W W W W Notes 1 1 2 3
Table 12. DC Power Supply Loads
Output Pin
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 13. System Clocking Specifications
Figure 3. Clocking Waveform
2.0V 1.5V 0.8V TCH TC TCL
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Spread Spectrum Clocking
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PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 14. Peripheral Interface I / O Clock Timings
Figure 4. Input Setup and Hold Timing Waveform
System Clock
1.5V TIS MIN
TIH MIN
Inputs
Valid
Figure 5. Output Delay and Float Timing Waveform
System Clock 1.5V TOV MAX TOH MIN
Outputs
1.5V Valid MAX MIN
Outputs
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 15. I / O Specifications-All CPU Speeds (Sheet 1 of 2)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. 2. For all interfaces, I / O H is specified at 2.4 V and I / O L is specified at 0.4 V. 3. Maximum skew between IIC output signals is 6ns. 4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between channels. 5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew between channels.
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 15. I / O Specifications-All CPU Speeds (Sheet 2 of 2)
Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. 2. For all interfaces, I / O H is specified at 2.4 V and I / O L is specified at 0.4 V. 3. Maximum skew between IIC output signals is 6ns. 4. Maximum skew between all SPI output signals is 3ns. All SPI inputs signals are latched with less than 4ns of skew between channels. 5. Maximum skew between all PWM output signals is 3.75ns. All PWM input signals are latched with less than 2.5ns of skew between channels.
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Table 16. I / O Specifications-416 MHz CPU
Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. 2. I / O H is specified at 2.4 V and I / O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na 1.6 1.6 na 1.6 na 1.6 na na Hold Time (TIH min) na na na na na na 2.1 2.1 na 2.1 na 2.1 na na 7.2 7.35 7.3 7.3 7.5 na 7.3 na 7.35 na 7.35 7.3 7.1 7.1 7.1 9.2 10 -0.7 0 7.1 7.1 na 5 na 0.9 7.3 na 0.9 0.9 2.1 na 7.1 2 2.16 2.1 2.1 2.1 na 2.1 na 2.15 na 2.15 2.15 0.9 0.9 0.9 0.9 Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I / O H (minimum) 19.1 19.1 19.1 19.1 19.1 19.1 19.1 na 19.1 na 19.1 na 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 I / O L (minimum) 8.7 8.7 8.7 8.7 8.7 8.7 8.7 na 8.7 na 8.7 na 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 Clock Notes
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Initialization
The following describes the method by which initial chip settings are established when a system reset occurs. Strapping When the SysReset input is driven low (system reset), the state of certain I / O pins is read in order to enable default initial conditions before PPC405EZ start-up. The actual instant of capture is the nearest system clock edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V, or 10k to +5V. The recommended pull-down is 1K to GND. These pins are only used for strap functions during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options. The signal names assigned to the pins for normal operation appear below the pin number. Table 17. Strapping Pin Assignments
Pin Strapping Function Option 8 bits wide Initialize from EBC 16 bits wide 32 bits wide 512 page, 3 addr cycle Initialize from NAND Flash 512 page, 4 addr cycle 2K page, 4 addr cycle 2K page, 5 addr cycle Initialize from SPI Reserved Slow Fast na F03 (GPIO114) 0 0 0 0 0 0 0 0 1 1 1 Initialize from IIC Note: If reading of initialization data from the IIC interface fails, the PPC405EZ defaults to strapping option 0010. 1 na 1 1 1 1 E03 (GPIO112) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D01 (GPIO111) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D02 (GPIO110) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Revision Log
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PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
AMCC Proprietary
PPC405EZ - PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Applied Micro Circuits Corporation 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (858) 450-9333 - (800) 755-2622 - Fax: (858) 450-9885 http://www.amcc.com
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