405EX PowerPC 405EX Embedded Processor AMCC PowerPC® 32-bit
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Part Number 405EX Revision 1.09 August 2007
405EX
PowerPC 405EX Embedded Processor
AMCC PowerPC® 32-bit RISC processor core operating from 333MHz 667MHz including 16KB D-caches with parity checking On-chip 128-bit processor local (PLB) operating 200MHz On-chip 32-bit peripheral (OPB) operating External 8-,16-, 32-bit peripheral (EBC) operating 100MHz External master (EBM) operating 100MHz On-chip Security feature with True Random Number generation Eight- 16-bit NAND Flash interface Inter-chip connectivity (SCP IIC) Boot from Flash external peripheral NAND Flash NAND Flash interface (4-channel) support on-chip slaves external bus, UARTs, devices DDR1/2 SDRAM interface operating Mbps
Preliminary Data Sheet
one-lane Express interfaces operating Gbps Gigabit Ethernet interfaces (half- fullduplex) external (GMII/RGMII) port configurable either Host Device Programmable universal interrupt controller (UIC) General Purpose Timer (GPT) serial ports (16750 compatible UART) interfaces operating 400kHz supporting standard EEPROMs (SPI) synchronous full-duplex channel operating General purpose I/Os (GPIOs), each with programmable interrupts outputs Supports JTAG board-level testing System power management, power dissipation small form factor Available RoHS compliant (lead-free) package
Description
With speeds 667MHz, flexible off-chip memory architecture, diverse communications package that includes Express, OTG, 10/100/1000 Ethernet, PowerPC 405EX embedded processor provides power small footprint system-on-a-chip (SOC) solution wide range high performance, cost-constrained embedded applications. This includes wireless applications, security appliances, internet appliances, line cards, intelligent peripherals. easily programmable general purpose, 32-bit RISC controller that offers upgrade path applications need performance connectivity improvements. Technology: Cu-08 CMOS, 90nm Package: 388-ball, 27mm 27mm, enhanced plastic ball grid array (EPBGA), ball pitch Power consumption (est.): less than typical Voltages required: 3.3V, 2.5V, 1.8V (DDR2 SDRAM only), 1.2V
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Contents
Features Description Table Contents List Figures List Tables Ordering, PVR, JTAG Information Address Maps Power Processor Internal Buses External Controller NAND Flash Controller Controller Interface DDR1/2 SDRAM Controller Express Security Function UART Interface Serial Communication Port Interface (SCP/SPI) General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) Gigabit Ethernet JTAG Signal Lists Signal Functional Descriptions Ratings Specifications Spread Spectrum Clocking SDRAM Specifications Initialization
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
List Figures
Figure PPC405EX Embedded Controller Functional Block Diagram Figure Package 27mm, 388-Ball EPBGA Figure Clocking Waveform Figure Input Setup Hold Timing Waveform Figure Output Delay Float Timing Waveform Figure SDRAM Simulation Signal Termination Model Figure SDRAM Write Cycle Timing Figure SDRAM Read Data Path Figure SDRAM Memory Data Figure SDRAM Read Cycle Timing-Example
List Tables
Table System Memory Address (4GB System Memory) Table Address Table Signals Listed Alphabetically Table Signals Listed Ball Assignment Table Groups Table Signal Functional Description Table Absolute Maximum Ratings Table Package Thermal Specifications Table Recommended Operating Conditions Table Input Capacitance Table Typical Power Supply Requirements with DDR1 SDRAM Table Typical Power Supply Requirements with DDR2 SDRAM Table Power Supply Loads with DDR1 SDRAM Table Power Supply Loads with DDR2 SDRAM Table System Clocking Specifications Table Peripheral Interface Clock Timings Table Specifications-All Speeds Table Specifications-333 Table SDRAM Output Driver Specifications Table SDRAM Write Operation Conditions Table Timing-DDR SDRAM Table Timing-DDR SDRAM TSK, TSA, Table Timing-DDR SDRAM Write TimingTSD Table Timing-DDR SDRAM Read Timing Table Strapping Assignments
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Ordering, PVR, JTAG Information
This section provides part number nomenclature. availability, contact your local AMCC sales office.
Order Part Number (see Notes:) PPC405EX-SpAfffTx PPC405EX-NpAfffTx Level
Product Name PPC405EX PPC405EX Notes:
Package 27mm, 388-ball, EPBGA 27mm, 388-ball, EPBGA
Value 0x12911477 0x12911475
JTAG 0x1405B1E1 0x1405B1E1
security feature present, security feature present Package: lead-free (RoHS compliant), leaded Chip revision level Processor frequency 333MHz 400MHz 533MHz 667MHz Case temperature range, -40°C +85°C Shipping package type tape-and-reel blank tray
part number contains part modifier. Included modifier revision code. This refers mask revision number specified part numbering scheme identification purposes only. (Processor Version Register) JTAG register software accessible (read-only) contain information that uniquely identifies part. PPC405EX Embedded Processor User's Manual details about accessing these registers. Order Part Number
PPC405EX-SSA667TZ
Shipping Package AMCC Part Number
Case Temperature Range Processor Speed (MHz)
Security
Chip Package
Revision Level
Note: example above security feature, lead-free, capable running 667MHz, shipped tape-and-reel packaging.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Block Diagram
Figure PPC405EX Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Power Mgmt
Timers Power Processor JTAG Trace
DCRs UART IICx2/ (SPI) NAND Flash Controller
GPIO
Arbiter
On-chip Peripheral (OPB)
16KB D-Cache 16KB I-Cache OPB/PLB Bridges TRNG
Arbiter
Processor Local (PLB4)-128 bits
DDR1/2 SDRAM Controller
EIP-94 Security Feature
PCI-E PCI-E 1-lane 1-lane
Controller (4-Channel)
MAL/w Interrupt Coalescing
AHB-PLB Bridge
Ethernet 1Gbit
Controller ULPI
PPC405EX designed using Microelectronics Blue Logicmethodology which major functional blocks integrated together create ASIC (application-specific integrated circuit) product. This approach provides consistent create complex ASICs using CoreConnectBus Architecture.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Address Maps
PPC405EX incorporates address maps. first address defines possible addressable memory regions that processor access. second address defines Device Configuration Register (DCR) addresses (numbers). DCRs accessed software running PPC405EX processor through mtdcr mfdcr instructions. Table System Memory Address (4GB System Memory)
Function Local Memory Express UART Reserved UART Reserved Reserved Reserved Peripherals Reserved Arbiter Reserved GPIO Reserved Ethernet Ethernet RGMII Bridge Reserved +TRNG Express Interrupt Handler PLB/AHB Peripherals Reserved Security Reserved Notes: peripheral boot selected, peripheral bank automatically configured reset address range listed above. After boot process, software reassign boot memory regions other uses. Express address range 0000 0000 FFFF FFFF FFFF FFFF even though access Memory Memory-Boot Subfunction SDRAM Start Address (Hex) 0000 0000 8000 0000 9000 0000 EF60 0000 EF60 0200 EF60 0208 EF60 0300 EF60 0308 EF60 0400 EF60 0420 EF60 0500 EF60 0520 EF60 0600 EF60 0606 EF60 0700 EF60 0740 EF60 0800 EF60 0880 EF60 0900 EF60 0A00 EF60 0B00 EF60 0C04 EF61 0000 EF62 0000 EF62 0100 EF6C 0000 EF70 0000 EF78 0000 F000 0000 FFE0 0000 Address (Hex) 7FFF FFFF 8FFF FFFF EF5F 00FF EF60 01FF EF60 0207 EF60 02FF EF60 0307 EF60 03FF EF60 041F EF60 04FF EF60 051F EF60 05FF EF60 0605 EF60 06FF EF60 073F EF60 07FF EF60 087F EF60 08FF EF60 09FF EF60 0AFF EF60 0C03 EF60 FFFF EF61 FFFF EF62 00FF EF6B FFFF EF6F FFFF EF77 FFFF EFFF FFFF FFDF FFFF FFFF FFFF Size 256MB 1.5GB 512B 248B 248B 224B 224B 250B 192B 128B 128B 256B 256B 260B 62KB 64KB 256B 640KB 256KB 512KB 8.9MB 254MB
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Address
Function Total Address Space Reserved (Clocking, Power-on Reset) System DCRs SDRAM Controller External Controller (EBC) External Master (EBM) Reserved PLB4XAHB Bridge Reserved Express Express PLB4 Arbiter PLB-to-OPB Bridge OPB-to-PLB Bridge Reserved Power Management Reserved Reserved Reserved Ethernet Reserved
Start Address (Hex) 0x000
Address (Hex) 0x3FF
Size (4KB)1 128W
Notes: address bits (1024 unique addresses). Each unique address represents single 32-bit (word) register, kiloword (KW) (which equals 4KB).
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Power Processor
PPC405 processor fixed-point, 32-bit RISC unit. Features include: Five-stage pipeline with single-cycle execution most instructions, including loads stores Separate, configurable I-caches, both two-way associative Thirty-two 32-bit general purpose registers (GPRs) Unaligned load/store support Hardware multiply/divide Parity detection reporting instruction cache, data cache, translation look-aside buffer (TLB) Double word instruction fetch from cache Translation four logical address space into physical addresses Built-in timer debug support Power management interface bits wide Selectable processor clock ratios (N:1 ratio only, where 3,or
Internal Buses
PPC405EX contains four internal buses: processor local (PLB), Advanced High-Performance (AHB), on-chip peripheral (OPB), device control register (DCR) bus. High performance devices such processor, SDRAM memory controller, Express, Ethernet MAL, utilize PLB. Lower bandwidth interfaces such communications timer interfaces utilize OPB. daisychained provides lower bandwidth path passing status control information between processor other on-chip peripheral functions. Processor Local (PLB) high-performance on-chip used connect PLB-equipped master slave devices PPC405 CPU. provides 128-bit data path with 64-bit addressing operates 200MHz. There bridges between OPB. Features include: Separate simultaneous 6.4GB/s read write data paths Decoupled address data buses Address pipelining Late master request abort capability Hidden (overlapped) request/grant protocol arbitration-locking mechanism Byte-enable capability allows unaligned half word transfers transfers Support 64-B burst transfers Read word address capability Sequential burst protocol Guarded unguarded memory transfers Simultaneous control, address, data phases buffered, flyby, peripheral-to-memory, memory-to-peripheral, memory-to-memory operations Advanced High-Performance (AHB) dedicated 2.0. Features include: 32-bit data path 32-bit address Synchronous From 60MHz 100MHz.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
provides 32-bit address data interfaces, operates 100MHz. There bridges between PLB. Features include: Pipelined read support Dynamic sizing Single-cycle data transfer between masters slaves daisy-chained provides path passing status control information between processor core other on-chip cores. DCRs bits width with 10-bit addressing.
External Controller
external controller (EBC transfers data between external memory peripheral devices attached external peripheral bus. provides direct attachment memory devices such SRAM, device paced memory devices, peripheral devices. Features include: From 60MHz speed Data bits with 27-bit address four chip selects Arbitration multi-master supported Flash interface Boot from (including NAND Flash interface) support Direct support 8-,16-, 32-bit SRAM external peripherals External master support
NAND Flash Controller
NAND Flash controller (NDFC) provides simple interface between External Controller (EBC) variety NAND Flash-based storage devices. Features include: Attachment internal slave device Eight- 16-bit NAND Flash interface four banks NAND Flash supported Device sizes 256MB (32Mb 2Gb) supported 512B device page sizes supported generation hamming code, single-bit correction, double-bit detection (SEC/DED) Eight-bit command write, address write, data read/write Interrupt device ready (after long page write block erase operations) Boot from NAND Executes boot code first block Automatic page read accesses performed based device configuration read address
Controller
Direct Memory Access (DMA) controller Processor Local (PLB) master that enables faster data transfer between memory peripherals than possible under program control. 4-channel controller handles data transfers between memory peripherals from memory-to-memory. Each channel independent registers needed data transfer: control register, source address register, destination address register, transfer count register.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Features include: Memory-to-memory transfers Buffered memory-to-peripheral transfers Buffered peripheral-to-memory transfers Four independent channels Scatter/gather capability dynamically programming multiple transfers Programmable address increment decrement Internal data buffering transfer data to/from slave, including external
Interface
On-the-Go (OTG) controller that configured either Host Device port. Features include: Low- (Host only), Full- High-Speed support Internal optimize performance offload IN/OUT Endpoints Device mode (one isochronous) Supports maximum packet size 1024B (isochronous) 512B (bulk) Support isochronous traffic Three packets microframe (24MB/s throughput) Eight buffer ULPI interface
DDR1/2 SDRAM Controller
Double Data Rate (DDR1/2) SDRAM memory controller supports industry standard discrete devices that compatible with both DDR1 DDR2 specifications. correct supply voltage must provided types devices: DDR1 devices require +2.5V DDR2 devices require +1.8V. Global memory timings, address bank sizes, memory addressing modes programmable. Features include: 32-bit memory interface Optional 8-bit error checking correcting (ECC) 1.6-GB/s peak data rate memory banks each Maximum capacity Support memory bank with latencies 2.5, Clock frequencies from 133MHz (266Mbps) 200MHz (400Mbps) supported (Faster parts used, must clocked faster than 200MHz) Page mode accesses open pages) with configurable paging policy Programmable address mapping timing Software initiated self-refresh Power management (self-refresh, suspend) regions (two chip selects, clock driver)
Express
Express single-lane interfaces include following features: Features include: Compliant with Express base specification Each Express port Point Root Complex. (Upstream Downstream) Applications compliant with rules limited Point port PPC405EX
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
PCI-Express PCI-Express opaque (Non-Transparent) bridge Power Management Supports virtual channel (VC0) with Traffic Class (TC) filtering Maximum Payload block size 256B Supports 512B maximum Read request size Requests supported: posted outbound Write requests (memory messages) posted inbound Write requests outbound Read requests outstanding Express inbound Read requests outstanding Express Outbound request Express Root Port Inbound request Express Point Buffering each Express Port following transaction types: Replay buffer: eight flight transactions 512B Outbound posted Writes 512B Outbound Reads completion 512B Inbound posted Writes 512B Inbound Reads completion Parity checking each buffer Programmable Outbound Memory Regions: Memory, I/O, Message, config, Internal Regs Programmable Inbound Memory Regions: Memory, I/O, Expansion INTx Interrupts support (PCI legacy): four INTx Termination Root Ports. A/B/C/D interrupts wired A/B/C/D INTx types Generation Endpoints Message Signaled Interrupts Generation Point Termination Root Ports MSI_X Termination Root Ports
Security Function
built-in security function cryptographic engine attached 128-bit with built-in interrupt controllers. Features include: Federal Information Processing Standard (FIPS) 140-2 design Support unlimited number Security Associations (SA) Different formats each supported protocol (IPsec, SSL/TLS/DTLS, MACSec, L2/L3 sRTP) Internet Protocol Security (IPSec) features Full packet transforms (ESP Complete header trailer processing (IPv4 IPv6) Multi-mode automatic padding "Mutable bit" handler including IPv4 option IPv6 extension headers Secure Socket Layer (SSL), Transport Layer Security (TLS), Datagram Transport Layer Security (DTLS) Packet transforms One-pass hash-then-encrypt decrypt-then-hash SSL, DTLS packet transforms using ARC4 Stream Cipher Secure Real-Time Protocol (sRTP) features Packet transforms removal insertion Variable bypass offset header length packet
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Media Access Control Security (MACSec) features Cipher suite GCM-AES-128 Header insertion removal Integrity confidentiality with MSDU supported features: GCM-AES with 128-bit key. Integrity only with confidentiality MSDU generation validation supported features AES-GCM, AES-GMAC with 128, key. IPsec/SSL security acceleration engine DES, 3DES, AES, ARC-4, AES-GCM, GMAC-AES encryption/decryption MD-5, SHA-1, SHA-256 hashing Public acceleration RSA, Diffie-Hellman Combined encryption-hash hash-decryption with AES-CCM algorithm. True pseudo random number generators Non-deterministic true random numbers Pseudo random numbers with lengths ANSI X9.17 Annex compliant using algorithm Interrupt controller Fifteen programmable, maskable interrupts Initiate commands input interrupt Sixteen programmable interrupts indicating completion certain operations interrupts mapped level- edge-sensitive programmable interrupt output controller Autonomous, 4-channel 1024-words bits/word) transfer Scatter/gather capability with byte aligned addressing Byte reverse capability descriptors
UART
Universal Asynchronous Receiver/Transmitter (UART) interface provides four configurations: 8-signal port 4-signal ports. 2-signal ports 4-signal port 2-signal port UART performs serial-to-parallel conversion data received from peripheral device modem, parallel-to-serial conversion data received from processor. Features include: Compatible with the16750 software modem control functions (CTS, RTS, DSR, DTR, DCD) UART0 Programmable auto flow (data flow controlled signals) Characters bits Programmable start, stop, parity insertion Sixty-four byte FIFOs buffering data sub-bus specification compliant line break generation/detection false start detection Programmable internal/external loopback capabilities Power Sleep mode Register conformance (after reset) configuration NS16450 register Hold shift registers (eliminate need precise synchronization between processor serial data character mode) Complete status reporting Full prioritized interrupt system controls
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Independently controlled transmit, receive, line status, data interrupts Programmable baud generator (divides serial clock input generates clock) Ability add/delete standard asynchronous communication bits such start, stop, parity to/from serial data Even, odd, no-parity generation detection Stop generation 1.5, bits Variable baud rate Internal diagnostic capability Loopback controls isolating communications link faults Break, parity, overrun, framing error simulation interface with optional support
Interface
Inter-Integrated Circuit (IIC) interface provides Philips I2C® compatible interface operating 400kHz either master, slave, both with bootstrap controller (BSC) included. During chip reset, bootstrap controller read configuration data from compatible memory device (e.g., EEPROM). This data used replace default configuration settings provided chip. Features include: channels Compliant with Philips Semiconductors Specification, dated 1995 Operation 100kHz 400kHz Byte (8-bit) data Addresses bits Slave Transmit Receive Master Transmit Receive Multiple masters supported Programmable master, slave, master/slave Boot parameters read from attached memory (Port with bootstrap controller slave interface bits wide
Serial Communication Port Interface (SCP/SPI)
Serial Communication Port (SCP) (also known Serial Peripheral Interface SPI) full-duplex, synchronous, character-oriented (byte) port that allows exchange data with other serial devices. master serial port supporting three-wire interface (receive, transmit, clock), slave OPB. Features include: channel, full duplex synchronous master 25MHz Programmable internal loopback capabilities Multi-master protocol supported Independent masking interrupts (master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, receive FIFO overflow) Dynamic control serial rate data transfer (serial-master mode only) Data Item size each data transfer under programmer control (4-to-16 bits) slave interface bits wide
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
General Purpose (GPIO) Controller
GPIO controller enables multiplexing module pins with multiple functions within chip. That single package assigned multiple functions. Which function assigned determined register settings controlled software. This significantly reduces number package pins needed support multiple groups. Features include: GPIOs available GPIOs multiplexed with alternate functions dedicated functions, I/Os available GPIOs Direct control functions from registers programmed means master accesses Time multiplexing controller outputs module outputs Programmable conversion module outputs open-drain outputs (enables sharing active outputs externally) Time multiplexing module inputs controller inputs
Universal Interrupt Controller (UIC)
Universal Interrupt Controller (UIC) provides control, status, communications necessary between various sources interrupts PPC405 processor. Features include: external interrupt sources supported Generate interrupt level (high low) edge (rising falling) Programmable synchronous (edge-capture level-sensitive) asynchronous (edge- level-sensitive triggering) Each interrupt source/bit programmable critical critical interface bits wide Optional interrupt handler vector generation Programmable vector base address Programmable vector offset size Programmable interrupt priority ordering Programmable polarity interrupt types Interrupts same type need contiguous positions Status registers provide: current state interrupts, current state enabled interrupts
Gigabit Ethernet
Ethernet support provides Gigabit (10/100/1000 Mbps) interfaces (GMII/RGMII Features include: ANSI/IEEE Std. 802.3 IEEE 802.3u supplement compliant Half-duplex full-duplex supported Receive FIFOs bytes with programmable thresholds control transmit/receive packets Multiple packet handling transmit receive FIFOs Unicast, multicast, broadcast, promiscuous address filtering 256-bit hash filters unicast multicast frames Automatic retransmission collided frames Runt frame rejection Programmable inter-frame IEEE 802.3x compliant frame-based flow control mechanism, including self-assembled control frame transmitting) Wake-on-LAN Power-over-Internet supported
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Programmable internal/external loopback capabilities slave (MAC) master (MAL) interfaces bits wide Extensive error/status vector generation each processed packet VLAN supported (according IEEE Draft 802.3ac/D1.0 standard) Programmable automatic source address inclusion/replacement transmit packets Programmable automatic Pad/FCS stripping receive packets Programmable VLAN inclusion/replacement transmit packets Half- full-duplex GMII/RGMII Jumbo frames support Memory Access Layer (MAL) provides capability Ethernet channel Interrupt coalescence support transmit receive channels
General Purpose Timer (GPT)
provides time base counter system timers addition those defined processor. Features include: 32-bit time base counter driven clock Seven 32-bit compare timers
JTAG
Features include: IEEE 1149.1 test access port JTAG Boundary Scan Description Language (BSDL) Refer list AMCC partners supplying probes with JTAG interface.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Figure Package 27mm, 388-Ball EPBGA
Gold Gate Release Corresponds Ball Location
View
Logo View
Part Number Number
PPC405EX
1YWWBZZZZZ
Side View
Substrate
Epoxy Mold Compound
2.65
27.0
Bottom View
25.0 Basic
27.0
0.60 SOLDERBALL
Notes: dimensions Package conforms JEDEC MS-034C Package available leaded lead-free versions
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Signal Lists
following table lists external signals alphabetical order shows ball (pin) number which signal appears. Shared signals shown with default signal (following reset) brackets alternate signal brackets. Signals that have different functions different modes with same function separated commas. Shared signals appear alphabetically multiple times list-once each signal name ball. Page column indicates page within table "Signal Functional Description" page which signals indicated interface group begin. Table Signals Listed Alphabetically (Sheet
Signal Name AGND AGND AGND AGND AHVDD AHVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD BankSel0 BankSel1 [BusReq]GPIO27[DMAEOT3][IRQ5] [DMAAck0]PerAddr07[TS1] [DMAAck1]GPIO31[IRQ0] [DMAAck2][HoldReq]GPIO22 [DMAAck3][ExtAck]GPIO25[IRQ3] [DMAEOT0][PerAddr05]GPIO26[TS3] [DMAEOT1]GPIO29[IRQ2] [DMAEOT2][ExtReq]GPIO24[IRQ4] [DMAEOT3][BusReq]GPIO27[IRQ5] [DMAReq0]PerAddr06[TS2] [DMAReq1]GPIO30[IRQ1] [DMAReq2][HoldAck]GPIO23 [DMAReq3]PerAddr08[TS0] AMCC Proprietary Ball AD22 AF24 AE24 AF21 AE20 AF20 AD16 AD13 SDRAM SDRAM External Master SDRAM SDRAM Power Power Power Interface Group Page
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 EAGND EAVDD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD [ExtAck]GPIO25[DMAAck3][IRQ3] [ExtReq]GPIO24[DMAEOT2][IRQ4] ExtReset Ball AE16 AE12 AE07 AE08 AB26 AB25 AA26 AA25 AC05 AB04 AC07 AC08 External Master Power SDRAM Power SDRAM Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name GMCCD, GMC1RxClk GMCCrS, GMC1TxClk GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMCRefClk GMCRxClk, GMC0RxClk GMCRxD0, GMC0RxD0 GMCRxD1, GMC0RxD1 GMCRxD2, GMC0RxD2 GMCRxD3, GMC0RxD3 GMCRxD4, GMC1RxD0 GMCRxD5, GMC1RxD1 GMCRxD6, GMC1RxD2 GMCRxD7, GMC1RxD3 GMCRxDV, GMC0RxCtl GMCRxEr, GMC1RxCtl GMCTxClk GMCTxD0, GMC0TxD0 GMCTxD1, GMC0TxD1 GMCTxD2, GMC0TxD2 GMCTxD3, GMC0TxD3 GMCTxD4, GMC1TxD0 GMCTxD5, GMC1TxD1 GMCTxD6, GMC1TxD2 GMCTxD7, GMC1TxD3 GMCTxEn, GMC0TxCtl GMCTxEr, GMC1TxCtl Ball AD04 AF04 AE04 AE03 AF02 AD07 AD09 AC11 AE10 AD10 AF09 AE09 AF07 AF06 AE06 AE05 AF05 AC06 AE01 AD02 AD01 AC03 AC02 AC01 AB03 AB02 AD05 AF03 Ethernet Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball Power Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name Ball AB01 AC04 AC09 AC13 AC18 AC23 AD03 AD24 AE02 AE25 AF01 AF08 AF14 AF19 AF26 Power Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name GPIO00[PerDataPar0] GPIO01[PerDataPar1] GPIO02[PerDataPar2] GPIO03[PerDataPar3] GPIO04[PerData20][USB2Data4] GPIO05[PerData21][USB2Data5] GPIO06[PerData22][USB2Data6] GPIO07[PerData23][USB2Data7] GPIO08[PerCS1][NFCE1][IRQ7] GPIO09[PerCS2][NFCE2][IRQ8] GPIO10[PerCS3][NFCE3][IRQ9] GPIO11[IRQ6] GPIO12[PerData16][USB2Data0] GPIO13[PerData17][USB2Data1] GPIO14[PerData18][USB2Data2] GPIO15[PerData19][USB2Data3] GPIO16[UART0DCD][UART1CTS] GPIO17[UART0DSR][UART1RTS] GPIO18[UART0CTS] GPIO19[UART0RTS] GPIO20[UART0DTR][UART1Tx] GPIO21[UART0RI][UART1Rx] GPIO22[HoldReq][DMAAck2] GPIO23[HoldAck][DMAReq2] GPIO24[ExtReq][DMAEOT2][IRQ4] GPIO25[ExtAck][DMAAck3][IRQ3] GPIO26[PerAddr05][DMAEOT0][TS3] GPIO27[BusReq][DMAEOT3][IRQ5] GPIO28 GPIO29[IRQ2][DMAEOT1] GPIO30[IRQ1][DMAReq1] GPIO31[IRQ0][DMAAck1] Halt [HoldAck]GPIO23[DMAReq2] [HoldReq]GPIO22[DMAAck2] IIC0SData IIC0SClk IIC1SData[SCPDO] IIC1SClk[SCPClkOut] Ball AA01 AA04 AA02 System External Master System Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [IRQ0]GPIO31[DMAAck1] [IRQ1]GPIO30[DMAReq1] [IRQ2]GPIO29[DMAEOT1] [IRQ3][ExtAck]GPIO25[DMAAck3] [IRQ4][ExtReq]GPIO24[DMAEOT2] [IRQ5][BusReq]GPIO27[DMAEOT3] [IRQ6]GPIO11 [IRQ7][PerCS1][NFCE1]GPIO08 [IRQ8][PerCS2][NFCE2]GPIO09 [IRQ9][PerCS3][NFCE3]GPIO10 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemAddr13 MemAddr14 MemClkEn MemClkOut0 MemClkOut0 Ball AE21 AD20 AF22 AE22 AF23 AD21 AC21 AE23 AE26 AD25 AD26 AC24 AB24 AC25 AC26 AA23 AA24 DDR1/2 SDRAM DDR1/2 SDRAM Interrupts Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 MemFBD MemFBR MemODT0 MemODT1 Ball AE17 AF17 AE15 AF15 AF18 AD17 AF16 AD15 AE13 AF12 AF10 AD11 AE14 AF13 AF11 AE11 AD23 AF25 AD18 AE18 DDR1/2 SDRAM DDR1/2 SDRAM Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [NFALE]PerData30 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO08[IRQ7] [NFCE2][PerCS2]GPIO09[IRQ8] [NFCE3][PerCS3]GPIO10[IRQ9] [NFCLE]PerData29 [NFData00]PerData00 [NFData01]PerData01 [NFData02]PerData02 [NFData03]PerData03 [NFData04]PerData04 [NFData05]PerData05 [NFData06]PerData06 [NFData07]PerData07 [NFData08]PerData08 [NFData09]PerData09 [NFData10]PerData10 [NFData11]PerData11 [NFData12]PerData12 [NFData13]PerData13 [NFData14]PerData14 [NFData15]PerData15 [NFRdyBusy]PerData31 [NFREn]PerData27 [NFWEn]PerData28 OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball Power NAND Flash Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PCIE0ATB PCIE0ClkC PCIE0ClkT PCIE0RExt PCIE0RExtG PCIE0Rx PCIE0Rx PCIE0Tx PCIE0Tx PCIE1ATB PCIE1ClkC PCIE1ClkT PCIE1RExt PCIE1RExtG PCIE1Rx PCIE1Rx PCIE1Tx PCIE1Tx [PerAddr05]GPIO26[TS3][DMAEOT0] PerAddr06[TS2][DMAReq0] PerAddr07[TS1][DMAAck0] PerAddr08[TS0][DMAReq3] PerAddr09[TS1E] PerAddr10[TS0E] PerAddr11[TS1O] PerAddr12[TS0O] PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk Ball External Peripheral External Peripheral Express Express Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PerCS0[NFCE0] [PerCS1][NFCE1]GPIO08[IRQ7] [PerCS2][NFCE2]GPIO09[IRQ8] [PerCS3][NFCE3]GPIO10[IRQ9] PerData00[NFData00] PerData01[NFData01] PerData02[NFData02] PerData03[NFData03] PerData04[NFData04] PerData05[NFData05] PerData06[NFData06] PerData07[NFData07] PerData08[NFData08] PerData09[NFData09] PerData10[NFData10] PerData11[NFData11] PerData12[NFData12] PerData13[NFData13] PerData14[NFData14] PerData15[NFData15] [PerData16]GPIO12[USB2Data0] [PerData17]GPIO13[USB2Data1] [PerData18]GPIO14[USB2Data2] [PerData19]GPIO15[USB2Data3] [PerData20]GPIO04[USB2Data4] [PerData21]GPIO05[USB2Data5] [PerData22]GPIO06[USB2Data6] [PerData23]GPIO07[USB2Data7] PerData24[USB2Dir] PerData25[USB2Stop] PerData26[USB2Next] PerData27[NFREn] PerData28[NFWEn] PerData29[NFCLE] PerData30[NFALE] PerData31[NFRdyBusy] [PerDataPar0]GPIO00 [PerDataPar1]GPIO01 [PerDataPar2]GPIO02 [PerDataPar3]GPIO03 PerErr PerOE PerReady PerRW PerWBE0 PerWBE1 PerWBE2 PerWBE3 AMCC Proprietary Ball External Peripheral External Peripheral External Peripheral External Peripheral External Peripheral Interface Group Page
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name PSROUser Reserved SAGND SAVDD [SCPClkOut]IIC1SClk SCPDI [SCPDO]IIC1SData SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVDD SVREF1A SVREF1B SVREF2A SVREF2B SysClk SysErr SysReset TestEn TmrClk TrcClk TRST [TS0]PerAddr08[DMAReq3] [TS1]PerAddr07[DMAAck0] [TS2]PerAddr06[DMAReq0] [TS3][PerAddr05]GPIO26[DMAEOT0] [TS0E]PerAddr10 [TS0O]PerAddr12 [TS1E]PerAddr09 [TS1O]PerAddr11 Ball AD19 AD12 AA02 AA03 AA04 AB23 AC19 AC20 AC22 AD14 AC14 AC16 AD06 AD08 Trace Trace System JTAG Trace JTAG JTAG System DDR1/2 SDRAM Power Serial Communication Port System SDRAM Other Power Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Alphabetically (Sheet
Signal Name [UART0CTS]GPIO18 [UART0DCD][UART1CTS]GPIO16 [UART0DSR][UART1RTS]GPIO17 [UART0DTR][UART1Tx]GPIO20 [UART0RI][UART1Rx]GPIO21 [UART0RTS]GPIO19 UART0Rx UART0Tx [UART1CTS][UART0DCD]GPIO16 [UART1RTS][UART0DSR]GPIO17 [UART1Rx][UART0RI]GPIO21 [UART1Tx][UART0DTR]GPIO20 UARTSerClk USB2Clk [USB2Data0][PerData16]GPIO12 [USB2Data1][PerData17]GPIO13 [USB2Data2][PerData18]GPIO14 [USB2Data3][PerData19]GPIO15 [USB2Data4][PerData20]GPIO04 [USB2Data5][PerData21]GPIO05 [USB2Data6][PerData22]GPIO06 [USB2Data7][PerData23]GPIO07 [USB2Dir]PerData24 [USB2Next]PerData26 [USB2Stop]PerData25 Ball AC10 AC12 AC15 AC17 AE19 DDR1/2 SDRAM Power UART Peripheral UART Peripheral UART Peripheral Interface Group Page
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
following table, only default signal name shown each ball. Shared balls marked with asterisk (*). determine what signals functions shared those balls, look default signal name "Signals Listed Alphabetically" page following table lists signals ball assignment. Table Signals Listed Ball Assignment (Sheet
Ball Halt GPIO24 PerData31 PerData27 PerData29 PerData24 PSROUser GPIO14 SAGND SAVDD PerData13 PerData11 GPIO00 PerData08 PerData03 PerClk GPIO09 PerWBE3 PerWBE0 PerOE PerAddr28 Signal Name Ball GPIO27 GPIO03 GPIO22 PerData26 PerData25 GPIO13 GPIO05 GPIO15 PerReady GPIO01 PerData15 PerData12 PerData09 PerData07 PerData05 PerData01 ExtReset GPIO10 PerCS0 PerWBE2 PerRW PerAddr29 PerAddr27 Signal Name Ball GPIO25 GPIO23 PerData30 USB2Clk PerData28 GPIO02 SysClk GPIO12 GPIO06 GPIO04 PerData14 PerData10 PerData06 PerData02 PerData00 PerErr GPIO08 PerWBE1 PerAddr31 PerAddr30 PerAddr25 PerAddr21 Signal Name Ball Signal Name GPIO31 GPIO30 GPIO29 OVDD TmrClk OVDD OVDD GPIO07 EOVDD OVDD PerData04 OVDD OVDD PerBLast OVDD PerAddr26 PerAddr22 PerAddr19
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball UARTSerClk OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD PerAddr24 PerAddr18 PerAddr15 Signal Name Ball Signal Name GPIO21 GPIO17 GPIO20 GPIO16 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball PerAddr23 PerAddr20 PerAddr16 PerAddr14 Ball Signal Name GPIO19 GPIO18 UART0Rx OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD PerAddr17 PerAddr13 PerAddr11 Ball UART0Tx GPIO11 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD PerAddr12 PerAddr09 Signal Name
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name PCIE0Rx PCIE0Rx AVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball PerAddr10 PerAddr08 PerAddr07 Ball Signal Name AGND PCIE0Tx PCIE0Tx AVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball PerAddr06 GPIO26 Ball Signal Name PCIE0ClkC PCIE0ClkT PCIE0ATB AGND ball ball ball ball ball ball OVDD OVDD ball ball ball ball ball ball SVREF2B TrcClk MemData04 MemData05 Ball AVDD PCIE0RExtG PCIE0RExt AHVDD ball ball ball ball ball ball OVDD OVDD ball ball ball ball ball ball MemData00 DQS0 Signal Name
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball Signal Name PCIE1Rx PCIE1Rx AVDD AVDD ball ball ball ball ball ball ball ball ball ball ball ball SVDD MemData01 MemData06 Ball Signal Name AVDD PCIE1Tx PCIE1Tx AGND ball ball ball ball ball ball ball ball ball ball ball ball MemData03 MemData02 MemData07 Ball Signal Name AGND PCIE1ATB PCIE1ClkT AHVDD ball ball ball ball ball ball OVDD SVDD ball ball ball ball ball ball MemData08 MemData12 MemData13 Ball AVDD PCIE1ClkC PCIE1RExt PCIE1RExtG ball ball ball ball ball ball EOVDD SVDD ball ball ball ball ball ball SVREF1B MemData09 DQS1 Signal Name
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball GPIO28 ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball MemData11 MemData15 MemData14 Signal Name Ball OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ECC0 ECC4 MemData10 Signal Name Ball OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball SVDD ECC1 ECC5 Signal Name Ball Signal Name TRST TestEn IIC0SClk OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball SVDD MemClkEn DQS4
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 Signal Name IIC0SData IIC1SClk SCPDI IIC1SData ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball MemClkOut0 MemClkOut0 ECC7 ECC6 Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 GMCTxD7 GMCTxD6 EOVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball ball SVDD MemAddr12 ECC3 ECC2 Signal Name Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 Signal Name GMCTxD5 GMCTxD4 GMCTxD3 EOVDD GMCTxClk EOVDD EOVDD GMCRxD0 SVREF1A SVREF2A SVDD SVDD MemAddr06 SVDD MemAddr11 MemAddr13 MemAddr14 Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 Signal Name GMCTxD2 GMCTxD1 GMCCD GMCTxEn SysErr GMCRefClk SysReset GMCRxClk GMCRxD2 MemData27 Reserved SVDD MemData23 MemData21 MemODT0 MemAddr01 MemAddr05 MemFBD MemAddr09 MemAddr10
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signals Listed Ball Assignment (Sheet
Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 Signal Name GMCTxD0 GMCMDClk GMCGTxClk GMCRxDV GMCRxD7 EAGND EAVDD GMCRxD4 GMCRxD1 MemData31 DQS3 MemData24 MemData28 MemData18 DQS2 MemData16 MemODT1 BankSel1 MemAddr00 MemAddr03 MemAddr07 MemAddr08 Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 GMCMDIO GMCTxEr GMCCrS GMCRxEr GMCRxD6 GMCRxD5 GMCRxD3 MemData26 MemData30 MemData25 MemData29 MemData19 MemData22 MemData17 MemData20 BankSel0 MemAddr02 MemAddr04 MemFBR Signal Name Ball Signal Name Ball Signal Name
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Group List following table provides summary number package pins (balls) associated with each functional interface group. Table Groups
Group
Total Signal Pins OVDD EOVDD SVDD AVDD AHVDD SAVDD SAGND EAVDD EAGND AGND Total Power Pins Reserved Total Pins
Pins
table "Signal Functional Description" page each external signal listed along with short description signal function. Active-low signals (for example, Halt) marked with overline. preceding table, "Signals Listed Alphabetically" page (ball) number which each signal assigned. Shared Pins Some signals shared same package that used different functions. most cases, signal names shown this table accompanied signal names that might share same pin. need know what, any, signals shared with particular signal, look name "Signals Listed Alphabetically" page expected that single application particular will always programmed serve same function. flexibility sharing allows single chip offer richer selection than would otherwise possible. Initialization Strapping group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Initialization" page 65). Note that these pins strapping considered multiplexing since strapping function programmable. Pull-Up Pull-Down Resistors Pull-up pull-down resistors used strapping during reset retain unused undriven inputs appropriate state. recommended pull-up value +3.3V pull-down value GND, applies only individually terminated signals. prevent possible damage device, I/Os capable becoming outputs must never tied together terminated through common resistor. your system-level test methodology permits, input-only signals connected together terminated through either common resistor directly +3.3V GND. When resistor used, value must ensure that grouped I/Os reach valid logical zero logical state when accounting total input current into PPC405EX.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Signal Functional Descriptions
following table provides description signals PPC405EX. Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
Ethernet Interface
GMCCD, GMC1RxClk GMCCrS, GMC1TxClk GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMII: Collision detect. RGMII Receive clock. GMII: Carrier sense. RGMII Transmit clock. GMII: Transmit clock GMII 1000Mbps. RGMII Transmit clock. Management data clock. Management data I/O. 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS receiver 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS
GMCRefClk GMCRxClk, GMC0RxClk GMCRxD0:3, GMC0RxD0:3 GMCRxD4:7, GMC1RxD0:3 GMCRxDV, GMC0RxCtl GMCRxEr, GMC1RxCtl GMCTxClk GMCTxD0:3, GMC0TxD0:3 GMCTxD4:7, GMC1TxD0:3 GMCTxEn, GMC0TxCtl GMCTxEr, GMC1TxCtl
GMII, RGMII: Reference clock 1000Mbps. GMII: Receive clock. RGMII Receive clock. GMII: Receive data. RGMII Receive data. GMII: Receive data. RGMII Receive data. GMII: Receive data valid. RGMII Receive control. GMII: Receive error. RGMII Receive control. GMII: Transmit clock 10/100Mbps. GMII: Transmit data. RGMII Transmit data. GMII: Transmit data. RGMII Transmit data. GMII: Transmit enable. RGMII Transmit control. GMII: Transmit error. RGMII Transmit control.
Interface
IIC0SClk IIC0SData IIC1SClk IIC1SData Serial Clock. Serial Data. Serial Clock. Serial Data. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
Express Interface
PCIEnATB PCIEnClkC PCIEnClkT PCIEnRExt PCIEnRExtG PCIEnRx PCIEnRx PCIEnTx PCIEnTx Analog Test manufacturing test. Differential input external reference clock. External reference resistor. Attach 1.37 resistor between RExt RExtG provide reference both bias currents impedance calibration circuitry. Differential receiver received serial data. Differential driver transmitted serial data.
LVDS receiver LVDS driver
Interrupts Interface
IRQ0:2 IRQ3:5 IRQ6 IRQ7:9 External interrupt requests. External interrupt requests. External interrupt requests. External interrupt requests. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
JTAG Interface
TRST Test clock. Test data Test data out. Test mode select. Test reset. Must power-on initialize JTAG controller normal operation PPC405EX. 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL w/pull-up
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
System Interface
SysClk System input clock. 3.3V tolerant 2.5V CMOS receiver 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3V LVTTL receiver w/pull-down 3.3V LVTTL receiver w/pull-up 3.3V LVTTL receiver w/pull-up 3.3V LVTTL
SysErr SysReset
Machine check exception occurred. Main system reset. This signal driven PPC405EX cause board level reset occur. Test enable. Reserved manufacturing LSSD test.
TestEn
Halt
External request stop processor.
TmrClk
Processor timer external input. General purpose I/O. Most GPIO signals multiplexed with other signals. Which signal connected external depends setting bits GPIO registers. General purpose I/O. Most GPIO signals multiplexed with other signals. Which signal connected external depends setting bits GPIO registers. Performance screen ring output. module characterization screening only.
GPIO00:27 GPIO29:31
GPIO28
3.3V tolerant 2.5V CMOS
PSROUser
Trace Interface
TrcClk TS0E TS1E TS0O TS1O TS0:3 Trace interface clock. Operates half core frequency. Even trace execution status. trace execution status. Trace status. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
External Peripheral Interface
PerAddr05:31 PerClk PerCS0 PerCS1:3 PerData00:31 PerDataPar0:3 PerOE PerReady PerBLast PerErr PerRW PerWBE0:3 ExtReset Address 5:31. Clock output. Chip selects Chip selects 1:3. Data 0:31. Data parity 0:3. Output enable. Slave ready trasfer data. Last transfer burst access. External error. Read/Write. Write Byte enable 0:3. External reset. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL receiver 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External Master Interface
BusReq ExtAck ExtReq HoldReq HoldAck External request. External data transfer complete. External data transfer request. External request access. External request acknowledge. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Interface
DMAAck0:1 DMAAck2:3 DMAReq0:1 DMAReq2 DMAReq3 DMAEOT0:1 DMAEOT2:3 External peripheral acknowledge. External peripheral acknowledge. External peripheral request. External peripheral request. External peripheral request. External peripheral end-of-transmission. External peripheral end-of-transmission. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
NAND Flash Interface
NFALE NFCE0 NFCE1:3 NFCLE NFData00:15 NFRdyBusy NFRE NFWE Address latch enable. Chip select Chip selects 1:3. Command latch enable. Data Read/Busy. low, indicates that Read/Erase command process. high, indicates that command complete. Read enable. Write enable. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DDR1/2 SDRAM Interface
MemData00:31 MemAddr00:14 MemClkEn MemClkOut0 MemClkOut0 MemFBD MemFBR MemODT0:1 DM0:4 DQS0:4 BA0:2 BankSel0:1 ECC0:7 Memory data. Memory address. address strobe. Column address strobe. Clock enable. Differential SDRAM clock output. Feedback driver. Feedback receiver. Connect externally MemFBD. On-die termination. Write data byte lane mask. byte lane mask byte lane. Byte lane strobe. DQS4 strobe lane. Bank address eight banks. Bank select SDRAM memory banks. check byte. Write enable. 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv 2.5V (1.8V) SSTL2 Dr/Rcv
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name SVREF1A:B SVREF2A:B Description (DDR2) Reference voltage inputs: Min. +1.15 (+0.825)V Nom. +1.25 (+0.9)V Max. +1.35 (0.975)V Type 1.25V (0.9V) Volt receiver
Notes
Serial Communication Port (SCP) Interface
SCPClkOut SCPDI SCPDO Output clock. Data input. Data output. 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
UART Peripheral Interface
UART interface configured follows: 8-pin 4-pin 2-pin (pull DCD, DSR, RTS) 4-pin 2-pin UARTSerClk UARTnCTS UARTnDCD UARTnDSR UARTnDTR UARTnRI UARTnRTS UARTnRx UARTnTx Serial clock input. Clear send. Data carrier detect. Data ready. Data terminal ready. Ring indicator. Request send. Receive data. Transmit data. 3.3V LVTTL receiver w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL receiver w/pull-down 3.3V LVTTL
Interface
USB2Clk USB2Data0:7 USB2Dir USB2Next USB2Stop clock. Parallel data bus. Data direction control. Next data byte control. When data being transferred PHY, next byte should sent. When data being received from PHY, next byte available. Stop output control. 3.3V LVTTL receiver 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Signal Functional Description (Sheet
Notes: Receiver input hysteresis. Must pull "Pull-Up Pull-Down Resistors" page recommended termination values. Must pull down. "Pull-Up Pull-Down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required.
Signal Name Description Type
Notes
Power
OVDD SVDD EOVDD AVDD SAVDD SAGND EAVDD EAGND AHVDD AGND Logic supply (+1.2V). supply (+3.3V). DDR1/2 SDRAM supply (+2.5 +1.8V) CMOS supply (+2.5V) System ground. Logic Analog supply (+1.2V) System analog supply (+2.5V). System analog ground. Ethernet analog supply (+2.5V). Ethernet analog ground. SerDes analog supply (+2.5V). Analog ground.
Other
Reserved connect voltages, grounds, signals these pins.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Ratings Specifications
Table Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device. None performance specification contained this document guaranteed when operating these maximum ratings.
Characteristic Supply Voltage (Internal Logic) Core SerDes Analog Supply Voltage SerDes Analog Supply Voltage Supply Voltage SDRAM DDR1(2) Supply Voltage CMOS Supply Voltage System Analog Supply Voltage Ethernet Analog Supply Voltage Input Voltage (3.3V LVTTL receivers) Storage Temperature Range Case Temperature Range under bias Junction Temperature Range Symbol AVDD AHVDD OVDD SVDD EOVDD SAVDD EAVDD TSTG TJMax Value +1.6 +1.6 +2.6 +3.6 +2.6 (+1.9) +2.6 +2.6 +2.6 +3.6 +150 +120 +125 Unit Notes
analog voltages derived from +1.2V +2.5V supplies, must filtered shown below before entering PPC405EX. separate filter each voltage. This circuit used AVDD, AHVDD SAVDD, EAVDD. AGND with AVDD AHVDD. SAGND with SAVDD. EAGND with EAVDD. These analog grounds must brought connected digital ground plane filter capacitor. Keep wire lengths short possible.
AVDD
Murata BLM18AG121SN1D ceramic
AGND
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Thermal Management Table Package Thermal Specifications
PPC405EX designed operate within case temperature range defined "Recommended Operating Conditions" page Thermal resistance values EPBGA packages convection environment follows:
Parameter Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink Junction-to-case thermal resistance Junction-to-board thermal resistance Notes: Values table achieved with following JEDEC standard board: 114.5mm 101.6mm 1.6mm, layers. chip mounted card with least signal power planes, following relationships exist: Case temperature, measured center case surface with device soldered circuit board. PxCA, where ambient temperature power consumption. PxJC, where TJMax maximum junction temperature power consumption. Symbol (0.51) 16.6 (1.02) 15.8 Airflow ft/min (m/sec) (1.52) 15.4 (2.02) 15.0 (2.53) 14.7 (3.03) 14.4 °C/W Unit
18.9
15.5
12.5
11.4
10.9 Resistance Value
10.7
10.5
10.3
°C/W
8.96 13.74
°C/W °C/W
following heat sink used above thermal analysis: 26.92mm 27mm 11.43mm heat sink manufactured Aavid Thermalloy, 62925
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Supply Voltage SDRAM DDR1(2) Supply Voltage CMOS Supply Voltage Symbol OVDD SVDD EOVDD AHVDD Analog Supply Voltage SAVDD EAVDD Analog Supply Voltage Input (3.3V LVTTL) Input High (3.3V LVTTL) Output (3.3V LVTTL) Output High (3.3V LVTTL) Input (3.3V tol, 2.5V CMOS) Input High (3.3V tol, 2.5V CMOS) Output (3.3V tol, 2.5V CMOS) Output High (3.3V tol, 2.5V CMOS) Input DDR1 (DDR2) (SSTL2) Input High DDR1 (DDR2) (SSTL2) Output DDR1 (DDR2) (SSTL2) Output High DDR1 (DDR2) (SSTL2) Input Common-Mode Input (LVDS) Input High (LVDS) Output (LVDS) Output High (LVDS) Input Leakage Current pull-up pull-down) Input Leakage Current (with internal pull-down) Input Leakage Current (with internal pull-up) AVDD VICM IIL1 IIL2 IIL3 +1.1 +2.0 +2.4 +1.7 +2.0 SVREF 0.18 (0.125) +1.2 +1.2 +0.8 +3.6 +0.4 +3.6 +0.7 +3.6 +0.4 +2.7 SVREF 0.18 (0.125) SVDD +2.4 +2.5 +2.6 Minimum +1.1 +3.15 +2.4 (+1.7) +2.4 Typical +1.2 +3.3 +2.5 (+1.8) +2.5 Maximum +1.3 +3.45 +2.6 (+1.9) +2.6 Unit Notes
JESD8-9 (JESD8-15A) standard. JESD8-9 (JESD8-15A) standard. VICM 0.05 +0.832 +1.243 (LPDL) -150 (LPDL) +1.01 +1.377 VICM 0.05 +1.9 +1.197 +1.509 (MPUL) (MPUL)
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Recommended Operating Conditions (Sheet
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Maximum Allowable Overshoot (3.3V LVTTL) Maximum Allowable Undershoot (3.3V LVTTL) Case Temperature Notes: LPDL least positive down level; MPUL most positive level. Symbol VMAO VMAU -0.6 Minimum Typical Maximum +3.9 Unit Notes
Table Input Capacitance
Parameter 3.3V LVTTL 2.5V CMOS 2.5/1.8V SSTL2 Express differential data receiver Express differential data transmitter Express differential clock receiver Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 Maximum 1.59 1.16 0.188 Unit Notes
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Typical Power Supply Requirements with DDR1 SDRAM
Frequency (MHz) Notes: Values estimates subject change. DDR1 running 333MHz., running 166MHz. DDR1 running 400MHz., running 200MHz. DDR1 running 355MHz., running 177MHz. DDR1 running 333MHz., running 166MHz. +1.2V 1.15 1.25 1.25 1.27 +1.8V +2.5V 0.54 0.60 0.58 0.54 +3.3V 0.10 0.14 0.12 0.10 Total 1.79 1.99 1.95 1.91 Unit Notes
Table Typical Power Supply Requirements with DDR2 SDRAM
Frequency (MHz) Notes: Values estimates subject change. DDR2 running 333MHz., running 166MHz. DDR2 running 400MHz., running 200MHz. DDR2 running 355MHz., running 177MHz. DDR2 running 333MHz., running 166MHz. +1.2V 1.15 1.25 1.25 1.27 +1.8V 0.26 0.28 0.27 0.26 +2.5V 0.17 0.17 0.20 0.17 +3.3V 0.10 0.14 0.12 0.10 Total 1.689 1.84 1.84 1.80 Unit Notes
Table Power Supply Loads with DDR1 SDRAM
Parameter (+1.2V) active operating current AVDD (+1.2V) active operating current AHVDD (+2.5V) active operating current OVDD (+3.3V) active operating current SVDD EOVDD (+2.5V) active operating current SAVDD (+2.5V) active operating current EAVDD (+2.5V) active operating current Notes: Typical Maximum values estimates subject change. Symbol IDD1.2 IADD IAHDD IODD ISADD IEADD Typical Maximum 1390 Unit Notes
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Power Supply Loads with DDR2 SDRAM
Parameter (+1.2V) active operating current AVDD (+1.2V) active operating current AHVDD (+2.5V) active operating current OVDD (+3.3V) active operating current SVDD (+1.8V) active operating current EOVDD (+2.5V) active operating current SAVDD (+2.5V) active operating current EAVDD (+2.5V) active operating current Notes: Typical Maximum values estimates subject change. Symbol IADD IAHDD IODD ISDD IEODD ISADD IEADD Typical Maximum 1390 Unit Notes
Test Conditions Clock timing switching characteristics specified accordance with minimum operating conditions shown table "Recommended Operating Conditions" page signals, specifications characterized 85°C with test load shown figure right. Table System Clocking Specifications
Symbol SysClk Input SCFC SCTCS SCTCH SCTCL SCRT Other Clocks VCOFC PLBFC OPBFC frequency frequency frequency 1800 Frequency Edge stability (phase jitter, cycle-to-cycle) High time nominal period) time nominal period) Rise time 33.33 Processor clock frequency (must SCFC) 333.33 666.66 Parameter Units
Output
10pF
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Figure Clocking Waveform
Note: SysClk GMCRefClk 2.5V (3.3V tolerant) signals. Rise time should measured between 0.7V 1.7V.
(2.0) 1.25 (1.5) (0.8)
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Spread Spectrum Clocking
Care must taken using spread spectrum clock generator (SSCG) with PPC405EX. This controller uses clock generation inside chip. accuracy with which follows SSCG called tracking skew. bandwidth phase angle determine much tracking skew exists between SSCG given frequency deviation modulation frequency. using SSCG with PPC405EX following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating PPC405EX with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation must exceed -3%, modulation frequency must exceed 40kHz. some cases, on-board PPC405EX peripherals impose more stringent requirements (see Note peripheral clock logic that synchronous peripheral because this clock tracks modulation. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur, assuming that connected device running precise baud rates. external serial clock used, baud rate unaffected modulation. Ethernet operation unaffected. operation unaffected. Caution: system designer must ensure that SSCG used with PPC405EX meets these requirements does adversely affect other aspects system.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Peripheral Interface Clock Timings
Clock GMCTxClk frequency GMCTxClk high time GMCTxClk time GMCRxClk frequency GMCRxClk high time GMCRxClk time GMCGTxClk GMCMDClk GMCRefClk GMCRefClk edge stability (phase jitter, cycle-to-cycle) GMCRefClk rise time GMCRefClk high time GMCRefClk time GMCnRxClk GMCnTxClk UARTSerClk TmrClk PerClk USB2Clk (60MHz 0.05%) PCIEnClkC, (Differential clock input) Notes: TOPB period clock. internal clock runs integral divisor ratio frequency clock. maximum clock frequency 100MHz. 57.97 nominal nominal nominal nominal nominal nominal 1000/(2TOPB1 2ns) 60.03 Units
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Figure Input Setup Hold Timing Waveform
Clock
1.25 (1.5)V
Inputs 1.25 (1.5)V Valid
Figure Output Delay Float Timing Waveform
Clock
1.25 (1.5)V
Outputs 1.25 (1.5)V Valid
1.25 (1.5)V
Outputs 1.25 (1.5)V
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal Express Interface PCIEnATB PCIEnRx PCIEnRx PCIEnTx PCIEnTx Ethernet GMII Interface GMCCD GMCCrS GMCMDIO GMCRxD0:7 GMCTxD0:7 GMCRxDV GMCRxEr GMCTxEr GMCTxEn GMCMDIO GMCnRxD0:3 GMCnRxCtl GMCnTxD0:3 GMCnTxCtl Internal Peripheral Interface IICnSData UARTnCTS UARTnRTS UARTnDSR UARTnDCD UARTnDTR UARTnRI UARTnRx UARTnTx SCPDI SCPDO USB2Data0:7 USB2Dir USB2Next USB2Stop Interface DMAAck0:3 DMAReq0:3 DMAEOT0:3 Interrupts Interface IRQ0:9 AMCC Proprietary 15.75 10.46 15.75 15.75 15.75 10.46 10.46 10.46 15.75 15.75 15.75 15.75 15.75 15.75 15.75 15.75 15.75 15.75 15.75 15.75 15.75 10.46 10.46 10.46 10.46 10.46 10.46 10.46 10.46 10.46 10.46 10.46 10.46 10.46 5.51 5.51 5.51 5.51 5.51 5.51 5.51 5.51 7.23 7.23 7.23 7.23 7.23 7.23 7.23 7.23 Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (min) (min) Clock Notes
Ethernet RGMII Interface
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Specifications-All Speeds (Sheet
Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard.
Input (ns) Signal JTAG Interface TRST System Interface GPIO00:10 GPIO11:15 GPIO16:27 GPIO28 GPIO29:31 Halt SysErr SysReset TestEn 11.08 5.51 11.08 15.75 11.08 5.51 5.51 7.37 7.23 7.37 10.46 7.37 7.23 7.23 15.75 10.46 Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (min) (min) Clock Notes
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Specifications-333
Notes: PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) (minimum) 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 11.08 (minimum) 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 7.37 Clock Notes
External Peripheral Interface PerClk PerAddr05:31 PerCS0:3 PerData00:31 PerDataPar0:3 PerOE PerReady PerRW PerWBE0:3 PerBLast PerErr ExtReset BusReq HoldReq HoldAck ExtAck ExtReq NFALE NFCE0:3 NFCLE NFData0:15 NFRdyBusy NFREn NFWEn PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
SDRAM Specifications
SDRAM controller times operation using internal clock signal generates MemClkOut from clock. clock internal signal that cannot directly observed. However MemClkOut same frequency clock signal phase with clock signal. Note: MemClkOut advanced with respect clock means SDRAM0_CLKTR programming register. typical system, users advance MemClkOut 90°. This depends specific application requires thorough understanding memory system general (refer SDRAM Controller chapter PPC405EX Embedded Processor User's Manual). signals terminated indicated Figure timing data following sections. Board Layout Restrictions Clocking Figure SDRAM Simulation Signal Termination Model
MemClkOut 10pF 10pF MemClkOut SOVDD/2
PPC405EX
Addr/Ctrl (DDR2) Addr/Ctrl/Data/DQS/DM (DDR1)
30pF
Note: This diagram illustrates model SDRAM interface used when generating simulation timing data. recommended physical circuit design this interface. actual interface design will depend many factors, including type memory used board layout.
DDR2 SDRAM On-Die Termination Impedance Setting DDR2 applications, On-Die Termination (ODT) impedance value must ohms DIMM Extended Mode Register (EMR) order optimize data transmission during memory write operations.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table SDRAM Output Driver Specifications
Signal Path Write Data MemData00:31 ECC0:7 DM0:4 MemClkOut MemAddr00:14 BA0:2 BankSel0:1 MemClkEn DQS0:4 MemODT0:1 Output Current (mA) (maximum) (maximum)
SDRAM Write Operation rising edge MemClkOut aligns with first rising edge signal writes. following data generated means simulation includes logic, driver, package RLC, lengths. Values calculated over best case worst case processes with speed, junction temperature, voltage follows: Table SDRAM Write Operation Conditions
Case Best Worst Process Speed Fast Slow Junction Temperature (°C) +125 Voltage +1.3 +1.1
Note: following tables timing diagrams, minimum values measured under best case conditions maximum values measured under worst case conditions. timing numbers following sections obtained using simulation that assumes model shown Figure
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
following diagram illustrates relationship among signals involved with write operation. Figure SDRAM Write Cycle Timing
MemClkOut Addr/Cmd
MemData
Delay from rising edge MemClkOut rising/falling edge signal (skew) Setup time address command signals MemClkOut Hold time address command signals from MemClkOut Setup time data signals (minimum time data valid before rising/falling edge DSQ) Hold time data signals (minimum time data valid after rising/falling edge DSQ) Delay from rising/falling edge clock rising/falling edge
Note: timing data following tables based simulation runs using Einstimer. Table Timing-DDR SDRAM
Notes: signals referenced MemClkOut with delay line programmed cycle. Clock speed 200MHz.
Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 (ns) Minimum Maximum
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Timing-DDR SDRAM TSK, TSA,
Signal Name MemAddr00:14 BA0:2 BankSel0:1 MemClkEn 0.20 0.20 +2.3 +2.3 (ns) Minimum Maximum (ns) Minimum (ns) Minimum
Table Timing-DDR SDRAM Write TimingTSD
Notes: measured under worst case conditions. Clock speed values table 200MHz. time values table include cycle 200MHz (5ns 0.25 1.25 ns). obtain adjusted values lower clock frequencies, subtract from values table cycle time lower clock frequency (for example, 1.25 0.25TCYC).
Signal Names MemData00:07, MemData08:15, MemData16:23, MemData24:31, ECC0:7, Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 (ns) 0.84 0.84 0.84 0.84 0.84 (ns) 1.15 1.15 1.15 1.15 1.15
SDRAM Read Operation Read incoming Data from SDRAM done rising falling edges differential signal. Data must centered these edges correct operation. PPC405EX delay with very fine granularity through register programming. SDRAM MemClkOut0 Read Clock Delay order accommodate timing variations introduced system designs using this chip, three-stage data path shown below used eliminate metastability allow data sampling adjusted minimum latency. data stored eight Flip Flops Stage such that transferred later within period.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Figure SDRAM Read Data Path
FeedBack Signals
Clock
Flip-Flop
MemDCFdbkD Driver
Coarse Delay
FeedBack Signal
Delay
Read Start Read Latency adjust circuit
Fine Delay
Clock
Stage Store aligned signal Feedback Data Capture Window Cycles Delay Oversampling Fine Delay
MemDCFdbkR
adjust
Q2_Ovs
Oversampling Clock
Package pins
Compare
(x32)
Read FIFO Upper
[0:63]
Data (x32)
Rising Edge Sync Stage
Stage (x32)
Lower
Stage
[64:127]
Programmed Read Delay
Falling Edge Sync Clock Clock
SDRAM Read Cycle Timing following diagram illustrates relationship signals involved with read operation. Figure SDRAM Memory Data
MemData
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Table Timing-DDR SDRAM Read Timing
measured under worst case conditions. Clock speed values table 200MHz. time values table include cycle 200MHz (5ns 0.25 1.25 ns). obtain adjusted values lower clock frequencies, subtract 0.75 from values table cycle time lower clock frequency (e.g., 1.25 0.25TCYC).
Signal Names MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 Read Data (ns) 0.35 0.35 0.35 0.35 0.35 Read Data Hold (ns) 0.45 0.45 0.45 0.45 0.45
following example, data strobes (DQS) data shown coincident. There actually slight skew specified SDRAM specifications, there additional skew loading signal routing. recommended that signal length signals matched. following example shows timing relationship between SDRAM Data input storing data Stage
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Figure SDRAM Read Cycle Timing-Example
Oversampling Guard Band Clock Clock Memclk (Diff.) MemCntl Data
Feedback Output Clock cycle Delayed
Store Data Stage
Data Stage
Data Stage
Data Stage Valid High Data Stage
Clock
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Initialization
following describes method which initial chip settings established when system reset occurs. Strapping When SysReset input driven (system reset), state certain pins read order enable default initial conditions before PPC405EX start-up. actual instant capture nearest system clock edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. recommended pull-up +3.3V, +5V. recommended pull-down GND. These pins only used strap functions during reset. They used other signals during normal operation. following table lists strapping pins along with their functions strapping options. signal names assigned pins normal operation appear below number.
Table Strapping Assignments
Strapping Initialization Source 8-bit wide 16-bit wide 16-bit wide 8-bit wide NAND Flash 8-bit wide NAND Flash address 0xA8 8-bit wide address 0xA4 Option (UART0DCD) (UART0DSR) (UART0CTS)
Note: PPC405EX Embedded Processor User's Manual option descriptions other details regarding boot process.
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Revision
Date 02/27/2007 03/01/2007 Version 1.00 1.01 Initial creation document. Updates following review initial document. Change package drawing eliminate confusion. Expand system memory map. Define FSource0 signal Reserved. Recommended Operating Conditions data. thermal data. Misc. updates additions. Misc. updates additions including some limited timing data. Correct three ball numbers assigned PerData28. Swap four balls between GND. 05/24/2007 1.04 Swap ball between OVDD SVDD. Correct typographical errors Table missing alphabetical entries PerAddr05, NAND Flash, IIC1. output current values Tables Input various review comments. Update Table Notes column. Update Block Diagram. Swap SAVDD EAVDD signal name assignments package balls. 06/04/2007 1.05 UART configurations. SDRAM section extracted from 460EX with changes appropriate 405EX. Update timing information interfaces. power values. Update capacitance values. Remove Confidential status. Input various review comments. Input review comments corrections. Change default signals GPIO balls GPIO00-GPIO27 signals. Eliminate confusing terminology initialization section. Change voltage names that SDRAM voltage always SVDD both DDR1 DDR2 types. voltage pins originally labeled SVDD changed EOVDD. Update GMCRefClk specifications (rise time, jitter, etc.) Contents Modification
03/22/2007
1.02
04/24/2007
1.03
06/07/2007
1.06
06/28/2007
1.07
07/12/2007 08/21/2007
1.08 1.09
AMCC Proprietary
PPC405EX PowerPC 405EX Embedded Processor
Revision 1.09 August 2007
Preliminary Data Sheet
Applied Micro Circuits Corporation Moffett Park Drive, Sunnyvale, 94089 Phone: (858) 450-9333 (800) 755-2622 Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves right make changes products, datasheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available datasheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered Trademark Applied Micro Circuits Corporation. Copyright 2007 Applied Micro Circuits Corporation.
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