Document Issue 1.00 September 2004 PowerNP NPe405L Data Sheet
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AMCC NPe405L PowerNP Data Sheet
Document Issue 1.00 September 2004
PowerNP NPe405L Data Sheet
AMCC reserves right make changes products, datasheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available datasheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFESUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered Trademark Applied Micro Circuits Corporation. Copyright 2004 Applied Micro Circuits Corporation.
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PowerNP NPe405L Embedded Processor Data Sheet
Features
PowerNP technology using PowerPC 32-bit RISC processor core operating PC-133 synchronous DRAM (SDRAM) interface 32-bit interface non-ECC applications 40-bit interface serves bits data plus check bits applications External peripheral devices Flash interface Direct support 16-bit SRAM external peripherals devices support external peripherals, internal UARTs memory Scatter-gather chaining supported Four channels 10/100 Ethernet MACs supporting external PHYs MII, RMII, SMII interfaces HDLC interface with channels through ports 4.096 Mbps each 8.192 Mbps single port Programmable interrupt controller Seven external internal Edge triggered level-sensitive Positive negative active Non-critical critical interrupt processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector Programmable timers serial ports (16550 compatible UART) interface General Purpose (GPIO) available Supports JTAG board level testing Internal processor local (PLB) runs SDRAM interface frequency
Description
Designed specifically address embedded applications, NPe405L provides highperformance, low-power solution that interfaces wide range peripherals incorporating on-chip power management features lower power dissipation requirements. This chip contains high-performance RISC processor core, SDRAM controller, Ethernet EMACs, HDLC controller, external controller ROM, Flash, peripherals, with scattergather support, serial ports, interface, general purpose I/O. Technology: CMOS SA-12E 0.25 (0.18 Leff) Package: 23mm, 324-ball enhanced plastic ball grid array (E-PBGA) Power (typical): 1.3W 133MHz, 1.7W 200MHz, 1.8W 266MHz
While information contained herein believed accurate, such information preliminary, should relied upon accuracy completeness, representations warranties accuracy completeness made.
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PowerNP NPe405L Embedded Processor Data Sheet
Contents
Ordering, PVR, JTAG Information Address Support SDRAM Memory Controller External Controller (EBC) Controller Serial Interface Interface HDLCEX Interface General Purpose (GPIO) Controller Universal Interrupt Controller (UIC) 10/100 Mbps Ethernet JTAG Signal Lists Signal Description Test Conditions Spread Spectrum Clocking Initialization
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PowerNP NPe405L Embedded Processor Data Sheet
Tables
System Address Address Signals Listed Alphabetically Signals Listed Ball Assignment Summary Signal Functional Description Absolute Maximum Ratings Package Thermal Specifications Recommended Operating Conditions Input Capacitance Electrical Characteristics Clocking Specifications Peripheral Interface Clock Timings Specifications-All Specifications-133 200MHz Specifications-266MHz
Figures
NPe405L Embedded Controller Functional Block Diagram 23mm, 324-Ball E-PBGA Package Input Setup Hold Waveform Output Delay Float Timing Waveform
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PowerNP NPe405L Embedded Processor Data Sheet
Ordering, PVR, JTAG Information
Processor Frequency 133MHz 133MHz 200MHz 200MHz 266MHz 266MHz Level
Product Name NPe405L NPe405L NPe405L NPe405L NPe405L NPe405L
Order Part Number1 IBM25NPe405L-3FA133C IBM25NPe405L-3FA133CZ IBM25NPe405L-3FA200C IBM25NPe405L-3FA200CZ IBM25NPe405L-3FA266C IBM25NPe405L-3FA266CZ
Package 23mm, E-PBGA 23mm, E-PBGA 23mm, E-PBGA 23mm, E-PBGA 23mm, E-PBGA 23mm, E-PBGA
Value 0x416100C0 0x416100C0 0x416100C0 0x416100C0 0x416100C0 0x416100C0
JTAG 0x04247409 0x04247409 0x04247409 0x04247409 0x04247409 0x04247409
Note Order Part Number indicates tape reel shipping package. Otherwise, chips shipped tray.
This section provides part numbering nomenclature NPe405L. availability, contact your local sales office. part number contains part modifier. This modifier provides identification future enhancements (for example, higher performance). Each part number also contains revision code. This refers mask revision number specified part numbering scheme identification purposes only. (Processor Version Register) software accessible contains additional information about revision level part. Refer NPe405L User's Manual details register content.
Part Number
IBM25NPe405L-3FA200Cx
Shipping Package Blank Tray Tape reel Part Number Grade Reliability Operational Case Temperature Range (-40°C +85°C) Processor Speed 133MHz 200MHz 266MHz Revision Level
Package (E-PBGA)
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PowerNP NPe405L Embedded Processor Data Sheet
NPe405L Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers PPC405 Processor Core JTAG D-Cache Trace 16KB I-Cache On-chip Peripheral (OPB) GPIO UART Power Mgmt DCRs
Peripheral Interface Clock Timing table
Controller (4-Channel)
Bridge
Processor Local (PLB) Ethernet HDLCEX
MAL0
MAL1 SDRAM Controller 13-bit addr 32-bit data External Controller 28-bit addr 16-bit data
ZMII
32-channel ports
MII, RMII, SMII
NPe405L designed using Microelectronics Blue Logic methodology which major functional blocks integrated create application-specific ASIC product. This approach provides consistent generate complex ASICs using CoreConnect Architecture.
Address Support
NPe405L incorporates separate address maps. first fixed processor address that serves PowerPC family processors. This address defines possible contents various address regions which processor access. second address Device Configuration Registers (DCRs). DCRs accessed software running NPe405L processor through mtdcr mfdcr commands.
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PowerNP NPe405L Embedded Processor Data Sheet
System Address Total System Memory
Function Subfunction Start Address 0x00000000 SDRAM, External peripherals Note: address ranges listed right above functions. 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xEF900000 Boot-up External peripheral boot UART0 UART1 IIC0 Arbiter Internal peripherals GPIO0 controller registers GPIO1 controller registers Ethernet registers Ethernet registers ZMII control registers HDLCEX Notes: When external peripheral boot selected, peripheral bank automatically configured reset address range listed above. After boot process, software reassign boot memory regions other uses. address ranges listed above reserved. 0xFFE00000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600780 0xEF600800 0xEF600900 0xEF600C10 0xEF610000 Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6007FF 0xEF6008FF 0xEF6009FF 0xEF600C1F 0xEF61FFFF Size 3712MB 44MB 263MB 128B 128B 256B 256B 64KB
General
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PowerNP NPe405L Embedded Processor Data Sheet
Address Device Configuration Register
Function address space Reserved Memory controller registers External controller registers Reserved registers Reserved bridge-out registers Reserved Clock, control reset Power management Interrupt controller Interrupt controller Reserved Miscellaneous controller registers Reserved MAL0 registers (Ethernet) MAL1 registers (HDLCEX) Reserved Notes: address space addressable with bits (1024 unique addresses). Each unique address represents single 32-bit (word) register, kiloword (KW) (which equals KB).
Start 0x000 0x000 0x010 0x012 0x014 0x080 0x090 0x0A0 0x0A8 0x0B0 0x0B8 0x0C0 0x0D0 0x0E0 0x0F0 0x100 0x140 0x180 0x200 0x280
0x3FF 0x00F 0x011 0x013 0x07F 0x08F 0x09F 0x0A7 0x0AF 0x0B7 0x0BF 0x0CF 0x0DF 0x0EF 0x0FF 0x13F 0x17F 0x1FF 0x27F 0x3FF
Size (4KB)1 108W 128W 128W 384W
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PowerNP NPe405L Embedded Processor Data Sheet
SDRAM Memory Controller
NPe405L Memory Controller provides latency access path SDRAM memory. memory controller supports four logical banks. 256MB bank supported, maximum total. Memory access refresh timing, address bank sizes, memory addressing modes programmable. Features include: 11x8 13x11 row-column address modes 4-bank devices supported) Memory operates same frequency 32-bit memory interface support Programmable address range each bank memory address space Industry standard 168-pin DIMMS supported (some configurations) NPe405H supports memory with PC100 support NPe405H supports memory with PC133 support 256MB bank Programmable timing Auto refresh Page Mode Accesses with open pages Power Management (self-refresh) Error Checking Correction (ECC) support Standard single error correct, double error detect coverage Aligned nibble error detect Address error logging
External Controller (EBC)
Supports four ROM, EPROM, SRAM, Flash, Slave Peripheral banks supported 66.66MHz operation Burst non-burst devices 16-bit byte-addressable data width support Latch data Ready, Synchronous Asynchronous Programmable clock-cycle time-out counter with disable Ready
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PowerNP NPe405L Embedded Processor Data Sheet
Programmable access timing device 0-255 wait states non-bursting devices Burst Wait States first access Wait States subsequent accesses Programmable chip select assertion/negation relative driving address Programmable output write-enable assertion/negation relative assertion chip select Programmable address mapping Peripheral device wait "Ready"
Controller
Supports following transfers: Memory-to-memory transfers Buffered peripheral memory transfers Buffered memory peripheral transfers Four channels Scatter/Gather capability programming multiple operations 16-, 32-bit peripheral support (OPB external attached) 32-bit addressing Address increment decrement Internal 32-byte data buffering capability Supports internal external peripherals Support memory mapped peripherals Support peripherals running slower frequency buses
Serial Interface
8-pin UART interfaces provided Selectable internal external serial clock allow wide range baud rates Register compatibility with NS16550 register Complete status reporting capability Transmitter receiver each buffered with 16-byte FIFOs when FIFO mode Fully programmable serial-interface characteristics Supports using internal engine
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PowerNP NPe405L Embedded Processor Data Sheet
Interface
Compliant with Phillips® Semiconductors Specification, dated 1995 Operation 100kHz 400kHz 8-bit data 7-bit address Slave transmitter receiver Master transmitter receiver Multiple masters Supports fixed interface independent byte data buffers programmable interrupt request signal Provides full management protocol Programmable error recovery
HDLCEX Interface
32-channel HDLC controller full-duplex Pulse Code Modulation (PCM) Highway ports speeds 4.096 Mbps port 8.192 Mbps when using single port Supports HDLC protocol well Transparent mode single channel port, autonomous management I-Frames S-Frames Normal Response mode (NRM) protocol channel port. U-frames handled software. Supports software emulation channels
General Purpose (GPIO) Controller
Most GPIOs pin-shared with other functions. Configuration registers provided determine whether particular that GPIO capabilities acts GPIO used another purpose. GPIO function I/Os. Each GPIO output separately programmable emulate open-drain driver (drives zero, threestated output
Universal Interrupt Controller (UIC)
cascaded Universal Interrupt Controllers (UICs) provide control, status, communications necessary interrupt sources PowerPC processor. Features include:
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PowerNP NPe405L Embedded Processor Data Sheet
Seven external internal interrupts Edge triggered level-sensitive Positive negative active Selectable non-critical critical interrupt requests PPC405 processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector generation reduced latency interrupt handling
10/100 Mbps Ethernet
units capable full- half-duplex, Mbps Mbps operation Integrated ZMII Bridge supports MII, SMII RMII connections external PHYs (PHYs included chip) Reduced Media Independent Interface (RMII) Serial Media Independent Interface (SMII) applications Media Independent Interface (MII) single dual applications Dedicated media access layer (MAL) provides support
JTAG
IEEE 1149.1 Test Access Port Debugger support JTAG boundary scan support (BSDL file available)
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PowerNP NPe405L Embedded Processor Data Sheet
23mm, 324-Ball E-PBGA Package
View
Gold gate release corresponds ball location
Note: dimensions
Bottom View
23.0 0.60 0.30
Thermal balls
23.0
0.60 Solder Ball
2.65
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PowerNP NPe405L Embedded Processor Data Sheet
Signal Lists
following table lists external signals alphabetical order shows ball number which signal appears. Multiplexed signals shown with default signal (following reset) brackets alternate signal signals brackets. Multiplexed signals appear alphabetically multiple times list- once each signal name ball. page number listed gives page "Signal Functional Description" page where signals indicated interface group begin.
Signals Listed Alphabetically
Signal Name AVDD BankSel0 BankSel1 BankSel2 BankSel3 ClkEn0 ClkEn1 [DMAAck0]GPIO13 [DMAAck1]GPIO14 [DMAAck2]GPIO15 [DMAAck3]GPIO16 [DMAReq0]GPIO09 [DMAReq1]GPIO10 [[DMAReq2]GPIO11 [DMAReq3]GPIO12 DQM0 DQM1 DQM2 DQM3 DQMCB ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMC0MDClk EMC0MDIO [EMC0Sync]EMC0TxEn[EMC0Tx0En]
(Part
Ball AB15 AA07 AB06 AA06 AA12 AA13 AA04 AA05 AB04 AA03 AB03 AB16 AA16 AB21 Ethernet Ethernet Ethernet SDRAM SDRAM SDRAM External Peripheral External Peripheral SDRAM SDRAM SDRAM Power SDRAM Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] EMC0TxD2[EMC0Tx1D0] EMC0TxD3[EMC0Tx1D1] EMC0TxEn[EMC0Tx0En][EMC0Sync] EMC0TxErr[EMC0Tx1En] [EMC0Tx0En]EMC0TxEn[EMC0Sync] [EMC0Tx1En]EMC0TxErr [EOT0/TC0]GPIO24 [EOT1/TC1]GPIO25 [EOT2/TC2]GPIO26 [EOT3/TC3]GPIO27
(Part
Ball AA22 AB21 AB20 AB21 AB20 J09-J14 K09-K14 L09-L14 Power Note: J09-J14, K09-K14, L09-L14, M09-M14, N09N14, P09-P14 also thermal balls. External Peripheral Ethernet Ethernet Ethernet Ethernet Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name
(Part
Ball M09-M14 N09-N14 P09-P14 AA02 AA21 AB01 AB05 AB09 AB14 AB18 AB22 Power Note: J09-J14, K09-K14, L09-L14, M09-M14, N09N14, P09-P14 also thermal balls. Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name GPIO00[TrcClk] GPIO01[TS1E]GPIO08[TS6] GPIO02[TS2E] GPIO03[TS1O] GPIO04[TS2O] GPIO05[TS3] GPIO06[TS4] GPIO07[TS5] GPIO08[TS6] GPIO09[DMAReq0] GPIO10[DMAReq1] GPIO11[DMAReq2] GPIO12[DMAReq3] GPIO13[DMAAck0] GPIO14[DMAAck1] GPIO15[DMAAck2] GPIO16[DMAAck3] GPIO17[IRQ0] GPIO18[IRQ1] GPIO19[IRQ2] GPIO20[IRQ3] GPIO21[IRQ4] GPIO22[IRQ5] GPIO23[IRQ6] GPIO24[EOT0/TC0] GPIO25[EOT1/TC1] GPIO26[EOT2/TC2] GPIO27[EOT3/TC3] GPIO28[UART1_DCD][HDLCEXTxEnA] GPIO29[UART1_RI][HDLCEXTxEnB] GPIO30 GPIO31[PerWE] Halt HDLCEXRxClk HDLCEXRxDataA HDLCEXRxDataB HDLCEXRxFS HDLCEXTxClk HDLCEXTxDataA HDLCEXTxDataB [HDLCEXTxEnA]GPIO28[UART1_DCD] [HDLCEXTxEnB]GPIO29[UART1_RI] HDLCEXTxFS
(Part
Ball AA17 AB17 AA15 AA15 System HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel HDLC 32-Channel System Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name IICSCL[IECSCL] IICSDA[IECSDA] [IRQ0]GPIO17 [IRQ1]GPIO18 [IRQ2]GPIO19 [IRQ3[GPIO20 [IRQ4[GPIO21 [IRQ5]GPIO22 [IRQ6[GPIO23 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1
(Part
Ball AA17 AB17 AB11 AA11 AA10 AB10 AA09 AB08 AA08 AB07 AA14 AB13 SDRAM SDRAM Note: During cycle MemAddr00 least significant (lsb) this bus. Interrupts Interface Group Internal Peripheral Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemDatar07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31
(Part
Ball AB02 AA01 SDRAM Notes: MemData00 most significant (msb). MemData31 least significant (lsb) Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
(Part
Ball Power Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0 PerCS1 PerCS2 PerCS3
(Part
Ball External Peripheral External Peripheral External Peripheral External Peripheral Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerErr PerOE PerPar0 PerPar1 PerR/W PerReady PerWBE0 PerWBE1 [PerWE]GPIO31 PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] [PHY0CrS1DV]PHY0RxDV PHY0RxClk [PHY0RefClk]PHY0TxClk PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] PHY0RxD2[PHY0Rx1D0] PHY0RxD3[PHY0Rx1D1] PHY0RxDV[PHY0CrS1DV] PHY0RxErr[PHY0Rx0Er] [PHY0Rx0Er]PHY0RxErr PHY0TxClk[PHY0RefClk] SysClk SysErr SysReset
(Part
Ball AB19 AA18 AA19 AA20 AA20 AB12 Ethernet Ethernet Ethernet Ethernet SDRAM System System System JTAG Ethernet External Peripheral External Peripheral External Peripheral External Peripheral External Peripheral External Peripheral External Peripheral Ethernet Ethernet Ethernet Ethernet Ethernet External Peripheral Note: PerData00 most significant (msb) this bus. Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name [TC0/EOT0]GPIO24 [TC1/EOT1]GPIO25 [[TC2/EOT2]GPIO26 [TC3/EOT3]GPIO27 TestEn TmrClk [TrcClk]GPIO00 TRST [TS1E]GPIO01 [TS2E]GPIO02 [TS1O]GPIO03 [TS2O]GPIO04 [TS3]GPIO05 [TS4]GPIO06 [TS5]GPIO07 [TS6]GPIO08 UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_CTS [UART1_DCD]GPIO28[HDLCEXTxEnA] UART1_DSR UART1_DTR [UART1_RI]GPIO29[HDLCEXTxEnB] UART1_RTS UART1_Rx UART1_Tx UARTSerClk
(Part
Ball AA15 Internal Peripheral Internal Peripheral Trace JTAG JTAG System System JTAG Trace JTAG Trace Trace External Peripheral Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name
(Part
Ball Power SDRAM Interface Group Page
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name PerPar1 PerAddr06 PerAddr09 UART0_DSR PerAddr17 PerAddr20 PerAddr23 PerAddr27 PerAddr30 GPIO31[PerWE] PerCS2 PerR/W PerClk IICSDA[IECSDA] GPIO02[TS2E] SysReset Ball PerPar0 PerAddr08 PerAddr11 PerAddr12 PerAddr14 PerAddr16 PerAddr19 PerAddr22 PerAddr25 PerAddr26 PerAddr31 PerWBE0 PerCS0 PerCS3 PerReady GPIO27[EOT3/TC3] GPIO25[EOT1/TC1] GPIO24[EOT0/TC0] GPIO00[TrcClk] UART0_CTS
(Part
Ball Signal Name PerData13 PerData11 PerAddr05 PerAdd7 PerAddr10 PerAddr13 PerAddr15 PerAddr21 PerAddr24 PerAddr28 PerAddr29 PerWBE1 PerCS1 PerBLast GPIO26[EOT2/TC2] IICSCL[IECSCL] GPIO01[TS1E] UART0_DCD SysErr UART0_Rx Ball Signal Name PerData10 PerData08 PerData14 OVDD PerAddr04 OVDD PerAddr18 PerOE OVDD GPIO16[DMAAck3] OVDD TmrClk UART0_RTS UART0_RI
Signal Name
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name PerData07 PerData12 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD UARTSerClk Ball PerData04 PerData05 PerData09 PerData15 ball ball ball ball ball ball ball ball ball ball ball ball ball ball UART0_Tx GPIO17[IRQ0] Halt
(Part
Ball Signal Name PerData01 PerData02 PerData06 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD UART0_DTR SysClk Ball Signal Name MemData30 MemData31 PerData03 ball ball ball ball ball ball ball ball ball ball ball ball ball ball TestEn AVDD TRST
Signal Name
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name MemData28 MemData29 PerData00 ball ball ball ball ball ball ball ball GPIO18[IRQ1] PerErr Ball MemData27 MemData25 MemData26 ball ball ball ball ball ball ball ball HDLCEXTxClk HDLCEXTxDataA HDLCEXTxFS
(Part
Ball Signal Name DQM3 MemData24 MemData23 ball ball ball ball ball ball ball ball HDLCEXRxClk GPIO19[IRQ2] HDLCEXTxDataB Ball Signal Name MemData21 MemData20 MemData22 ball ball ball ball ball ball ball ball HDLCEXRxFS GPIO20[IRQ3] HDLCEXRxDataA
Signal Name
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name MemData17 MemData19 MemData18 ball ball ball ball ball ball ball ball GPIO3[TS1O] HDLCEXRxDataB GPIO4[TS2O] Ball MemData16 MemData15 MemData13 ball ball ball ball ball ball ball ball GPIO09[DMAReq0] GPIO06[TS4] GPIO05[TS3]
(Part
Ball Signal Name MemData14 DQM2 MemData11 ball ball ball ball ball ball ball ball ball ball ball ball ball ball GPIO12[DMAReq3] GPIO08[TS6] GPIO07[TS5] Ball Signal Name GPIO29[UART1_RI] [HDLCEXTxEnB] MemData12 GPIO30 OVDD ball ball ball ball ball ball ball ball ball ball ball ball ball ball OVDD GPIO15[DMAAck2] GPIO11[DMAReq2] GPIO10[DMAReq1]
Signal Name
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball Signal Name DQM1 MemData10 DQM0 MemData02 ball ball ball ball ball ball ball ball ball ball ball Ball MemData09 MemData05 OVDD ball ball ball ball ball ball ball ball ball ball ball
(Part
Ball Signal Name MemData07 MemData08 MemData03 OVDD ECC7 OVDD MemAddr11 GPIO23[IRQ6] Ball Signal Name MemData04 MemData06 ECC6 ECC4 ECC1 BankSel1 MemAddr08 MemAddr05 MemAddr01 MemAddr00 ClkEn0 PHY0RxD0 [PHY0Rx0D0] [PHY0Rx0D] PHYRxD1 [PHY0Rx0D1] [PHY0Rx1D] PHY0RxDV [PHY0CrS1DV] PHY0CrS [PHY0CrS0DV] PHY0TxClk [PHY0RefClk] UART1_Tx EMC0TxD3 [EMC0Tx1D1]
Signal Name
ball ball ball EMC0TxD1 [EMC0Tx0D1] [EMC0Tx1D] UART1_DTR GPIO14[DMAAck1] GPIO13[DMAAck0]
ball ball ball OVDD UART1_Rx UART1_RTS
OVDD PHY0Col[PHY0Rx1Er] OVDD EMC0TxD2 [EMC0Tx1D0] UART1_DSR UART1_CTS
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PowerNP NPe405L Embedded Processor Data Sheet
Signals Listed Ball Assignment
Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 Signal Name MemData01 ECC3 DQMCB ECC0 BankSel3 BankSel0 MemAddr10 MemAddr07 MemAddr04 MemAddr03 ClkEn1 MemClkOut0 GPIO28[UART1_DCD] [HDLCEXTxEnA] EMC0MDIO GPIO21[IRQ4] PHY0RxD2 [PHY0Rx1D0] PHY0RxD3 [PHY0Rx1D1] PHY0RxErr [PHY0Rx0Er] EMC0TxD0 [EMC0Tx0D0] [EMC0Tx0D] Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 MemData00 ECC5 ECC2 BankSel2 MemAddr12 MemAddr09 MemAddr06 MemAddr02 MemClkOut1 EMC0MDClk GPIO22[IRQ5] PHY0RxClk EMC0TxErr [EMC0Tx1En] EMC0TxEn [EMC0Tx0En] [EMC0Sync]
(Part
Ball Signal Name Ball Signal Name
Signal Name
AA22
AB22
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PowerNP NPe405L Embedded Processor Data Sheet
Signal Description
following table provides summary number package pins (balls) associated with each functional interface group.
Summary
Group
Nonmultiplexed Signals Multiplexed Signals Total Signal Pins AVDD OVDD (and thermal) Reserved Total Pins
Pins
Multiplexed pins table "Signal Functional Description" page each external signal listed along with short description signal function. signals grouped together according their function. Some signals multiplexed same package (ball) that used different functions. most cases, signal name shown this table unaccompanied multiplexed signal names that associated with cases where multiplexed signals same functional group, names appear default signal followed secondary signals square brackets (for example, EMC0TxErr[EMC0Tx1En]). Active-low signals (for example, RAS) marked with overline. signal that primary (default) signal multiplexed shown square brackets. active signal multiplexed controlled programming. expected that single application, particular will always programmed serve same function. flexibility multiplexing allows single chip offer richer selection than would otherwise possible. Initialization Strapping group pins used strapped inputs during system reset. These pins function strapped inputs only during reset used other functions during normal operation (see "Initialization" page 51). Note that these pins strapping considered multiplexing since strapping function programmable. Pull-up Pull-down Resistors Pull-up pull-down resistors used strapping during reset retain unused undriven inputs appropriate state. recommended pull-up value +3.3V (10k used tolerant I/Os) pull-down value GND, applies only individually terminated signals. prevent possible damage device, I/Os capable becoming outputs must never tied together terminated through common resistor. your system-level test methodology permits, input-only signals connected together terminated through either common resistor directly +3.3V GND. When resistor used, value must ensure
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PowerNP NPe405L Embedded Processor Data Sheet
that grouped I/Os reach valid logic zero logic state when accounting total input current into NPe405L. Unused I/Os Strapping some pins necessary when they unused. Although NPe405L requires only pull-up pull-down terminations specified "Signal Functional Description" page good design practice terminate unused inputs configure I/Os such that they always drive. unused, peripheral SDRAM should configured terminated follows: Peripheral interface-PerAddr00:31, PerData00:31, control signals driven default. Terminate PerReady high PerError low. SDRAM-Program SDRAM0_CFG[EMDULR]=1 SDRAM0_CFG[DCE]=1. This causes NPe405L actively drive SDRAM address, data, control signals. External Peripheral Control Signals external peripheral control signals (PerCS0:3, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) high-impedance state when ExtReset=0. addition, detailed PowerNP NPe405L Embedded Processor User's Manual, peripheral controller programmed EBC0_CFG float some these control signals between transactions. result, pull-up resistor should added those control signals where undriven state affect devices receiving that particular signal. following table lists signals provided NPe405L. Please "Signals Listed Alphabetically" page number which each signal assigned. cases where multiplexed signal (indicated square brackets) shown without other signals that assigned that pin, what other signals referring same table.
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PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name Description Type
Notes
HDLCEX Interface
HDLCEXTxClk HDLCEXTxFS HDLCEXTxDataA HDLCEXTxDataB HDLCEXRxClk HDLCEXRxFS HDLCEXRxDataA HDLCEXRxDataB [HDLCEXTxEnA] [HDLCEXTxEnB] Transmit Clock Transmit Frame Synchronization Transmit Data port Transmit Data port Receive Clock Receive Frame Synchronization Receive Data port Receive Data port Transmit Enable port Transmit Enable port 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Ethernet Interface
EMC0MDClk Management Data Clock. MDClk sourced PHY. Management information transferred synchronously with respect this clock (MII, RMII, SMII). Management Data Input/Output bidirectional signal between Ethernet controller PHY. used transfer control status information (MII, RMII, SMII). 3.3V LVTTL
EMC0MDIO
tolerant 3.3V LVTTL
EMC0TxD0[EMC0Tx0D0][EMC0Tx0D] Transmit Data. nibble wide data towards net. EMC0TxD1[EMC0Tx0D1][EMC0Tx1D] data synchronous with PHY0TxClk EMC0TxD2[EMC0Tx1D0] (MII 0[RMII 1][SMII 1]). EMC0TxD3[EMC0Tx1D1] Transmit Enable. This signal driven EMAC2 PHY. Data valid during active state this signal. Deassertion this signal indicates frame EMC0TxEn[EMC0Tx0En][EMC0Sync] transmission. This signal synchronous with PHYTxClk (MII 0[RMII 0]). SMII Sync. Transmit Error. This signal generated Ethernet controller, connected synchronous with PHY0TxClk. informs that error detected (MII Transmit Enable [RMII
3.3V LVTTL
3.3V LVTTL
EMC0TxErr[EMC0Tx1En]
3.3V LVTTL
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name Description Collision [receive error] signal from PHY. This asynchronous signal (MII Receive Error ([RMII 1]). Carrier Sense signal from PHY. This asynchronous signal (MII Carrier sense data valid ([RMII 0]). Receiver medium clock. This signal generated (MII Type tolerant 3.3V LVTTL
Notes
PHY0Col[PHY0Rx1Er]l
PHY0CrS[PHY0CrS0DV]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PHY0RxClk
PHY0RxD0[PHY0Rx0D0][PHY0Rx0D] Received Data. This nibble wide from PHY. PHY0RxD1[PHY0Rx0D1][PHY0Rx1D] data synchronous with PHY0RxClk PHY0RxD2[PHY0Rx1D0] (MII 0[RMII 1][SMII 1]). PHY0RxD3[PHY0Rx1D1] Receive Data Valid. Data Data valid when this signal activated. Deassertion this signal indicates frame reception (MII Carrier sense data valid ([RMII Receive Error. This signal comes from synchronous with PHY0RxClk (MII [RMII 0]). Transmit medium clock. This signal generated ([MII 0]). Reference Clock [RMII SMII].
PHY0RxDV[PHY0CrS1DV]
tolerant 3.3V LVTTL
PHY0RxErr[PHY0Rx0Er]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PHY0TxClk[PHY0RefClk]
SDRAM Interface
Memory Data Notes: MemAddr00 most significant (msb). MemData31 least significant (lsb). Memory Address bus. Notes: MemAddr12 most significant (msb). MemAddr00 least significant (lsb). Bank Address supporting internal banks Address Strobe. Column Address Strobe. byte lane (MemAddr00:7), (MemAddr08:15), (MemData16:23), (MemData24:31) check bits.
MemAddr00:31
3.3V LVTTL
MemAddr12:00
3.3V LVTTL
BA1:0
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
3.3V LVTTL
DQMCB
3.3V LVTTL
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name ECC0:7 BankSel0:3 ClkEn0:1 MemClkOut0:1 check bits 0:7. Select four external SDRAM banks. Write Enable. SDRAM Clock Enable. copies SDRAM clock allows, some cases, glueless SDRAM attachment without requiring this signal repowered zero-delay buffer. Description Type 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
Notes
External Peripheral Interface
PerData00:15 External peripheral data Note: PerData00 most significant (msb) this bus. External peripheral address External peripheral byte parity signals. Peripheral write-bte enable. Byte-enables which valid entire cycle write-byte-enables which valid each byte each data transfer, allowing partial word transactions. Used either external controller controller depending upon type transfer involved. Peripheral write enable. when PerWBE signals low. Peripheral Chip Selects Peripheral output enable. Used either external controller controller depending upon type transfer involved. When NPe405L master, enables peripherals drive bus. Peripheral read/write. Used either external controller controller depending upon type transfer involved. High indicates read from memory, indicates write memory. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerAddr04:31 PerPar0:1
PerWBE0:1
tolerant 3.3V LVTTL
[PerWE] PerCS0:3
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
PerOE
PerR/W
tolerant 3.3V LVTTL
PerReady PerBLast PerClk PerErr
Indicates peripheral ready transfer data. Peripheral burst last. Used indicate last transfer memory access. Peripheral Clock. Used synchronous peripherals. Used indicate errors from peripherals.
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name Description request. Used peripherals request data transfer. Following system reset, default mode signals active-low. They programmed activehigh using DMA0_POL register. acknowledge. Used indicate peripherals that data transfer complete. Following system reset, default mode signals active-low. They programmed active-high using DMA0_POL register. Transfer/Terminal Count. Indication peripherals that data been transfered, controller that programmed amount data been transfered. Following system reset, default mode signals active-low. They programmed active-high using DMA0_POL register. Type tolerant 3.3V LVTTL
Notes
[DMAReq0:3]
[DMAAck0:3]
tolerant 3.3V LVTTL
[EOT0:3/TC0:3]
tolerant 3.3V LVTTL
Internal Peripheral Interface
Serial Clock used provide alternative clock internally generated serial clock. Used cases where allowable internally generated baud rates satisfactory. This input individually connected either both UART0 UART1. UART0 Receive data. UART0 Transmit data. UART0 Data Carrier Detect. UART0 Data Ready. UART0 Clear Send. UART0 Data Terminal Ready. UART0 Request Send. UART0 Ring Indicator. tolerant 3.3V LVTTL
UARTSerClk
UART0_Rx UART0_Tx [UART0_DCD] [UART0_DSR] [UART0_CTS] [UART0_DTR] [UART0_RTS] [UART0_RI]
tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name UART1_Rx UART1_Tx [UART1_DCD] [UART1_DSR] [UART1_CTS] [UART1_DTR] [UART1_RTS] [UART1_RI] IICSCL IICSDA UART1 Receive data. UART1 Transmit data. UART1 Data Carrier Detect. UART1 Data Ready. UART1 Clear Send. UART1 Data Terminal Ready. UART1 Request Send. UART1 Ring Indicator. Serial Clock. Serial Data. Description Type tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Notes
Interrupts Interface
[IRQ0:6] Interrupt Requests. tolerant 3.3V LVTTL
JTAG Interface
TRST Test Data Test Mode Select. Test Data Out. Test Clock. Test Reset. TRST must power-on reset JTAG boundary scan state machine. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Signal Functional Description
(Part Notes: Receiver input hysteresis. Must pull "Pull-up Pull-down Resistors" page recommended termination values. Must pull down. "Pull-up Pull-down Resistors" page recommended termination values. used, must pull used, must pull down. Strapping input during reset; pull pull down required. Pull-up required. "External Peripheral Control Signals" page
Signal Name Description Type
Notes
System Interface
SysClk SysReset SysErr Halt GPIO00:31 TestEn Main System Clock input. Main System Reset. when Machine Check generated. Halt from external debugger. General Purpose I/O. access this function, software must toggle bit. Test Enable. Used only manufacturing tests. Pull down normal operation. This input must toggle rate less than half core frequency (less than 100MHz most cases). most cases this input toggles much slower 1MHz 10MHz range). 3.3V Analog Wire w/ESD tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL 3.3V LVTTL Rcvr w/PD tolerant 3.3V LVTTL
TmrClk
Trace Interface [TS1E] [TS2E] [TS1O] [TS2O] [TS3:6] Even Trace execution status.To access this function, software must toggle bit. Trace execution status. access this function, software must toggle bit. Trace Status. access this function, software must toggle bit. Trace interface clock. toggling signal that always half core frequency. access this function, software must toggle bit. tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL tolerant 3.3V LVTTL
[TrcClk]
Power Pins
OVDD AVDD Ground Note: J09-J14, K09-K14, L09-L14, M09-M14, N09-N14, P09-P14 also thermal balls. Logic voltage-2.5V Output driver voltage-3.3V Filtered voltage-2.5V Hardwire Hardwire Hardwire 3.3V Wire w/ESD
Other Pins
Reserved connect signals, voltage, ground these pins.
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Absolute Maximum Ratings
absolute maximum ratings below stress ratings only. Operation beyond these maximum ratings cause permanent damage device.
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) Supply Voltage Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Notes: voltages specified with respect ground (GND). AVDD should derived from using following circuit: Symbol OVDD AVDD TSTG Value +2.7 +3.6 +2.7 -0.6 (OVDD 0.6) -0.6 (OVDD 2.4) +150 +120 Unit
AVDD
inductor (equivalent MuRata LQH3C2R2M34) chip ferrite bead (equivalent MuRata BLM31A700S) tantalum monolithic ceramic capacitor with dielectric equivalent 0.01 monolithic ceramic capacitor with dielectric equivalent
Package Thermal Specifications
NPe405L designed operate within case temperature range -40°C 85°C. Thermal resistance values E-PBGA packages convection environment follows: Airflow ft/min (m/sec)
23mm, 324-balls-Junction-to-Case 23mm, 324-balls-Case-to-Ambient Notes: chip mounted JEDEC 2S2P card without heat sink. chip mounted card with least signal power planes, following relationships exist: Case temperature, measured center case surface with device soldered circuit board. where ambient temperature power consumption. TCMax TJMax where maximum junction temperature power consumption.
Package-Thermal Resistance
Symbol
Unit
(1.02) °C/W °C/W
(0.51)
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Recommended Operating Conditions
Device operation beyond conditions specified recommended. Extended operation beyond recommended conditions affect device reliability.
Parameter Logic Supply Voltage Supply Voltage Supply Voltage Input Logic High (3.3V LVTTL receivers) Input Logic High (2.5V CMOS receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Output Logic High Output Logic 3.3V input current pull-up pull-down) Input Current (with internal pulldown) Input Current (with internal pull-up) Input Allowable Overshoot (2.5V CMOS receivers) Input Allowable Overshoot (3.3V LVTTL receivers) Input Allowable Overshoot (5.0V LVTTL receivers) Input Allowable Undershoot (3.3V 5.0V receivers) Output Allowable Overshoot (3.3V 5.0V receivers) Output Allowable Undershoot (3.3V 5.0V receivers) Case Temperature Notes:
Symbol OVDD AVDD IIL1 IIL2 IIL3 VIMAO25 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3
Minimum +2.3 +3.0 +2.3 +2.0 +1.7 +2.0 +2.4
Typical +2.5 +3.3 +2.5
Maximum +2.7 +3.6 +2.7 OVDD +5.5 +0.8 OVDD +0.4
Unit
Notes
-250
3.6V) 3.6V) OVDD +5.5
OVDD
"5V-Tolerant Input Current" page
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
5V-Tolerant Input Current
-100 Input Current (µA)
-200 -300
-400
-500
-600 -700 Input Voltage
Input Capacitance
Parameter 3.3V LVTTL I/O) tolerant LVTTL only pins Symbol CIN1 CIN2 CIN4 Maximum 0.75 Unit Notes
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Electrical Characteristics
Parameter Active Operating Current 133MHz Active Operating Current 200MHz Active Operating Current 266MHz Active Operating Current OVDD 133MHz Active Operating Current OVDD 200MHz Active Operating Current OVDD 266MHz Active Operating Current AVDD Active Operating Power 133MHz Active Operating Power 200MHz Active Operating Power 266MHz Notes: Maximum power characterized VDD=2.7V, OVDD=3.6V, TC=85 across silicon process (worse case best case), while running application designed maximize power consumption. maximum power values measured with following clock rate combinations: CPU=133.33MHz, PLB=66.66MHz, OPB=66.66MHz, EBC=33.33MHz CPU=200 MHz, PLB=100MHz, OPB=50MHz, EBC=50MHz CPU=266.66MHz, PLB=66.66MHz, OPB=66.66MHz, EBC=33.33MHz Symbol IODD IODD IODD IADD Minimum Typical Maximum 1.61 2.11 Unit
Test Conditions
Clock timing switching characteristics specified accordance with operating conditions shown table "Recommended Operating Conditions." specifications characterized OVDD 3.00V 85°C with 50pF test load shown figure right.
Output 50pF
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Clocking Specifications
Symbol SysClk Input SysClk clock input frequency SysClk clock period Clock edge stability (phase jitter, cycle cycle) Clock input high time Clock input time 66.66 0.15 nominal period nominal period nominal period nominal period Parameter Units
Note: Input slew rate 2V/ns MemClkOut Output Other Clocks frequency frequency-133MHz frequency-200MHz frequency-266MHz frequency-133MHz frequency-200MHz frequency-266MHz 66.66 133.33 MemClkOut clock output frequency-133MHz MemClkOut clock period-133MHz MemClkOut clock output frequency-200MHz MemClkOut clock period-200MHz MemClkOut clock output frequency-266MHz MemClkOut clock period-266MHz Clock output high time Clock output time nominal period nominal period nominal period nominal period 133.33 66.66
Notes: HDLCEX used, maximum frequency 66.66MHz.
Clocking Waveform
2.0V 1.5V 0.8V
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must taken when using spread spectrum clock generator (SSCG) with NPe405L. This controller uses clock generation inside chip. accuracy with which follows SSCG referred tracking skew. bandwidth phase angle determine much tracking skew there between SSCG given frequency deviation modulation frequency. When using SSCG with NPe405L following conditions must met: frequency deviation must violate minimum clock cycle time. Therefore, when operating NPe405L with more internal clocks their maximum supported frequency, SSCG only lower frequency. maximum frequency deviation cannot exceed -3%, modulation frequency cannot exceed 40kHz. some cases, on-board NPe405L peripherals impose more stringent requirements (see Note peripheral clock (PerClk) logic that synchronous peripheral since this clock tracks modulation. SDRAM MemClkOut since also tracks modulation. Please refer application note Using Spread Spectrum Clock Generator with PowerPC 405GP additional details. This application note available Microelectronics site http://www.chips.ibm.com. Notes: serial port baud rates synchronous modulated clock. serial port tolerance approximately 1.5% baud rate before framing errors begin occur. 1.5% tolerance assumes that connected device running precise baud rates. external serial clock used baud rate unaffected modulation Ethernet operation unaffected. operation unaffected. Caution: system designer ensure that SSCG used with NPe405L meets above requirements does adversely affect other aspects system.
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter EMC0MDClk output frequency EMC0MDClk period EMC0MDClk output high time EMC0MDClk output time PHY0TxClk input frequency PHY0TxClk period PHY0TxClk input high time PHY0TxClk input time PHY0RxClk input frequency PHY0RxClk period PHY0RxClk input high time PHY0RxClk input time PerClk output frequency-133MHz PerClk period-133MHz PerClk output frequency-200MHz PerClk period-200MHz PerClk output frequency-266MHz) PerClk period-266MHz PerClk output high time PerClk output time UARTSerClk input frequency (Note UARTSerClk period UARTSerClk input high time UARTSerClk input time TmrClk input frequency-133MHz TmrClk period-133MHz TmrClk input frequency-200MHz TmrClk period-200MHz TmrClk input frequency-266MHz TmrClk period-266MHz TmrClk input high time TmrClk input time HDLCEXTxClk, HDLCEXRxClk Notes: TOPB period clock. maximum clock frequency 33.33 133MHz parts, 200MHz parts, 66.66MHz 266MHz parts. nominal period nominal period nominal period nominal period nominal period nominal period 2TOPB TOPB TOPB nominal period nominal period 33.33 66.66 nominal period nominal period 1000/(2TOPB 2ns) 33.33 66.66 nominal period nominal period 8.192 Units
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Input Setup Hold Waveform
SysClk 1.5V Inputs
Valid
Output Delay Float Timing Waveform
SysClk
1.5V
Outputs
1.5V Valid
Outputs
1.5V
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Specifications-All
Input (ns) Signal Output (ns) Hold Time (TOH min) async async async async async async async async async async async Output Current (mA) (maximum) (minimum) Clock Notes
Setup Time Hold Time Valid Delay (TIS min) min) (TOV max) async async async async async async async async [async] async [async] async async async async async async async async async async async async async async async async async [async] async [async] async async async async async async async async async async async async async async async async async async async async
Internal Peripheral Interface
IICSCL IICSDA UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_CTS [UART1_DCD] UART1_DSR UART1_DTR [UART1_RI] UART1_RTS UART1_Rx UART1_Tx UARTSerClk
Interrupts Interface
[IRQ0:6] JTAG Interface TRST
System Interface
GPIO30 Halt SysClk SysErr SysReset TestEn TmrClk
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Specifications-133 200MHz
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative SysClk terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405L package pin. System designers must NPe405L IBIS model (available from www.chips.ibm.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Output (ns) Hold Time (TOH min) [2.3] [1.7] [2.3] [1.7] 2.9[2.4] Output Current (mA) (maximum) (minimum) EMC0MDClk PHYTX Clock Notes Setup Time Hold Time Valid Delay (TIS min) min) (TOV max) 10.5 [7.3] [5.0] 11.8 [7.2] [5.6] 11.8[7.4] 10.5 11.3 11.8 11.2
Ethernet Interface
EMC0MDClk EMC0MDIO EMC0TxD0:3 [EMC0Tx0:1D0:1] [EMC0Tx0:1D] EMC0TxEn [EMC0Tx0En] [EMC0Sync] EMC0TxErr[EMC0Tx1En] PHY0Col[PHY0Rx1Er] PHY0CrS[PHY0CrS0DV] PHY0RxClk PHY0RxD0:3 [PHY0Rx0:1D0:1] [PHY0Rx0:1D] PHY0RxDV[PHY0CRS1DV] PHY0RxErr[PHY0Rx0Er] PHY0TxClk[PHY0RefClk] async
async[0.2] async[0.1] [0.8] [0.9] 1.3[0.7] 1.3[0.7] 23.8 24.2 20.3
async[1.7] async[1.9] [1.7] [0.3] 1.7[1.7] 1.8[1.9]
PHYTX PHYTX
async
PHYRX PHYRX PHYRX
async
HDLCEX Interface
HDLCEXRxClk HDLCEXRxDataA:B HDLCEXRxFS HDLCEXTxClk HDLCEXTxDataA:B HDLCEXTxFS [HDLCEXTxEnA] [HDLCEXTxEnB]]
Trace Interface
[TrcClk]GPIO00 [TS1E]GPIO01 [TS2E]GPIO02 [TS1O]GPIO03 [TS2O]GPIO04 [TS3:6]GPIO05:08
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Specifications-133 200MHz
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative SysClk terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405L package pin. System designers must NPe405L IBIS model (available from www.chips.ibm.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Output (ns) Hold Time (TOH min) -1.2 [1.1] [1.1] [1.2] -0.9 [1.3] Output Current (mA) (maximum) (minimum) Clock Notes Setup Time Hold Time Valid Delay (TIS min) min) (TOV max) [4.8] [4.3] [0.0] [-0.1] -0.5 -0.6 [7.0] [7.5] [8.5] [8.3]
SDRAM Interface
BA1:0 BankSel3:0 ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:00 MemClkOut0:1 MemData00:31 [DMAReq0:3] [DMAAck0:3] [EOT0:3/TC0:3] PerAddr04:31 PerBLast PerCS0:3 PerData00:15 PerOE PerPar0:1 PerR/W PerReady PerWBE0:1 PerClk PerErr [PerWE] SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk
External Peripheral Interface
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Specifications-266MHz
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative SysClk terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405L package pin. System designers must NPe405L IBIS model (available from www.chips.ibm.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Setup Time Hold Time (TIS min) min) Output (ns) Valid Delay (TOV max) [5.6] [4.6] [5.5] [4.2] 9.4[5.7] [8.5] [8.9] Hold Time (TOH min) [2.3] [1.7] [2.3] [1.7] 2.9[2.4] [3.5] [3.8] Output Current (mA) (maximum) (minimum) EMC0MDClk PHYTX Clock Notes
Ethernet Interface
EMC0MDClk EMC0MDIO EMC0TxD0:3 [EMC0Tx0:1D0:1 [EMC0Tx0:1D] EMC0TxEn [EMC0Tx0En] [EMC0Sync] EMC0TxErr[EMC0Tx1En] PHY0Col[PHY0Rx1Er]l PHY0CrS[PHY0CrS0DV] PHY0RxClk PHY0RxD0:3 [PHY0Rx0:1D0:1] [PHY0Rx0:1D] PHY0RxDV[PHY0CRS1DV] PHY0RxErr[PHY0Rx0Er] PHY0TxClk[PHY0RefClk] async
async[0.1] async[0.1] [0.8] [0.8] 1.3[0.7] 1.3[0.7] 23.9 24.2 24.2
async[1.4] async[1.5] [1.3] [0.2] 1.3[1.3] 1.4[1.5]
PHYTX PHYTX
async
PHYRX PHYRX PHYRX
async
HDLCEX Interface
HDLCEXRxClk HDLCEXRxDataA:B HDLCEXRxFS HDLCEXTxClk HDLCEXTxDataA:B HDLCEXTxFS [HDLCEXTxEnA] [HDLCEXTxEnB]
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Specifications-266MHz
(Part Notes: Ethernet interface meets timing requirements defined IEEE 802.3 standard. SDRAM command interface configurable through SDRAM0_TR[LDF] provide cycle delay before command used SDRAM. Output times table cycle SDRAM timings specified relative SysClk terminated lumped 10pF load. SDRAM interface hold times guaranteed NPe405L package pin. System designers must NPe405L IBIS model (available from www.chips.ibm.com) ensure their clock distribution topology minimizes loading reflections, that relative delays clock wiring exceed delays other SDRAM signal wiring. PerClk rising edge package with 10pF load trails internal clock approximately 0.8ns.
Input (ns) Signal Setup Time Hold Time (TIS min) min) -0.1 -0.5 -0.6 Output (ns) Valid Delay (TOV max) Hold Time (TOH min) -1.2 -0.9 Output Current (mA) (maximum) (minimum) SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk SysClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk Clock Notes
Trace Interface
[TrcClk] [TS1E] [TS2E] [TS1O] [TS2O] [TS3:6]
SDRAM Interface
BA1:0 BankSe3:0 ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:00 MemClkOut0:1 MemData00:31 [DMAReq0:3] [DMAAck0:3] [EOT0:3/TC0:3] PerAddr04:31 PerBLast PerCS0:3 PerData00:15 PerOE PerPar0:1 PerR/W PerReady PerWBE0:1 PerClk PerErr [PerWE]
External Peripheral Interface
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Initialization
following describes method which initial chip settings established when system reset occurs. Strapping While SysReset input (system reset), state certain pins read enable default initial conditions prior NPe405L start-up. actual capture instant nearest SysClk edge before deassertion reset. These pins must strapped using external pull-up (logical pull-down (logical resistors select desired default conditions. recommended pull-up +3.3V +5V, recommended pull-down GND.These pins used strap functions only during reset. They used other signals during normal operation. following table lists strapping pins along with their functions strapping options.
Strapping Assignments
Function EXT_BootW Width boot device data bits bits ZMII_Mode Ethernet ZMII mode mode SMII mode RMII Mbps mode RMII Mbps mode Option Ball Strapping (UART1_Tx) (UART1_RTS) (UART1_DTR)
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
Copyright International Business Machines Corporation 1999, 2002
Rights Reserved Printed United States America, October 2002 following trademarks International Business Machines Corporation United States, other countries, both: Blue Logic PowerPC CodePack CoreConnect Logo PowerNP
Other company, product, service names trademarks service marks others. Preliminary Edition (October 2002) This document contains information product under development IBM. reserves right change discontinue this product without notice. This document preliminary edition PowerNP NPe405L data sheet. Make sure using correct edition level product. While information contained herein believed accurate, such information preliminary, should relied upon accuracy completeness, representations warranties accuracy completeness made. information contained this document subject change without notice. products described this document intended applications such implantation, life support, other hazardous uses where malfunction could result death, bodily injury, catastrophic property damage. information contained this document does affect change product specifications warranties. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. information contained this document obtained specific environments, presented illustration. results obtained other operating environments vary. INFORMATION CONTAINED THIS DOCUMENT PROVIDED BASIS. event will liable damages arising directly indirectly from information contained this document. Microelectronics Division 1580 Route Hopewell Junction, 12533-6351 home page www. ibm.com. Microelectronics Division home www.chips.ibm.com. SA14-2558-10
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