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TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Features
High-Quality Audio Performance: 102-dB ADC/105-dB (Typical) Eight-Channel Programmable Audio (Four-Channel Digital Four-Channel Analog) Three Differential Stereo Analog Inputs Multiplexed Stereo Input ADCs Differential Stereo Output DACs Serial Audio Inputs (Four Channels) Serial Audio Outputs (Four Channels) 135-MHz Maximum Speed, >2800 Processing Cycles Sample XTAL Input Master Mode, MCLK_IN Slave Mode 48-kHz Sample Rate Master Mode 44.1 48-kHz Sample Rate Slave Mode 48-Bit Data Path 28-Bit Coefficients Words 48-Bit Data Memory 1022 Words 28-Bit Coefficient Memory Words 55-Bit Program Hardware Single-Cycle Multiplier 2812 Instructions 5.88K Words 24-Bit Delay Memory (122.5 kHz) Data Formats: Left Justified, Right Justified, Ports Slave Master Download Single 3.3-V Power Supply Graphical Development Environment Provided Audio Processing; e.g., Algorithm Development, Etc.
Applications
Docking Systems Digital Televisions Mini-Component Audio
TAS3204
SDIN1 SDIN2 Differential Analog Stereo Stereo Input Digital Audio Processor Core 48-Bit Data Path 28-Bit Coefficients 76-Bit Output Stereo Stereo Differential Analog SDOUT1 SDOUT2
Code Upper Data Lower Data 1.2K Coeff. Boot
MCLK_IN LRCLK_IN SCLK_IN MCLK_OUTx LRCLK_OUT SCLK_OUT Port Port
Clock Control
Volume Update 8051 8-Bit Microprocessor IRAM ERAM Code Code
Interface
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this document.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2007, Texas Instruments Incorporated
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Contents
Introduction
Features Applications 8.6.1 8.6.2 8.6.3 Absolute Maximum Ratings Package Dissipation Ratings Recommended Operating Conditions Electrical Characteristics Audio Specifications Timing Characteristics. Master Clock
Analog Input/MUX/Stereo ADCs Stereo DACs Analog Reference System Power Supply Clocks, Digital PLL, Serial Data Interface Control Interface 8051 Microcontroller Audio Digital Signal Processor Core Physical Characteristics Terminal Assignments Ordering Information Terminal Descriptions Reset (RESET) Power-Up Sequence Voltage Regulator Enable (VREG_EN) Power-On Reset (RESET) Power Down (PDN) Control (CS0) Programmable (GPIO) 3.10 Input Output Serial Audio Ports
Functional Description Algorithm Software Development Tools TAS3204 Clock Controls Microprocessor Controller
Serial Audio Port, Slave Mode Serial Audio Port Master Mode Signals (TAS3204) 8.6.4 Pin-Related Characteristics Stages F/S-Mode 2C-Bus Devices 8.6.6 Reset Timing
Register
9.10 9.11 9.12 Clock Control Register (0x00)
Microcontroller Clock Control Register Status Register (0x02) Memory Load Control Data Registers (0x04 0x05) Memory Access Registers (0x06 0x07)
Device Version (0x08) Analog Power Down Control (0x10 0x11), ESFR (0xE1 0xE2) Analog Input Control (0x12), ESFR (0xE3)
Slave Mode Operation Master-Mode Device Initialization Digital Audio Processor (DAP) Arithmetic Unit Instructions Data Word Structure Electrical Specifications
8051 Microprocessor Addressing Mode General Operations
Dynamic Element Matching (0x13), ESFR (0XE4). Current Control Select (0x14, 0x15, 0x17, 0x18), ESFR (0xE5, 0xE6, 0xE7, 0xE9) Control (0x1A, 0x1B, 0x1D), ESFR (0xEB, 0xEC, 0xEE). Reset (0x1E), ESFR (0xFB)
9.13 Input Gain Control (0x1F), ESFR (0xFA) 9.14 MCLK_OUT Divider (0x21 0x22) 9.15 Digital Cross (0x30 0x3F) 9.16 Extended Special Function Registers (ESFR) Application Information 10.1 Schematics 10.2 Recommended Oscillator Circuit
Contents
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TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Functional Description
TAS3204 audio system-on-a-chip (SOC) designed mini/micro systems, multimedia-speaker, player docking systems. includes analog interface functions: three multiplex (MUX) stereo inputs with stereo analog-to-digital converters (ADCs), stereo digital-to-analog converters (DACs) with analog outputs consisting differential stereo line drivers. Four channels serial digital audio processing also provided. TAS3204 programmable audio digital signal processor (DSP) that preserves high-quality audio using 48-bit data path, 28-bit filter coefficients, single cycle multiplier. programmability feature allows users customize features RAM. TAS3204 composed eight functional blocks: Analog input/mux/stereo stereo DACs Analog reference system Power supply Clocks, digital pll, serial data interface control interface 8051 microcontroller Audio digital audio processing
512Fs XTAL
Oscillator
Master
DPLL
Master/Slave
8051 Microprocessor Core
Control Registers 8-Bit
Control Interface
SCL1/SDA1 SCL2/SDA2
MCLK_IN 512Fs
Slave
External Internal Clock Divider Code Clock Generation Control
GPIO1/2
Volume Update
LRCLK_IN SCLK_IN LRCLK_OUT SCLK_OUT
Memory Interface
Core
Coefficient 1.2K
Data
Serial Audio Port SDIN1/2
Input Cross Mixer
SDOUT1/2
256Fs
Output Cross Mixer
Data Path
Upper Lower
Code Stereo
Differential Stereo Analog Outputs
128Fs
Three Differential Stereo Analog Inputs Stereo
Power Supply
AVDD DVDD
Legend Clocks Digital Data
Internal Connection
Analog Data
External Connection
Figure 2-1. Expanded Functional Block Diagram
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Functional Description
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Analog Input/MUX/Stereo ADCs
These modules allow three differential analog stereo inputs sent either ADCs converted digital data. input multiplexers include preamplifier. This amplifier driving ADCs, digitally controlled with changes synchronized with sample clock ADC. Minimal crosstalk between selected channels unselected channels maintained. When inputs needed they configured minimal noise. Also included this module fully differential over sampled stereo ADCs. ADCs sigma-delta modulators with times over-sampling ratio. Because over-sampling nature audio ADCs integrated digital decimation filters, requirements analog anti-aliasing filtering relaxed. Filter performance ADCs specified under physical characteristics.
Stereo DACs
This module includes stereo audio DACs, each which consists digital interpolation filter, digital sigma-delta modulator analog reconstruction filter. Each operate maximum kHz. Each upsamples incoming data performs interpolation filtering processing this data before conversion stereo analog output signal. sigma-delta modulator always operates rate 128Fs, which ensures that quantization noise generated within modulator stays within frequency band below Fs/2.4 sample rates. digital interpolation filters interpolation from included audio upper memory (reserved analog processing), while interpolation from 128Fs done dedicated hardware sample hold filter. TAS3204 includes stereo line driver outputs. line drivers capable driving 10-k load. Each stereo output power-down mode when used. Popless operation achieved conforming start stop sequences device controller code.
Analog Reference System
This module provides internal references needed analog modules. also provides bias currents analog blocks. External decoupling capacitors needed along with external 1%-tolerance resistor internal bias currents. includes band-gap reference several voltage buffers tracking current reference. TAS3204 also uses internally generated supply that used rereference analog inputs present analog outputs. VMID analog supply used when buffered externally rereference analog inputs outputs. voltage reference REXT requires 22-k resistor ground. reference system powered down separately.
Power Supply
power supply contains supply regulators that provide analog digital regulated power various sections TAS3204. Only external 3.3-V supply required. other voltages generated chip from external 3.3-V supply.
Clocks, Digital PLL, Serial Data Interface
These modules provide timing serial data interface TAS3204. clocking system device illustrated Figure 2-2. TAS3204 either clock master clock slave depending configuration. However, master mode primary mode operation.
Functional Description
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TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
DPLL
135-MHz DCLK Microprocessor Clock MCLK_OUT Programmable Divider Programmable Divider
MCLK_OUT2 MCLK_OUT3 From Parallel Data
LRCLK Re-Creation Serial Audio Port Receiver
Serial Audio Port Transmitter
SDOUT
24.576
SDIN Oscillator
512Fs Crystal MCLKI
24.576
Parallel Data
256Fs
128Fs
64Fs
LRCLK_OUT SCLK_OUT
Master/ Slave
Figure 2-2. Clock Generation DISCLAIMER: Analog performance ensured slave mode, analog performance depends upon quality MCLK_IN. TAS3204 robust with respect MCLK_IN errors (glitches, etc.); MCLK_IN frequency changes under operation, device must reset. Master mode operation: External 512Fs crystal oscillator used generate internal clocks plus clocks external asynchronous sampling rate converter (ASRC) output external ASRC present). LRCLK_OUT fixed (Fs). SCLK_OUT fixed 64Fs. MCLK_OUT fixed 256Fs. master mode, external ASRC converts incoming serial audio data 48-kHz sample rate synchronous internally generated serial audio data clocks. master mode, clocks generated TAS3204 derived from 24.576-MHz crystal. internal oscillator drives crystal generates main clock digital (DPLL), master clock outputs, 256Fs clock ADC, 128Fs clock DAC. DPLL generates internal clocks 8051 microprocessor. Slave mode operation: MCLK_IN (512Fs), SCLK_IN (64Fs), LRCLK_IN (Fs) supplied externally. Clock generation similar master mode with exception blocks. MCLK_IN signal divided down sent directly blocks. Therefore, audio performance depends MCLK_IN signal. DSP, MCU, clocks still derived from external crystal oscillator. MCLK_OUT, SCLK_OUT, LRCLK_OUT passed through from clock inputs (MCLK_IN, SCLK_IN, LRCLK_IN). Internal analog clocks DACs derived from external MCLK_IN input, analog performance depends MCLK_IN quality (i.e., jitter, phase noise, etc.). Degradation analog performance expected. Sample rate change/clock change
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TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Sample rate change should handled customer system controller. TAS3204 device does include internal clock error click/pop detection/management. Customer-specific filter coefficients must uploaded customer system controller changing sample rate. slave mode, incoming serial audio data must synchronous incoming LRCLK_IN 44.1 kHz.
Control Interface
TAS3204 slave-only interface (SDA1 SCL1) receiving commands providing status system controller, separate master interface (SDA2 SCL2) download programs data from external memory such EEPROM. Section more information. interface tolerant.
8051 Microcontroller
8051 microcontroller receives distributes write data. retrieves outputs data requested from controller. performs most processing tasks requiring multi-frame processing cycles. microprocessor data storing intermediate values queuing commands, fixed boot program ROM, programmable RAM. microprocessor's boot program cannot altered. microcontroller specialized hardware master slave interface operation, volume updates, programmable interval-timer interrupt.
Audio Digital Signal Processor Core
audio digital signal processor core arithmetic unit fixed-point computational engine consisting arithmetic unit data coefficient memory blocks. audio processing structure, which include mixers, multiplexers, volume, bass treble, equalizers, dynamic range compression, third-party algorithms, running DAP. 8051 microcontroller access resources such coefficient able support with certain tasks; example, volume ramp. primary blocks audio core are: 48-bit data path with 76-bit accumulator controller Memory interface Coefficient Data 24-bit upper memory 48-bit lower memory Program discussed detail following sections.
Functional Description
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TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Physical Characteristics
Terminal Assignments
PACKAGE (TOP VIEW)
I2C2_SCL I2C2_SDA RESET SDIN1/GPIO3 SDIN2/GPIO4 SCLK_IN LRCLK_IN DVDD3 DVSS3 VR_DIG SDO1 SDO2 SCLK_OUT LRCLK_OUT RESERVED VREG_EN
I2C1_SCL I2C1_SDA GPIO2 GPIO1 MUTE DVSS1 DVDD1 VR_PLL AVSSI AIN1LP AIN1LM AIN1RP AIN1RM AIN2LP
MCLK_OUT1 MCLK_OUT2 MCLK_OUT3 DVDD2 DVSS2 MCLK_IN XTAL_OUT XTAL_IN AVDD3 VR_ANA AVSS_ESD AVSSO AOUT1RP AOUT1RM AOUT1LP AOUT1LM
Ordering Information
70°C PLASTIC 64-PIN PQFP (PN) TAS3204PAG
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AIN2LM AIN2RP AIN2RM AIN3LP AIN3LM AIN3RP AIN3RM AVDD1 VMID VREF REXT AVDD2 AOUT2LM AOUT2LP AOUT2RM AOUT2RP
Physical Characteristics
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Terminal Descriptions
TERMINAL NAME AIN1LM AIN1LP AIN1RM AIN1RP AIN2LM AIN2LP AIN2RM AIN2RP AIN3LM AIN3LP AIN3RM AIN3RP AOUT1LM AOUT1LP AOUT1RM AOUT1RP AOUT2LM AOUT2LP AOUT2RM AOUT2RP AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3 DVDD1 DVSS1 DVDD2 DVSS2 DVDD3 DVSS3 GPIO1 GPIO2 I2C1_SCL INPUT/ OUTPUT Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Analog Output Power Power Power Power Power Power Digital Input Power Power Power Power Power Power Digital Digital Digital Input Pull VMID Pull VMID Pull VMID Pull VMID Pull VMID PULLUP/ PULLDOWN Pull VMID DESCRIPTION Analog input, channel left, input Analog input, channel left, input Analog input, channel right, input Analog input, channel right, input Analog input, channel left, input Analog input, channel left, input Analog input, channel right, input Analog input, channel right, input Analog input, channel left, input Analog input, channel left, input Analog input, channel right, input Analog input, channel right,+ input Analog output, channel left, output Analog output, channel left, output Analog output, channel right, output Analog output, channel right, output Analog output, channel left, output Analog output, channel left, output Analog output, channel right, output Analog output, channel right,+ output 3.3-V analog power supply. This must decoupled according good design practices. Analog supply ground 3.3-V analog power supply. This must decoupled according good design practices. Analog supply ground 3.3-V analog power supply. This must decoupled according good design practices. Analog supply ground secondary address 3.3-V digital power supply. This must decoupled according good design practices. Digital supply ground 3.3-V digital power supply. This must decoupled according good design practices. Digital supply ground 3.3-V digital power supply. This must decoupled according good design practices. Digital supply ground General-purpose pin. When booting from internal ROM, TAS3204 streams audio when GPIO1 low; otherwise mutes. General-purpose Slave serial control data interface input/output. Normally connected system micro.
input; output pullups 20-µA weak pullups, pulldowns 20-µA weak pulldowns. pullups pulldowns included ensure proper input logic levels terminals left unconnected (pullups logic input; pulldowns logic input). Devices that drive inputs with pullups must able sink while maintaining logic-0 drive level. Devices that drive inputs with pulldowns must able source while maintaining logic-1 drive level. Pull VMID when analog input single-ended mode. Physical Characteristics Submit Documentation Feedback
TAS3204 AUDIO WITH ANALOG INTERFACE
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TERMINAL NAME I2C1_SDA I2C2_SCL I2C2_SDA LRCLK_IN LRCLK_OUT MCLK_IN MCLK_OUT1 MCLK_OUT2
INPUT/ OUTPUT Digital Digital Input Digital Digital Input Digital Output Digital Input Digital Output Digital Output
PULLUP/ PULLDOWN
DESCRIPTION Slave serial clock input. Normally connected system micro. Master serial control data interface input/output. Normally connected EEPROM. Master serial clock input. Normally connected EEPROM.
Pulldown
Serial data input left/right clock interface Serial data output left/right clock interface MCLK input used slave mode. MCLK_IN must locked LRCLK_IN, frequency 512Fs (24.576 48-kHz Fs). 12.288 clock output. This output valid even when reset LOW. frequency this clock 6.144 MHz/(n+1) where programable range 255. Default value 1.024 MHz. This output valid even when reset LOW. frequency this clock kHz/(n+1) where programmable range 255. Default value kHz. This output valid even when reset LOW.
Pulldown
MCLK_OUT3 MUTE RESERVED RESET REXT SCLK_IN SCLK_OUT SDIN1/GPIO3 SDIN2/GPIO4 SDOUT1 SDOUT2 VMID
Digital Output Digital Input Digital Input Digital Input Analog Output Digital Input Digital Output Digital Digital Digital Output Digital Output Analog Output Pullup Pullup Pulldown Pullup Pulldown
This needs programmed mute application code. function default after reset. Power down, active LOW. After successful boot, function defined boot code. Connect ground. System reset input, active low. system reset generated applying logic this terminal. Requires 22-k (1%) external resistor ground analog currents. Trace capacitance must kept low. Serial data input clock interface Serial data output clock interface Serial data input interface programmable GPIO Serial data input interface programmable GPIO Serial data output interface Serial data output interface Analog supply reference. This must decoupled with 0.1-µF low-ESR capacitor external 10-µF filter cap. Voltage reference analog supply. pin-out internally regulated power. 0.1-µF capacitor 4.7-µF filter capacitor must connected between this terminal AVSS_PLL. This terminal must used power external devices. Voltage reference digital supply. pin-out internally regulated power. 0.1-µF capacitor 4.7-µF filter capacitor must connected between this terminal DVSS. This terminal must used power external devices. Voltage reference DPLL supply. pin-out internally regulated 1.8-V power supply. 0.1-µF low-ESR capacitor 4.7-µF filter capacitor must connected between this terminal DVSS. This terminal must used power external devices. Band output. 0.1-µF capacitor should connected between this terminal AVSS_PLL. This terminal must used power external devices. Voltage regulator enable. When enabled LOW, this input causes power-supply regulators enabled. Crystal input. 24.576-MHz (512Fs) crystal should used. Crystal output.
VR_ANA
Power
VR_DIG
Power
VR_PLL
Power
VREF VREG_EN XTAL_IN XTAL_OUT
Analog Output Digital Input Digital Input Digital Output
desired, capacitance values implemented paralleling more ceramic capacitors equal value. Paralleling capacitors equal value provide extended high frequency supply decoupling.
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Physical Characteristics
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Reset (RESET) Power-Up Sequence
RESET asynchronous control signal that restores TAS3204 components default configuration. When reset occurs, audio core into idle state 8051 starts initialization. valid XTAL_IN must present when clearing RESET initiate device reset. reset initiated applying logic RESET. long RESET held LOW, device reset state. During reset, serial data operations ignored. interface lines into high-impedance state remain that state until device initialization completed. rising edge reset pulse begins initialization housekeeping functions clearing memory setting default register values. Once these complete, TAS3204 enables master interface disables slave interface. Using master interface, TAS3204 automatically tests external EEPROM address "1010x". value chip selects, other information, don't care, depending EEPROM selected. memory present contains correct header information more blocks program/memory data, TAS3204 begins load program, coefficient and/or data memories from external EEPROM. external EEPROM present, download considered complete when program header read TAS3204. this point, TAS3204 disables master interface, enable slave interface, start normal operation. After successful download, micro program counter reset, downloaded micro application firmware controls execution. external EEPROM present error occurs during EEPROM read, TAS3204 disables master interface enables slave interface initialization load slave default configuration. this default configuration, TAS3204 streams audio from input output GPIO1 asserted LOW; GPIO1 asserted HIGH, muted. Note: master slave interfaces operate simultaneously.
Voltage Regulator Enable (VREG_EN)
Setting VREG_EN high shuts down voltage regulators device. Internal register settings lost this power down mode. full power-up/reset/program-load sequence must completed before device operational.
Power-On Reset (RESET)
power recommended that TAS3204 RESET held until DVDD reached This done programming system controller using external delay circuit. 1-µF values provide delay approximately values adjusted provide other delay values necessary.
Power Down (PDN)
TAS3204 supports number power-down modes. used device into power saving standby mode. user-firmware definable. default configuration stop clocks, power down analog circuitry, ramp down volume digital inputs. This mode used minimize power consumption while preserving register settings. there EEPROM EEPROM invalid image-i.e., unsuccessful boot from EEPROM-and pulled low, TAS3204 powerdown mode. After successful boot, defined boot code.
Physical Characteristics
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TAS3204 AUDIO WITH ANALOG INTERFACE
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Individual power down Each stereo powered down individually. avoid audible artifacts outputs, sequences defined document TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) must followed. control signals these operations defined ESFR. feature made available board controller interface. Power down analog reference analog reference powered down powered down. This operation handled device controller through ESFRs, made available board controller interface.
Control (CS0)
TAS3204 control specify slave master address. This control permits TAS3204 devices placed system without external logic. GPIO pins level sensitive. They edge triggered. Section complete description this pin.
Programmable (GPIO)
TAS3204 four GPIO pins general purpose input pins that 8051 firmware programmable. GPIO1 GPIO2 pins single function pins. Upon power GPIO1 input. there unsuccessful boot GPIO1 pulled high externally, output disabled. there unsuccessful boot GPIO1 pulled externally, output enabled. there successful boot, GPIO1 pulled internal microprocessor, function defined boot code EEPROM. GPIO3 GPIO4 pins dual function pins. These pins used SDIN1 SDIN2 respectively. Mute power down functions have programmed EEPROM boot code. These general-purpose input pins programmed functions other than mute power down. more information, Texas Instruments document TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
3.9.1
EEPROM Present Memory Error Occurs
Following reset power-up initialization with EEPROM present memory error occurs, TAS3204 modes, depending setting GPIO1. GPIO1 logic HIGH With GPIO1 held HIGH during initialization, TAS3204 comes default configuration with serial data outputs active. Once TAS3204 completed default initialization procedure, after status register updated slave interface enabled, then GPIO1 output driven LOW. Following HIGH-to-LOW transition GPIO pin, system controller access TAS3204 through interface read status register determine load status. memory-read error occurs, TAS3204 reports error status register (I2C subaddress 0x02). GPIO1 logic With GPIO1 held during initialization, TAS3204 comes test configuration. this case, once TAS3204 completes default test initialization procedure, status register updated, slave interface enabled, TAS3204 streams audio unaltered from input output SDIN1 SDOUT1, SDIN2 SDOUT2, etc.
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Physical Characteristics
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
this configuration, GPIO1 output signal that driven LOW. external logic longer driving GPIO1 after load completed (~100 following reset EEPROM present), state GPIO1 observed. Then system controller access TAS3204 through interface read status register determine load status. GPIO1 state observed, only indication that device completed initialization procedure fact that TAS3204 streams audio slave interface been enabled.
3.9.2
GPIO Function After Device Programmed
Once TAS3204 been programmed, either through successful boot load slave download, operation GPIO programmed input and/or output.
3.10 Input Output Serial Audio Ports
Serial data input SDIN1/SDIN2 TAS3204, allowing four channels digital audio input. TAS3204 supports serial data 16-, 20-, 24-bit data left, right, serial data formats. parameters clock serial data interface input formats configurable. Serial data output SDOUT1 SDOUT2, allowing four channels digital audio output. SDOUT port supports same formats SDIN port. Output data rate same data rate input. SDOUT output uses SCLK_OUT LRCLK_OUT signals provide synchronization. TAS3204 supported data formats listed Table 3-1. Table 3-1. Supported Data Formats
Input (SDIN1, SDIN2) 2-channel 2-channel left-justified 2-channel right-justified Output (SDOUT1, SDOUT2) 2-channel 2-channel left-justified 2-channel right-justified
Table 3-2. Serial Data Input Output Formats
Mode Input Control IM[3:0] 0000 2-channel 0001 0010 Output Control OM[3:0] 0000 0001 0010 Serial Format Left-justified Right-justified Word Lengths 32-48 3.072 Data Rates (kHz) SCLK (MHz)
Physical Characteristics
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Input Port Word Size
Output Port Word Size
0x00
Slave Addr Subaddr
xxxxxxxx
xxxxxxxx
Figure 3-1. Serial Data Controls Table 3-3. Serial Data Input Output Data Word Sizes
IW1, IW0, FORMAT Reserved 16-bit data 20-bit data 24-bit data
Following reset, ensure that clock register (0x00) written before performing volume, treble, bass updates. Commands reconfigure accompanied mute unmute commands quiet operation. However, care must taken ensure that mute command completed before commanded reconfigure. Similarly, TAS3204 should commanded unmute until after completed reconfiguration. reason this that configuration change while volume bass treble update taking place cause update completed properly. When TAS3204 transmitting serial data, uses negative edge SCLK output data bit. TAS3204 samples incoming serial data rising edge SCLK.
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IW[2:0] OW[2:0] DWFMT (Data Word Format)
DWFMT
IM[3:0]
OM[3:0]
Input Port Format
Output Port Format
R0003-01
Physical Characteristics
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
3.10.1 2-Channel Timing
2-channel timing, LRCLK when left-channel data transmitted HIGH when right-channel data transmitted. SCLK clock running which clocks each data. There delay clock from time LRCLK signal changes state first data data lines. data written first valid rising edge clock. TAS3204 masks unused trailing data-bit positions.
2-Channel (Philips Format) Stereo Input/Output Clks Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-04
Figure 3-2. 64fS Format
Physical Characteristics
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3.10.2 2-Channel Left-Justified Timing
2-channel left-justified timing, LRCLK HIGH when left-channel data transmitted when right-channel data transmitted. SCLK clock running which clocks each data. first data appears data lines same time LRCLK toggles. data written first valid rising edge clock. TAS3204 masks unused trailing data-bit positions.
2-Channel Left-Justified Stereo Input Clks LRCLK Left Channel LRCLK Right Channel Clks
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-02
Figure 3-3. Left-Justified 64fS Format
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Physical Characteristics
TAS3204 AUDIO WITH ANALOG INTERFACE
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3.10.3 2-Channel Right-Justified Timing
2-channel right-justified (RJ) timing, LRCLK HIGH when left-channel data transmitted when right-channel data transmitted. SCLK clock running which clocks each data. first data appears data lines bit-clock periods (for 24-bit data) after LRCLK toggles. mode, last clock before LRCLK transitions always clocks data. data written first valid rising edge clock. TAS3204 masks unused leading data-bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input Clks LRCLK Left Channel Right Channel Clks
SCLK
24-Bit Mode 20-Bit Mode 16-Bit Mode
T0034-03
Figure 3-4. Right-Justified 64fS Format
3.10.4 Input Output-Processing Flow
data format options other than result two-sample delay from input output. formatting used both input output SAP, polarity LRCLK must inverted. However, format conversions performed between input output, delay becomes either samples samples, depending processing clock frequency selected audio core relative sample rate incoming data. format uses falling edge LRCLK begin sample period, whereas other formats rising edge LRCLK begin sample period. This means that input audio core operate sample windows that 180° phase with respect sample window used output SAP. This phase difference results output outputting data sample midpoint sample period used audio core process data. processing cycle completes processing tasks before midpoint processing sample period, output outputs this processed data. However, processing time extends past midpoint processing sample period, output outputs data processed during previous processing sample period. former case, delay from input output samples. latter case, delay from input output samples.
Physical Characteristics
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delay from input output thus either sample times when data format conversions performed that involve format. However, which delay time obtained particular application determinable fixed that application, providing care taken selection MCLK_IN/XTAL_IN with respect incoming sample clock, LRCLK.
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Physical Characteristics
TAS3204 AUDIO WITH ANALOG INTERFACE
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Algorithm Software Development Tools TAS3204
TAS3204 algorithm software development tool combination classical development tools graphical development tools. tool used build, debug, execute programs both audio 8051 sections TAS3204. Classical development tooling includes text editors, compilers, assemblers, simulators, source-level debuggers. 8051 programmed exclusively ANSI 8051 tool off-the-shelf tool set, with modifications specified this document. 8051 tool complete environment with IDE, editor, compiler, debugger, simulator. audio core programmed exclusively assembly. audio tool complete environment with IDE, context-sensitive editor, assembler, simulator/debugger. Graphical development tooling provides means programming audio core 8051 through graphical drag-and-drop interface using modular audio software components from component library. graphical tooling produces audio assembly 8051 ANSI code well coefficients data. classical tools also used produce executable code. addition building applications, tool supports debug execution audio 8051 code both simulators hardware.
Algorithm Software Development Tools TAS3204
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Clock Controls
Clock management TAS3204 consists control structures: Master clock management Oversees selection clock frequencies 8051 microprocessor, controller, audio core master clock (MCLK_IN XTAL_IN) source these clocks. most applications, master clock drives on-chip digital phase-locked loop (DPLL), DPLL output drives microprocessor audio clocks. Also available DPLL bypass mode, which high-speed master clock directly drives microprocessor audio clocks. Serial audio port (SAP) clock management Oversees master/slave mode Controls output SCLKOUT, LRCLK master mode Input MCLK_IN XTAL_IN provides master clock TAS3204. Within TAS3204, these inputs combined gate and, thus, only these sources active time. source that active must logic TAS3204 only supports dynamic sample-rate changes between supported sample frequencies when fixed-frequency master clock provided. During dynamic sample-rate changes, TAS3204 remains normal operation register contents preserved. avoid producing audio artifacts during sample-rate changes, volume mute control included application firmware that mutes output signal during sample-rate change. fixed-frequency clock provided crystal attached XTAL_IN XTAL_OUT external 3.3-V fixed-frequency source attached MCLK_IN. When TAS3204 used system which master clock frequency (fMCLK) change, TAS3204 must reset during frequency change. these cases, procedure shown Figure should used.
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Clock Controls
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Enable Mute Wait Completion
RESET
Change fMCLK
Clocks Stable?
RESET High
After TAS3204 Initializes, Re-initialize Registers
Figure 5-1. Master Clock Frequency (fMCLK) Change Procedure When serial audio port (SAP) master mode, uses XTAL_IN master clock drive serial port clocks SCLK_OUT LRCLK. When slave mode, MCLK_IN, SCLK_IN, LRCLK_IN input clocks. SCLK_OUT LRCLK_OUT derived from SCLK_IN LRCLK_IN, respectively. Clock Register (0x00), Section 9.1, information programming clock register. Table 5-1. TAS3204 MCLK LRCLK Common Values (MCLK 24.576 MCLK 22.579 MHz)
MCLK/ LRCLK Ratio MCLK Freq (MHz) SCLKIN Rate SCLK_IN Freq (MHz) SCLK_OUT Rate
Sample Rate (kHz)
SDIN
SDOUT
LRCLK (FS)
Multiplier
FDSPCLK (MHz)
fDSPCLK/fS
Slave Mode, Channels Channels 44.1 22.579 24.576 2.822 3.072 124.2 135.2 2816 2816
Master Mode, Channels Channels 24.576 135.2 2816
Clock Controls
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Microprocessor Controller
8051 microprocessor receives distributes write data, retrieves outputs controllers required read data, participates most processing tasks requiring multiframe processing cycles. microprocessor data storing intermediate values queuing commands, fixed boot-program ROM, program RAM. microprocessor boot program cannot altered. microprocessor controller specialized hardware master slave interface operation, volume updates, programmable interval timer interrupt. more information TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067). TAS3204 slave-only interface that compatible with Inter (I2C) protocol supports both 100-kbps 400-kbps data-transfer rates multiple 4-byte write read operations (maximum bytes). slave control interface used program registers device read device status. TAS3204 also master-only interface that compatible with protocol supports 375-kbps data transfer rates multiple 4-byte write read operations (maximum bytes). master interface used load program data from external EEPROM. power TAS3204, slave interface disabled master interface enabled. Following reset, TAS3204 disables slave interface enables master interface. Using master interface, TAS3204 automatically tests EEPROM address 1010x. value chip select, other information, don't cares, depending EEPROM selected. memory present contains correct header information more blocks program/memory data, TAS3204 loads program, coefficient, and/or data memories from EEPROM. memory present, download complete when header read that zero-length data segment. this point, TAS3204 disables master interface, enables slave interface, starts normal operation. memory present error occurred during EEPROM read, TAS3204 disables master interface, enables slave interface, loads unprogrammed default configuration. this default configuration, TAS3204 streams audio from input output GPIO LOW. master slave interfaces operate simultaneously. slave mode, used Load program coefficient data Microprocessor program memory Microprocessor extended memory Audio core program memory Audio core coefficient memory Audio core data memory Update coefficient other control values Read status flags Once microprocessor program memory been loaded, cannot updated until TAS3204 been reset. master slave modes operate simultaneously. When acting master, data transfer rate fixed kHz, assuming MCLK_IN XTAL_IN 24.576 MHz. When acting slave, data transfer rate determined master device bus. communication protocol slave mode shown Figure 6-1.
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Start Master) Slave Address Master)
Read Write Master) Data Byte Transmitter)
Stop Master) Data Byte Transmitter)
Acknowledge TAS3204)
Acknowledge Receiver)
Acknowledge Receiver)
Start Condition While
MSB-1 MSB-2
Stop Condition While
Figure 6-1. Slave-Mode Communication Protocol
8051 Microprocessor Addressing Mode
bytes internal data memory address space accessible using indirect addressing instructions (including stack operations). However, only lower bytes accessible using direct addressing. upper bytes direct address Data Memory space used access Extended Special Function Registers (ESFRs).
6.1.1
Register Banks
There four directly addressable register banks, only which selected time. register banks occupy Internal Data Memory addresses from hex.
6.1.2
Addressing
bytes Internal Data Memory that occupy addresses from addressable. SFRs that have addresses form 1XXXX000 binary also addressable.
6.1.3
External Data Memory
External data memory occupies address space. This space contains External Special Function Data Registers (ESFRs). ESFR permit access control hardware features internal interfaces TAS3204.
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6.1.4
Extended Special Function Registers
ESFRs provide signals needed M8051 control different blocks device. ESFR extension M8051. Figure shows these registers arranged.
8051 DESTIN_DO DESTIN_A Address Decoder CCLK SFRWA ESFRDI CCLK Control CCLK Internal Data Memory
SFRWE
Control
Figure 6-2. Extended Special Function Registers
6.1.5
Memory Mapped Registers Data Memory
following memory mapped registers used communication with digital audio processor. Table 6-1. Memory Mapped Registers
Address 0x0300 0x0301 0x0302 Register Dither Seed Start Reserved Comment Sets dither seed value Sets starting address Reserved
Note that TAS3204 same memory mapped registers distinction upper lower memory these registers.
General Operations
employs signals, (data) (clock), communicate between integrated circuits system. Data transferred serially time. address data transferred byte (8-bit) format with most-significant (MSB) transferred first. addition, each byte transferred acknowledged receiving device with acknowledge bit. Each transfer operation begins with master device driving start condition ends with master device driving stop condition bus. uses transitions data terminal (SDA) while clock HIGH indicate start stop conditions. HIGH-to-LOW transition indicates start, LOW-to-HIGH transition indicates stop. Normal data transitions must occur within time clock period. master generates 7-bit slave address read/write (R/W) open communication with another device then waits acknowledge condition. slave holds during acknowledge clock period indicate acknowledgement. When this occurs, master transmits next byte sequence. Each device addressed unique 7-bit slave address plus (one byte). compatible devices share same signals bidirectional using wired-AND connection. external pullup resistor must used signals HIGH level bus.
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There limit number bytes that transmitted between start stop conditions. When last word transfers, master generates stop condition release bus. Figure shows TAS3204 read write operation sequences. shown Figure 6-3, read transaction requires that master device first issue write transaction give TAS3204 subaddress used read transaction that follows. This subaddress assignment write transaction then followed read transaction. write transactions, subaddress supplied first byte data written, this byte followed data written. write transactions, subaddress must always included data written. There cannot separate write transaction supply subaddress, required read transactions. subaddress-assignment-only write transaction followed second write transaction supplying data, erroneous behavior results. first byte second write transaction interpreted TAS3204 another subaddress replacing previously written.
TAS3204 Subaddress Master)
Data TAS3204)
Data TAS3204)
TAS3204 Address
TAS3204 Address
Acknowledge TAS3204)
Acknowledge TAS3204)
Acknowledge TAS3204)
TAS3204 Subaddress Master)
TAS3204 Address
Acknowledge TAS3204)
Acknowledge TAS3204)
Acknowledge TAS3204)
Acknowledge TAS3204)
Acknowledge TAS3204)
Figure 6-3. Subaddress Access Protocol
Slave Mode Operation
slave mode mode that used change configuration parameters during operation perform program coefficient downloads from master device. coefficient download operation slave mode used replace master-mode EEPROM download. TAS3204 supports both random sequential transactions. TAS3204 slave address 011010xy, where first bits TAS3204 device address CS0, which TAS3204 internal microprocessor power bit. pulldown resistance creates default address when connection made pin. Table Table show legal addresses slave master modes. number data bytes plus bytes checksum must evenly divisible word size. size field equal (header payload checksum).
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checksum contained last data transfer bytes. These bytes single word transfers (DAP data, instruction), checksum always contained byte frame that follows last data word, last bytes. multiword data register transfers data (micro program, micro external data, coefficient RAM), checksum included same byte transfer data. meet requirement above, number words that transferred contain modulo case micro program data memory, modulo case coefficient memory. When slave download used replace update sections micro program, micro data, coefficient memory, necessary take these transfer size restrictions into consideration when determining program, data, coefficient placements. multi word transfers always store first word lower address increment such that last word transfer stored with highest target address. Consecutive frame transfers increment target address such that data last transfer last target memory address space. When first slave download register written system controlle, TAS3204 updates status register setting error indicate error memory type that being loaded. This error reset when operation complete valid checksum been received. example when micro program memory being loaded, TAS3204 sets micro program memory error indication status register start sequence. When last byte micro program memory checksum received, TAS3204 clears micro program memory error indication. This enables TAS3204 preserve error status indications that occur result incomplete transfers data/ checksum error during series data program memory load operations. checksum always contained last bytes data block. slave download terminated when termination header with zero-length byte-count file received. status register always reflects status EEPROM boot attempts, unless user writes slave control register. write slave boot control register causes EEPROM status register reflect slave boot attempt status.
NOTE Once micro program memory been loaded, further updates this memory prohibited until device reset. TAS3204 block does respond broadcast address (00h).
Table 6-2. Slave Addresses
Base Address 0110 0110 0110 0110 Slave Address 0x68 0x69 0x6A 0x6B
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Table 6-3. Master Addresses
Base Address 1010 1010 1010 1010 Master Address 0xA0 0xA1 0xA2 0xA3
following example master address access external EEPROM. TAS3204 address EEPROMs depending state CS0. Initially, TAS3204 comes master mode. finds memory such 24C512 EEPROM, reads headers data previously described. this master mode, TAS3204 addresses EEPROMs shown Table Table 6-5. Table 6-4. EEPROM Address TAS3204 Master Mode 0xA1/A0
(EEPROM)
Table 6-5. EEPROM Address TAS3204 Master Mode 0xA3/A2
(EEPROM)
Random Transactions Supplying subaddress each subaddress transaction referred random addressing. random read commands, TAS3204 responds with data, byte time, starting subaddress assigned, long master device continues respond with acknowledges. given subaddress does bits, unused bits read logic write commands, however, treated accordance with data assignment that address space. write command received mixer subaddress, example, TAS3204 expects five 32-bit words. fewer than five data words have been received when stop command another start command) received, data received discarded. Sequential Transactions TAS3204 also supports sequential addressing. write transactions, subaddress issued followed data that subaddress subaddresses that follow, sequential write transaction taken place, data subaddresses successfully received TAS3204. sequential write transactions, subaddress then serves start address amount data subsequently transmitted, before stop start transmitted, determines many subaddresses written true random addressing, sequential addressing requires that complete data transmitted. only partial data written last subaddress, data last subaddress discarded. However, other data written accepted; just incomplete data discarded. Sequential read transactions have restrictions outputting only complete subaddress data sets. master does issue enough data-received acknowledges receive data given subaddress, master device simply does receive data.
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master device issues more data-received acknowledges than required receive data given subaddress, master device simply receives complete partial sets data, depending many data-received acknowledges issued from subaddress(es) that follow. read transactions, both sequential random, impose wait states.
6.3.1
Multiple-Byte Write
Multiple data bytes transmitted master device slave shown Figure 6-4. After receiving each data byte, TAS3204 responds with acknowledge bit.
Start Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Device Address Read/Write
Subaddress
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
T0036-02
Figure 6-4. Multiple-Byte Write Transfer
6.3.2
Multiple-Byte Read
Multiple data bytes transmitted TAS3204 master device shown Figure 6-5. Except last data byte, master device responds with acknowledge after receiving each data byte.
Start Condition
Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
Acknowledge
Device Address Read/Write
Subaddress
Device Address Read/Write
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
T0036-04
Figure 6-5. Multiple-Byte Read Transfer
Master-Mode Device Initialization
master-mode operation enabled following reset power-on reset. Master-mode transactions start until idle. TAS3204 uses master mode download from EEPROM memory contents microprocessor program memory, microprocessor extended memory, audio core program memory, audio core coefficient memory, audio core data memory. TAS3204, when operating master, execute complete download internal memory section internal memory without requiring wait states. When TAS3204 operates master, TAS3204 generates repeated start without intervening stop command while downloading program memory data from EEPROM. When repeated start sent EEPROM read mode, EEPROM enters sequential read mode transfer large blocks data quickly. TAS3204 queries EEPROM address 1010xxx. value chip select, other information, don't cares, depending EEPROM selected.
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first action TAS3204 master transmit start condition along with device address EEPROM with read/write cleared indicate write. EEPROM acknowledges address byte, TAS3204 sends subaddress byte, which EEPROM acknowledges. Most EEPROMs have least 2-byte addresses acknowledge many appropriate. this point, EEPROM sends last acknowledge becomes slave transmitter. TAS3204 acknowledges each byte repeatedly continue reading each data byte that stored memory. memory load information starts with reading header data information that starts subaddress EEPROM. This information must then stored sequential memory addresses with intervening gaps. data blocks contiguous blocks data that immediately follow header locations. TAS3204 memory data stored loaded (almost) order. Additionally, this addressing scheme permits portions TAS3204 internal memories loaded.
EEPROM Memory
Block Header
Data Block
Block Header
Data Block
Block Header
Data Block
M0040-01
Figure 6-6. EEPROM Address TAS3204 sequentially reads EEPROM memory loads internal memory unless does find valid memory header block, able read next memory location because memory reached, detects checksum error, reads end-of-program header block. When encounters invalid header read error, TAS3204 attempts read header memory location three times before determines that error. TAS3204 encounters checksum error attempts reread entire block memory more times before determines that error. Once microprocessor program memory been loaded, cannot reloaded until TAS3204 been reset. error encountered, TAS3204 terminates memory-load operation, loads default configuration, disables further master operations. end-of-program data block read, TAS3204 completed initial program load.
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master mode uses starting ending checksums verify proper EEPROM download. first 16-bit data word received from EEPROM, checksum subaddress 0x00, stored compared against 16-bit data word received last subaddress, ending checksum, checksum that computed during download. These three values must equal. read computed values match, TAS3204 sets memory read error bits status register repeats download from EEPROM more times. comparison check fails third time, TAS3204 sets microprocessor program default value. Table shows format EEPROM other external memory load file. Each line file byte ASCII format). checksum summation bytes (with beginning ending checksum fields 00). final checksum inserted into checksum field lowest significant four bytes checksum. Example: Given following example 8051 data program block (must multiple bytes these blocks): checksum 240h, values checksum fields byte byte 40h. checksum >FFFFh, then 2-byte checksum field least-significant bytes. example, checksum 45B6h, checksum field byte byte B6h. Table 6-6. TAS3204 Memory Block Structures
STARTING BYTE 12-Byte Header Block Checksum code byte Checksum code byte Header byte 0x00 Header byte 0x1F bytes bytes Checksum bytes through this termination header, this value Must 0x001F TAS3204 load part initialization. other value terminates initialization memory load sequence. 0x00 Microprocessor program memory termination header 0x01 Microprocessor external data memory 0x02 Audio core program memory 0x03 Audio core coefficient memory 0x04 Audio core data memory 0x05-06 Audio upper program memory 0x07 Audio Upper Coefficient Memory 0x08-FF Reserved future expansion Unused this termination header, this value 0000. DATA BLOCK FORMAT SIZE NOTES
Memory loaded
byte
0x00 Start TAS3204 memory address byte Start TAS3204 memory address byte
byte bytes
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Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING BYTE DATA BLOCK FORMAT Total number bytes transferred byte Total number bytes transferred byte 0x00 0x00 Data byte byte) Data byte Data byte Data byte byte) Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte 0x00 0x00 Checksum code byte Checksum code byte Data Block Audio Core Coefficient Memory (Following 12-Byte Header) Data byte byte) Data byte Data byte Data byte byte) Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte 0x00 0x00 Checksum code byte Checksum code byte bytes Repeated checksum bytes through bytes Coefficient word bytes Coefficient word bytes Coefficient word (valid data D27-D0) D7-D0 D15-D8 D23-D16 D31-D24 bytes Repeated checksum bytes through bytes bytes microprocessor bytes bytes microprocessor bytes SIZE bytes bytes bytes NOTES data bytes last checksum bytes. this termination header, this value 0000. Unused Unused
Data Block Microprocessor Program Data Memory (Following 12-Byte Header)
Microprocessor Controller
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Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING BYTE DATA BLOCK FORMAT SIZE NOTES
Data Block Audio Core Data Memory (Following 12-Byte Header) Data byte byte) Data byte Data byte Data byte Data byte Data byte byte) Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte Data byte 0x00 0x00 0x00 0x00 Checksum code byte Checksum code byte Data Block Audio Core Program Memory (Following 12-Byte Header) Program byte byte) Program byte Program byte Program byte Program byte Program byte Program byte byte) Program byte Program byte Program byte Program byte Program byte Program byte Program byte bytes Program word bytes Program word (valid data D53-D0) D7-D0 D15-D8 D23-D16 D31-D24 D39-D32 D47-D40 D55-D48 bytes Repeated checksum bytes through bytes Data bytes Data bytes Data word D7-D0 D15-D8 D23-D16 D31-D24 D39-D32 D47-D40
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Table 6-6. TAS3204 Memory Block Structures (continued)
STARTING BYTE DATA BLOCK FORMAT Program byte Program byte Program byte Program byte Program byte Program byte Program byte 0x00 0x00 0x00 0x00 0x00 Checksum code byte Checksum code byte 20-Byte Termination Block (Last Block Entire Load Block) BLAST BLAST BLAST BLAST 0x00 0x00 0x00 0x1F 0x00 0x00 BLAST 0x00 byte bytes bytes byte byte Last bytes must each 0x00. First bytes termination block always 0x0000. Second bytes always 0x001F. bytes Repeated checksum bytes through bytes Program word SIZE NOTES
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Digital Audio Processor (DAP) Arithmetic Unit
arithmetic unit fixed-point computational engine consisting arithmetic unit data coefficient memory blocks. primary features are: pipe parallel processing architecture 48-bit data path with 76-bit accumulator Hardware single cycle multiplier Three 48-bit general-purpose data registers 28-bit coefficient register Four simultaneous operations machine cycle Shift right, shift left bi-modal clip Log2/Alog2 Magnitude Truncation Hardware acceleration units Soft volume controller Delay memory Dither generator estimator 1024 dual port ports words data bits, respectively) 1228 words coefficient memory bits) word program bits) 5.88K words 24-bits delay memory (1.22 Coefficient RAM, data RAM, LFSR seed, program counter, memory pointers mapped into same memory space convenient addressing microcontroller. Memory interface block contains four pointers, data memory coefficient memory.
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Micro
DATA
1022
COEF
1022
lsbs) (EREG4) lsbs) (EREG3)
(LFSR)
(BREG)
(CREG)
(AREG)
(RREG)
DLYO (EREG1)
Barrel Shift, NEG, ABS, THRU
(PREG1)
LOG, ALOG, NEG, ABS, THRU
(PREG2) PREG3 (PREG3)
Multiply
"ZERO"
Legend Register
28-bit data 32-bit data 48-bit data 76-bit data
Operand
Operand
CLIP Delay
5.8K DLYI (DREG9)
Output Register File (DO1 DO8) (DREG1 DREG8)
Output
Figure 7-1. Core Block Diagram
Instructions
Please this information TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).
Digital Audio Processor (DAP) Arithmetic Unit
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Data Word Structure
Figure shows data word structure arithmetic unit. Eight bits overhead guard bits provided upper 48-bit word, bits computational precision noise bits provided lower 48-bit word. incoming digital audio words positioned with most significant abutting 8-bit overhead/guard boundary. sign indicates that incoming audio samples treated signed data samples arithmetic engine 48-bit (25.23 format) processor consisting general-purpose 76-bit arithmetic logic unit function-specific arithmetic blocks. Multiply operations (excluding function-specific arithmetic blocks) always involve 48-bit words 28-bit coefficients (usually programmable coefficients). group products added together, 76-bit product each multiplication applied 76-bit adder, where DSP-like multiply-accumulate (MAC) operation takes place. Biquad filter computations operation maintain precision intermediate computational stages.
16-Bit Audio 18-Bit Audio Overhead/ Guard Bits 20-Bit Audio Precision/Noise Bits 24-Bit Audio
Figure 7-2. Arithmetic Unit Data Word Structure maximize linear range 76-bit ALU, saturation logic used. computations, intermediate overflows permitted, assumed that subsequent terms computation flow correct overflow condition (see Figure 7-3). memory banks include dual port data storing intermediate results, coefficient RAM, fixed program ROM. Only coefficient RAM, assessable bus, available user.
Rollover (-73) (-51) (-124) (-45) (57) (59) (-110) -124 -110
Figure 7-3. Operation With Intermediate Overflow
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Input 24-Bit Data
8-Bit Headroom 16-Bit Noise
47-40
15-0
Coefficient Representation
27-23
Scaling Headroom Multiplier Output 75-71 70-63
Data bits) 48-Bit Clipping
POS48 NEG48 0x7F_F 0x80_0 FFF_FFFF 000_0000
Fractional Noise 38-31
32-Bit Clipping
POS40 NEG40 0xXX_ 0xXX_ 7FFF_FFFF 8000_0000
28-Bit Clipping
POS20 NEG20 0xXXXXX_ 0xXXXXX_ 7FFF_FFFF 8000_0000
Figure 7-4. Data-Path Data Representation
Digital Audio Processor (DAP) Arithmetic Unit
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Electrical Specifications
Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
DVDD AVDD Tstg Digital supply voltage range Analog supply voltage range Input voltage range Output voltage range 3.3-V LVCMOS (XTLI) LVCMOS (XTLO) -0.5 -0.5 -0.5 DVDD -0.5 -0.5 DVDD -0.5 70°C -65°C 150°C
Input clamp current DVDD) Output clamp current DVDD) Operating free-air temperature range Storage temperature range
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. XTAL_OUT only TAS3204 output that derived from internal 1.8-V logic supply. absolute maximum rating listed reference; only crystal should connected XTAL_OUT. Note: VR_ANA derived from TAS3204 internal 1.8-V voltage regulator. This terminal must used power external devices. VR_DIG derived from TAS3204 internal 1.8-V voltage regulator. This terminal must used power external devices. VR_PLL derived from TAS3204 internal 1.8-V voltage regulator. This terminal must used power external devices.
Package Dissipation Ratings
Package Description Package Type TQFP Count Package Designator 25°C Power Rating (mW) 1869 Derating Factor Above 25°C (mW/°C) 23.36 70°C Power Rating (mW)
Recommended Operating Conditions
DVDD Digital supply voltage AVDD Analog supply voltage High-level input voltage Low-level input voltage Operating ambient temperature Operating junction temperature Analog differential input Analog output load Resistance Capacitance LVCMOS (XTL_IN) LVCMOS (XTL_IN) UNIT VRMS
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Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER 3.3-V High-level output voltage 1.8-V LVCMOS (XTL_OUT) 3.3-V Low-level output voltage High-impedance output current Low-level input current 1.8-V LVCMOS (XTL_OUT) 3.3-V 3.3-V 1.8-V LVCMOS (XTL_IN) 3.3-V High-level input current 1.8-V LVCMOS (XTL_IN) Normal operation Normal operation Normal operation Power Dissipation (Total) Digital analog supply current Standby mode Reset mode VR_ANA VR_PLL VR_DIG Internal voltage regulator analog Internal voltage regulator Internal voltage regulator digital TEST CONDITIONS -0.55 0.75 MCLK_IN 24.576 MHz, LRCLK MCLK_IN 24.576 MHz, LRCLK MCLK_IN 24.576 MHz, LRCLK With voltage regulators With voltage regulators 1.98 1.98 1.98 1.44 UNIT
IDVDD IAVDD
Digital supply current Analog supply current
Audio Specifications
25°C, AVDD DVDD kHz, 1-kHz sine wave full scale, over operating free-air temperature range (unless otherwise noted)
PARAMETER Overall performance: input line Dynamic range THD+N Dynamic range THD+N section Crosstalk Power supply rejection ratio Input resistance Input capacitance Pass band edge Pass band ripple decimation filter Stop band edge Stop band attenuation Group delay TEST CONDITIONS Evaluation module. A-weighted, with respect full scale Evaluation module. with respect full scale A-weighted, with respect full scale. with respect full scale. channel Other channel kHz, mVpp AVDD 0.45Fs ±0.01 0.55Fs 37÷Fs UNIT
Electrical Specifications
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Audio Specifications (continued)
25°C, AVDD DVDD kHz, 1-kHz sine wave full scale, over operating free-air temperature range (unless otherwise noted)
PARAMETER Differential full scale output voltage Dynamic range THD+N section Crosstalk Power supply rejection ratio offset Pass band edge Pass band ripple interpolation filter Transition band Stop band edge Stop band attenuation Filter group delay A-weighted, with respect full scale 0-dBFS input, 0-dB gain channel dBFS; Other channel channel Other channel channel dBFS; Other channel kHz, mVpp AVDD With respect VREF 0.45Fs ±0.06 1.45 0.55Fs 7.4Fs 21÷Fs TEST CONDITIONS UNIT VRMS
Figure 8-1. Frequency Response (ADC-DAC)
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Figure 8-2. THD+N (ADC-DAC)
Electrical Specifications
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Timing Characteristics
following sections describe timing characteristics TAS3204.
8.6.1
Master Clock
PARAMETER TEST CONDITIONS
over recommended operating conditions (unless otherwise noted)
512Fs 1÷512Fs 512Fs
UNIT
f(XTAL_IN) tc(1) f(MCLK_IN) tw(MCLK_IN) f(MCLKO) tr(MCLKO) tf(MCLKO) tw(MCLK_IN)
Frequency, XTAL_IN tc(1)) Cycle time, XTAL_IN Frequency, MCLK_IN tc(2)) Pulse duration, MCLK_IN high Crystal frequency deviation Frequency, MCLKO tc(3)) Rise time, MCLKO Fall time, MCLKO Pulse duration, MCLKO high XTAL_IN master clock source MCLK_IN master clock source MCLKO MCLK_IN MCLKO MCLK_IN
tc(2)
tc(2) 256Fs
tc(2)
HMCLKO
MCLKO jitter
td(MI-MO)
Delay time, MCLK_IN rising edge MCLKO rising edge
Duty cycle 50/50. Period MCLK_IN TMCLK_IN 1/fMCLK_IN HMCLKO 1/(2 MCLKO). MCLKO same duty cycle MCLK_IN when MCLKO MCLK_IN. When MCLKO MCLK_IN 0.25 MCLK_IN, duty cycle MCLKO typically 50%. When MCLKO derived from MCLK_IN, MCLKO jitter MCLK_IN jitter Only applies when MCLK_IN selected master source clock Also applies MCLKO falling edge when MCLKO MCLK_IN/2 MCLK_IN/4
XTALI tc(1) tw(MCLKI) MCLKI tc(2) tw(MCLKO) tf(MCLKO) MCLKO tc(3)
T0088-01
td(MI-MO) tr(MCLKO)
Figure 8-3. Master Clock Signal Timing Waveforms
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8.6.2
Serial Audio Port, Slave Mode
PARAMETER TEST CONDITIONS
over recommended operating conditions (unless otherwise noted)
tc(SCLKIN) tc(SCLKIN) tc(SCLKIN) UNIT
fLRCLK tw(SCLKIN) fSCLKIN tpd1 tsu1 tsu2 tpd2
Frequency, LRCLK (fS) Pulse duration, SCLKIN high Frequency, SCLKIN Propagation delay, SCLKIN falling edge SDOUT Setup time, LRCLK SCLKIN rising edge Hold time, LRCLK from SCLKIN rising edge Setup time, SDIN SCLKIN rising edge Hold time, SDIN from SCLKIN rising edge Propagation delay, SCLKIN falling edge SCLKOUT2 falling edge
Period SCLKIN TSCLKIN 1/fSCLKIN Duty cycle 50/50.
tw(SCLKIN) tc(SCLKIN)
SCLKIN
tsu1 LRCLK (Input)
tpd1 SDOUT1 SDOUT2 SDOUT3 SDOUT4 tsu2 SDIN1 SDIN2 SDIN3 SDIN4 tpd2 SCLKOUT2
T0090-01
Figure 8-4. Serial Audio Port Slave Mode Timing Waveforms
Electrical Specifications
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8.6.3
Serial Audio Port Master Mode Signals (TAS3204)
PARAMETER TEST CONDITIONS
over recommended operating conditions (unless otherwise noted)
64FS UNIT f(LRCLK) tr(LRCLK) tf(LRCLK) f(SCLKOUT) tr(SCLKOUT) tf(SCLKOUT) tpd1(SCLKOUT) tpd2 Frequency LRCLK Rise time, LRCLK Fall time, LRCLK
Duty cycle 50/50
Frequency, SCLKOUT Rise time, SCLKOUT Fall time, SCLKOUT Propagation delay, SCLKOUT falling edge LRCLK edge Propagation delay, SCLKOUT falling edge SDOUT1-2 Setup time, SDIN SCLKOUT rising edge Hold time, SDIN from SCLKOUT rising edge
Rise time fall time measured from maximum height waveform.
tr(SCLKOUT) tf(SCLKOUT)
SCLKOUT2 tr(SCLKOUT) tf(SCLKOUT) SCLKOUT1 tpd1(SCLKOUT2) tpd1(SCLKOUT1) LRCLK (Output) tf(LRCLK), tr(LRCLK) SDOUT1 SDOUT2 SDOUT3 SDOUT4 tpd2
SDIN1 SDIN2 SDIN3 SDIN4
T0091-01
Figure 8-5. Serial Audio Port Master Mode Timing Waveforms
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Electrical Specifications
TAS3204 AUDIO WITH ANALOG INTERFACE
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8.6.4 Pin-Related Characteristics Stages F/S-Mode 2C-Bus Devices
PARAMETER Vhys VOL1 tSP(SCL) tSP(SDA) LOW-level input voltage HIGH-level input voltage Hysteresis inputs LOW-level output voltage (open drain open collector) Output fall time from VIHmin VILmax Input current, each pulse duration spikes that must suppressed input filter pulse duration spikes that must suppressed input filter Capacitance, each 3-mA sink current capacitance from TEST CONDITIONS STANDARD MODE -0.5 FAST MODE -0.5 0.05 UNIT
capacitance line output fall time faster than standard specification. pins fast-mode devices must obstruct lines switched off. These values valid 135-MHz clock rate. clock reduced half, doubles.
values referred VIHmin VILmax (see Section 8.6.4)
PARAMETER fSCL tHD-STA tLOW tHIGH tSU-STA tSU-DAT tHD-DAT tSU-STO tBUF clock frequency Hold time (repeated) START condition. After this period, first clock pulse generated. period clock HIGH period clock Setup time repeated START Data setup time Data hold time
STANDARD MODE 3.45 1000 0.1VDVDD 0.2VDVDD
FAST MODE 0.1VDVDD 0.2VDVDD
UNIT
Rise time both signals Fall time both Setup time STOP condition free time between STOP START condition Capacitive load each line Noise margin level each connected device (including hysteresis) Noise margin HIGH level each connected device (including hysteresis)
master mode, maximum speed kHz. Note that does have standard specification 300-ns internal hold time. must valid rising falling edges SCL. recommends that pullup resistor used avoid potential timing issues. fast-mode I2C-bus device used standard-mode I2C-bus system, requirement tSU-DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line tr-max tSU-DAT 1000 1250 (according standard-mode specification) before line released. total capacitance line
Electrical Specifications
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NOTE does have standard specification 300-ns internal hold time. must valid rising falling edges SCL.
tLOW tSU-DAT tHD-STA tBUF
tHD-DAT tHD-STA tHIGH
tSU-STA
tSU-STO
T0114-01
Figure 8-6. Start Stop Conditions Timing Waveforms
8.6.5.1 Recommended Pullup Resistors
recommended that pullup resistors (see Figure 8-7). series resistor circuit (see Figure 8-8), then series resistor should less than equal
DVDD TAS3204 VI(SDA) VI(SCL) External Microcontroller
Figure 8-7. Pullup Circuit (With Series Resistor)
DVDD TAS3204
External Microcontroller
DVDD RS/(RS RP). When driven low, requirements.
Figure 8-8. Pullup Circuit (With Series Resistor)
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TAS3204 AUDIO WITH ANALOG INTERFACE
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8.6.6 Reset Timing
control signal parameters over recommended operating conditions (unless otherwise noted)
PARAMETER tw(RESET) tr(DMSTATE) tr(run) Pulse duration, RESET active Time outputs inactive Time enable UNIT
RESET tw(RESET)
Internal Reset tr(DMSTATE)
tr(run) Time enable
Initialization Complete
Figure 8-9. Reset Timing
Electrical Specifications
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Register
registers also mapped some Extended Special Function Registers (ESFR). They defined following sections. Table 9-1. Register
SUBADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x30-0x3F indicates unused bits. REGISTER NAME Clock Control Register Reserved Status Register Unused Memory Load Control Memory Load Data Memory Select Address Data Register Device Version Unused Analog Power Down Control Analog Power Down Control Analog Input Control Dynamic Element Matching ADC2 Current Control ADC2 Current Control Unused ADC1 Current Control ADC1 Current Control Unused Control Control Analog Test Modes Modulator Dither ADC/DAC Digital Reset Analog Input Gain Select Clock Delay Setting MCLK_OUT2 Divider MCLK_OUT3 Divider Bypass Time Clock Delay Setting Digital Cross Unused Description shown Section Description shown Section u(31:24) (1), MemSelect(23:16), Addr(15:8), Addr(7:0) D(63:56), D(55:48), D(47:40), D(39:32), D(31:24), D(23:16), D(15:8), D(7:0) TAS3204 version Unused Analog Power Down Control Analog Power Down Control Analog Input Control Dynamic Element Matching ADC1 Current Control ADC1 Current Control Unused ADC2 Current Control ADC2 Current Control Unused Control Control Analog Test Modes Modulator Dither ADC/DAC Digital Reset Analog Input Gain Select Clock Delay Setting MCLK_OUT2 Divider MCLK_OUT3 Divider Bypass Time Clock Delay Setting Digital Cross 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x05 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 Section 9.15 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 BYTES CONTENTS Description shown Section Reserved Description shown Section INITIALIZATION VALUE 0x00, 0x40, 0x1B, 0x22 0x00, 0x00, 0x00, 0x40 0x00, 0x00, 0x03, 0xFF 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x01 Unused 0x00, 0x00, 0x00, 0x1F 0x00, 0x00, 0x00, 0xFF 0x00, 0x00, 0x00, 0x01 0x00, 0x00, 0x00, 0x08 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00
following sections, BOLD indicates default state fields.
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Register
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Clock Control Register (0x00)
Register 0x00 provides user with control over MCLK, LRCLK, SCLKOUT1, SCLKOUT2, data-word size, serial audio port modes. Register 0x00 default 0x00 Table 9-2. Clock Control Register (0x00)
Input data format Output data format Output word Output word Output word Output word Input word Input word Input word Input word DESCRIPTION Master Mode (XTAL) Slave mode (MCLK_IN) DESCRIPTION Firmware definable DESCRIPTION DESCRIPTION
Microcontroller Clock Control Register
This register reserved.
Register
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Status Register (0x02)
During download, write operation indicate that particular memory written causes TAS3204 error indicate load that memory type. This error cleared when operation completes successfully. Table 9-3. Status Register (0x02)
Firmware definable DESCRIPTION Microprocessor program memory load error Microprocessor external data memory load error Audio core program memory load error Audio core upper coefficient memory load error Audio core upper data memory load error Invalid memory select End-of-load header error sampling clock divided errors Firmware definable DESCRIPTION Firmware definable DESCRIPTION DESCRIPTION
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Register
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Memory Load Control Data Registers (0x04 0x05)
Registers 0x04 (Table 9-4) 0x05 (Table 9-5) allow user download TAS3204 program code data directly from system controller. This mode called slave mode (from TAS3204 point view). TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) more details. slave memory load port permits system controller load TAS3204 memories alternative having TAS3204 load memory from EEPROM. Micro program memory Micro extended memory program memory coefficient memory data memory transfer performed writing registers. first register eight byte register that holds checksum, memory written, starting address, number data bytes transferred. second location holds bytes data. memory load operation starts with first register being set. Then data written into second register using format shown. After last data byte written into second register, additional bytes written which contain two-byte checksum. that point, transfer complete status operation reported status register. checksum always contained last bytes data block. Table 9-4. TAS3204 Memory Load Control Register (0x04)
BYTE DATA BLOCK FORMAT Checksum code SIZE bytes NOTES Checksum bytes through this termination header, this value Microprocessor program memory Microprocessor external data memory Audio core program memory Audio core coefficient memory Audio core data memory Audio core upper data memory Audio core upper coefficient memory 7-15: Reserved future expansion Reserved future expansion this termination header, this value 0000. this termination header, this value 0000.
Memory loaded
bytes
Unused Starting TAS3204 memory address Number data bytes transferred
byte bytes bytes
Table 9-5. TAS3204 Memory Load Data Register (0x05)
BYTE 8-BIT DATA Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 Datum D7-D0 28-BIT DATA 0000 D27-D24 D7-D0 D15-D8 D7-D0 0000 D27-D24 D23-D16 D15-D8 D7-D0 48-BIT DATA 0000 0000 0000 0000 D47-D40 D39-D32 D31-D24 D23-D16 D15-D8 D7-D0 54-BIT DATA 0000 0000 D53-D48 D47-D40 D39-D32 D31-D24 D23-D16 D15-D8 D7-D0
Register
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Memory Access Registers (0x06 0x07)
Registers 0x06 (Table 9-6) 0x07 (Table 9-7) allow user access internal resources TAS3204. TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) more details. Table 9-6. Memory Select Address Register (0x06)
Memory address Memory address DESCRIPTION Unused DESCRIPTION Audio core coefficient memory select Audio core data memory select Reserved Microprocessor internal data memory select Microprocessor external data memory select select Microprocessor program select Audio core program select Audio core upper memory select Audio core program select DESCRIPTION DESCRIPTION
Table 9-7. Data Register (Peek Poke) (0x07)
Data written read Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION Data written read DESCRIPTION DESCRIPTION
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Register
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Device Version (0x08)
Table 9-8. Device Version
TAS3204 device version Firmware definable DESCRIPTION Firmware definable DESCRIPTION Firmware definable DESCRIPTION DESCRIPTION
Analog Power Down Control (0x10 0x11), ESFR (0xE1 0xE2)
ESFR 0xE1, 0xE2 have same mapping functions registers 0x10, 0x11, respectively. Table 9-9. Analog Power Down Control (0x10/0xE1)
Central reference enable Power down central reference ADC1 enable ADC1 power down ADC2 enable ADC2 power down reference enable reference power down reference enable reference power down DESCRIPTION
Table 9-10. Analog Power Down Control (0x11/0xE2)
DAC1 left enable DAC1 left power down DAC1 right enable DAC1 right power down DAC2 left enable DAC2 left power down DAC2 right enable DAC2 right power down Line left enable Line left power down Line right enable Line right power down Line left enable Line left power down Line right enable Line right power down Submit Documentation Feedback DESCRIPTION
Register
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Analog Input Control (0x12), ESFR (0xE3)
ESFR 0xE3 same mapping functions register 0x12. Table 9-11. Analog Input Control
Select input Select input Select input Select input Select input Select input differential input single ended input differential input single ended input DESCRIPTION
Dynamic Element Matching (0x13), ESFR (0XE4)
ESFR 0xE4 same mapping functions register 0x13. Table 9-12. Dynamic Element Matching
DESCRIPTION dynamic element matching algorithm enabled (recommended setting) dynamic element matching algorithm disabled Dynamic weighted averaging enabled (recommended setting) Dynamic weighted averaging disabled Unused Unused Fast charge VREF (filtering disabled recommended setting startup) Slow charge VREF (filtering enabled recommended setting during normal operation) Unused Unused Unused Unused Unused Unused Unused Unused
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9.10 Current Control Select (0x14, 0x15, 0x17, 0x18), ESFR (0xE5, 0xE6, 0xE7, 0xE9)
ESFR 0xE5, 0xE6, 0xE7, 0xE9 have same mapping functions register 0x14, 0x15, 0x17, 0x18, respectively. Table 9-13. Current Control Select (0x14/0xE5)
DESCRIPTION ADC2 summer current setting (left right) 130% nominal current (recommended setting) ADC2 summer current setting (left right) 100% nominal current ADC2 summer current setting (left right) 100% nominal current ADC2 summer current setting (left right) nominal current ADC2 quantizer current setting (left right) 137.5% nominal current (recommended setting) ADC2 quantizer current setting (left right) 100% nominal current ADC2 quantizer current setting (left right) 100% nominal current ADC2 quantizer current setting (left right) 62.5% nominal current ADC2 third integrator current setting (left right) 130% nominal current (recommended setting) ADC2 third integrator current setting (left right) 100% nominal current ADC2 third integrator current setting (left right) 100% nominal current ADC2 third integrator current setting (left right) nominal current ADC2 reference buffer current setting (left right) 130% nominal current (recommended setting) ADC2 reference buffer current setting (left right) 100% nominal current ADC2 reference buffer current setting (left right) 100% nominal current ADC2 reference buffer current setting (left right) nominal current
Register
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Table 9-14. Current Control Select (0x15/0xE6)
DESCRIPTION ADC2 second integrator current setting (left right) 130% nominal current (recommended setting) ADC2 second integrator current setting (left right) 100% nominal current ADC2 second integrator current setting (left right) 100% nominal current ADC2 second integrator current setting (left right) nominal current ADC2 second integrator current setting (left right) 130% nominal current (recommended setting) ADC2 first integrator current setting (left right) 100% nominal current ADC2 first integrator current setting (left right) 100% nominal current ADC2 first integrator current setting (left right) nominal current ADC2 current common mode buffer integrator ADC2 current common mode buffer integrator ADC2 current common mode buffer integrator ADC2 current common mode buffer integrator ADC2 current buffer sampling switches ADC2 current buffer sampling switches ADC2 current reference buffer ADC2 Current Reference Buffer
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Register
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Table 9-15. Current Control Select (0x17/0xE7)
DESCRIPTION ADC1 summer current setting (left right) 130% nominal current (Recommended Setting) ADC1 summer current setting (left right) 100% nominal current ADC1 summer current setting (left right) 100% nominal current ADC1 summer current setting (left right) nominal current ADC1 quantizer current setting (left right) 137.5% nominal current (recommended setting) ADC1 quantizer current setting (left right) 100% nominal current ADC1 quantizer current setting (left right) 100% nominal current ADC1 quantizer current setting (left right) 62.5% nominal current ADC1 third integrator current setting (left right) 130% nominal current (Recommended Setting) ADC1 third integrator current setting (left right) 100% nominal current ADC1 third integrator current setting (left right) 100% nominal current ADC1 third integrator current setting (left right) nominal current ADC1 reference buffer current setting (left right) 130% nominal current (Recommended Setting) ADC1 reference buffer current setting (left right) 100% nominal current ADC1 reference buffer current setting (left right) 100% nominal current ADC1 reference buffer current setting (left right) nominal current
Register
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Table 9-16. Current Control Select (0x18/0xE9)
DESCRIPTION ADC1 second integrator current setting (left right) 130% nominal current (recommended setting) ADC1 second integrator current setting (left right) 100% nominal current ADC1 second integrator current setting (left right) 100% nominal current ADC1 second integrator current setting (left right) nominal current ADC1 second integrator current setting (left right) 130% nominal current (recommended setting) ADC1 first integrator current setting (left right) 100% nominal current ADC1 first integrator current setting (left right) 100% nominal current ADC1 first integrator current setting (left right) nominal current ADC1 current common mode buffer integrator ADC1 current common mode buffer integrator ADC1 current common mode buffer integrator ADC1 current common mode buffer integrator ADC1 current buffer sampling switches ADC1 current buffer sampling switches ADC1 current reference buffer ADC1 current reference buffer
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9.11 Control (0x1A, 0x1B, 0x1D), ESFR (0xEB, 0xEC, 0xEE)
ESFR 0xEB, 0xEC, 0xED have same mapping functions register 0x1A, 0x1B, 0x1D, respectively. Table 9-17. Control (0x1A/0xEB)
DESCRIPTION DAC1 current control local reference block lineout amps default (recommended setting) DAC1 current control local reference block lineout amps 125% bias current DAC1 current control local reference block lineout amps bias current DAC1 current control local reference block lineout amps bias current DAC2 current control local reference block lineout amps default (recommended setting) DAC2 current control local reference block lineout amps 125% bias current DAC2 current control local reference block lineout amps bias current DAC2 current control local reference block lineout amps bias current
Register
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Table 9-18. Control (0x1B/0xEC)
DESCRIPTION DAC1 chopper stabilization disable DAC1 chopper stabilization enable DAC2 chopper stabilization disable DAC2 chopper stabilization enable offset subtraction DACs disable offset subtraction DACs enable Connected microprocessor SDA2
Table 9-19. Control (0x1D/0xEE)
DESCRIPTION DAC1 current control local reference block lineout amps default (recommended setting) DAC1 current control local reference block lineout amps 125% bias current DAC1 current control local reference block lineout amps bias current DAC1 current control local reference block lineout amps bias current DAC2 current control local reference block lineout amps default (recommended setting) DAC2 current control local reference block lineout amps 125% bias current DAC2 current control local reference block lineout amps bias current DAC2 current control local reference block lineout amps bias current
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Register
TAS3204 AUDIO WITH ANALOG INTERFACE
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9.12 Reset (0x1E), ESFR (0xFB)
ESFR 0xFB same mapping functions register 0x1E. Table 9-20. Reset (0x1E/0xFB)
reset channel reset channel reset channel reset channel reset channel reset channel reset channel reset channel DESCRIPTION
9.13 Input Gain Control (0x1F), ESFR (0xFA)
Table 9-21. Input Gain Control (0x1F/0xFA)
DESCRIPTION Channel 1Sinc input gain control Channel 1Sinc input gain control Channel 1Sinc input gain control +600 Channel 1Sinc input gain control Channel 2Sinc input gain control Channel 2Sinc input gain control Channel 2Sinc input gain control Channel 2Sinc input gain control Channel 3Sinc input gain control Channel 3Sinc input gain control Channel 3Sinc input gain control =+60 Channel 3Sinc input gain control Channel 4Sinc input gain control Channel 4Sinc input gain control Channel 4Sinc input gain control Channel 4Sinc input gain control
Register
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9.14 MCLK_OUT Divider (0x21 0x22)
Table 9-22. MCLK_OUT (0x21)
DESCRIPTION MCLK_OUT2 frequency 6.144 MHz/(divider+1)
Table 9-23. MCLK_OUT (0x22)
DESCRIPTION MCLK_OUT3 frequency kHz/(divider+1)
9.15 Digital Cross (0x30 0x3F)
Table 9-24. Digital Cross (0x30 0x3F)
SUBADDRESS REGISTER NAME BYTES CONTENTS INITIALIZATION VALUE 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00
0x30
Input Mixer
Input cross
0x31
Input Mixer
Input cross
0x32
Input Mixer
Input cross
0x33
Input Mixer
Input cross
0x34
Input Mixer
Input cross
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Register
TAS3204 AUDIO WITH ANALOG INTERFACE
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Table 9-24. Digital Cross (0x30 0x3F) (continued)
SUBADDRESS REGISTER NAME BYTES CONTENTS INITIALIZATION VALUE 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00
0x35
Input Mixer
Input cross
0x36
Input Mixer
Input cross
0x37
Input Mixer
Input cross
0x38
Output Mixer
Input cross
0x39
Output Mixer
Input cross
0x3A
Output Mixer
Input cross
0x3B
Output Mixer
Input cross
0x3C
Output Mixer
Input cross
Register
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Table 9-24. Digital Cross (0x30 0x3F) (continued)
SUBADDRESS REGISTER NAME BYTES CONTENTS INITIALIZATION VALUE 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x08
0x3D
Output Mixer
Input cross
0x3E
Output Mixer
Input cross
0x3F
Output Mixer
Input cross
9.16 Extended Special Function Registers (ESFR)
TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067) more details ESFR. Table 9-25. Extended Special Fucntion Registers (ESFR)
ESFR MAPPED_TO BITS DIRECTION CONNECTING BLOCK REGISTER TYPE 8-bit asynchronous rstz positive edge triggered Reset DESCRIPTION Data transferred from microprocessor Data transferred from microprocessor during slave write slave-write mode controls interface Indicates type information being relayed microprocessor. This affects microprocessor changes data that follows subaddress.
di_o
da_i
direct input
sub_addr_i
direct input
data_out1_i data_out2_i data_out3_i data_out4_i
direct input direct input direct input direct input 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 5-bit asynchronous rstz positive edge triggered Reset Address internal registers. Mentor product specification. definition follows functional spec definition specification WORD byte definition follows functional spec definition specification mode byte definition follows functional spec definition specification MLRCLK field These registers used deliver data from block microprocessor.
i2s_word_byte_t
i2s_mode_byte_t
MLRCLK_t
CLOCK
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Register
TAS3204 AUDIO WITH ANALOG INTERFACE
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Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR MAPPED_TO BITS DIRECTION CONNECTING BLOCK CLOCK REGISTER TYPE 8-bit asynchronous rstz positive edge triggered Reset 4-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 5-bit asynchronous rstz positive edge triggered Reset 2-bit asynchronous rstz positive edge triggered Reset 3-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 4-bit asynchronous rstz positive edge triggered Reset direct input direct input direct input direct input direct input direct input direct input 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered 8-bit asynchronous rstz positive edge triggered 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset Microprocessor uses these bits Micro addresses Data from microprocessor DESCRIPTION
SCLK_t
definition follows functional spec definition specification SCLK field
addr_sel_t
DELAY_MEM
Delay memory select lines
addr_t
DELAY_MEM
Delay memory address
addr_t
DELAY_MEM
Delay memory address high bits
vol_mode_i_t
VOLUME
Specify slew rate (2048, 4096, 8192)
volume_index_i_t
VOLUME
Host control channel specification
VOLUME
vol_data_i_t
VOLUME
Volume coefficient
vol_data_i_t
VOLUME
vol_data_i_t To_micro_i[7:0] To_micro_i[15:8] To_micro_i[23:16] To_micro_i[31:24] To_micro_i[39:32] To_micro_i[47:40] To_micro_i[53:48] Data_to_DSP_o[7:0]
VOLUME
Data_to_DSP_o[15:0] Data_to_DSP_o[23:16]
Data_to_DSP_o[31:24]
Data from microprocessor
Data_to_DSP_o[39:32
Data_to_DSP_o[47:40]
Data_to_DSP_o[53:48]
micro_addr_o[7:0]
Register
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Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR MAPPED_TO BITS DIRECTION CONNECTING BLOCK REGISTER TYPE DESCRIPTION Microprocessor uses these bits Micro addresses address selects between audio coefficient audio data memory
micro_addr_o[13:8]
8-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered, Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 4-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 8-bit asynchronous rstz positive edge triggered Reset direct input direct input direct input 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset
Mode0_o
Mode3_o
Miscellaneous signal microprocessor-DSP communication. This bit-addressable register, contains data. firmware must read data, mask change, write back out.
Mode4_o
Mode5_o
Mode6_o
Mode7_o
Miscellaneous signal microprocessor-DSP communication. This bit-addressable register, contains data. firmware must read data, mask change, write back out.
Mode8_o
GPIO_IN_t
Registered input GPIO sense line GPIO bidirect configuration-low output, high input Drive value GPIO line when configured output Reset-low sense lines chip-select input/output
gpio_enz_t
GPIO
gpio_out_t
GPIO
CHIP_SEL
tb_loop_count_t dlymemif_out dlymemif_out dlymemif_out cntrl1_treb_active_t
TONE DLY_MEM DLY_MEM DLY_MEM TONE
Tone slew rate counter configuration Low-byte delay interface date port High-byte delay interface date port High-byte delay interface date port
cntrl2_treb_active_t
TONE
cntrl3_treb_active_t
TONE
Schedule tone coefficient calculations audio
cntrl4_treb_active_t
TONE
cntrl1_bass_active_t
TONE
cntrl2_bass_active_t
TONE
cntrl3_bass_active_t
TONE
Schedule tone coefficient calculations audio
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Register
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR MAPPED_TO BITS DIRECTION CONNECTING BLOCK TONE REGISTER TYPE 1-bit asynchronous rstz positive edge triggered Reset DESCRIPTION
cnrtrl4_bass_active_t
Schedule tone coefficient calculations audio PULSE REGISTER Slave read: high when recognizes that SLAVE_READ been high. Slave write: RCVD_DATA_STAT high I2C, microprocessor sets high response. PULSE REGISTER I2C_MCU assumes control over interface. block control. microprocessor reads slave_read, sends sets I2C_MCU high. Signoff assertion that volume coefficients volume block updated execution commanded Used during initialization inspire self-clearing logic activation delay PULSE REGISTER write pulse slave transmit master transmit registers which microprocessor write. This signal selects them. PULSE REGISTER When DSP_HOST microprocessor direct control RAMs pulses this signal write them. When DSP_HOST high microprocessor complete control RAMS, this N/A. When DSP_HOST low, microprocessor uses this submit read request DSP. Power-down sense Volume busy flag Indicates chip firmware BIST mode Indicates status warp IFLAG sets this notify microprocessor captured data
C0(0)
I2c_irg_o
1-bit asynchronous rstz positive edge triggered SHOT (PULSE) Reset
C0(1)
I2c_mcu_o
1-bit asynchronous rstz positive edge triggered RESET
C0(2)
update_volume_t
VOLUME
1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered SHOT (PULSE) 1-bit asynchronous rstz positive edge triggered 1-bit asynchronous rstz positive edge triggered SHOT (PULSE)
C0(3)
clr_dly_RAM_t
DLY_MEM
C0(4)
wr_t
C0(5)
I2c_sel_o
C0(6)
micro_RAM_we_req_o
C0(7)
micro_rd_req_o
1-bit asynchronous rstz positive edge triggered SHOT (PULSE) direct input 1-bit asynchronous rstz positive edge triggered Reset High Direct input Direct input 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset direct input 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset
C8(0) C8(2) C8(3) C8(4) C8(5)
power_down_in vol_busy_o mem_bist_i intr micro_ack_I
CNTL membist CNTL
C8(6)
clearing_dly_RAM_t
Busy flag from Delay Init clear process HIGH signal that BIST completed successfully HIGH microprocessor. (Need more info)
C8(7)
dsp_rom_bist_I
D8(0)
power_down_o
Multiple blks
D8(1)
watchdog_clr_t
CNTL
Strobe watchdog timer logic
D8(2)
slave_mode_t
DLY_MEM
Asserted provide direct delay memory access host (microprocessor) Write assertion delay memory during host control configuration
D8(3)
addr_wr_t
DLY_MEM
Register
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TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Table 9-25. Extended Special Fucntion Registers (ESFR) (continued)
ESFR MAPPED_TO BITS DIRECTION CONNECTING BLOCK REGISTER TYPE 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset high 1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset DESCRIPTION
D8(4)
micro_wr_en_i_t
Write enable signal audio coefficients DATA RAMs Sets host mode. Microprocessor control Microprocessor notifies block that bass data been processed ready. Microprocessor notifies block that treble data been processed ready. Audio coefficient/data (Depending address Audio instruction Microprocessor instruction Reserved
D8(5)
host_DSP_o
D8(6)
bass_data_ready_o
D8(7)
treble_data_ready_o
MEM_SEL
MICRO
2-bit asynchronous rstz positive edge triggered Reset
i2c_ms_ctl
1-bit asynchronous rstz positive edge triggered Reset 1-bit asynchronous rstz positive edge triggered Reset
Select Master Slave mode switching Changes source from microprocessor program microprocessor program Expected toggle high, then low, inspire recent change activate.
pc_source
sap_en_t
1-bit asynchronous rstz positive edge triggered Reset
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Register
TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Application Information
10.1 Schematics
Figure 10-1 shows typical TAS3204 application. this application following conditions apply: TAS3204 clock-master mode. TAS3204 generates MCLK_OUT1, SCLK_OUT, LRCLOK_OUT. XTAL_IN 24.576 register 0x00 contains default settings, which means: Audio data word size 24-bit input 24-bit output. Serial data format 2-channel, input output. data transfer approximately kbps both master slave interfaces. Sample frequency (fS) kHz, which means that fLRCLK fSCLKIN 3.072 MHz. Application code data loaded from external EEPROM using master interface. Application commands come from system microprocessor TAS3204 using slave interface.
Good design practice requires isolation between digital analog power shown. Power supply capacitors should placed near power supply pins AVDD (AVSS) DVDD (DVSS). TAS3204 reset needs external glitch protection. Also, reset going HIGH should delayed until TAS3204 internal power good (~200 after power up). This provided resistor, 1-µF capacitor, diode placed near RESET pin. recommended that 4.7-µF capacitor (fast ceramic type) placed near (VR_DIG). This must used source external components.
Application Information
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TAS3204 AUDIO WITH ANALOG INTERFACE
SLES197 APRIL 2007
Master Mode Application
Input
EEPROM
SDOUT1
SDIN1/GPIO3
LRCLK_IN DVDD3
SDIN2/GPIO4
LRCLK_OUT
RESERVED
I2C2_SDA RESET
SCLK_OUT
VREG_EN
DVSS3 VR_DIG
I2C2_SCL
SCLK_IN
SDOUT2
Output
MCLK_OUT1 MCLK_OUT2 MCLK_OUT3 DVDD2 DVSS2 XTAL_OUT XTAL_IN AVDD3 VR_ANA AVSS3 AVSS2 AOUT1RP AOUT1RM AOUT1LP AOUT2LM MCLK_IN 24.576
I2C1_SCL
External Controller
I2C1_SDA GPIO2 GPIO1 MUTE DVSS1 DVDD1 VR_PLL 0.1uF AVSS1 AIN1LP AIN1LM AIN1RP AIN1RM AIN2LP
Three Differential
AOUT2RM AOUT2LM AIN2RM AIN3RM AIN2LM AIN2RP AIN3LM AIN3RP AIN3LP AVDD1
Input
VMID
VREF
AOUT2LP
AVDD2
Stereo Analog
AOUT2RP
REXT
Differential Stereo Analog Output
Capacitors should placed close possible power supply pins.
Figure 10-1. Typical Application Diagram
10.2 Recommended Oscillator Circuit
TAS3204
Oscillator Circuit AVSS
Crystal type parallel-mode, fundamental-mode crystal drive-level control resistor vendor specified Crystal load capacitance (capacitance circuitry between terminals crystal) C2)/(C1 (where board stray capacitance,
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Application Information
PACKAGE OPTION ADDENDUM
25-Sep-2007
PACKAGING INFORMATION
Orderable Device TAS3204PAG TAS3204PAGR
Status ACTIVE ACTIVE
Package Type TQFP TQFP
Package Drawing
Pins Package Plan Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU
Peak Temp Level-4-260C-72 Level-4-260C-72
1500 Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MTQF006A JANUARY 1995 REVISED DECEMBER 1996
(S-PQFP-G64)
0,50 0,27 0,17
PLASTIC QUAD FLATPACK
0,08
0,13 7,50 10,20 9,80 12,20 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 0,75 0,45
1,20
0,08 4040282 11/96
NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026
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