KK74HC03A Quad 2-Input NAND Gate with Open-Drain Outputs KK7

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KK74HC03A Quad 2-Input NAND Gate with Open-Drain Outputs KK7

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KK74HC03A
KK74HC03A
Quad 2-Input NAND Gate with Open-Drain Outputs
KK74HC03A identical pinout LS/ALS03. device inputs compatible with standard CMOS outputs; with pullup resistors, they compatible with LS/ALSTTL outputs. KK74HC03A NAND gate has, output, high-performance N-Channel transistor. This NAND gate can, therefore, with suitable pullup resistor, used wired-AND applications. Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices
ORDERING INFORMATION KK74HC03AN Plastic KK74HC03AD SOIC -55° 125° packages
LOGIC DIAGRAM
ASSIGNMENT
FUNCTION TABLE
Inputs =VCC Output
High Impedance
KK74HC03A
MAXIMUM RATINGS*
Symbol VOUT IOUT Tstg
Parameter Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Output Current, Supply Current, Pins Power Dissipation Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, from Case Seconds (Plastic SOIC Package)
Value -0.5 +7.0 -1.5 +1.5 -0.5 +0.5 +150
Unit
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. +Derating Plastic DIP: mW/°C from 125°C SOIC Package: mW/°C from 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol VIN, VOUT Parameter Supply Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure =2.0 =4.5 =6.0 +125 1000 Unit
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, VOUT should constrained range GND(VIN VOUT)VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
KK74HC03A
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Symbol Parameter Test Conditions Guaranteed Limit -55°C 3.15 1.35 0.26 0.26 ±0.1 3.15 1.35 0.33 0.33 ±1.0 3.15 1.35 ±1.0 Unit
Minimum HighLevel Input Voltage Maximum Level Input Voltage Maximum LowLevel Output Voltage
VOUT=0.1 VCC-0.1 IOUT VOUT=0.1 VCC-0.1 IOUT VIN=VIH IOUT VIN=VIH IOUT IOUT
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Maximum ThreeState Leakage Current
VIN=VCC VIN=VCC IOUT=0µA Output High-Impedance State VIN= IOUT=
±0.5
±5.0
KK74HC03A
ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0
Symbol Parameter Guaranteed Limit -55°C 85°C 125°C Unit
tPLZ, tPZL
Maximum Propagation Delay, Input Output (Figures Maximum Output Transition Time, Output (Figures Maximum Input Capacitance Maximum Three-State Output Capacitance (Output High-Impedance State) Power Dissipation Capacitance (Per Gate) Used determine no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
tTHL
COUT
Typical @25°C,VCC=5.0
.Figure Switching Waveforms
Figure Test Circuit
EXPANDED LOGIC DIAGRAM (1/4 Device)
Denotes open-drain outputs
KK74HC03A
SUFFIX PLASTIC 001AA)
Dimension, Symbol 18.67 19.69 7.11 5.33 0.36 1.14 2.54 7.62 2.92 7.62 0.38 3.81 8.26 0.36 0.56 1.78
SEATING 0.25 (0.010)
PLANE
NOTES: Dimensions "A", include mold flash protrusions. Maximum mold flash protrusions 0.25 (0.010) side.
SUFFIX SOIC 012AB) Dimension,
Symbol
8.55 1.35 0.33 1.27 5.27 0.19 0.25
8.75 1.75 0.51 1.27
0.25 (0.010)
SEATING PLANE
0.25 0.25
NOTES: Dimensions include mold flash protrusion. Maximum mold flash protrusion 0.15 (0.006) side 0.25 (0.010) side.

KK74HC03A Quad 2-Input NAND Gate with Open-Drain Outputs KK7

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