QUAD-UART ASYNCHRONOUS COMMUNICATIONS ELEMENT KK16C554 enhan
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KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
KK16C554 enhanced quadruple version 16C550 UART (Universal Asynchronous Receiver Transmitter). Each channel into FIFO mode relieve excessive software overhead. this mode, internal FIFOs activated bytes plus error data byte stored both receive transmit modes. Each channel performs serial-to-parallel conversion data characters received from peripheral device MODEM, parallel-to-serial conversion data characters received from CPU. read complete status UART time during functional operation. Status information includes type condition transfer operations being performed UART, well error conditions such parity, overrun, framing, break interrupt. KK16C554 includes programmable baud rate generator which capable dividing timing reference clock input divisors 216-1, producing clock driving internal transmitter logic. Provisions also included this clock drive receiver logic. KK16C554 complete MODEM-control capability interrupt system that programmed user's requirements, minimizing computing required handle communication links.
Features
FIFO mode, Each channel's transmitter receiver buffered with 16-byte FIFO reduce number interrupts CPU. Adds deletes standard asynchronous communication bits (start, stop, parity) from serial data. Holding Register Shift Register eliminate need precise synchronization between serial data. Independently controlled transmit, receive, line status data interrupts. Programmable Baud Rate Generators which allow division input reference clock 216-1 generate internal clock. Independent receiver clock input Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, DCD#). Fully programmable serial interface characteristics. 8-bit characters Even-, Odd-, No-Parity 1.5-, 2-Stop generation. Like other general UARTs, KK16C554 checks only stop bit, matter many they are) False start detection Generates Detects Line Break Internal diagnostic capabilities Loop-back controls communications link fault isolation. Full prioritized interrupt system controls
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Signal Description
NAME CS0#, CS1# CS2#, CS3# (48) (47) (46) 16,20 (28, 50,54 (68, DESCRIPTION Register select pins. three inputs used select register UART during read write operations. Chip Select. Each CSx# enables read write operations respective channel. Clear send. CTSx# modem status signal. status known reading modem status register. CTS# does affect transmitor receive operation. Data Bus. Eight data lines with 3-state outputs provide bidirectional path data, control, status information between KK16C554 CPU. LSB. Data Carrier Detect. DCDx# indicates carrier been detected modem. condition known reading modem status register.
CTS0#, 11,25 (23, CTS1# CTS2, CTS3# 45,59 (63, D7~D3, D2~D0 DCD0#, DCD1# DCD2#, DCD3# DSR0#, DSR1# DSR2#, DSR3# DTR0#, DTR1# DTR2#, DTR3# 66~68(15~11) (9~7)
9,27 (19, (59,
10,26 (22, Data ready. DSRx# modem status signal. condition DSRx# checked reading modem status register. DSR# does 44,60 (62, affect transmit receive operation. Data Terminal Ready. DTRx# output that indicates modem data that UART ready establish communications. Setting modem control register activates DTRx# placed inactive state either result master reset during loop mode operation clearing modem control register. signal power ground Interrupt normal. INTN# conjunction with modem status register affects operation four interrupts (INT0~INT3).
24(24, 58(64,77)
(16,36) (56,76)
INTN#
INTN# Float
Operation Interrupts Interrupts enabled according state OUT2 (MCR When cleared, 3-state interrupt output that UART high state. When set, interrupt output UART enabled. Interrupts always activated.
High INT0, INT1 INT2, INT3 IOR# 15,21(27,34) 19,55(67,74) (70)
External interrupt output. When activated, INTx output informs that UART interrupt serviced. Read strobe. level IOR# transfers contents KK16C554 data external bus.
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NAME IOW# RESET
(31) (53)
DESCRIPTION Write strobe. IOW# allows write into selected address address register. Master reset. When active, RESET clears most UART registers sets state various signals. transmitter output receiver input disabled during reset time.
RI0#, RI1# RI2#, RI3# RTS0#, RTS1# RTS2#, RTS3#
(18,43) (58, (26,35) (66,75)
Ring detect indicator. Rix# indicates modem received ring signal from telephone line. condition this signal checked reading modem status register.
Request Send. When active, RTSx# informs modem data that UART ready receive data. Writing modem control register sets this state. After reset, this terminal high. These terminals have affect transmit receive operation.
RXD0, RXD1 RXD2, RXD3 RXRDY TXD0, TXD1 TXD2, TXD3 TXRDY
(17, (57,
Serial Input. RXDx serial data input from connected communications device. During loopback mode, RXDx input disabled from external connection connected TXDx output internally. Receive ready. RXRDY# goes when receive FIFO full. used single transfer multi transfer. Transmit output. TXDx composite serial data output that connected communications device. TXD1, TXD2, TXD3, TXD4 high state result reset. Transmit Ready. TXRDY# goes when transmit FIFO full. used single transfer multi transfer.
(54) (29,32) (69,72) (55) (45,65) (50)
XTAL1
Power supply. Crystal input external clock input. crystal connected XTAL1 XTAL2 utilize internal oscillator circuit. external clock connected drive internal clock circuits. Crystal output buffered clock output.
XTAL2
(51)
number outside parenthesis means number KK16C554PL, number inside parenthesis means number KK16C554TQ.
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Functional Block Diagram
D7-D0
Logic
Receive Control Logic
RXDx
A2-A0 CSx# IOR# IOW# RESET
Logic
Logic
Transmit Control Logic
TXDx
INTx TXRDY# RXRDY#
Logic
Logic
XTAL1 XTAL2
Clock
Circuit
Logic
Modem Control Logic
CTSx# RTSx# DSRx# DTRx# RIx# DCDx#
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Register Description
ADDRESS REGISTER MNEMONIC
REGISTER ADDRESS Data Data Data Data Data Data Data (LSB) Data Data Data Data Data Data Data
(read only)
Data (MSB) Data
(write only)
(EDSSI) Enable modem status interrupt
(ERLSI) Enable receiver line status interrupt
(ETBEI) Enable Transmitte Holding register empty interrupt
(ERBI) Enable received data available interrupt
Receiver (write only) (read only) (DLAB) Divisor latch access Trigger (MSB) FIFOs Enabled
Receiver Trigger (LSB) FIFOs Enabled break
Reserved
Reserved
mode select
Transmit FIFO reset Interrupt (STB) Number Stop bits
Receiver FIFO reset Interrupt (WLSB1) Word length select
FIFO enable interrupt pending (WLSB0) Word length select (DTR) Data terminal ready
Interrupt
Stick Parity
(EPS) Even parity select Loop
(PEN) Parity Enable
OUT2 Enable external interrupt (INT)
Reserved
(RTS) Request Send
Error receiver FIFO
(TEMT) Transmitte registers empty
(THRE) Transmitte holding register empty (DSR) Data Ready
(BI) Break interrupt
(FE) Framing Error
(PE) Parity Error
(OE) Overrun error
(DR) Data ready
(DCD) Data carrier detect
(RI) Ring indicator
(CTS) Clear Send
(DCD) Delta data carrier detect
(TERI) Trailing Edge ring indicator
(DSR) Delta data ready
(CTS) Delta clear send
DLAB This always state when FIFO disabled.
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5.1. FIFO control register(FCR)
write-only register same address IIR. enables FIFO, sets trigger level receiver FIFO, selects type signaling. FCR0 enables transmit receiver FIFOs. bytes both FIFOs cleared clearing this bit. Data cleared automatically from FIFOs when changing from FIFO mode 16C550 mode vice versa. Programming other bits enabled setting this bit. When set, FCR1 clears bytes receiver FIFO resets counter. This does clear shift register. When set, FRC2 clears bytes transmitter FIFO resets counter. This does clear shift register. When set, FRC3 changes RXRDY# TXRDY# from mode mode FCR0 set. Reserved future use. FCR6 FCR7 trigger level receiver FIFO interrupt. (see Table
Table Receiver FIFO Trigger Level Receiver FIFO Trigger Level FIFO interrupt mode operation following receiver status occurs when receiver FIFO receiver interrupts enabled. LSR0 when character transferred from shift register receiver FIFO. When FIFO empty, reset. Receiver line status interrupt(IIR higher priority than receive data available interrupt(IIR 04). Receive data available interrupt issued when programmed trigger level reached FIFO. soon FIFO drops below programmed trigger level, cleared. Receive data available indicator(IIR=04) also occurs when FIFO reaches trigger level. cleared when FIFO drops below programmed trigger level.
following receiver FIFO character time-out status occurs when receiver FIFO receiver interrupts enabled. When following conditions exist, FIFO character time-out interrupt occurs. Minimum character FIFO. Last received serial character longer than four continuous previous character times ago. stop bits programmed, second included time delay. Only first stop checked UART.) last FIFO read more than four continuous character times earlier.
using XTAL1 input clock signal, character times calculated. delay proportional baud rate.
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
time-out timer reset after reads receiver FIFO after character received. This occurs when there been time-out interrupt. time-out interrupt cleared timer reset when reads character from receiver FIFO.
Transmit interrupts occurs follows when transmitter transmit FIFO interrupts enabled (FCR=0, IER=1). When transmitter FIFO empty, transmitter holding register interrupt (IIR=02) occurs. interrupt cleared when transmitter holding register written read. characters written transmit FIFO when servicing this interrupt. transmitter FIFO empty indicators delayed character time minus last stop time whenever following occurs. THRE=1, there been minimum bytes same time transmit FIFO since last THRE=1. first transmitter interrupt after changing FCR0 immediate, however, assuming enabled. Receiver FIFO trigger level character time-out interrupts have same priority receive data available interrupt. transmitter holding register empty interrupt same priority transmitter FIFO empty interrupt.
5.2. Line Control Register
format data character controlled LCR. LCR0 LCR1 word length select bits. (see Figure LCR2 stop select bit. receiver always checks stop bit. LCR3 parity enable bit. When LCR3 set, parity generated checked. LCR4 even parity select bit. When LCR3 this set, even parity generated checked. When LCR3 this cleared, parity selected. LCR5 stick parity select bit. When LCR3 this set, transmission reception parity forced opposite state from value LCR4. Clearing this disenables stick parity. LCR6 break control bit. When this set, serial outputs TXDxs forced `0'. break control acts only serial output does affect transmitter logic. following sequence used, invalid characters transmitted because break. Load zero byte response transmitter holding register empty(THRE) status indicator. next THRE signal response break. Wait transmitter idle, when transmitter empty status signal (TEMT=1) then clear break, start normal transmission.
LCR7 divisor latch access bit(DLAB). This must access divisor latches baud rate generator during read write operation. LCR7 must cleared access Receiver Buffer Register, Transmitter Holding Register, Interrupt Enable Register.
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Word Length Select
Data Data Data Data
Bits Bits Bits Bits
Stop Select
Stop Stop Bits Data Bits Selected Stop Bits 6,7,8 Data Bits Selected
Parity Disabled
Parity Enable Parity Enabled
Even Parity
Parity Even Parity
Stick Parity
Stick Parity Disabled Stick Parity Enabled
Break Control
Break Disabled Break Enabled
Divisor Latch Access Receiver Buffer Access Divisor Latches Access
Figure Line Control Register
Programmable Baud Generator UART contains programmable Baud Generator that capable taking clock input from 14.7456MHz dividing divisor from 216-1. 4MHz highest clock input recommended when divisor output frequency baud generator baud [divisor (frequency input)/(baud rate 16)]. 8-bit latches store divisor 16-bit binary format. These Divisor Latches must loaded during initialization ensure proper operation Baud Generator. (see Table
Table Baud rates
This table provides decimal divisors with crystal frequencies 1.8432MHz, 3.6864MHz, 7.3728MHz 14.7456MHz. baud rates 38400 below, error obtained minimal. accuracy desired baud rate dependent frequency crystal. recommended using divisor zero.
Desired baud rate 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19.2K 38.4K 57.6K 115.2K 230.4K 460.8K 921.6K
1.8432MHz 2304 1536
Decimal divisor generate Clock 3.6864MHz 7.3728MHz 4608 9216 3072 6144 1714 3428 1536 3072 1536
14.7456MHz 18432 12288 6856 6144 3072 1536
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5.3. Line Status Register
This register provides status information concerning data transfer. Data Ready(DR) indicator. logic whenever complete incoming character been received transferred into Receiver Buffer Register FIFO. This cleared reading data Receiver Buffer Register FIFO. Overrun Error(OE) indicator. indicates that data Receiver Buffer Register read before next character transferred into Receiver Buffer Register, thereby destroying previous character. This logic when overrun occurs cleared whenever reads contents Line Status Register. FIFO mode data continues fill FIFO beyond trigger level, overrun error will occur only after FIFO full next character been completely received shift register. indicated soon happens. character shift register overwritten, transferred FIFO. Parity Error indicator. logic upon detection parity error reset logic whenever reads contents Line Status Register. FIFO mode, this error revealed when associated character FIFO. Framing Error indicator. indicates that received character have valid stop bit. This logic whenever stop following last data parity detected logic bit. reset logic whenever reads contents Line Status Register. FIFO mode, this error revealed when associated character FIFO. When this error been detected, assumes next start bit, samples this start twice take data. Break Interrupt indicator. logic when received data input held spacing state longer than full word transmission time (start data bits parity stop bits). indicator reset logic whenever reads contents Line Status Register. FIFO mode, this error revealed when associated character FIFO. When break occurs, only zero character loaded into FIFO. next character transfer enabled after goes HIGH receives next start bit. Transmitter holding register empty(THRE) indicator. indicates that UART ready take character transmission. addition, this causes UART issue interrupt when Transmit Holding Register Empty interrupt enable HIGH. This logic when character transferred from Transmitter Holding Register into Transmitter shift register. reset logic when transfers data Transmitter Holding Register. FIFO mode, this logic when XMIT FIFO empty, reset logic when least byte written XMIT FIFO. Transmitter Empty indicator. This when Transmitter Holding Register Transmitter Shift Register both empty, reset logic when contains data character. FIFO mode, logic when both Transmitter FIFO Transmitter Shift Register empty. 16C550 mode, this FIFO mode logic when contains least error such parity error, framing error break error. This reset logic when reads Line Status Register there exists error.
KK16C554PL/KK16C554TQV
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5.4. Interrupt Identification Register
order provide minimum software overhead during data transfer, UART prioritizes interrupts into levels record these Interrupt Identification Register. four levels interrupt conditions are, order priority: Receiver Line Status Received Data Ready Transmitter Holding Register Empty MODEM Status When accesses IIR, UART freezes interrupts indicates highest priority pending interrupt CPU. While this access occurring, UART records interrupts, does change current indication until access complete.
This used prioritized interrupt environment indicate whether interrupt pending. When logic interrupt pending contents used pointer appropriate interrupt service routine. When logic interrupt pending. These bits used identify highest priority interrupt pending indicated Table 16C550 mode, this FIFO mode, this along with when time-out interrupt pending. These bits always logic These bits whenever FCR0 logic
Table Interrupt Control Function
FIFO mode only Priority Level Interrupt Type Receiver Line Status Receiver Data Available Character Timeout Indication Transmitter Holding Register Empty Modem Status CTS, DSR, Reading character been removed since last transfer there transfer FIFO during character time. Transmitter Empty Holding Register Reading source interrupt writing Receiver Data Available Trigger level reached Reading FIFO drops below trigger level Reading Reading Interrupt Source Interrupt Reset Control Interrupt Identification Register Interrupt reset Function
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5.5. Interrupt Enable Register
independently enables four serial channel interrupt sources that activate interrupt( INT0, INT1, INT2, INT3) output. interrupts disabled clearing IER0-IER3 IER. Interrupts enabled setting appropriate bits IER. Disabling interrupt system inhibits active high interrupt output. other system functions operate their normal manner, including setting MSR. contents described following bulleted list.
When IER0 set, IER0 enables received data available interrupt timeout interrupts FIFO mode. When IER1 set, transmitter holding register empty interrupt enabled. When IER2 set, receiver line status interrupt enabled. When IER3 set, modem status interrupt enabled. These bits cleared.
5.6. Modem Control Register
controls interface with modem data described Figure written read. RTS# DTR# outputs directly controlled their control bits this register. high input asserts signal output terminals. bits shown follows. When MCR0 set, DTR# output forced low. When MCR0 cleared, DTR# output forced high. DTR# output serial channel input into inverting line driver order obtain proper polarity input modem data set. When MCR1 set, RTS# output forced When MCR1 cleared, RTS# output forced high. DTR# output serial channel input into inverting line driver order obtain proper polarity input modem data set. MCR2 affect operation. When MCR3 set, external serial channel interrupt enabled. MCR4 provides local loopback feature diagnostic testing channel. When MCR4 set, serial output TXDx high state disconnected. output looped back into input. four modem control inputs (CTS#, DSR#, DCD#, RI#) disconnected. modem control outputs (DTR#, RTS#) internally connected four modem control inputs. modem control output terminals forced their inactive state KK16C554. diagnostic mode, data transmitted immediately received. This allows processor verify transmit receive data path selected serial channel. Interrupt control fully operational; however, interrupts generated controlling lower four bits internally. Interrupts generated activity external terminals represented those four bits. These bits permanently cleared.
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5.7. Modem Status Register
provides with status modem input lines modem peripheral devices. allows read serial channel modem signal inputs accessing data interface UART. also reads current status four bits that indicate whether modem inputs have changed since last reading MSR. delta status bits when control input from modem changes states cleared when reads MSR. contents shown follows. Delta Clear Send(DCTS) indicator. DCTS indicates that CTS# input serial channel changed state since last read CPU. Delta Data Ready(DDSR) indicator. DDSR indicates that DSR# input serial channel changed state since last read CPU. Trailing Edge Ring Indicator(TERI) indicator. TERI indicates that input serial channel changed states from high since last time read CPU. High transitions activate TERI. Delta Data Carrier Detect(DDCD) indicator. DDCD indicates that DCD# input serial channel changed state since last read CPU. note interrupt generated whenever bit0~3 logic Clear Send bit. complement CTS# input from modem indicating serial channel that modem ready provice received data from serial channel receiver circuitry. When channel loop mode, MSR4 reflects value MCR. Data Ready bit. complement DSR# input from modem serial channel that indicates that modem ready provide received data from serial channel receiver circuitry. When channel loop mode, MSR5 reflects value MCR. Ring indicator bit. complement Rix# inputs. When channel loop mode, MSR6 reflects value OUT1# MCR. Data Carrier Detect bit. Data carrier detect indicates status data carrier detect input. When channel loop mode, MSR7 reflects value OUT2# MCR.
5.8. Scratch Register
This 8-bit read/write register affect either channel UART. intended used programmer hold data temporarily.
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Package Diagram
PACKAGE (Top)
DCD0# RXD0 RXD3 DCD3# INTN# RI0# RI3#
DSR0# CTS0# DTR0# RTS0# INT0 CS0# TXD0 IOW# TXD1 CS1# INT1 RTS1# DTR1# CTS1# DSR1#
DSR3# CTS3# DTR3# RTS3# INT3 CS3# TXD3 IOR# TXD2 CS2# INT2 RTS2# DTR2# CTS2# DSR2#
XTAL1 XTAL2 RXD1 RI1# TXRDY# DCD1# RI2# RESET RXRDY# DCD2# RXD2
internal connection
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
KK16C554TQ PACKAGE (Top)
RXRDY#
TXRDY#
DCD2#
RESET
RXD2
RXD1
DCD1#
XTAL2
XTAL1
RI2#
RI1#
DSR2#
CTS2#
DSR1#
DTR2#
RTS2#
INT2
CTS1#
DTR1#
RTS1#
INT1
CS2#
CS1#
TXD1
IOW#
TXD2
IOR#
TXD3
TXD0
CS0#
CS3#
INT3
RTS3#
INT0
RTS0#
DTR0#
CTS0#
DTR3#
CTS3#
DSR3#
DCD0#
DSR0#
INTN#
RI3#
DCD3#
RXD3
internal connection
RXD0
RI0#
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Operating Conditions
7.1. General Operating Conditions
Supply Voltage, Clock high-level input voltage XTAL1, VIH(CLK) Clock low-level input voltage XTAL1, VIL(CLK) High-level input voltage, Low-level input Voltage, Clock frequency, fCLOCK Operating free-air temperature, 4.75 -0.5 -0.5 5.25 Vcc+0.5 UNIT
7.2. Read cycle timing requirements over recommended ranges operating free-air temperature supply voltage (See
tcsr trcs tfrc Pulse duration, IOR# time, CSx# valid before IOR# time, A2~A0 valid before IOR# Hold time, A2~A0 valid after IOR# high Hold time, CSx# valid after IOR# high Delay time, tar+trd+trc Delay time, IOR# high IOR# IOW# UNIT
internal address strobe always active state. FIFO mode, td1=425ns (min) between reads FIFO status register.
7.3. Write cycle timing requirements over recommended ranges operating free-air temperature supply voltage (See
tcsw twcs tfwc Pulse duration, IOW# Setup time, CSx# valid before IOW# Setup time, A2~A0 valid before IOW# Setup time, D7~D0 valid before IOW# Hold time, A2~A0 valid after IOW# Hold time, CSx# valid after IOW# Hold time, D7~D0 valid after IOW# Delay time, taw+twr+twc Delay time, IOW# IOW# IOR# UNIT
7.4. Read cycle switching characteristics over recommended ranges operating free-air temperature supply voltage
trvd Enable time, IOR# D7~D0 valid Disable time, IOR# D7~D0 released UNIT
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
7.5. Transmitter switching characteristics over recommended ranges operating free-air temperature supply voltage (See 3~5.)
tirs tsti tsxa twxi Delay time, INTx TXDx start Delay time, TXDx start INTx Delay time, IOW# high THR) INTx Delay time, TXDx start TXRDY# Propagation delay time, IOW#(WR THR) INTx Propagation delay time, IOR#(RD IIR) INTx Propagation delay time, IOW#(WR THR) TXRDY# UNIT RCLK cycles RCLK cycles RCLK cycles RCLK cycles
7.6. Receiver switching characteristics over recommended ranges operating free-air temperature supply voltage (Fig 6~9.)
tsint trint trint Delay time, stop INTx stop RXRDY# read interrupt Propagation delay time, Read RBR/LSR INTx/LSR interrupt Propagation delay time, IOR# RCLK RXRDY# UNIT RCLK cycle
7.7. Modem control switching characteristics over recommended ranges operating free-air temperature supply voltage (See 10.)
tmdo tsim trim tsim Propagation delay time, IOW#(WR MCR) RTSx#, DTRx# Propagation delay time, modem input CTSx#, DSRx#, DCDx# INTx Propagation delay time, IOR#(RD MSR) interrupt Propagation delay time, Rix# INTx#
A[2:0]
VALID ADDRESS
CSx#
IOR#
ACTIVE
IOW#
VALID DATA
D[7:0]
Read Cycle Timing
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
A[2:0]
VALID ADDRESS
CSx#
IOR#
ACTIVE
IOW#
D[7:0]
VALID DATA
Write Cycle Timing Waveforms
TXDx
START
DATA(5-8)
PARITY
STOP(1-2)
START
INTx
IOW# THR)
IOR# IIR)
Transmitter Timing Waveforms
IOW# THR)
BYTE
TXDx
DATA
PARITY
STOP
START
TXRDY#
Transmitter Ready Mode Timing Waveforms
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
IOW# THR)
BYTE
TXDx
DATA
PARITY
STOP
START
TXRDY#
FIFO FULL
Transmitter Ready Mode Timing Waveforms
RXDx
START
DATA(5-8)
PARITY
STOP
Sample Clock
INTx(TRIGGER LEVEL INTERRUPT (FCR6,
sint
rint
(FIFO ABOVE TRIGGER LEVEL)
(FIFO BELOW TRIGGER LEVEL)
INTERRUPT
IOR# LSR)
rint
IOR# RBR)
Receiver FIFO First Byte (Sets RDR) Waveforms
RXDx
Sample Clock
TIMEOUT TRIGGER LEVEL INTERRUPT
STOP
(FIFO ABOVE TRIGGER LEVEL)
sint
rint
(FIFO BELOW TRIGGER LEVEL)
INTERRUPT
IOR# LSR)
BYTE FIFO
sint
rint
IOR# RBR)
PREVIOUS BYTE READ FROM FIFO
Receiver FIFO After First Byte (After Set) Waveforms
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
IOR# RBR)
RXDx (FIRST BYTE)
Sample Clock
STOP
RXRDY#
sint
rint
Receiver Ready Mode Timing Waveforms
IOR# RBR) RXDx (FIRST BYTE THAT REACHES TRIGGER LEVEL)
STOP
Sample Clock
RXRDY#
sint rint
Receiver Ready Mode Timing Waveforms
IOW# MCR)
RTSx#, DTRx#
CTSx#, DSRx#, DCDx#
INTx
IOR# MSR)
RIx#
Modem Control Timing Waveforms
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Typical Clock Circuits
XTAL1 Crystal
KK16C554
XTAL2
10~30pF, 40~60pF, 1.5K
Mechanical Data
PLCC(Plastic Leaded Chip Carrier) Package
0.995 (25,273) 0.985 (25,019) 0.032 (0.081) 0.026 (0,66) 0.956 (24,282) 0.950 (24,130)
0.18 (4,57) 0.120 (3,05) 0.090 (2,29) 0.02 (0,51)
0.995 (25,273) 0.985 (25,019)
0.956 (24,282) 0.950 (24,130)
0.050 (1,27)
Note dimensions inches (millimeters). Falls within ANSI Y14.5-1982
0.021 (0,53) 0.013 (0,33)
0.469 (11,913) 0.441 (11,201)
0.469 (11,913) 0.441 (11,201)
KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
TQFP(Thin Quad Flat Pack) Package
0,27 0,17
0,50
1,20
9,50 12,00 14,00 1,05 0,95 1.00
0,10 0,75 0,45
Note dimensions millimeters. Falls within ANSI Y14.5-1982.
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