High-Performance Optical Mouse Sensor ADNS-3080 high performance

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High-Performance Optical Mouse Sensor ADNS-3080 high performance

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ADNS 3080
High-Performance Optical Mouse Sensor
ADNS-3080 high performance addition Avago Technologies' popular ADNS family optical mouse sensors. ADNS-3080 based new, faster architecture with improved navigation. sensor capable sensing high speed mouse motion inches second acceleration increased user precision smoothness. ADNS-3080 along with ADNS-2120 ADNS-2120001) lens, ADNS-2220 ADNS-2220-001) assembly clip HLMP-ED80-XX000 form complete, compact optical mouse tracking system. There moving parts, which means high reliability less maintenance user. addition, precision optical alignment required, facilitating high volume assembly. sensor programmed registers through four-wire serial port. packaged 20-pin staggered dual inline package (DIP).
Features
High speed motion detection architecture greatly improved optical navigation technology Programmable frame rate over 6400 frames second SmartSpeed self-adjusting frame rate optimum performance Serial port burst mode fast data transfer 1600 selectable resolution Single volt power supply Four-wire serial port along with Chip Select, Power Down, Reset pins
Applications
Mice game consoles computer games Mice desktop PC's, Workstations, portable PC's Trackballs Integrated input devices
Theory Operation
ADNS-3080 based Optical Navigation Technology, which measures changes position optically acquiring sequential surface images (frames) mathematically determining direction magnitude movement. contains Image Acquisition System (IAS), Digital Signal Processor (DSP), four-wire serial port. acquires microscopic surface images lens illumination system. These images processed determine direction distance motion. calculates relative displacement values. external microcontroller reads information from sensor serial port. microcontroller then translates data into signals before sending them host game console.
Pinout
Name MISO SCLK MOSI LED_CTRL RESET OSC_OUT GUARD OSC_IN OPTP REFC REFB VDD3 VDD3 Description Chip select (active input) Serial data output (Master In/Slave Out) Serial clock input Serial data input (Master Out/Slave control output Reset input Power down (active input) Oscillator output Oscillator guard (optional) Oscillator input connect Connect VDD3 Reference capacitor Reference capacitor Supply voltage Ground Supply voltage connect Ground connect
MISO SCLK MOSI LED_CTRL RESET OSC_OUT GUARD OSC_IN OPTP REFC REFB VDD3
VIEW
VDD3
A3080 XYYWWZ
PINOUT
Figure Package outline drawing (top view)
Figure Package outline drawing
CAUTION: advised that normal static precautions taken handling assembly this component prevent damage and/or degradation which induced ESD.
Overview Optical Mouse Sensor Assembly Assembly Drawing ADNS-3080
Shown with ADNS-2120, ADNS-2220 HLMP ED80XX000. Avago Technologies provides IGES file drawing describing base plate molding features lens alignment. components interlock they mounted onto defined features base plate. ADNS-3080 sensor designed mounting through hole PCB, looking down. There aperture stop features package that align lens. ADNS-2120 lens provides optics imaging surface well illumination surface optimum angle. Features lens align sensor, base plate, clip with LED. lens also large round flange provide long creepage path events that occur opening base plate. ADNS-2220-001 clip holds relation lens. must inserted into clip LED's leads formed prior loading PCB. clip interlocks sensor lens, through lens alignment features base plate. HLMP-ED80-XX000 recommended illumination. used with table, sufficient illumination
Figure Recommended mechanical cutouts spacing
Figure Assembly drawing ADNS-3080 (top side view)
NOTE: These Avago Technologies optical mouse sensors, lenses clips have different physical configurations that require different mounting method optimize navigation performance. Refer Application Notes 5035 further information.
Assembly Considerations
HLMP-ED80-XX000 (LED) ADNS-2220 (Clip) ADNS-3080 (Sensor) Customer supplied ADNS-2120 (Lens) Customer supplied base plate with recommended alignment features IGES drawing.
Figure Exploded view drawing
Insert sensor other electrical components into PCB. Insert into assembly clip bend leads degrees. Insert LED/clip assembly into PCB. Wave Solder entire assembly no-wash solder process utilizing solder fixture. solder fixture needed protect sensor during solder process. also sets correct sensor-to -PCB distance lead shoulders normally rest surface. fixture should designed expose sensor leads solder while shielding optical aperture from direct solder contact. Place lens onto base plate.
Remove protective kapton tape from optical aperture sensor. Care must taken keep contaminants from entering aperture. During mouse assembly process, recommended that held vertically when kapton tapes being removed. Insert assembly over lens onto base plate aligning post retain assembly. sensor aperture ring should self-align lens. optical position reference base plate lens. Note that motion button presses must minimized maintain optical alignment. Install mouse case. There MUST feature case press down
SCLK MOSI MISO
Serial Port
OSC_IN OSCILLATOR OSC_OUT REFB REFC OPTP VDD3
RESONATOR
IMAGE PROCESSOR
LED_CTRL RESET CTRL
VOLTAGE REGULATOR POWER CONTROL
REFERENCE VOLTAGE FILTER NODE
POWER
Figure Block diagram ADNS-3080 optical mouse sensor
Design considerations improving Performance
flange lens been designed increase creepage clearance distance electrostatic discharge. table below shows typical values assuming base plate construction Avago Technologies supplied IGES file ADNS-2120 lens flange. improved performance, lens flange sealed (i.e. glued) base plate. Note that lens material polycarbonate therefore, cyanoacrylate based adhesives other adhesives that damage lens should used.
Typical Distance Creepage Clearance
Millimeters 16.0
Clip Sensor
Lens/Light Pipe Base Plate
Surface
Figure Cross section assembly
LP2950ACZ-3.3 D1.3 DP0.7* P0.6 P0.5* CYPRESS CY7C63743A-PC P0.4* P0.2 P0.3 4.7uF 0.1uF 0.1uF 0.1uF 4.7uF ADNS 2120 Lens
Internal Image Sensor SCLK MISO MOSI RESET ADNS-3080
HLMP-ED80 BS170
SURFACE
Vreg P1.7 P1.5
LED_CTRL
SHLD
REFC
Ceramic Resonator Murata CSALS 3.3V
REFB OSC_IN GUARD OSC_OUT
Scroll Wheel Encoder ALPS EC10E P1.4
P1.0 P1.2 P1.1
Buttons
XTALOUT XTALIN
(Optional)
OPTP
Notes: capacitors close chip 24MHz 6MHz oscillators close chip Outputs configured open drain
Figure Schematic Diagram USB, PS/2 mouse application with ADNS-3080
Notes Caps pins MUST have trace lengths LESS than nearest ground pin. Pins caps MUST GND. used, should connected reduce potential emissions. caps must ceramic. Caps should have less than self inductance. Caps should have less than ESR. pins should connected traces. Surface mount parts recommended. Care must taken when interfacing microcontroller ADNS-3080. Serial port inputs sensor should connected opendrain outputs from microcontroller active drive level shifter. RESET should connected microcontroller outputs through resistor divider other level shifting technique. VDD3 should have impedance connections power supply. Capacitors connected should connected then
Enabling SROM
best tracking performance,SROM required loaded into ADNS-3080. This architecture enables immediate adoption features improved performance algorithms. external program supplied Avago Technologies file which burned into programmable device. micro-controller with sufficient memory used. power-up reset, ADNS-3080 program downloaded into volatile memory using burst-mode procedure described Synchronous Serial Port section. program size 1986 bits.
Regulatory Requirements
Passes worldwide analogous emission limits when assembled into mouse with shielded cable following Avago Technologies' recommendations. Passes IEC-1000-4-3 radiated susceptibility level when assembled into mouse with shielded cable following Avago Technologies' recommendations. Passes EN61000-4-4/IEC801-4 tests when assembled into mouse with shielded cable following Avago Technologies' recommendations. flammability level UL94 V-0. Provides sufficient creepage/clearance distance avoid discharge 15kV when assembled into mouse according usage instructions above.
Sensor Lens 2.40 0.094
Object Surface
Figure Distance from lens reference plane surface
Absolute Maximum Ratings
Parameter
Storage Temperature Operating Temperature Lead Solder Temp Supply Voltage Input Voltage Output current Iout -0.5 VDD3 -0.5
Symbol
Minimum Typical
Maximum
VDD3+0.5
Units
Notes
seconds, 1.6mm below seating plane.
pins, human body model Method 3015 NPD, NCS, MOSI, SCLK, RESET, OSC_IN, OSC_OUT, REFC. LED_CTRL, MISO
Recommended Operating Conditions
Parameter
Operating Temperature Power supply voltage Power supply rise time Supply noise (Sinusoidal) Oscillator capable Frequency Serial Port Clock Frequency Resonator Impedance Distance from lens reference plane surface Speed Acceleration Light level onto
Symbol
VDD3B fCLK fSCLK
Minimum Typical Maximum
3.10 3.30 3.60
Units
Volts
Notes
3.0V 10kHz- 300KHZ 300KHz-50MHz ceramic resonator Active drive, duty cycle Open drain drive with pull-ups load
XRES
Results ±0.2 DOF, drawing below 6469fps 6469fps FR=1500 FR=1500 FR=6469 FR=6469 Frame_Period register section HLMP-ED80-XX000, brighter. Maximum frame rate maintained dark surfaces minimum drive current
IRRINC
in/sec mW/m2
2000
6,000 7,200 6,000 7,200 6469
Frame Rate Drive Current
ILED
Frames/s
Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values VDD3=3.3V, fclk=24MHz. Parameter
RESET Data delay after RESET Input delay after reset Power Down Wake from
Symbol
tPU-RESET TIN-RST tPUPD
Min.
Typical
Max.
Units
Notes
From 3.0V RESET sampled From RESET falling edge valid motion data 2000 shutter bound 8290. From RESET falling edge inputs active (NPD, MOSI, NCS, SCLK) From falling edge initiate power down cycle 500fps (tpd frame period 100ms From rising edge valid motion data 2000 shutter bound 8290. assumes surface change while low. From rising edge registers contain data from images 2000fps (see Figure 50pF 50pF From SCLK falling edge MISO data valid, load conditions Data held until next falling SCLK edge Amount time data valid after SCLK rising edge From data valid SCLK rising edge From rising SCLK last first data byte, rising SCLK last second data byte. From rising SCLK last first data byte, rising SCLK last second address byte. From rising SCLK last first data byte, falling SCLK first second address byte. From rising SCLK last address byte, falling SCLK first data being read. registers except Motion Motion_Burst From rising SCLK last address byte, falling SCLK first data being read. Applies 0x02 Motion, 0x50 Motion_Burst, registers From falling edge first SCLK rising edge From last SCLK falling edge rising edge, valid MISO data transfer From rising edge MISO high-Z state (see Figure
Data delay after RESET pulse width MISO rise time MISO fall time MISO delay afterSCLK MISO hold time MOSI hold time MOSI setup time time between write commands time between write read commands
tCOMPUTE tPW-RESET tr-MISO tf-MISO tDLY-MISO thold-MISO thold-MOSI tsetup-MOSI tSWW tSWR
time between tSRW read subsequent tSRR commands read address-data delay motion read address-data delay SCLK active SCLK inactive MISO high-Z tSRAD
tSRAD-MOT
tNCS-SCLK tSCLK-NCS tNCS-MISO
SROM download tLOAD frame capture byte-to-byte delay burst mode exit Transient Supply Current tBEXIT
Time must held high exit burst mode
IDDT
supply current during VDD3 ramp from 3.6V
Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values VDD3=3.3V, fclk=24MHz. Parameter
Supply Current Power Down Supply Current Input Voltage Input High Voltage Input hysteresis Input current, pull-up disabled Input current, CMOS inputs Output current, pulled-up inputs Output Voltage LED_CTRL Output High voltage, LED_CTRL Output Voltage, MISO Output High Voltage, MISO Input Capacitance
Symbol Minimum Typical Maximum Units Notes
IDD_AVG IDDPD VI_HYS IIH_DPU IOH_PU VOL,LED VDD3 average 6469 fps. load LED_CTRL, MISO. NPD=GND; SCLK, MOSI, NCS=GND VDD3; RESET=GND SCLK, MOSI, NPD, NCS, RESE SCLK, MOSI, NPD, NCS, RESET SCLK, MOSI, NPD, NCS, RESET Vin=0.8*VDD3, SCLK, MOSI, NPD, RESET, Vin=0.8*VDD3 Vin=0.2V, SCLK, MOSI, Iout=2mA, LED_CTRL
VOH_LED
0.8*VDD3
Iout=-2mA, LED_CTRL
0.8*VDD3 14-22
Iout=2mA, MISO Iout=-2mA, MISO OSC_IN, OSC_OUT
Detail rising edge timing
Reset Count Oscillator Start CURRENT (shutter mode) SCLK Optional transactions with image data tCOMPUTE 590us Frame Periods "Motion" motion detected. First read
Frame
Frame
Frame
Frame
Frame
Figure Rising Edge Timing Detail
Typical Performance Characteristics
Mean Resolution (White Paper) 2000 1800 1600 Resolution (counts/inch) 1400 1200 1000
White Paper Manila Burl Black Walnut Black Copy
OPERATING REGION
Distance from Nominal Focus (mm)
Figure Mean Resolution (White Paper)
Maximum Distance (Mouse Count)
Typical Path Deviation Largest Single Perpendicular Deviation From Straight Line Degrees Path length inches; Speed ips; Resolution 1600 White Paper Manila Burl Black Walnut Black Copy
Distance From Lens Reference Plane Navigation Surface (mm) Relationship mouse count distance (mouse count) (cpi) Deviation mouse count 7/1600 0.004375 inch 0.004 inch where 1600
Figure Average error Distance (mm)
Relative responsivity wavelength (nm) 1000
Figure Relative responsivity
120% 100%
Average Supply Current Frame Rate VDD=3.6V 100%
Relative Current
2000
4000 Frame Rate (Hz)
6000
8000
Figure Frame Rate
Synchronous Serial Port
synchronous serial port used read parameters ADNS-3080, read motion information. serial port also used load SROM data into ADNS-3080. port four-wire, serial port. host micro-controller always initiates communication; ADNS-3080 never initiates data transfers. serial port cannot activated while chip power down mode (NPD low) reset (RESET high). SCLK, MOSI, driven directly 3.3V output from micro-controller, they placed open drain configuration enabling on-chip pull-up current sources. open drain drive allows micro-controller without level shifting components. port pins shared with other slave devices. When high, inputs ignored output tri-stated. lines which comprise port are: SCLK: Clock input. always generated master (the micro- controller). MOSI: Input data (Master Out/Slave In). MISO: Output data (Master In/Slave Out). NCS: Chip select input (active low). needs activate serial port; otherwise, MISO will high-Z, MOSI SCLK will ignored. also used reset serial port case error.
Chip Select Operation
serial port activated after goes low. raised during transaction, entire transaction aborted serial port will reset. This true transactions including SROM download. After transaction aborted, normal address-to-data transaction-to-transaction delay still required before beginning next transaction. improve communication reliability, serial transactions should framed NCS. other words, port should remain enabled during periods non-use because EFT/B events could interpreted serial communication chip into unknown state. addition, must raised after each burst-mode transaction complete terminate burst-mode. port available further until burst-mode terminated.
Write Operation
Write operation, defined data going from microcontroller ADNS-3080, always initiated micro-controller consists bytes. first byte contains address (seven bits) indicate data direction. second byte contains data. ADNS-3080 reads MOSI rising edges SCLK.
Read Operation
read operation, defined data going from ADNS3080 micro-controller, always initiated micro-controller consists bytes. first byte contains address, sent micro-controller over MOSI, indicate data direction. second byte contains data driven ADNS-3080 over MISO. sensor outputs MISO bits falling edges SCLK samples MOSI bits every rising edge SCLK. NOTE: minimum high state SCLK also minimum MISO data hold time ADNS-3080. Since falling edge SCLK actually start next read write command, ADNS-3080 will hold state data MISO until falling edge SCLK.
SCLK
MOSI tHold,MOSI tSetup, MOSI
SCLK tDLY-MISO MISO
tHOLD-MISO
Figure MOSI setup hold time
Figure MISO delay hold time
SCLK MOSI MISO
MOSI Driven Micro-Controller
Figure Write Operation
SCLK Cycle SCLK MOSI MISO
Figure Read operation
tSRAD delay
Required timing between Read Write Commands (tsxx)
There minimum timing requirements between read write commands serial port.
tSWW 50µs
SCLK
Address Write Operation Data Address Write Operation Data
Figure Timing between write commands
rising edge SCLK last data second write command occurs before microsecond required delay, then first write command complete correctly.
tSWR 50µs
SCLK
Address Write Operation Data Address Next Read Operation
Figure Timing between write read commands
rising edge SCLK last address read command occurs before microsecond required delay, write command complete correctly.
tSRAD non-motion read tSRAD-MOT register 0x02 tSRW tSRR
SCLK
Address Read Operation Data Address
Next Read Write Operation
Figure Timing between read either write subsequent read commands
falling edge SCLK first address either read write command must least after last SCLK rising edge last data previous read operation. addition, during read operation SCLK should delayed after last address ensure that ADNS-3080 time prepare requested data.
Burst Mode Operation
Burst mode special serial port operation mode which used reduce serial transaction time three predefined operations: motion read SROM download frame capture. speed improvement achieved continuous data clocking from multiple registers without need specify register address, requiring normal delay period between data bytes.
Motion Read
This mode activated reading Motion_Burst register. ADNS-3080 will respond with contents Motion, Delta_X, Delta_Y, SQUAL, Shutter_Upper, Shutter_Lower Maximum_Pixel registers that order. After sending register address, microcontroller must wait tSRAD-MOT then begin reading data. data bits read with delay between bytes driving SCLK normal rate. data latched into output buffer after last address received. After burst transmission complete, micro-controller must raise line least tBEXIT terminate burst mode. serial port available until reset with NCS, even second burst transmission.
tSRAD-MOT
SCLK
Motion_Burst Register Address Read First Byte Read Second Byte Read Third Byte
First Read Operation
Figure Motion burst timing
SROM Download
This function used load Avago Technologiessupplied firmware file contents into ADNS-3080. firmware file ASCII text file with each 2-character byte (hexadecimal representation) single line. This mode activated following steps: Perform hardware reset toggling RESET Write 0x44 register 0x20 Write 0x07 register 0x23 Write 0x88 register 0x24 Wait least frame period Write 0x18 register 0x14 (SROM_Enable register) Begin burst mode write data file register 0x60 (SROM_Load register) After first data byte complete, SROM microcontroller must write subsequent bytes presenting data MOSI line driving SCLK normal rate. delay least tLOAD must exist between data bytes shown. After download complete, micro-controller must raise line least tBEXIT terminate burst mode. serial port available until reset with NCS, even second burst transmission. Avago Technologies recommends reading SROM_ID register verify that download successful. addition, self-test executed, which performs SROM contents reports results register. test initiated writing particular value SROM_Enable register; result placed Data_Out register. those register descriptions more details. Avago Technologies provides data file download; file size 1986 data bytes. chip will ignore additional bytes written SROM_Load register after SROM file. SROM file available download Avago Technologies' website.
exit burst mode tBEXIT writes, text MOSI
frame period
SROM_Enable write address data
SROM_Load write address byte enter burst mode byte byte 1985 address
SCLK tNCS-SCLK >120ns
40µs 10µs
tLOAD
tLOAD 10µs
10µs 100µs
soonest read SROM_ID
Figure SROM download burst mode
Frame Capture
This fast download full array pixel values from single frame. This mode disables navigation overwrites downloaded firmware. hardware reset required restore navigation, firmware must reloaded afterwards required. trigger capture, write Frame_Capture register. next available complete frames (1536 values) will stored memory. data retrieved reading Pixel_Burst register once using normal read method, after which remaining bytes clocked driving SCLK normal rate. byte time must least tLOAD. Pixel_ Burst register read before data ready, will return zeros. read single frame, read total bytes. next bytes will approximately next frame. first pixel first frame (1st read) start-of-frame marker. first pixel second partial frame (901st read) will also have other bytes have zero. bytes Pixel_Burst register read past data (1537 reads data returned will zeros. After download complete, micro-controller must raise line least tBEXIT terminate burst mode. read aborted time raising NCS. Alternatively, frame data also read byte time from Frame_Capture register. register description more information.
exit burst mode tBEXIT frame capture write MOSI address data pixel dump read address enter burst mode SCLK tNCS-SCLK >120ns MISO tCAPTURE tSRAD 50µs
10µs
frame capture address soonest begin again
10µs
tLOAD
10µs
tLOAD
P899 note
Notes: bytes. bytes except pixel both frames which frame marker. Reading beyond pixel will return first pixel second partial frame. tCAPTURE 10µs frame periods. This figure illustrates reading single complete frame pixels. additional pixels from next frame available.
Figure Frame capture burst mode timing
pixel output order related surface shown below.
Cable Xray View Mouse
Positive
Positive
A3080
expanded view surface viewed through lens last output
etc.
first output
Figure Pixel address (surface referenced)
Error detection recovery
ADNS-3080 micro-controller might synchronization events, power supply droops micro-controller firmware flaws. such case, micro-controller should pulse high least ADNS-3080 will reset serial port (but control registers) will prepared beginning transmission after normal transaction delay. Invalid addresses: Writing invalid address will have effect. Reading from invalid address will return zeros. Termination transmission micro-controller sometimes required (for example, suspend interrupt during read operation). accomplish this micro-controller should raise NCS. ADNS-3080 will write register will reset serial port (but control registers) prepared beginning future transmissions after goes low. normal delays between reads writes (tSWW, tswr, tSRAD, tSRAD-mot) still required after aborted transmissions. micro-controller verify success write operations issuing read command same address comparing written data read data. micro-controller verify synchronization serial port periodically reading product inverse product registers. microcontroller read SROM_ID register verify that sensor running downloaded SROM code. similar noise events cause sensor revert native execution. this should happen, pulse RESET reload SROM instructions.
Notes Power-up serial port Reset Circuit
ADNS-3080 does perform internal power self-reset. reset must raised lowered reset chip. This should done every time power applied. During power-up there will period time after power supply high before clocks available. table below shows state various pins during power-up reset when RESET driven high micro-controller. chip into power down (PD) mode lowering input. When mode, oscillator stopped register contents retained. achieve lowest current state, inputs must held externally within 200mV rail, either ground VDD3. chip outputs driven hi-Z during prevent current consumption external load.
Drive Mode
modes operation: Shutter. mode times chip powered except when power down mode pin. shutter mode only during portion frame that light required. LED_MODE Configuration_bits register sets mode.
Power Down Circuit
following table lists states during power down.
State Signal Pins After Valid pullups MISO SCLK MOSI LED_CTRL RESET Before Reset Undefined Hi-Z control functional Driven hi-Z (per NCS) Undefined Undefined Undefined Functional Undefined During Reset Hi-Z control functional Driven hi-Z (per NCS) Ignored Ignored High (externally driven) Ignored After Reset (default) Functional hi-Z (per NCS) Functional Functional High Functional Functional
State Signal Pins During Power Down pullups MISO SCLK MOSI LED_CTRL RESET REFC OSC_IN OSC_OUT hi-Z control functional hi-Z (per NCS) ignored ignored functional (driven externally) VDD3 high After wake from pre-PD state functional pre-PD state hi-Z functional functional high functional functional REFC OSC_IN OSC_OUT
Registers
ADNS-3080 registers accessible serial port. registers used read motion data status well device configuration. Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20-0x3c 0x3d 0x3e 0x3f 0x40 0x50 0x60
Register
Product_ID Revision_ID Motion Delta_X Delta_Y SQUAL Pixel_Sum Maximum_Pixel Reserved Reserved Configuration_bits Extended_Config Data_Out_Lower Data_Out_Upper Shutter_Lower Shutter_Upper Frame_Period_Lower Frame_Period_Upper Motion_Clear Frame_Capture SROM_Enable Reserved Reserved Reserved Reserved Frame_Period_Max_Bound Lower Frame_Period_Max_Bound_Upper Frame_Period_Min_Bound_Lower Frame_Period_Min_Bound_Upper Shutter_Max_Bound_Lower Shutter_Max_Bound_Upper SROM_ID Reserved Observation Reserved Inverse Product Pixel_Burst Motion_Burst SROM_Load
Read/Write
SROM Default Value
0x17 0xNN 0x00 0x00 0x00 0x00 0x00 0x00
0x09 0x00 0x85 0x00 0x00 0x00
0xE0 0x2E 0x7E 0x0E 0x00 0x20 0x00 0x00 0xF8 0x00 0x00
Product_ID
Access: Read Field PID7 PID6
Address: 0x00
Reset Value: 0x17 PID5 PID4 PID3 PID2 PID1 PID0
Data Type: 8-Bit unsigned integer USAGE: This register contains unique identification assigned ADNS-3080. value this register does change; used verify that serial communications link functional.
Revision_ID
Access: Read Field RID7 RID6
Address: 0x01
Reset Value: 0xNN RID5 RID4 RID3 RID2 RID1 RID0
Data Type: 8-Bit unsigned integer. USAGE: This register contains revision. subject change when versions released. NOTE: downloaded SROM firmware revision separate value available SROM_ID register.
Motion
Access: Read Field Reserved
Address: 0x02
Reset Value: 0x00 Reserved Reserved Reserved Reserved
Data Type: field. USAGE: Register 0x02 allows user determine motion occurred since last time read. then user should read registers 0x03 0x04 accumulated motion. also tells motion buffers have overflowed, current resolution setting. Field Name Reserved Reserved Description Motion since last report motion Motion occurred, data ready reading Delta_X Delta_Y registers Reserved Reserved Motion overflow, Delta_Y and/or Delta_X buffer overflowed since last report overflow Overflow occurred Reserved Reserved Reserved Resolution counts inch 1600
Reserved Reserved Reserved
Notes Motion: Reading this register freezes Delta_X Delta_Y register values. Read this register before reading Delta_X Delta_Y registers. Delta_X Delta_Y read before motion register read second time, data Delta_X Delta_Y will lost. Avago Technologies RECOMMENDS that registers 0x02, 0x03 0x04 read sequentially. Motion burst mode also. Internal buffers accumulate more than eight bits motion either internal buffers overflows, then absolute path data lost set. This cleared once some motion been read from Delta_X Delta_Y registers, buffers full scale. Since more data present buffers, cycle reading Motion, Delta_X Delta_Y registers should repeated until motion (MOT) cleared. Until cleared, either Delta_X Delta_Y registers will read either positive negative full scale.
Delta_X
Access: Read Field
Address: 0x03
Reset Value: 0x00
Data Type: Eight complement number. USAGE: movement counts since last report. Absolute value determined resolution. Reading clears register.
Motion -128 -127 +126 +127
Delta_X
Delta_Y
Access: Read Field
Address: 0x04
Reset Value: 0x00
Data Type: Eight complement number. USAGE: movement counts since last report. Absolute value determined resolution. Reading clears register.
Motion -128 -127 +126 +127
Delta_Y
SQUAL
Access: Read Field
Address: 0x05
Reset Value: 0x00
Data Type: Upper bits 10-bit unsigned integer. USAGE: SQUAL (Surface Quality) measure number valid* features visible sensor current frame. following formula find total number valid features. Number features SQUAL register value maximum SQUAL register value 169. Since small changes current frame result changes SQUAL, variations SQUAL when looking surface expected. graph below shows sequentially acquired SQUAL values, while sensor moved slowly over white paper. SQUAL nearly equal zero, there surface below sensor. SQUAL typically maximized when navigation surface optimum distance from imaging lens (the nominal Z-height). Squal Values (White Paper) SQUAL Value
Figure Squal values (white paper)
SQUAL -1.0 -0.8 -0.6
Mean SQUAL (White Paper) 3sigma 3sigma
-0.4
-0.2
Delta from Nominal Focus (mm)
Figure Mean squal (white paper)
Pixel_Sum
Access: Read Field
Address: 0x06
Reset Value: 0x00
Data Type: High bits unsigned 16-bit integer. USAGE: This register used find average pixel value. reports upper byte 16-bit counter which sums pixels current frame. described full divided 256. find average pixel value, following formula: Average Pixel Register Value Register Value/3.51 maximum register value 900/256 truncated integer). minimum pixel value change every frame.
Maximum_Pixel
Access: Read Field
Address: 0x07
Reset Value: 0x00
Data Type: number. USAGE: Maximum Pixel value current frame. Minimum value maximum value maximum pixel value vary with every frame.
Reserved Reserved
Address: 0x08 Address: 0x09
Configuration_bits
Access: Read/Write Field LED_MODE
Address: 0x0a
Reset Value: 0x09 Test Reserved Reserved Reserved Reserved
Data Type: field USAGE: Register 0x0a allows user change configuration sensor. Shown below bits, their default values, optional values. Field Name LED_MODE Description Must always zero Shutter Mode Shutter mode (LED always Shutter mode (LED only when illumination required) System Tests tests perform system tests, output Data_Out_Upper Data_Out_Lower registers. NOTE: test will fail SROM loaded. Perform hardware reset before executing this test. Reload SROM after test completed. NOTE: Since part system test test, SRAM will overwritten with default values when test done. configuration changes from default needed operation, make changes AFTER system test run. system test takes 200ms (@24MHz) complete. NOTE: access Synchronous Serial Port during system test. Resolution counts inch 1600 Reserved Reserved Reserved Reserved
Test
Reserved Reserved Reserved Reserved
Extended_Config
Access: Read/Write Field Busy Reserved
Address: 0x0b
Reset Value: 0x00 Reserved Reserved Serial_NPU NAGC Fixed_FR Reserved
Data Type: field USAGE: Register 0x0b allows user change configuration sensor. Shown below bits, their default values, optional values. Field Name Busy Description Read-only bit. Indicates safe write more following registers: Frame_Period_Max_Bound_Upper Lower Frame_Period_Min_Bound_Upper Lower Shutter_Max_Bound_Upper Lower After writing Frame_Period_Max_Bound_Upper register, least frames must pass before writing again above registers. This used lieu timer since actual frame rate known when running auto mode. writing registers allowed write registers Reserved Reserved Reserved Reserved Disable serial port pull-up current sources current sources yes, current sources Disable AGC. Shutter will value Shutter_Max_Bound registers. active yes, disabled Fixed frame rate (disable automatic frame rate control). When this set, frame rate will determined value Frame_Period_Max_Bound registers. automatic frame rate fixed frame rate
Reserved Reserved Reserved Reserved Serial_NPU
NAGC
Fixed_FR
Data_Out_Lower
Access: Read Field
Address: 0x0c
Reset Value: Undefined
Data_Out_Upper
Access: Read Field DO15 DO14
Address: 0x0d
Reset Value: Undefined DO13 DO12 DO11 DO10
Data Type: Sixteen word. USAGE: Data these registers come from system self test SROM test. data read 0x0d, 0x0d first, then 0x0c. Data_Out_Upper System test results: SROM Test Result: 0x1B 0xBE Data_Out_Lower 0xBF 0xEF
System Test: This test initiated Configuration_Bits register. performs several tests verify that hardware functioning correctly. Perform hardware reset just prior running test. SROM contents register settings will lost. SROM Test: Performs SROM contents. test initiated writing particular value SROM_Enable register.
Shutter_Lower
Access: Read Field
Address: 0x0e
Reset Value: 0x85
Shutter_Upper
Access: Read Field
Address: 0x0f
Reset Value: 0x00
Data Type: Sixteen unsigned integer. USAGE: Units clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should read consecutively. shutter adjusted keep average maximum pixel values within normal operating ranges. shutter value checked automatically adjusted value needed every frame when operating default mode. When shutter adjusts, changes 1/16 current value. shutter value manually setting mode Disable using Extended_Config register writing Shutter_Maximum_Bound registers. Because automatic frame rate feature related shutter value. also appropriate enable Fixed Frame Rate mode using Extended_Config register. Shown below graph sequentially acquired shutter values, while sensor moved slowly over white paper.
Mean Shutter (White Paper) Shutter value (counts) -1.0 -0.8 -0.6 -0.4 -0.2 Distance from Nominal Focus (mm)
Figure Mean shutter (white paper)
3sigma 3sigma
maximum value shutter dependent upon setting Shutter_Max_Bound_ Upper Shutter_Max_Bound_Lower registers.
Frame_Period_Lower
Access: Read Field
Address: 0x10
Reset Value: Undefined
Frame_Period_Upper
Access: Read Field FP15 FP14
Address: 0x11
Reset Value: Undefined FP13 FP12 FP11 FP10
Data Type: Sixteen unsigned integer. USAGE: Read these registers determine current frame period calculate frame rate. Units clock cycles. formula Frame Rate Clock Frequency/Register value read from registers, read Frame_Period_Upper first followed Frame_Period Lower. frame rate manually, disable automatic frame rate mode Extended_Config register write desired count value Frame_Period_Maximum_Bound registers. following table lists some Frame_Period values popular frame rates with 24MHz clock. Frames/second 6469 5000 3000 2000 Counts Decimal 3,710 4,800 8,000 12,000 OE7E 12C0 1F40 2EE0 Upper Frame_Period Lower
Motion_Clear
Access: Write Data Type: Any.
Address: 0x12
Reset Value: Undefined
USAGE: Writing value this register will cause Delta_X, Delta_Y, internal motion registers cleared. this fast reset motion counters zero without resetting entire chip.
Frame_Capture
Access: Read/Write Field
Address: 0x13
Reset Value: 0x00
Data Type: field USAGE: Writing 0x83 this register will cause next available complete frames pixel values stored SROM RAM. Writing this register required before using Frame Capture burst mode read pixel values (see Synchronous Serial Port section more details). Writing this register will stop navigation cause firmware loaded SROM overwritten. hardware reset required restore navigation, firmware must reloaded using SROM Download burst method. This register also used read frame capture data. same data available reading Pixel_Burst register using burst mode available reading this register normal fashion. data pointer automatically incremented after each read 1536 pixel values frames) obtained reading this register 1536 times row. Both methods share same pointer such that reading pixel values from this register will increment pointer causing subsequent reads from Pixel_Burst register (without initiating frame dump) start current pointer location. This register will return zeros read before frame capture data ready. Frame Capture description Synchronous Serial Port section more information. This register will retain last value written. Reads will return zero frame capture data.
SROM_Enable
Access: Write Field
Address: 0x14
Reset Value: 0x00
Data Type: 8-bit number. USAGE: Write this register start either SROM download SROM test. Write 0x18 this register before downloading SROM firmware SROM_Load register. download will successful unless this register contains correct value. Write 0xA1 start SROM test. Wait plus frame period then read result from Data_Out_Lower Data_Out_Upper registers. Navigation halted port should used during this test.
Reserved
Address: 0x15 0x18
Frame_Period_Max_Bound_Lower
Access: Read/Write Field FBm7 FBm6
Address: 0x19
Reset Value: 0xE0 FBm5 FBm4 FBm3 FBm2 FBm1 FBm0
Frame_Period_Max_Bound_Upper
Access: Read/Write Field FBm15 FBm14
Address: 0x1A
Reset Value: 0x2E FBm13 FBm12 FBm11 FBm10 FBm9 FBm8
Data Type: 16-bit unsigned integer. USAGE: This value sets maximum frame period (the MINIMUM frame rate) which selected automatic frame rate control, sets actual frame period when operating manual mode. Units clock cycles. formula Frame Rate Clock Frequency Register value read from registers, read Upper first followed Lower. write registers, write Lower first, followed Upper. frame rate manually, disable automatic frame rate mode Extended_Config register write desired count value these registers. Writing Frame_Period_Max_Bound_Upper Lower registers also activates values following registers: Frame_Period_Max_Bound_Upper Lower Frame_Period_Min_Bound_Upper Lower Shutter_Max_Bound_Upper Lower data written these registers will saved will take effect until write Frame_Period_Max_ Bound_Upper Lower complete. After writing this register, complete frame times required implement settings. Writing above registers before implementation complete chip into undefined state requiring reset. "Busy" Extended_Config register used lieu timer determine when safe write. Extended_Config register more details. following table lists some Frame_Period values popular frame rates (clock rate 24MHz). addition, three bound registers must also follow this rule when non-default values: Frame_Period_Max_Bound Frame_Period_Min_Bound Shutter_Max_Bound. Frames/second 6469 5000 3000 2000 Counts Decimal 3,710 4,800 8,000 12,000 OE7E 12C0 1F40 2EE0 Upper Frame_Period Lower
Frame_Period_Min_Bound_Lower
Access: Read/Write
Address: 0x1B
Reset Value: 0xAC (before SROM download) 0x7E (after SROM download)
Field
FBm7
FBm6
FBm5
FBm4
FBm3
FBm2
FBm1
FBm0
Frame_Period_Min_Bound_Upper
Access: Read/Write Field FBm15 FBm14
Address: 0x1C
Reset Value: 0x0D (before SROM download) 0x0E (after SROM download) FBm13 FBm12 FBm11 FBm10 FBm9 FBm8
Data Type: 16-bit unsigned integer. USAGE: This value sets minimum frame period (the MAXIMUM frame rate) that selected automatic frame rate control. Units clock cycles. formula Frame Rate Clock Rate Register value read from registers, read Upper first followed Lower. write registers, write Lower first, followed Upper, then execute write Frame_Period_Max_Bound_Upper Lower registers. minimum allowed write value 0x7E0E; maximum 0xFFFF. Reading this register will return most recent value that written However, value will take effect only after write Frame_Period_Max_Bound_Upper Lower registers. After writing Frame_Period_Max_ Bound_Upper, wait least frame times before writing Frame_Period_Min_Bound_Upper Lower again. "Busy" Extended_Config register used lieu timer determine when safe write. Extended_Config register more details. addition, three bound registers must also follow this rule when non-default values: Frame_Period_Max_Bound Frame_Period_Min_Bound Shutter_Max_Bound.
Shutter_Max_Bound_Lower
Access: Read/Write Field
Address: 0x1D
Reset Value: 0x8C (before SROM download) 0x00 (after SROM download)
Shutter_Max_Bound_Upper
Access: Read/Write Field SB15 SB14
Address: 0x1E
Reset Value: 0x20 SB13 SB12 SB11 SB10
Data Type: 16-bit unsigned integer. USAGE: This value sets maximum allowable shutter value when operating automatic mode. Units clock cycles. Since automatic frame rate function based shutter value, value these registers limit range frame rate control. read from registers, read Upper first followed Lower. write registers, write Lower first, followed Upper, then execute write Frame_Period_Max_Bound_Upper Lower registers. shutter manually, disable Extended_Config register write desired value these registers. Reading this register will return most recent value that written However, value will take effect only after write Frame_Period_Max_Bound_Upper Lower registers. After writing Frame_Period_Max_Bound_ Upper, wait least frame times before writing Shutter_Max_Bound_Upper Lower again. "Busy" Extended_Config register used lieu timer determine when safe write. Extended_Config register more details. addition, three bound registers must also follow this rule when non-default values: Frame_Period_Max_Bound Frame_Period_Min_Bound Shutter_Max_Bound.
SROM_ID
Access: Read Field
Address: 0x1F
Reset Value: 0x00
Data Type:8-Bit unsigned integer. USAGE: Contains revision downloaded Shadow firmware. firmware been successfully downloaded chip operating SROM, this register will contain SROM firmware revision, otherwise will contain 0x00. Note: hardware revision available reading Revision_ID register (register 0x01).
Reserved
Address: 0x20 0x3C
Observation
Access: Read/Write Field Reserved
Address: 0x3D
Reset Value: 0x00 Reserved Reserved Reserved
Data Type: field USAGE: Each some process action regular intervals, when event occurs. user must clear register writing 0x00, wait appropriate delay, read register. active processes will have their corresponding bit(s). This register used part recovery scheme detect problem caused EFT/B ESD. Field Name Reserved Reserved Reserved Reserved Description set, chip running SROM code Reserved pulse detected Reserved Reserved Reserved once frame once frame
Reserved
Address: 0x3E
Inverse_Product_ID
Access: Read Field NPID7 NPID6
Address: 0x3F
Reset Value: 0xF8 NPID4 NPID3 NPID2 NPID1 NPID0
NPID5
Data Type: Inverse 8-Bit unsigned integer USAGE: This value inverse Product_ID, located inverse address. used test port.
Pixel_Burst Access: Read
Data Type: Eight unsigned integer Field
Address: 0x40 Reset Value: 0x00
USAGE: Pixel_Burst register used high-speed access pixel values from complete frame. Synchronous Serial Port section details.
Motion_Burst
Access: Read Field
Address: 0x50
Reset Value: 0x00
Data Type: Various, depending data USAGE: Motion_Burst register used high-speed access Motion, Delta_X, Delta_Y, SQUAL, Shutter_ Upper, Shutter_Lower Maximum_Pixel registers. Synchronous Serial Port section details.
SROM_Load
Access: Write Data Type: Eight unsigned integer
Address:
Rset Value:
USAGE: SROM_Load register used high-speed programming ADNS-3080 from external SROM microcontroller. Synchronous Serial Port section details.
Read Also
ADNS-3080 Product Overview ADNK-3080 Sample
Ordering Information
Specify part number follows: ADNS-3080 Sensor plastic optical package, tube. ADNB-3081 Sensor ADNS-2120 round lens bundle kit, 1000 incremental ADNB-3082 Sensor ADNS-2120-001 trim lens bundle kit, 1000 incremental ADNS-2120 Round Optical Mouse Lens ADNS-2120-001 Trim Optical Mouse Lens ADNS-2220 Assembly Clip (Clear) ADNS-2220-001 Assembly Clip (Black) HLMP-ED80-XX000
Relevant Application Notes
Application Note 5035* Application Note 5034* Application Note 5036*
application notes content applicable ADNS-3080 well.
product information complete list distributors, please site: www.avagotech.com Avago, Avago Technologies, logo trademarks Avago Technologies, Limited United States other countries. Data subject change. Copyright 2006 Avago Technologies Limited. rights reserved. Obsoletes 5989-3422EN AV02-0366EN April 2007

High-Performance Optical Mouse Sensor ADNS-3080 high performance

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