Chip Size: 2730 1300 (108 51.6 mils) Chip Size Tolerance: (±0.4 mils)

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Chip Size: 2730 1300 (108 51.6 mils) Chip Size Tolerance: (±0.4 mils)

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AMMC-5033 17.7 Power Amplifier
Chip Size: 2730 1300 (108 51.6 mils) Chip Size Tolerance: (±0.4 mils) Chip Thickness: mils) Dimensions: (2.95 mils)
Avago's AMMC-5033 MMIC power amplifier designed wireless transmitters that operate within 17.7 range. GHz, provides output power (P-1dB) small- signal gain from small easy-to-use device. device input output matching circuitry environments. AMMC- 5033 also integrates temperature compensated power detection circuit that enables power detection GHz. improved reliability moisture protection, passivated active areas.
Features
Wide frequency range: 17.7 High power: P-1dB High gain: Return loss: Input: Output: Integrated power detector
Applications
Designed transmitters that operate various frequency bands between 17.7 GHz. driven AMMC-5040 (20-40 GHz) AMMC-5618 (6-20 GHz) MMIC amplifiers, increasing power handling capability transmitters requiring linear operation.
AMMC-5033 Absolute Maximum Ratings[1]
Symbol
Vd1,2 Vg1, Bias Tstg Tmax
Parameters/Conditions
Positive Drain Voltage Gate Supply Voltage Applied Detector Bias (Optional) First Stage Drain Current Input Power Operating Channel Temp. Storage Case Temp. Maximum Assembly Temp. max)
Units
Min. Max.
+150 +150 +300
Second Stage Drain Current
Note: Operation excess these conditions result permanent damage this device.
Note: These devices sensitive. following precautions strongly recommended: Ensure that approved carrier used when dice transported from destination another. Personal grounding worn times when handling these devices.
AMMC-5033 Specifications/Physical Properties[1]
Symbol DETBias c1(ch-bs) c2(ch-bs) Parameters Test Conditions First Stage Drain Supply Current (Vd1 Open, Typical) Second Stage Drain Supply Current (Vd2 Open, Typical) Gate Supply Operating Voltage (Id1(Q) Id2(Q) (mA)) Detector Bias Voltage (Optional) First Stage Thermal Resistance[2] (Backside Temperature, 25°C) Second Stage Thermal Resistance[2, (Backside Temperature, 25°C) Units °C/W °C/W -0.75 Min. Typ. -0.6 -0.4 Max.
Notes: Backside temperature 25°C unless otherwise noted. Channel-to-backside Thermal Resistance (ch-b) 42°C/W Tchannel (Tc) 150°C measured using infrared microscopy. Thermal Resistance backside temperature (Tb) 25°C calculated from measured data. Channel-to-backside Thermal Resistance (ch-b) 24°C/W Tchannel (Tc) 150°C measured using infrared microscopy. Thermal Resistance backside temperature (Tb) 25°C calculated from measured data.
AMMC-5033 Specifications[4,
25°C, Id1(Q) Id2(Q)
Lower Band Specifications (17.7 GHz) Unit
Parameters Symbol Gain P-1dB P-3dB OIP3 Test Condition Small-Signal Gain Output Power Gain Compression[6] Output Power Gain Compression[6]
Band Upper Band Specifications Specifications 26.5 GHz) (26.5 GHz) Max. Min. 17.5 25.5 Typ. 29.5 Max. Min. 16.5 Typ. 18.5 26.5 Max.
Min. 23.5
Typ.
Output Third Order Intercept Point;[6]; MHz; Input Return Loss[5] Output Return Loss
RLin RLout Isolation
11.5
13.5
Min. Reverse Isolation
Notes: Data measured wafer form 25°C. 100% on-wafer test done frequency 17.7, 26.5 GHz. 100% on-wafer test frequency 17.7, 26.5 GHz.
AMMC-5033 Typical Performances
25°C, Zout
(dB)
(dB) (dB)
RETURN LOSS (dB)
(dB) (dB)
(dB)
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure Gain reverse isolation
Figure Return loss (input output)
(dBm), (dBm) NOISE FIGURE (dB)
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure Output power gain compression
Figure Noise figure
(dBm)
FREQUENCY (GHz)
Figure Output order intercept point
AMMC-5033 Typical Performance Curves (Over Temperature Voltage)
0.10
0.08 (DET_R)-(DET_O) (DET_R)-(DET_O)
GAIN (dB)
0.06 0.01 0.04
0.02 0.001 Output Power (dBm)
5V/0.5A 4V/0.5 3.5V/0.5A
0.00
FREQUENCY (GHz)
Figure Linear detector voltage output power, freq. GHz, Det_B
Figure Gain voltage, (constant)
(dB)
S11_85 S11_25 S11_-40 S22_85 S22_25 S22_-40
(dBm)
5V/0.5A 4V/0.5 3.5V/0.5A
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure Output power gain compression voltage, (constant)
Figure Return-loss with temperature
Pout (dBm),
Pout
1200 1000 (mA)
(dBm)
FREQUENCY (GHz)
(dBm)
Figure Output power gain compression temperature
Figure Output power, PAE, total drain. Current input power
(dB)
FREQUENCY (GHz)
Figure Gain with temperature
Typical Scattering Parameters[1]
25°C, Zout
Freq [GHz] -10.7 -11.0 -11.4 -12.1 -15.3 -12.2 -14.0 -15.3 -17.6 -19.4 -18.6 -19.7 -24.5 -27.4 -30.6 -24.1 -21.2 -18.0 -15.5 -14.0 -13.3 -13.0 -12.9 -12.9 -13.0 -13.3 -13.9 -14.9 -15.8 -17.0 -19.1 -21.0 -20.5 -17.0 -14.9 -12.8 -10.7 -9.8 -9.1 -8.5 -8.6 -8.6 -8.0 -7.6 -6.0 -4.4 -3.5 -2.7 -1.8 -1.7 0.29 0.28 0.27 0.25 0.17 0.25 0.17 0.13 0.11 0.12 0.06 0.04 0.03 0.06 0.09 0.13 0.17 0.22 0.22 0.23 0.23 0.23 0.22 0.18 0.16 0.14 0.11 0.09 0.14 0.18 0.23 0.29 0.33 0.35 0.38 0.37 0.37 0.42 0.67 0.74 0.81 0.83 Phase -148 -121 -116 -116 -123 -133 -142 -151 -157 -163 -172 -178 -102 -111 -118 -51.1 -70.1 -46.6 -37.3 -22.6 -20.4 -20.5 -25.4 -33.1 -18.9 -18.2 -29.0 -15.4 12.7 22.6 28.8 28.7 26.4 24.7 23.4 22.4 21.5 20.8 20.3 19.9 19.7 19.5 19.4 19.3 19.1 18.6 18.1 17.2 16.2 14.6 12.1 -3.5 -9.2 -16.1 -23.2 -32.0 -31.7 -40.7 -46.2 -58.4 -46.4 -44.2 0.003 0.005 0.014 0.074 0.096 0.095 0.053 0.022 0.113 0.123 0.035 0.169 1.107 4.316 13.52 27.62 27.25 20.92 17.18 14.82 13.2 11.9 10.97 10.36 9.895 9.691 9.457 9.384 9.247 8.972 8.519 7.989 7.281 6.44 5.378 4.014 2.42 1.238 0.671 0.347 0.157 0.069 0.025 0.026 0.009 0.005 0.001 0.005 0.006 Phase -163 -103 -103 -151 -141 -104 -171 -134 -172 -148 -164 -95.1 -83.1 -74.5 -74.5 -80.3 -80.1 -80.3 -74.1 -81.4 -81.4 -81.3 -74.6 -81.3 -81.2 -74.6 -76.2 -74.7 -64.8 -64.3 -64.4 -69.7 -58.2 -63.3 -61.0 -66.1 -64.3 -63.1 -60.2 -61.9 -56.3 -57.7 -58.2 -56.0 -57.7 -59.0 -60.8 -62.9 -57.1 -61.0 -60.9 -67.6 -59.2 -61.0 -62.0 -64.6 -61.1 -102.4 -60.1 -59.2 -61.9 1.77E-05 6.97E-05 1.89E-04 1.88E-04 9.66E-05 9.90E-05 9.68E-05 1.97E-04 8.52E-05 8.56E-05 8.59E-05 1.86E-04 8.65E-05 8.70E-05 1.86E-04 1.55E-04 1.84E-04 5.75E-04 6.08E-04 6.03E-04 3.27E-04 1.23E-03 6.80E-04 8.96E-04 4.97E-04 6.09E-04 7.00E-04 9.75E-04 8.00E-04 1.53E-03 1.31E-03 1.23E-03 1.59E-03 1.31E-03 1.12E-03 9.14E-04 7.13E-04 1.40E-03 8.94E-04 9.04E-04 4.15E-04 1.09E-03 8.95E-04 7.96E-04 5.91E-04 8.84E-04 7.57E-06 9.93E-04 1.10E-03 8.00E-04 Phase -126 -162 -180 -164 -123 -171 -0.5 -0.7 -1.2 -2.2 -2.4 -2.8 -4.0 -4.2 -3.5 -3.8 -4.4 -5.2 -6.3 -7.9 -10.1 -13.3 -20.5 -20.0 -19.4 -19.1 -18.7 -18.5 -19.0 -20.7 -21.8 -22.9 -22.9 -22.6 -22.1 -22.4 -24.9 -31.9 -31.4 -24.4 -20.0 -16.2 -13.1 -11.1 -10.1 -9.8 -9.7 -10.1 -10.6 -11.4 -12.3 -13.2 -14.2 -14.8 -14.7 -14.9 0.95 0.92 0.87 0.78 0.76 0.73 0.63 0.62 0.67 0.64 0.55 0.48 0.41 0.31 0.22 0.09 0.11 0.11 0.12 0.12 0.11 0.09 0.08 0.07 0.07 0.07 0.08 0.08 0.06 0.03 0.03 0.06 0.16 0.22 0.28 0.31 0.33 0.33 0.31 0.29 0.27 0.24 0.22 0.18 0.18 0.18 Phase -112 -130 -146 -150 -166 -148 -141 -145 -152 -167
Note: Data obtained from on-wafer measurements.
Biasing Operation
recommended quiescent bias condition optimum efficiency, performance, reliability volts volts with connection Vg1). This bias arrangement results default quiescent drain currents single gate supply connected will bias gain stages. operation with both volts desired, additional wire bond connection from external bypass chip capacitor (shorting Vgg) will balance current each gain stage. Vg1) adjusted Muting accomplished setting and/or pinchoff voltage optional output power detector network also provided. Detector sensitivity adjusted biasing diodes with typically volts applied Det- bias terminal. Simply connecting Det-Bias supply convenient method biasing this detector network. differential voltage between Det-Ref Det-Out pads correlated with power emerging from output port. detected voltage given (Vref Vdet) Vofs Where Vref voltage DET_REF port, Vdet voltage DET_OUT port, Vofs zero-input-power offset voltage. There three methods calculate Vofs: Vofs measured before each detector measurement removing switching power source measuring Vref Vdet This method gives error temperature drift less than 0.0002 dB/°C. Vofs measured single reference temperature. drift error will less than 0.25 Vofs either characterized over temperature stored lookup table, measured temperatures linear used calculate Vofs temperature. This method gives error close method With reference Figure input coupled shunt resistor blocked input first stage. output blocked output second stage, however, coupled detector bias circuit. output detector biased using on-chip optional Det-Bias network, external blocking capacitor required Output port. ground wires needed since ground connections made with plated through-holes backside device.
Assembly Techniques
backside AMMC- 5033 chip ground. microstripline applications, chip should attached directly ground plane (e.g., circuit carrier heatsink) using electrically conductive epoxy.[1] best performance, topside MMIC should brought same height circuit surrounding This accomplished mounting gold plated metal shim (same length width MMIC) under chip, which correct thickness make chip adjacent circuit coplanar. amount epoxy used chip shim attachment should just enough provide thin fillet around bottom perimeter chip shim. ground plane should free residue that jeopardize electrical mechanical attachment. location bond pads shown Figure Note that input output ports Ground-Signal-Ground configuration. connections should kept short reasonable minimize performance degradation undesirable series inductance. single bond wire sufficient signal connections, however double-bonding with gold wire gold mesh[2] recommended best performance, especially near high frequency range. Thermosonic wedge bonding preferred method wire attachment bond pads. Gold mesh attached using round tracking tool tool force approximately grams with ultrasonic power roughly duration guided wedge ultrasonic power level used wire. recommended wire bond stage temperature 2°C. Caution should taken exceed Absolute Maximum Rating assembly temperature time. chip thick should handled with care. This MMIC exposed bridges surface should handled edges with custom collet pick with vacuum center.) This MMIC also static sensitive handling precautions should taken.
Notes: Ablebond 84-1 silver epoxy recommended. Buckbee-Mears Corporation, Paul, 800-262-3824
DET.
Input
BIAS Ref_ 1000
Figure AMMC-5033 schematic
Figure AMMC-5033 bonding locations, dimensions microns
VD1,
VD2,
RFInput
RFOutput
Notes: capacitors gate drain lines shown required.
AMMC-5033
Figure AMMC-5033 assembly diagram
Ordering Information:
AMMC-5033-W10 devices tray AMMC-5033-W50 devices tray
product information complete list distributors, please website:
www.avagotech.com
Avago, Avago Technologies, logo trademarks Avago Technologies Limited United States other countries. Data subject change. Copyright 2007 Avago Technologies Limited. rights reserved. Obsoletes 5989-3935EN AV02-0682EN September 2007

Chip Size: 2730 1300 (108 51.6 mils) Chip Size Tolerance: (±0.4 mils)

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