Ultra-Precision Gray Code Absolute Encoder Module encoder consist
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AEAS 7500
Ultra-Precision Gray Code Absolute Encoder Module
encoder consists signal photo diode channels monitor photo diode channel used optical reading rotary linear code carriers (i.e. discs scales). photodiodes accompanied with precision amplifiers plus additional circuitry. monitor channel used drive constant current source highly collimated illumination system.
Functional Description Background
signal channels precision defining signals (A0, A09), which electrical shifted sine, cosine signals. These signals conditioned compensated offset gain errors. After conditioning they on-chip interpolated computed combined absolute Gray code, together with signal channels A1-A11. analog (A1-A11) channels, which directly digitized precision comparators with hysteresis tracking. digitized signals called D1-D11. internal correction synchronization module allows composition true gray code merging data bits still keeping code monotonic. There Gray code correction feature this encoder. This Gray code correction disabled/enabled KORR. gain offset conditioning value sine cosine signals preloaded on-chip factory. This will minimize mechanical sensor misalignment error.
Features
Sine/Cosine true differential outputs with 1024 periods unit alignment Integrated highly collimated illumination system digital tracks plus sin/cos tracks generate precise Gray code Ultra fast, cycle serial data output word equals 16MHz bits functionable 12000 RPM, 1000RPM inverted changing counting direction Monitor track tracking light level Watch with alarm output LERR operating temperature
Benefits
battery capacitor required position detection during power failure Immediate position detection power
Applications
Rotary application bits 360° absolute position Cost effective solution direct integration into systems Linear positioning system
Signal-channels A1-A11
photocurrent photodiodes into transimpedance amplifier. analog output amplifier voltage swing of(dark/light) about 1.3V. Every output transformed precision comparators into digital signals (D1-D11). threshold VDD/2(=Analog-reference), regulated monitor channel.
gray code Correction (Pin KORR)
This function block synchronizes switching points gray code digital signals with (digitized signal A09). accuracy complete gray defined precision signals D0/D09. these signals generated gain offset conditioned analog signals A09, they very precise. This Gray code correction only works full (4096 steps revolution). correction excess interpolated bits Gray code. Gray code correction switched putting KORR =1(on) =0(off
Monitor Channel with Control pins LEDR LERR
analog output signal monitor channel regulated current. external bipolar transistor(to connected user) sets this level VDD/2 (control voltage LEDR). Thus signal swing each output symmetrical VDD/2(=Analog-reference) error LERR triggered internal bipolar transistor larger than VDD/2
MSBINV DOUT pins
serial interface consists shift register. most MSBINV.
Signals Channels with signal conditioning cali- significant bit, MSB(D11) will always sent first DOUT. inverted (change code direction) using bration
These channels give sine cosine wave, which degree phase shifted. These signals have amplitudes, which almost constant current monitoring. amplifier mismatch mechanical misalignment signals have gain offset errors. These errors eliminated adaptive signal conditioning circuitry. conditioning values on-chip preprogrammed factory. analog output signals supplied true-differential voltage with peak peak value 2.0V pins A09P, A09N, A0P, A0N.
pins
Serial input allows configuration ring register multiple transmissions cascading more encoders. input shift register that shifts data DOUT. controls shift register, switch between load shift(0) mode. Under load mode, DOUT will give logic MSB, i.e. D11. Under shift mode (0), coupled with SCL, register will clocked, gives serial word output bit. clock frequency MHz, transmission full word done within Valid data DOUT should read when clock low. Please refer timing diagram Figure
Interpolator Channels A0,A09
interpolator generates digital signals D0,D09 D-4. interpolated signals extend Gray code signals D11.D0 form Gray code. digitized from A09. channels A0-A11 have very high dynamic bandwidth, which allows real time monotone 12Bit Gray code 12000 RPM. interpolated Gray code used 1000RPM only. more than 1000RPM, only Gray code from side used.
Package Dimensions
Radial Tangential+
Notes: Angle Projection Dimensions millimeters Unless specified otherwise, tolerances are: ±0.5; XX.X ±0.2; XX.XX ±0.03 Note: Codewheel readhead mounting tolerances radial, tangential are: Radial Tangential 40um 50um Figure Package Dimensions
Device Selection Guide
Part Number
AEAS-7500-1GSG0
Resolution
Operating Temperature (°C)
Output
1024 Sine/Cosine Incremental
Output Code
Gray Code
Supply Voltage
+4.5 +5.5
Notes: other options absolute encoder module, please refer factory.
Absolute Maximum Ratings
Parameter
Supply Voltage Input Voltage Output Voltage Moisture Level (Non-Condensing) Operating Temperature Storage Temperature
Symbol
Vout
Limits
-0.3 -0.3 +0.3 -0.5 +0.3
Units
Notes: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Recommended Operating Condition
Values Parameter
Supply Voltage Operating Temperature Input High Level Input Level
Symbol
Min.
0.7*VD
Typ.
Max.
+5.5 0.3*VD
Units
Notes
Notes: Voltage ripple supply voltage, Vripple, should within 100mVpp less improved accuracy.
Electrical Characteristics
Electrical Characteristics over Recommended Operating Range, typical TA=25 Values Parameter
Total Operating Current Digital Input-Pull Down Current Digital Input-Pull Current Digital Ouput-H-Level Digital Ouput-L-Level Clock Frequency Duty Cycle Clock Accuracy within revolution1,
Symbol
Itotal fSCL
Condition
Typ.
Units
-0.5
H/(L+H) fSCL 5MHz Vripple <50mVpp
Signal frequency
fA0, fA09
Notes: accuracy will also depend mechanical precision shaft, bearings, etc. AEAS-7500 detached encoder different from AEAS-7000 series, which modular, where final testing, programming assembly take place customer facility, final accuracies encoder cannot guaranteed Avago. Accuracy would influenced installation control bearing shaft type being used. Other test conditions determine accuracy briefly listed follows: nominal radial, tangential position dual preloaded bearing with absolute assembly total runout exceeding 0.01 Both VDDA filters placed more than 20mm from header pins
Name
KORR PROBE_ON STCAL
Function
Notes
Digital-input Digital-Input Digital Input Positive edge Digital Input Positive edge Negative edge Digital-Input Digital Input Digital-Input Digital-Input Positive Edge Digital Output Digital Output Digital Output Supply Voltage Ground supply voltage Analog output Ground supply voltage Analog Output Analog output Supply Voltage Analog Output Digital Output Analog Output
Gray Code Correction Active unnecessarily
CMOS, internal CMOS, internal CMOS, internal CMOS, internal
MSBINV DOUT DPROBE A09P A09N VDDA LERR LEDR
Most Significant Bit, MSB, inverted Shift Register Input. cascading only. Shift-register Shift (=0) Load(=1) Control Shift-register Clock Shift-Register Data (MSB first) signal signal Supply Digital supply analog/digital positive(+True diff.) supply analog/digital positive(+True diff.) negative(-True diff.) Supply Analog negative True dif) IR-LED Current Limit Signal connected user base transistor with series resistor Figure
CMOS, internal CMOS, internal CMOS, internal CMOS, internal CMOSS, CMOS, CMOS,
CMOS, analog
CMOS, analog CMOS, analog
CMOS, analog CMOS, CMOS, analog
Notes: Internal pu/pd internal pull-up (typ. 50uA)/ pull-down (typ. 10uA) CMOS-transistor-Rs
Figure Pinout Configuration
Module Dimensions
Notes: Angle Projection Dimensions millimeters Module spatial misalignment tolerance absolute limits follows: (Refer Figure directional indication) Radial limit from nominal Tangential limit from nominal module placement height direction long contact with codewheel) Tilting plane along Center line (CL) degree Figure Module Dimensions
Figure Timing Diagram
Using AEAS-7500
IMPORTANT NOTE: RC-filter combination, especially VDDA, used filter spikes transients strongly recommended. advised that tantalum caps close VDDA pins possible. recommended ground PROBE_ON during normal operation. Leave unconnected. A09N negative cosine sine waves, negative versions A09P A0P. used check signal. digitized signal DPROBE used check D09, digitized signal A09. Recommended used testing purpose only. KORR Gray Code correction bits resolution only. MSBINV user change between counting counting down given rotating direction. MSB(D11) will always sent DOUT first LEDR internal voltage monitor which linked Monitor channel. should connected base transistor series resistor control brightness photodiodes' need. (Refer Figure LERR will high when light output perceived photo diode array low, current under overdrive mode. This indicator when light intensity critical stage affecting performance encoder. caused either contamination codewheel degradation.
Operation
After powering unit using =+5V connecting ground, trigger input pins using timing diagram (Figure control internal shift register. NSL=1 load mode while NSL=0 shift mode shift register. When NSL=0 combined with clock pulses, serial Gray code will shifted DOUT every clock pulse. Valid data DOUT should sampled point clock pulses. serial gray code tapped from DOUT, most significant (D11) first. rate 16bit Gray code serial transfer rate dependent clock frequency. faster clock, faster transfer rate. maximum clock rate AEAS-7500 take MHz, which means entire Gray code serially transferred Whenever high (load mode), DOUT will have logic (D11). After goes low, number bits being transferred will depend number clock pulses given SCL. default clock pulses Gray code.
Analog-Outputs
A09P A09N 100µ Tantal BC86B VDDA Tantal
(+V)
(C's optional)
DOUT MSBINV
DPROBE DOUT MSBINV STCAL STCAL PROBE_ON
-LED
LEDR LERR
PROBE_ON KORR
Configuration Probe Control
KORR LERR
Figure Schematic using AEAS-7500
Application-Logic
Ordering Information
AEAS-7500-1GSG0 Single-turn, +85oC, detached encoder set, serial,
Note: alignment process, please refer Avago Technologies' website application note contact factory.
product information complete list distributors, please site: www.avagotech.com Avago, Avago Technologies, logo trademarks Avago Technologies, Pte. United States other countries. Data subject change. Copyright 2006 Avago Technologies Pte. rights reserved. 5989-3095EN March 2006
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