Miniature Surface-Mount Digital Color Sensor Module ADJD-S37-QR99
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ADJD-S371-QR999
Miniature Surface-Mount Digital Color Sensor Module
ADJD-S37-QR999 cost effective, channel digital output RGB+CLEAR sensor miniature surface-mount package with mere size module with combination White CMOS with integrated filters Clear channel analog-to-digital converter front end. ideal applications like color detection, measurement, illumination sensing display backlight adjustment such colors, contrast brightness enhancement mobile devices which demand higher package integration, small footprint power consumption. 2-wire serial output allows direct interface microcontroller other logic control further signal processing without additional component such analog digital converter. With wide sensing range 00,000 lux, sensor used many applications with different light levels adjusting gain setting. Additional features include selectable sleep mode minimize current consumption when sensor use.
Features
Four channel integrated light digital converter (Red, Green, Blue Clear). digital output resolution Independent gain selection each channel Wide sensitivity coverage: klux klux wire serial communication Built oscillator/selectable external clock power mode (sleep mode) Small module Integrated solution with sensor, separator module ease design Lead free
Applications
Mobile appliances Consumer appliances
Functional Block Diagram
CLEAR ANODE SAMPLING BLOCK DIGITAL OUTPUT
Electrical Specifications Absolute Maximum Ratings (Sensor)
Parameter Storage Temperature Digital Supply Voltage, DVDD DVSS Analog Supply Voltage, AVDD AVSS Input Voltage Human Body Model Rating Symbol TSTG_ABS VDDD_ABS VDDA_ABS VIN_ABS ESDHBM_ABS Minimum Maximum Units pins pins, human body model JESD22-A4 Notes
Absolute Maximum Ratings 25°C (LED)
Parameter Forward Current Power Dissipation Reverse Voltage Operating Temperature Range Storage Temperature Range Symbol Minimum Maximum Units
Recommended Operating Conditions (Sensor)
Parameter Free Operating Temperature Digital Supply Voltage, DVDD DVSS Analog Supply Voltage, AVDD AVSS Output Current Load High Output Current Load Input Voltage High Level[4] Input Voltage Level[4] Symbol VDDD VDDA VDDD Minimum Typical Maximum VDDD VDDD Units
Electrical Characteristics 25°C (LED)
Parameter Forward Voltage Reverse Breakdown Voltage Symbol Minimum Typical 2.85 Maximum 3.35 Units
Electrical Specifications (Sensor)
Parameter Output Voltage High Level[5] Output Voltage Level[6] Supply Current[7] Sleep-Mode Supply Current[7] Input Leakage Current
Over Recommended Operating Conditions (unless otherwise specified) Symbol IDD_STATIC IDD_SLP ILEAK Conditions (Note (Note Minimum Typical[3] VDDD Maximum Units
Electrical Specifications (Sensor)
Over Recommended Operating Conditions (unless otherwise specified) Parameter Internal Clock Frequency External Clock Frequency 2-Wire Interface Frequency Symbol f_CLK_int f_CLK_ext f_2wire Conditions Minimum Typical[3] Maximum Units
Optical Specification (Sensor)
Parameter Dark Offset Symbol Conditions Minimum Typical[3] Maximum Units
Minimum Sensitivity
Parameter Symbol Conditions Refer Note Irradiance Responsivity Refer Note Refer Note Refer Note Clear Minimum Typical (Note LSB/(mW cm-2) Maximum Units
Maximum Sensitivity
Parameter Symbol Conditions Refer Note Irradiance Responsivity Refer Note Refer Note Refer Note Clear Minimum Typical (Note 3796 4725 6288 6590 LSB/(mW cm-2) Maximum Units
Saturation Irradiance Minimum Sensitivity [12]
Parameter Symbol Conditions Refer Note Saturation Irradiance Refer Note Refer Note Refer Note Clear Minimum Typical (Note 6.73 5.74 4.03 3.87 mW/cm2 Maximum Units
Saturation Irradiance Maximum Sensitivity [12]
Parameter Symbol Conditions Refer Note Saturation Irradiance Refer Note Refer Note Refer Note Clear Minimum Typical (Note 0.27 0.22 Maximum Units mW/cm2
Notes: "Absolute Maximum Ratings" those values beyond which damage device occur. device should operated these limits. parametric values defined "Electrical Specifications" table guaranteed absolute maximum ratings. "Recommended Operating Conditions" table will define conditions actual device operation. Unless otherwise specified, voltages referenced ground. Specified room temperature (25°C) VDDD VDDA Applies pins. Applies pins. SDASLV tri-state when output logic high. Minimum depends pull-up resistor value. Applies pins. Refers total device current consumption. Output bidirectional pins loaded. Test condition blue light peak wavelength (lP) spectral half width (l/2) Test condition green light peak wavelength (lP) spectral half width (l/2) Test condition light peak wavelength (lP) spectral half width (l/2) Saturation irradiance (MSB)/(Irradiance responsivity).
RELATIVE SENSITIVITY WAVELENGTH (nm)
Figure Typical spectral response when gains color channels equal
Serial Interface Timing Information
Parameter Clock Frequency (Repeated) START Condition Hold Time Data Hold Time Clock Period Clock High Period Repeated START Condition Setup Time Data Setup Time STOP Condition Setup Time Free Time Between START STOP Conditions Symbol fscl tHD:STA tHD:CAT tLOW tHIGH tSU:STA tSU:DAT tSU:STD tBUF Minimum Maximum 3.45 Units
tHD:STA
tHIGH
tSU:DAT
tSU:STA
tBUF
tLOW tHD:DAT
tHD:STA
tSU:STO
Figure Serial interface timing waveforms
Serial Interface Reference
Description programming interface ADJD-S37-QR999 2-wire serial bus. consists serial clock (SCL) serial data (SDA) line. line bi-directional ADJD-S37-QR999 must connected through pull-up resistor positive power supply. When free, both lines HIGH. 2-wire serial ADJD-S37-QR999 requires device master while other devices must slaves. master device that initiates data transfer bus, generates clock signal terminates data transfer while device addressed master called slave. Slaves identified unique device addresses.
Both master slave transmitter receiver master controls direction data transfer. transmitter device that sends data receiver device that receives data from bus. ADJD-S37-QR999 serial interface always operates slave transceiver with data transfer rate 00kbit/s. START/STOP Condition master initiates terminates serial data transfers. begin serial data transfer, master must send unique signal called START condition. This defined HIGH transition line while HIGH.
master terminates serial data transfer sending another unique signal called STOP condition. This defined HIGH transition line while HIGH. considered busy after START condition. will considered free certain time after
STOP condition. stays busy repeated START (Sr) sent instead STOP condition. START repeated START conditions functionally identical.
START CONDITION
STOP CONDITION
Figure START/STOP condition
Data Transfer master initiates data transfer after START condition. Data transferred bits with master generating clock pulse each sent. data
valid, data line must stable during HIGH period clock line. Only during period clock line data line change state either HIGH LOW.
DATA VALID DATA CHANGE
Figure Data transfer
clock line synchronizes serial data transmission data line. always generated master. frequency clock line vary throughout transmission long still meets minimum timing requirements. master default drives data line. slave drives data line only when sending acknowledge after master writes data slave when master requests slave send data.
data line driven master implemented negative edge clock line. master sample data driven slave positive edge clock line. Figure shows example master implementation clock line data line synchronized.
data sampled positive edge
data driven negative edge
Figure Data synchronization
complete data transfer 8-bits long -byte. Each byte sent most significant (MSB) first followed acknowledge acknowledge bit. Each data transfer send unlimited number bytes (depending data format).
STOP repeated START CONDITION
START repeated START CONDITION
Figure Data byte transfer
Acknowledge/Not Acknowledge receiver must always acknowledge each byte sent data transfer. case slave-receiver master-transmitter, slave-receiver does send acknowledge bit, master-transmitter either STOP transfer generate repeated START start transfer.
pulled receiver (SLAVE-RECEIVER) ACKNOWLEDGE
(MASTER-TRANSMITTER)
left HIGH transmitter
(MASTER)
ACKNOWLEDGE CLOCK PULSE
Figure Slave-receiver acknowledge
case master-receiver slave-transmitter, master generates acknowledge signal data transfer slave-transmitter. master then send STOP repeated START condition begin data transfer. cases, master generates acknowledge acknowledge clock pulse.
(SLAVE-TRANSMITTER)
left HIGH transmitter
(MASTER-RECEIVER)
left HIGH receiver
ACKNOWLEDGE ACKNOWLEDGE CLOCK PULSE
(MASTER)
STOP repeated START condition
Figure Master-receiver acknowledge
Addressing Each slave device serial needs have unique address. This first byte that sent mastertransmitter after START condition. address defined first seven bits first byte. eighth least significant (LSB) determines direction data transfer. `one' first byte indicates that master will read data from addressed slave (master-receiver slave-transmitter).
`zero' this position indicates that master will write data addressed slave (master-transmitter slave-receiver). device whose address matches address sent master will respond with acknowledge first byte itself slave-transmitter slavereceiver depending first byte. slave address ADJD-S37-QR999 0x74 (7-bits).
SLAVE ADDRESS
Figure Slave addressing
Data Format ADJD-S37-QR999 uses register-based programming architecture. Each register unique address controls specific function inside chip. write register, master first generates START condition. Then sends slave address device wants communicate with. least significant (LSB) slave address must indicate that master
wants write slave. addressed device will then acknowledge master. master writes register address wants access waits slave acknowledge. master then writes register data. Once slave acknowledges, master generates STOP condition data transfer.
START CONDITION
MASTER WILL WRITE DATA
STOP CONDITION
MASTER SENDS SLAVE ADDRESS MASTER WRITES REGISTER ADDRESS SLAVE ACKNOWLEDGE MASTER WRITES REGISTER DATA
SLAVE ACKNOWLEDGE
SLAVE ACKNOWLEDGE
Figure Register byte write protocol
read from register, master first generates START condition. Then sends slave address device wants communicate with. least significant (LSB) slave address must indicate that master wants write slave. addressed device will then acknowledge master. master writes register address wants access waits slave acknowledge. master then generates repeated START condition resends
slave address sent previously. least significant (LSB) slave address must indicate that master wants read from slave. addressed device will then acknowledge master. master reads register data sent slave sends acknowledge signal stop reading. master then generates STOP condition data transfer.
START CONDITION
MASTER WILL WRITE DATA
REPEATED START CONDITION
MASTER WILL READ DATA
STOP CONDITION
MASTER SENDS SLAVE ADDRESS MASTER WRITES REGISTER ADDRESS SLAVE ACKNOWLEDGE SLAVE ACKNOWLEDGE MASTER SENDS SLAVE ADDRESS
MASTER READS REGISTER DATA
SLAVE ACKNOWLEDGE
MASTER ACKNOWLEDGE
Figure Register byte read protocol
Mechanical Drawing
4.50 SENSOR LIGHT SEPARATOR 3.90
1.80
SECTION
BOTTOM SIDE
SIDE)
SIDE (LED AREA)
0.80
ORIENTATION MARK
FOOTPRINT BOTTOM SIDE
Name DVDD AVDD SLEEP
Description cathode connection anode Bidirectional data pin. pull-up resistor should tied because goes tri-state output logic Digital power Serial interface clock Analog power Sleep pin. When SLEEP device goes into sleep mode. sleep mode, analog circuits powered down clock signal gated away from core logic resulting very current consumption. Analog ground Reset pin. Global, asynchronous, active-low system reset. When asserted low, XRST resets registers. Minimum reset pulse must provided external circuitry. Digital ground External clock input
AGND XRST DGND XCLK
Description Body size Body size Overall thickness Terminal pitch (mm)
Nominal 3.90 4.50
Tolerances +0.6 ±0.2 ±0.2 ±0.08
Figure Forward current forward voltage (LED)
Figure Luminous intensity forward current (LED)
Reflow Profile
recommended that Henkel Pb-free solder paste LF30 used soldering ADJD-S37-QR999. Below recommended reflow profile.
DELTAFLUX 2°C/SEC. MAX. PEAK 230° REFLOW 218°C TMAX 160°C TMIN 120°C DELTARAMP 1°C/SEC. MAX.
DELTACOOLING 2°C/SEC. MAX.
tPRE SEC. MAX.
tREFLOW SEC. MAX.
Recommended Land Pattern customer board)
3.00 0.50 2.10 0.80 (12x) 0.50 (12x)
4.40 2.40 1.60
2.10
2.20 5.00
Recommended Aperture Dimensions with Respect Mounting Axis Customer Board
4.50
WINDOW/ BOUNDARY OBSTACLE-FREE LIGHT PATH MIN. 2.90 LAND PATTERN CUSTOMER BOARD)
CENTER FOOTPRINT
Recommendations Handling Storage ADJD-S371-QR999
This product qualified Moisture Sensitive Level Jedec J-STD-020. Precautions when handling this moisture sensitive product important ensure reliability product. refer Avago Application Note AN5305 Handling Moisture Sensitive Surface Mount Devices details. Storage before Unopened moisture barrier (MBB) stored 30°C less maximum year. recommended open prior assembly (e.g., IQC). should also sealed with moisture absorbent material (Silica Gel) indicator card (cobalt chloride) indicate moisture within bag. Control after opening humidity indicator card (HIC) shall read immediately upon opening MBB. components must kept <30°C/60% time high temperature related process including soldering, curing rework need completed within hrs. Control unfinished reel unused components, they need stored sealed with desiccant desiccator Control assembled boards soldered with components subjected other high temperature processes, need stored sealed with desiccant desiccator ensure components have exceeded their floor life hrs. Baking required "0%" "5%" indicator turns pink. components exposed condition >30°C/60% time. components floor life exceeded hrs. Recommended baking condition component form): 25°C hrs.
Package Tape Reel Dimensions Reel Dimensions
Note: Dimensions milimeters (mm)
Carrier Tape Dimensions
(E1)1.75±0.10 (F)5.50±0.05
(PO)4.00±0.10
0.10 0.00
(T)0.30±0.05
(P2)2.00±0.05
(Ref 1.50)
(Ref 0.75)
R0.50
(P1)8.00±0.10 (KO)1.95±0.10
(AO)4.20±0.10
Notes: measured 0.3mm above base pocket pitches cumulative tolerance ±0.2mm Dimensions millimeters (mm)
(W)12.00±0.10
Appendix Typical Application Diagram
HOST SYSTEM
SLEEP
XCLK
BUFFER EXTERNAL OSCILLATOR EXTERNAL CLOCK MODE SELECTED
DVDD
COLOR SENSOR MODULE
XRST DVDD DGND AGND AVDD DRIVER
XRST HOST SYSTEM
DECOUPLING CAPACITOR (100
VOLTAGE REGULATOR
VOLTAGE REGULATOR
DECOUPLING CAPACITOR (100
Note: recommended drive with current
Appendix Sensor Register List
CTRL: Control Register
GSSR GOFS available. sensor reading. Active high automatically cleared. Result stored registers 64-7 (DEC). offset reading. Active high automatically cleared. Result stored registers 72-75 (DEC). GOFS GSSR
CONFIG: Configuration Register
EXTCLK SLEEP TOFS available. External clock mode. Active high. Sleep mode. Active high external clock mode only. Automatically cleared otherwise. Trim offset mode. Active high. EXTCKL SLEEP TOFS
CAP_RED: Capacitor Settings Register Channel
CAP_RED available. Number channel capacitors. CAP_RED[3:0]
CAP_GREEN: Capacitor Settings Register Green Channel
CAP_GREEN available. Number green channel capacitors. CAP_GREEN[3:0]
CAP_BLUE: Capacitor Settings Register Blue Channel
CAP_BLUE available. Number blue channel capacitors. CAP_BLUE[3.0]
CAP_CLEAR: Capacitor Settings Register Clear Channel
CAP_CLEAR available. Number clear channel capacitors. CAP_CLEAR[3:0]
INT_RED: Integration Time Slot Setting Register Channel
CAP_RED[7:0] INT_RED Number channel integration time slots.
INT_RED[:8]
INT_GREEN: Integration Time Slot Setting Register Green Channel
INT_GREEN[7:0] INT_GREEN Number green channel integration time slots.
INT_GREEN[:8]
INT_BLUE: Integration Time Slot Setting Register Blue Channel
INT_BLUE[7:0] INT_BLUE Number blue channel integration time slots.
INT_BLUE[:8]
INT_CLEAR: Integration Time Slot Setting Register Clear Channel
INT_CLEAR[7:0] INT_CLEAR Number clear channel integration time slots.
INT_CLEAR[:8]
DATA_RED_LO: Byte Register Channel Sensor Reading
DATA_RED[7:0] DATA_RED channel data.
DATA_RED_HI: High Byte Register Channel Sensor Reading
DATA_RED available. channel data. DATA_RED[9:8]
DATA_GREEN_LO: Byte Register Green Channel Sensor Reading
DATA_GREEN[7:0] DATA_GREEN Green channel data.
DATA_GREEN_HI: High Byte Register Green Channel Sensor Reading
DATA_GREEN available. Green channel data. DATA_GREEN[9:8]
DATA_BLUE_LO: Byte Register Blue Channel Sensor Reading
DATA_BLUE[7:0] DATA_BLUE Blue channel data.
DATA_BLUE_HI: High Byte Register Blue Channel Sensor Reading
DATA_BLUE available. Blue channel data. DATA_BLUE[9:8]
DATA_CLEAR_LO: Byte Register Clear Channel Sensor Reading
DATA_CLEAR[7:0] DATA_CLEAR Clear channel data.
DATA_CLEAR_HI: High Byte Register Clear Channel Sensor Reading
DATA_CLEAR available. Clear channel data. DATA_CLEAR[9:8]
OFFSET_RED: Offset Data Register Channel
SIGN_RED SIGN_RED OFFSET_RED Sign bit. POSITIVE, NEGATIVE. channel offset data. OFFSET_RED[6:0]
OFFSET_GREEN: Offset Data Register Green Channel
SIGN_GREEN SIGN_GREEN OFFSET_GREEN OFFSET_GREEN[6:0] Sign bit. POSITIVE, NEGATIVE. Green channel offset data.
OFFSET_BLUE: Offset Data Register Blue Channel
SIGN_BLUE SIGN_BLUE OFFSET_BLUE OFFSET_BLUE[6:0] Sign bit. POSITIVE, NEGATIVE. Blue channel offset data.
OFFSET_CLEAR: Offset Data Register Clear Channel
SIGN_CLEAR SIGN_CLEAR OFFSET_CLEAR OFFSET_CLEAR[6:0] Sign bit. POSITIVE, NEGATIVE. Clear channel offset data.
product information complete list distributors, please website:
www.avagotech.com
Avago, Avago Technologies, logo trademarks Avago Technologies Limited United States other countries. Data subject change. Copyright 2007 Avago Technologies Limited. rights reserved. AV02-0314EN July 2007
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