±2.5 kSps, 24-bit, High-throughput Features Description Diff

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CS5560
±2.5 kSps, 24-bit, High-throughput
Features Description
Differential Analog Input On-chip Buffers High Input Impedance Conversion Time Settles Conversion Linearity Error 0.0007% Signal-to-Noise Bits, Missing Codes Self-calibration:
Maintains accuracy over time temperature.
General Description
CS5560 single-channel, 24-bit analog-to-digital converter capable kSps conversion rate. input accepts fully differential analog input signal. On-chip buffers provide high input impedance both inputs VREF+ input. This significantly reduces drive requirements signal sources reduces errors source impedances. CS5560 delta-sigma converter capable switching multiple input channels high rate with loss throughput. uses low-latency digital filter architecture. filter designed fast settling settles full accuracy conversion. converter's 24-bit data output serial form, with serial port acting either master slave. converter designed support bipolar, ground-referenced signals when operated from ±2.5V analog supplies. CS5560 uses self-calibration achieve offset gain errors. converter achieves Linearity ±0.0007% full scale. converter operate from analog supply 0-5V from ±2.5V. digital interface supports standard logic operating from 1.8, 2.5, ORDERING INFORMATION: Ordering Information page
Simple three/four-wire serial interface Power Supply Configurations:
Analog: +5V/GND; +1.8V +3.3V Analog: ±2.5V; +1.8V +3.3V
Power Consumption:
Input Buffers Input Buffers Off:
CS5560
VREF+ VREFSMODE
DIGITAL FILTER LOGIC
SERIAL INTERFACE
SCLK
BUFEN
SLEEP
OSC/CLOCK GENERATOR
CALIBRATION MICROCONTROLLER
CONV BP/UP MCLK
Advance Product Information
http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 2007 (All Rights Reserved)
DS713A5
CS5560
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS SWITCHING CHARACTERISTICS DIGITAL CHARACTERISTICS DIGITAL FILTER CHARACTERISTICS GUARANTEED LOGIC LEVELS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS OVERVIEW THEORY OPERATION Reset Calibration 3.1.1 Offset Register 3.1.2 Gain Register Conversion Clock Voltage Reference Analog Input Output Coding Format Typical Connection Diagrams VREF Sampling Structures Converter Performance 3.10 Digital Filter Characteristics 3.11 Serial Port 3.11.1 Mode 3.11.2 Mode 3.12 Power Supplies Grounding 3.13 Using CS5560 Multiplexing Applications 3.14 Synchronizing Multiple Converters DESCRIPTIONS PACKAGE DIMENSIONS ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION REVISION HISTORY
DS713A5
CS5560
LIST FIGURES
Figure Mode Read Timing, remaining Figure Mode Read Timing, falling after falls Figure Mode Read Timing (Not Scale) Figure Mode Calibration Register Read Timing Figure Mode Write Timing Figure Voltage Reference Circuit Figure CS5560 Configured Using ±2.5V Analog Supplies Figure CS5560 Configured Using Single Analog Supply Figure CS5560 Plot. Figure CS5560 Spectral Response fs/2) Figure CS5560 Spectral Response kHz) Figure CS5560 Spectral Response 4fs) Figure Simple Multiplexing Scheme Figure More Complex Multiplexing Scheme
LIST TABLES
Table Offset Gain Calibration Register Read/Write Commands Table Output Coding, Two's Complement Table Output Coding, Offset Binary
DS713A5
CHARACTERISTICS SPECIFICATIONS
CS5560
characteristics specifications guaranteed over specified operating conditions. Typical characteristics specifications measured nominal supply voltages 25°C. voltages with respect
ANALOG CHARACTERISTICS +2.5 ±5%; -2.5 ±5%; -VLR ±5%; VREF (VREF+) (VREF-) 4.096V; MCLK MHz; SMODE BUFEN unless otherwise stated. Connected Figure Bipolar mode unless otherwise stated.
Parameter Accuracy Linearity Error Differential Linearity Error Positive Full-scale Error Negative Full-scale Error Full-scale Drift Unipolar Offset Unipolar Offset Drift Bipolar Offset Bipolar Offset Drift Noise Dynamic Performance Peak Harmonic Spurious Noise Total Harmonic Distortion Signal-to-Noise S/(N Ratio Input Bandwidth
After Reset After Calibration (Note After Reset After Calibration (Note After Reset After Calibration (Note After Reset After Calibration (Note kHz, -0.5 Input kHz, -0.5 Input -0.5 Input, Input,
0.0003 ±0.1 0.01 0.01 ±2000 ±400 ±1000 ±200 -110 -110
Unit ±%FS LSB24 LSB24 LSB24 LSB24 LSB24 LSB24 µVrms
(Note (Note
(Note
(Note
(Note
(Note
Applies after calibration temperature within missing codes guaranteed bits resolution over specified temperature range. Total drift over specified temperature range after calibration power-up, Scales with MCLK.
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ANALOG CHARACTERISTICS (CONTINUED)
Parameter Analog Input Analog Input Range Input Capacitance Current (Note Buffer (BUFEN Buffer (BUFEN ACOM Unipolar Bipolar +VREF ±VREF
CS5560
+2.5 ±5%; -2.5 ±5%; -VLR ±5%; VREF (VREF+) (VREF-) 4.096V; MCLK MHz; SMODE VL.; BUFEN unless otherwise stated. Connected Figure Unit
Voltage Reference Input Voltage Reference Input Range (VREF+) (VREF-) Input Capacitance Current VREF+ Buffer (BUFEN VREF+ Buffer (BUFEN VREFIV1 Normal Operation Buffers Buffers (Note Supplies V1-, Supplies (Note 4.096
Power Supplies Power Supply Currents
Power Consumption Power Supply Rejection
Measured using input signal optimum performance, VREF+ should always less than (V+) volts prevent saturation VREF+ input buffer. Tested with mVP-P supply kHz. supplies same voltage potential, supplies same voltage potential.
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SWITCHING CHARACTERISTICS
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Logic VD+; Parameter Master Clock Frequency Master Clock Duty Cycle Reset Time rising falling Calibration pulse width high setup time rising Calibration Time rising (CAL high) falling Calibration Time rising (RST high) falling Conversion CONV Pulse Width BP/UP setup CONV falling CONV start conversion Perform Single Conversion (CONV high before falling) Conversion Time Sleep Mode SLEEP low-power state SLEEP high device active (Note
CS5560
Symbol Internal Oscillator External Clock fclk
1536 331458 331458 3083
16.2
Unit MCLKs MCLKs MCLKs MCLKs MCLKs MCLKs MCLKs MCLKs MCLKs
tres Internal Oscillator External Clock (Note (Note twup
tccw tscl tcal
tcpw (Note tscn tscn tbus tbuh tcon tcon
(Note Start Conversion falling
controlled same signal used RST. goes high simultaneously with RST, calibration will performed, must remain high until falls. BP/UP changed coincident CONV falling. BP/UP must remain stable until falls. CONV held continuously, conversions occur every MCLK cycles. tied CONV, conversions will occur every MCLKs. CONV operated asynchronously MCLK, conversion take MCLKs. falls conversion. will fall when device fully operational when coming sleep mode.
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Logic VD+; Parameter Serial Port Timing Mode (SMODE falling stable Data hold time after SCLK rising Serial Clock (Out) (Note rising after last SCLK rising
CS5560
Symbol Pulse Width (low) Pulse Width (high)
Unit MCLKs MCLKs
SCLK will high impedance when high. some systems require pull-down resister. SCLK MCLK/2.
MCLK
SCLK(o)
MSB-1
LSB+1
Figure Mode Read Timing, remaining (Not Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Logic VD+; Parameter Serial Port Timing Mode (SMODE Data hold time after SCLK rising Serial Clock (Out) (Note rising after last SCLK rising falling stable First SCLK rising after falling hold time (low) after SCLK rising SCLK, tristate after rising
CS5560
Symbol Pulse Width (low) Pulse Width (high)
Unit MCLKs MCLKs
SCLK will high impedance when high. some systems require pull-down resister. SCLK MCLK/2.
MCLK
SCLK(o)
MSB-1 LSB+1
Figure Mode Read Timing, falling after falls (Not Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Logic VD+; Parameter Serial Port Timing Mode (SMODE VLR) SCLK(in) Pulse Width (High) SCLK(in) Pulse Width (Low) hold time (high) after falling hold time (high) after SCLK rising Hi-Z Data hold time after SCLK rising Data setup time before SCLK rising hold time (low) after SCLK rising rising after SCLK falling
CS5560
Symbol
Unit
(Note
will high impedance when high. some systems require pull-down resistor.
MCLK
SCLK(i)
Figure Mode Read Timing (Not Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Logic VD+; Parameter
Calibration Register Read Timing
CS5560
Symbol
Unit
hold time (high) after SCLK rising Data setup time before SCLK rising Data hold time after SCLK rising SCLK rising data stable Data hold time after SCLK rising SCLK rising rising tristate after rising
SCLK(i)
Command Time SCLKs
Data Time SCLKs
Figure Mode Calibration Register Read Timing (Not Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Logic VD+; Parameter
Calibration Register Write Timing
CS5560
Symbol
Unit
Data setup time before SCLK rising Data hold time after SCLK rising SCLK rising rising
will high impedance when high. some systems require pull-down resister.
SCLK(i)
Command Time SCLKs
Data Time SCLKs
Figure Mode Write Timing (Not Scale)
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DIGITAL CHARACTERISTICS
TMIN TMAX; 3.3V, 2.5V, 1.8V, ±5%; Parameter Calibration Memory Retention Power Supply Voltage [V1+ V2+] [V1- V2-] Input Leakage Current Digital Input Capacitance Digital Output Capacitance
CS5560
Symbol (Note Cout
Unit
value from memory retention. Neither should allowed positive. AIN1, AIN2, VREF must greater than VD+. This parameter guaranteed characterization.
DIGITAL FILTER CHARACTERISTICS
TMIN TMAX; 3.3V, 2.5V, 1.8V, ±5%; Parameter Group Delay Symbol Unit MCLKs
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GUARANTEED LOGIC LEVELS
+2.5 ±5%; -2.5 ±5%; ±5%, ±5%, Input levels: Logic Logic VD+; Guaranteed Limits Parameter Logic Inputs
Minimum High-level Input Voltage:
CS5560
Unit
Conditions
0.95
Maximum Low-level Input Voltage:
Logic Outputs
Minimum High-level Output Voltage:
1.65 0.36 0.36 0.44
Maximum Low-level Output Voltage:
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RECOMMENDED OPERATING CONDITIONS
(VLR Note
CS5560
Parameter Single Analog Supply Power Supplies: (Note V1V2(Note V1V2(Note [VREF+] [VREF-]
Symbol
Unit
V2V1+
4.75 4.75
5.25 5.25
Dual Analog Supplies Power Supplies: V2V1+ V2VREF +2.375 +2.375 -2.375 -2.375 +2.5 +2.5 -2.5 -2.5 4.096 +2.625 +2.625 -2.625 -2.625
Analog Reference Voltage
logic supply value +1.6 +3.6 volts long differential voltage reference magnitude constrained supply magnitude.
ABSOLUTE MAXIMUM RATINGS
(VLR
Parameter Power Supplies: [V1+] [V1-] (Note |V1-| (Note Input Current, Except Supplies Analog Input Voltage Digital Input Voltage Storage Temperature Notes: V2+; V222.
Symbol VINA VIND Tstg
(V1-)
(V1+)
Unit
(Note
(AIN VREF pins)
V2Transient currents will cause latch-up.
WARNING: Operation beyond these limits result permanent damage device.
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OVERVIEW
CS5560
CS5560 24-bit analog-to-digital converter capable kSps conversion rate. device capable switching multiple input channels high rate with loss throughput. uses low-latency digital filter architecture. filter designed fast settling settles full accuracy conversion. converter serial output device. serial port configured function either master slave. CS5560 provides self-calibration circuitry achieve offset gain errors. converter operate from analog supply from ±2.5V. digital interface supports standard logic operating from 1.8, 2.5, CS5560 converts kSps when operating from input clock.
THEORY OPERATION
CS5560 converter provides high-performance measurement signals. converter includes on-chip calibration circuitry minimize offset gain errors. converter used perform single conversions continuous conversions upon command. Each conversion independent previous conversions settle full specified accuracy, even with full-scale input voltage step. This converter architecture which uses combination high-speed delta-sigma modulator low-latency filter architecture. Once power established converter, reset must performed. reset initializes internal converter logic sets offset register zero gain register decimal value 1.0. when transitions from high, calibration will performed. high when goes high, converter's offset gain slope will calibrated. CONV held then converter will convert continuously with falling every MCLKs. This equivalent kSps MCLK 16.0 MHz. CONV tied RDY, conversion will occur every MCLKs. CONV operated asynchronously MCLK, take MCLKs from CONV falling falling. Multiple converters operate synchronously they driven same MCLK source CONV each converter falls same MCLK falling edge. Alternately, CONV held devices reset with rising same falling edge MCLK. output coding conversion word function BP/UP pin. active-low SLEEP signal causes device enter low-power state. calibration register contents preserved during sleep. When exiting sleep, converter will take 3083 MCLK cycles before conversions performed. should remain inactive (high) when SLEEP asserted (low).
Reset Calibration
After power supplies voltage reference stable, converter must reset. reset function initializes internal logic converter, does initiate calibration. After reset been performed, converter used uncalibrated, calibration performed. Calibration minimizes offset gain errors inside converter. device used without calibration, conversions will include offset gain errors uncalibrated converter, converter will maintain differential integral linearity. Calibration offset gain performed upon command.
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CS5560
Calibration initiated either ways. high when transitions from high, calibration cycle will performed. When calibration performed, offset full-scale points converter calibrated. calibration cycle takes 327,680 MCLK cycles. signal falls upon completion reset calibration sequence. held when transitions from high, calibration will performed. Calibrations initiated time converter idle taking input high. will fall calibration cycle. should returned when being used. calibration cycle calibrates offset full-scale points converter transfer function. When offset portion calibration performed, AIN+ AIN- pins disconnected from input shorted internally. offset converter then measured correction factor stored offset calibration register. Then voltage reference internally connected input signal converter gain calibration performed. gain correction results placed gain calibration register. contents 24-bit offset gain registers used conversion data prior output from converter. offset gain calibration registers read written desired. read write calibration registers inside converter, converter must idle, serial port must mode (SMODE VLR). Table depicts commands necessary read write calibration registers.
Table Offset Gain Calibration Register Read/Write Commands
Register Offset Register Gain Register
Read Command 0x40 0x20
Write Command 0xC0 0XA0
3.1.1 Offset Register
Sign 2-11 2-12 2-24
offset register maps with conversion word when gain register decimal. After reset bits zero. 3.1.2 Gain Register
2-10 2-11 2-12 2-13 2-14 2-21). 2-15 2-16 2-17 2-18 2-19 2-20 2-21
gain register spans from imal gain value 1.000.000.
After reset, others This results dec-
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CS5560
on-chip calibration registers read written serial port. Reading writing into calibration registers requires that serial port mode. write into offset gain register, appropriate 8-bit command (see Table page first shifted into pin. Rising edges SCLK latch bits. perform write, 8-bit command immediately followed data word written. When read command used, data word from register will output from pin. data bits will output rising edges SCLK. data bits have sufficient hold time latched externally next rising edge SCLK.
Conversion
CS5560 converts kSps when synchronously operated (CONV VLR) from 16.0 master clock. Conversion initiated taking CONV low. conversion lasts master clock cycles, CONV asynchronous MCLK there uncertainty MCLK cycles after CONV falls when conversion actually begins. This extend throughput MCLKs When conversion completed, output word placed into serial port goes low. convert continuously, CONV should held low. continuous conversion mode with CONV held low, conversion performed MCLK cycles. Alternately tied CONV conversion will occur every MCLK cycles. perform only conversion, CONV should return high least master clock cycles before falls. Once conversion completed falls, will return high when bits data word emptied from serial port conversion data read held low, will high MCLK cycles before conversion. will fall next conversion when data into port register. Serial Port page information about reading conversion data. Conversion performance affected several factors. These include choice clock source chip, timing CONV, choice serial port mode. converter operated from internal oscillator. This clock source greater jitter than external crystal-based clock. Jitter issue when measuring signals, very-low-frequency signals, become issue higher frequency signals. maximum performance when digitizing signals, low-jitter MCLK should used. maximize performance, CONV should held continuous conversion state perform multiple conversions, CONV should occur synchronous MCLK, falling when MCLK falls. converter operated maximum throughput, serial port mode less likely cause interference measurements SCLK output synchronized MCLK. Alternately, interference serial port clocking also minimized data read serial port mode when conversion progress.
Clock
CS5560 operated from internal oscillator from external master clock. state MCLK determines which clock source will used. MCLK tied low, internal oscillator will start used clock source converter. external CMOS-compatible clock input into MCLK converter will power down internal oscillator external clock. MCLK held high, internal oscillator will held stopped state. MCLK input held high delete clock cycles operating multiple converters different phase relationships.
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CS5560
internal oscillator used signals measured essentially internal oscillator exhibits jitter about picoseconds rms. CS5560 used digitize signals, external low-jitter clock source should used. internal oscillator used clock CS5560, maximum conversion rate will dictated oscillator frequency.
Voltage Reference
voltage reference CS5560 range from volts volts. 4.096 volt reference required achieve specified performance. Figure Figure illustrate connection voltage reference with either single analog supply with ±2.5 optimum performance, voltage reference device should that provides capacitor connection provide means noise filtering, output should include some type bandwidth-limiting filter. Some 4.096 volt reference devices need only volts total supply operation connected shown Figure Figure reference should have local bypass capacitor appropriate output capacitor. Some older 4.096 voltage reference designs require more headroom must operate from input voltage volts. this type voltage reference used ensure that when power applied system, voltage reference rise time slower than rise time power supply voltage converter. example circuit slow output startup time reference illustrated Figure
10µF
VOUT
Refer VREF1 pins.
Figure Voltage Reference Circuit
4.096
Analog Input
analog input converter fully differential with peak input 4.096 volts each input. This illustrated Figure Figure These diagrams also illustrate differential buffer amplifier configuration driving CS5560. capacitors outputs amplifiers provide charge reservoir dynamic current from inputs while resistors isolate dynamic current from amplifier. amplifiers powered from higher supplies than those used precautions should taken ensure that output voltage remains within power supply limits A/D, especially under start-up conditions.
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Output Coding Format
CS5560
reference voltage directly defines input voltage range both unipolar bipolar configurations. unipolar configuration (BP/UP low), first code transition occurs above zero, final code transition occurs LSBs below VREF. bipolar configuration (BP/UP high), first code transition occurs above -VREF last transition occurs LSBs below +VREF. Table output coding converter.
Table Output Coding, Two's Complement
Bipolar Input Voltage
>(VREF-1.5 LSB) VREF-1.5 -0.5 -VREF+0.5 <(-VREF+0.5 LSB)
Two's Complement
NOTE: VREF (VREF+) (VREF-)
Table Output Coding, Offset Binary
Unipolar Input Voltage
>(VREF-1.5 LSB) VREF-1.5 (VREF/2)-0.5 +0.5 <(+0.5 LSB)
Offset Binary
NOTE: VREF (VREF+) (VREF-)
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Typical Connection Diagrams
CS5560
following figure depicts CS5560 powered from bipolar analog supplies, +2.5
4700pF
49.9
AIN+
60pF
CS5560
4.99k
+2.048 -2.048
4.99k
49.9
+2.048 -2.048
SMODE
SCLK
AIN60pF
4.99k
4700pF
4.99k
(V+) Buffers
+2.5
CONV
BUFEN
(V-) Buffers
+4.096 Voltage Reference (NOTE VREF+
BP/UP
SLEEP
MCLK
VREF-
-2.5
+2.5
+3.3 +1.8
-2.5
NOTES Section Voltage Reference information required voltage reference performance criteria. 2.Locate capacitors minimize loop length. ±2.5 supplies should also bypassed ground converter. power supply ground ±2.5 should connected same ground plane under chip. SCLK require pull-down resistors some applications. input filter used band limit input reduce noise. Select equal parallel combination feedback feedback resistors 4.99k 4.99k 2.5k
Figure CS5560 Configured Using ±2.5V Analog Supplies
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following figure depicts CS5560 device powered from single analog supply.
4700pF
CS5560
49.9
47pF
4.99k
2.048
AIN+
4.548 -0.452
+4.548 -0.452
CS5560
SMODE
49.9
47pF
4.99k
AIN4.096
4700pF
SCLK
(V+) Buffers
BUFEN
CONV
BP/UP
SLEEP
(V-) Buffers
+4.096 Voltage Reference (NOTE
VREF+
MCLK
VREF-
+3.3
NOTES Section Voltage Reference information required voltage reference performance criteria. Locate capacitors minimize loop length. V1-, V2-, should connected same ground plane under chip. SCLK require pull-down resistors some applications.
Figure CS5560 Configured Using Single Analog Supply
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VREF Sampling Structures
CS5560
CS5560 uses on-chip buffers AIN+, AIN-, VREF+ inputs. Buffers provide much higher input impedance therefore reduce amount drive current required from external source. This helps minimize errors. Buffer Enable (BUFEN) determines on-chip buffers used not. BUFEN connected supply buffers will enabled. BUFEN connected buffers off. converter will consume about less power when buffers off, input impedances AIN+, AIN- VREF+ will significantly less than with buffers enabled.
Converter Performance
CS5560 achieves excellent differential nonlinearity (DNL) shown Figure Figure illustrates code widths typical scale zoomed scale ±0.2 LSB.
(Zoom View) Figure CS5560 Plot
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3.10 Digital Filter Characteristics
CS5560
digital filter designed fast settling, therefore exhibits very little in-band attenuation. filter attenuation 1.040 when sampling kSps.
-0.0414
kSps
-0.166 -0.3725
-0.2
Attenuation (dB)
-0.4 -0.6
-0.664
-0.8 -1.0 -1.2
Frequency (Hz)
-1.040
Figure CS5560 Spectral Response fs/2)
-0.001646 -0.00663 -0.0149
kSps
-0.0262
-0.0414
Frequency (Hz)
Figure CS5560 Spectral Response kHz)
kSps
Figure CS5560 Spectral Response 4fs)
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3.11 Serial Port
CS5560
serial port CS5560 operate different modes: synchronous self clock (SSC) mode synchronous external clock (SEC) mode. serial port must placed into mode offset gain registers converter read written. converter must idle when reading writing on-chip registers. 3.11.1 Mode SMODE high (SMODE VL), serial port operates (Synchronous Self Clock) mode. mode port shifts conversion data words with SCLK output. SCLK generated inside converter from MCLK. Data output from (Serial Data Output) pin. high, SCLK pins will stay high-impedance state. when falls, conversion data word will output from first. Data output rising edge SCLK should latched into external logic subsequent rising edge SCLK. When bits conversion word output from port signal will return high. 3.11.2 Mode SMODE (SMODE VLR), serial port operates (Synchronous External Clock mode). this mode, user usually monitors RDY. When falls conversion, conversion data word placed into output data register serial port. then activated enable data output. Note that held continuously necessary have output operate high impedance state. When taken (after falls) conversion data word then shifted driving SCLK from system logic external converter. input must held when reading conversion word data. Data bits advanced rising edges SCLK latched subsequent rising edge SCLK. held continuously, signal will fall conversion conversion data will placed into serial port. user starts read, user will maintain control over serial port until port empty. However, SCLK toggled, converter will overwrite conversion data completion next conversion. held read performed, will rise just prior next conversion then fall signal that data been written into serial port.
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3.12 Power Supplies Grounding
CS5560
CS5560 configured operate with analog supply operating from with analog supplies operating from ±2.5V. digital interface supports digital logic operating from either 1.8V, 2.5V, 3.3V. Figure page illustrates device configured operate from ±2.5V analog. Figure page illustrates device configured operate from analog. maximize converter performance, analog ground logic ground converter should connected converter. dual analog supply configuration, analog ground ±2.5V supplies should connected converter with converter placed entirely over analog ground plane. single analog supply configuration (+5V), ground supply should directly tied converter with converter placed entirely over analog ground plane. Refer Figure page
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3.13 Using CS5560 Multiplexing Applications
CS5560
CS5560 delta-sigma converter. Delta-sigma converters oversampling means achieve high signal noise. This means that once conversion started converter takes many samples compute resulting output word. analog input signal converted must remain active during entire conversion until falls. CS5560 used multiplexing applications, system timing changing multiplexer channel starting conversion will depend upon multiplexer system architecture. simplest system illustrated Figure time multiplexer changed, analog signal presented converter must fully settle. After signal settled, CONV signal issued converter start conversion. Being delta-sigma converter, signal must remain present input converter until conversion completed. Once conversion completed, falls. this time multiplexer changed next channel data read from serial port. CONV signal should delayed until after data read until analog signal settled. this configuration, throughput converter will dictated settling time analog input circuit conversion time converter. conversion data read from serial port after multiplexer changed channel while analog input signal settling.
CS556x
4700pF
CH1+ CH2+ CH3+ CH4+ CH1CH2CH3CH4-
49.9 60pF 4.99k
AIN+
49.9 60pF 4.99k 4700pF
AIN-
Amplifier Settling Time
Conversion Time
Amplifier Settling Time
CONV
Advance
Throughput
Figure Simple Multiplexing Scheme
more complex multiplexing scheme used increase throughput converter illustrated Figure this circuit, banks multiplexers used.
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CS5560
same time converter performing conversion channel from bank multiplexers, second multiplexer bank used select channel next conversion. This configuration allows buffer amplifier second multiplexer bank fully settle while conversion being performed channel from first multiplexer bank. multiplexer output buffer amplifier CONV signal changed same time this configuration. This multiplexing architecture allows maximum multiplexing throughput from converter.The following figure depicts recommended analog input amplifier circuit.
4700pF 49.9
B1B2-
60pF 4.99k
49.9
CS556x
4700pF
60pF 4.99k
AIN+ A1A2AIN-
C1C2-
4700pF 49.9
60pF 4.99k
49.9
60pF 4.99k
4700pF
CONV
Select Select Select Select Select
Select
Select
Select
Select
Select
Select
Convert
Convert
Convert
Convert
Convert
Figure More Complex Multiplexing Scheme
3.14 Synchronizing Multiple Converters
Many measurement systems have multiple converters that need operate synchronously. converters should driven from same master clock. this configuration, converters will convert synchronously same CONV signal used drive converters, CONV falls falling edge MCLK. CONV held continuously, reset (RST) used synchronize multiple converters released falling edge MCLK.
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DESCRIPTIONS
Chip Select Serial Data Input Serial Mode Select Differential Analog Input Differential Analog Input Negative Power Positive Power Buffer Enable Voltage Reference Input Voltage Reference Input Bipolar/Unipolar Select Sleep Mode Select SMODE AIN+ AINV1V1+ BUFEN VREF+ VREFBP/UP SLEEP SCLK MCLK V2V2+ CONV Ready Serial Clock Input/Output Serial Data Output Logic Interface Power Logic Interface Return Master Clock Negative Voltage Positive Voltage Digital Core Regulator Convert Calibrate Reset
CS5560
Chip Select, Chip Select allows external device access serial port. SMODE (SSC Mode) held high, output SCLK output will held high-impedance output state. Serial Data Input, input reading writing calibration registers serial port. only accessible when SMODE enable serial mode. Data shifted into this SCLK. should held when serial port mode. SMODE Serial Mode Select, serial interface mode (SMODE) dictates whether serial port behaves master slave interface.If SMODE tied high VL), port will operate Synchronous Self-Clocking (SSC) mode. mode port acts master which converter outputs both SCLK signals. SMODE tied VLR) port will operate Synchronous External Clocking (SEC) mode. mode, port acts slave which external logic microcontroller generates SCLK used output conversion data word from pin. AIN+, AIN- Differential Analog Input, AIN+ AIN- differential inputs converter. Negative Power pins provide negative supply voltage core circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single supply operation these voltages nominally (Ground). dual supply operation they nominally -2.5 Positive Power pins provide positive supply voltage core circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single supply operation these voltages nominally dual supply operation they nominally +2.5 BUFEN Buffer Enable, Buffers input pins AIN+ AIN- enabled BUFEN connected disabled connected V1-.
DS713A5
CS5560
VREF+, VREF- Voltage Reference Input, differential voltage reference input these pins functions voltage reference converter. voltage between these pins range between volts volts, with 4.096 volts being nominal reference voltage value. BP/UP Bipolar/Unipolar Select, BP/UP determines span output coding converter. When high select (bipolar), input span converter -4.096 volts +4.096 volts fully differential (assuming voltage reference 4.096 volts) outputs data coded two's complement format. When select (unipolar), input span +4.096 fully differential output data coded binary format. SLEEP Sleep Mode Select, When taken low, SLEEP will cause converter enter into low-power state. SLEEP will stop internal oscillator power down internal analog circuitry. Reset, Reset necessary after power initially applied converter. When input taken low, logic converter will reset. When released high, certain portions analog circuitry started. falls when reset complete. Calibrate, After power applied, reset should performed prior calibration. After initial reset, calibration performed time. Calibration initiated either ways. high when coming reset, (RST going high), calibration will performed. taken high with low, calibration performed, calibration initiated taking high time converter idle. will also fall when calibration completed. CONV Convert, CONV initiates conversion cycle taken low, unless calibration cycle previous conversion progress. When conversion cycle completed, conversion word output serial port register signal goes low. CONV held remains when falls another conversion cycle will started. Digital Core Regulator, output on-chip regulator digital logic core. should bypassed with capacitor V2-. designed power external load. Positive Power pins provide positive supply voltage circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single supply operation these voltages nominally dual supply operation they nominally +2.5 Negative Power pins provide negative supply voltage circuitry chip. These pins should decoupled shown application block diagrams. should supplied from same source voltage. single supply operation these voltages nominally (Ground). dual supply operation they nominally -2.5 MCLK Master Clock, master clock (MCLK) multi-function pin. tied (MCLK VLR) on-chip oscillator will enabled. tied high (MCLK VL), clocks internal circuitry converter will stop. When MCLK held high internal oscillator will also stopped. MCLK also function input external CMOS-compatible clock that conforms supply voltages pins.
DS713A5
CS5560
VLR, Logic Interface Power/Return, supply voltages digital logic interface. configured with wide range common mode voltage. following interface pins function from VL/VLR supply: SMODE, SCLK, SDI, SDO, RDY, SLEEP, CONV, RST, CONV, CAL, BP/UP, MCLK. Serial Data Output, output serial output port. Data from this will output rate determined SCLK format determined BP/UP pin. Data output first advances next data rising edges SCLK. will high impedance state when high. SCLK Serial Clock Input/Output, SMODE determines whether SCLK signal input output signal. SCLK determines rate which data clocked pin. converter mode, SCLK frequency will determined master clock frequency converter (either MCLK internal oscillator). mode, user determines SCLK frequency. SMODE (SSC Mode), SCLK will high-impedance state when high. Ready, signal rises when calibration initiated. When calibration near completion state CONV examined. CONV high, signal will fall upon completion calibration. CONV converter will immediately start conversion will remain high until conversion completed. conversion falls indicate that conversion word been placed into serial port. will return high after data bits shifted serial port master clock cycles before data becomes available inactive (high); master clock cycles before data becomes available user holds started reading data from converter when mode.
DS713A5
PACKAGE DIMENSIONS
CS5560
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
-0.002 0.064 0.009 0.311 0.291 0.197 0.022 0.025
INCHES -0.006 0.068 -0.323 0.307 0.209 0.026 0.03
0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.030 0.041
-0.05 1.62 0.22 7.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.13 1.73 -8.20 7.80 5.30 0.65 0.75
NOTE 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.75 1.03
JEDEC MO-150
Controlling Dimension Millimeters. Notes:
1."D" "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. 2.Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. 3.These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS713A5
ORDERING INFORMATION
Model Linearity Temperature Conversion Time Throughput
CS5560
Package
CS5560-ISZ
0.0007%
kSps
24-pin SSOP
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number Peak Reflow Temp Rating* Floor Life Days
CS5560-ISZ
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
REVISION HISTORY
Revision Date 2007 2007 2007 2007 2007 Advance release. Updated serial interface timing parameters. Added plot. Updated Typical Connection diagram. Corrected liearity spec. Ordering Information section. Changes
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
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DS713A5

±2.5 kSps, 24-bit, High-throughput Features Description Diff

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